WO2013129229A1 - Procédé de fabrication d'un dispositif semi-conducteur - Google Patents

Procédé de fabrication d'un dispositif semi-conducteur Download PDF

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Publication number
WO2013129229A1
WO2013129229A1 PCT/JP2013/054323 JP2013054323W WO2013129229A1 WO 2013129229 A1 WO2013129229 A1 WO 2013129229A1 JP 2013054323 W JP2013054323 W JP 2013054323W WO 2013129229 A1 WO2013129229 A1 WO 2013129229A1
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Prior art keywords
metal
aluminum
semiconductor chip
bonding
wiring metal
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PCT/JP2013/054323
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English (en)
Japanese (ja)
Inventor
宮本　健二
中川　成幸
義貴 上原
千花 山本
南部　俊和
井上　雅之
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日産自動車株式会社
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Priority to JP2014502163A priority Critical patent/JP5733466B2/ja
Publication of WO2013129229A1 publication Critical patent/WO2013129229A1/fr

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/20—Preliminary treatment of work or areas to be soldered, e.g. in respect of a galvanic coating
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Definitions

  • the present invention relates to a method of manufacturing a semiconductor device, in particular, a semiconductor device comprising a semiconductor chip having an aluminum-based metal on the surface and a wiring metal having at least a surface made of an aluminum-based metal, and manufactured by such a method.
  • the present invention relates to a semiconductor device.
  • Recent semiconductor devices particularly semiconductor devices called high power modules having a large current density, are required to be usable even in a high temperature environment. Therefore, in a mounting structure of a semiconductor device, a joint having excellent high temperature durability when held at a high temperature or subjected to a high temperature thermal cycle is strongly desired. From the viewpoint of environmental protection, a Pb (lead) -free joining technique is essential.
  • solder is widely used for bonding for mounting such semiconductor devices, but the operating temperature is the melting point of the solder (for example, It is limited to about 200 ° C. or less. Also, for example, in a joint where the electrode is Cu, a Cu—Sn brittle intermetallic compound layer is formed at the interface, resulting in poor high-temperature durability. Therefore, various attempts have been made to ensure the high temperature durability of the joint.
  • a low temperature bonding method has been proposed in which active surface energy of metal nanoparticles is used to agglomerate and bond at a low temperature (see Patent Document 1). If this joining method is used, the joining interface after agglomeration becomes a bulk metal, and thus has high durability at high temperatures.
  • High-temperature solders include Au-Ge (germanium) solders and Au-Sn solders that have an Au-based composition.
  • Au-Ge (germanium) solders and Au-Sn solders that have an Au-based composition.
  • Au which is a noble metal. It becomes very expensive and is not realistic as described above.
  • the present invention has been made in view of the above-described problems in the conventional bonding technology applied to the mounting structure of a semiconductor device.
  • the object of the present invention is excellent in high-temperature durability, and furthermore, precious metal and Pb. It is an object of the present invention to provide a method for manufacturing a semiconductor device that enables low-cost bonding without using a semiconductor device. It is another object of the present invention to provide a low-cost and high-temperature durability semiconductor device to which such a bonding method is applied.
  • the present inventors have made the joining surface of the semiconductor chip and the wiring metal an aluminum-based metal, and interposed an insert material between them to make the joining surface fine. It has been found that the above problems can be solved by forming irregularities and causing a eutectic reaction between Al and the insert material at the bonding interface, and the present invention has been completed.
  • the present invention is based on the above knowledge, and in the method for manufacturing a semiconductor device according to the present invention, an aluminum-based metal provided on the bonding surface of the semiconductor chip and an aluminum-based metal provided on at least the bonding surface of the wiring metal. And an insert material containing a metal that causes a eutectic reaction with Al, and fine irregularities for breaking the oxide film on the aluminum-based metal surface are formed on at least a part of the bonding surface and the insert material surface.
  • the semiconductor chip and the wiring metal are heated while being relatively pressurized, the eutectic reaction melt generated at the bonding interface is discharged together with the oxide film, and the semiconductor chip and the wiring metal are formed at least at a part of the bonding interface.
  • the aluminum-based metal is directly joined to each other.
  • the semiconductor device of the present invention is a semiconductor device in which a semiconductor chip and a wiring metal are joined, and can be manufactured by the above method, and the semiconductor chip has an aluminum-based metal on the surface, and the wiring metal Has an aluminum-based metal at least on the surface, and the semiconductor chip and the aluminum metal of the wiring metal are directly bonded at least at a part of the bonding interface, and an eutectic composition of Al and Al It is characterized by the presence of effluents containing the oxides.
  • the oxide film on the surface of the aluminum-based metal is destroyed by the fine unevenness provided in the joint, and a eutectic reaction occurs between Al and the insert material, and the oxide film is removed at low temperature and low pressure.
  • the semiconductor chip and the aluminum metal of the wiring metal can be firmly bonded to each other, and bonding with excellent high-temperature durability can be achieved at low cost.
  • (A)-(e) is process drawing which shows roughly the joining process of the semiconductor chip and wiring metal by the manufacturing method of the semiconductor device of this invention.
  • (A)-(c) is a perspective view which shows the example of the shape of the fine unevenness
  • (A)-(c) is sectional drawing which respectively shows the form example of the wiring metal which comprises the other of the semiconductor device by the manufacturing method of this invention.
  • (A)-(d) is a schematic sectional drawing which respectively shows the embodiment of the semiconductor device by the manufacturing method of this invention.
  • (A) And (b) is each schematic sectional drawing which shows the other embodiment of the semiconductor device by the manufacturing method of this invention.
  • % means mass percentage unless otherwise specified.
  • the aluminum-based metal and the insert material are brought into contact with each other to cause a eutectic reaction between Al and the metal contained in the insert material at the bonding interface.
  • the eutectic reaction melt is discharged together with the oxide film so that the semiconductor chip and the aluminum metal of the wiring metal are directly bonded to each other at least at a part of the bonding interface.
  • the oxide film can be destroyed without damaging the chip with a relatively low applied pressure.
  • the aluminum-based metal and the insert material come into contact with each other through the fractured portion, and the eutectic reaction generated from the contacted portion expands to the entire joining surface, so that the oxide film on the joining surface has a low temperature (co-current). Therefore, direct bonding between aluminum-based metals becomes possible. Therefore, since strength is ensured by direct bonding between noble metals and Pb-free aluminum-based metals, even when kept at high temperatures, brittle intermetallic compound layers and Kirkendall voids are not generated, and excellent high-temperature durability A semiconductor device provided with a Pb-free bonding portion provided with can be manufactured at low cost.
  • 1 (a) to 1 (e) are process charts for explaining step by step a bonding process between a semiconductor chip and a wiring metal in a method for manufacturing a semiconductor device according to the present invention.
  • the insert material 4 is disposed between the wiring metal 2 and the semiconductor chip 3.
  • the wiring metal 2 is made of an aluminum-based metal in this example, and fine unevenness 2r is formed in advance on the bonding surface, and the aluminum-based metal is formed on the bonding surface of the semiconductor chip 3.
  • An aluminum layer 3c made of is formed.
  • strong oxide films 2f and 3f mainly composed of Al 2 O 3 are formed on the surfaces of the wiring metal 2 and the aluminum layer 3c made of these aluminum-based metals.
  • a pure aluminum material (industrial pure aluminum) or an alloy material containing 80% or more of Al as a main component is used.
  • aluminum-based metal means such aluminum or aluminum alloy.
  • the shape of the fine irregularities 2r formed on the joint surface of the wiring metal 2 is not limited as long as it has a function of concentrating stress and promoting the destruction of the oxide film.
  • FIG. Those shown in a) to (c) can be employed. That is, as shown in FIG. 2 (a), if the convex-convex tip is made to be a substantially flat surface as a trapezoidal cross-sectional concavo-convex structure, the stress concentration means can be easily formed even if the stress concentration level is slightly reduced. Costs can be reduced.
  • FIG. 2B it is also possible to adopt a concavo-convex structure in which triangular prisms are arranged in parallel, whereby the convex tip of the concavo-convex structure becomes linear, and the stress concentration degree is increased. This can enhance the effect of breaking the oxide film.
  • FIG. 2 (c) it is possible to adopt a concavo-convex structure in which square pyramids are juxtaposed in the vertical and horizontal directions. Thus, the breaking performance of the oxide film can be improved.
  • the shape of the fine unevenness 2r is not particularly limited as long as it has a function of concentrating stress and promoting the destruction of the oxide film as described above.
  • the tip of the convex part such as a hemisphere can be curved. Needless to say, the smaller the radius of curvature of the curved surface, the more the stress concentration becomes more prominent, and the oxide film is easily broken.
  • Such fine irregularities 2r can be formed by, for example, cutting, grinding, plastic processing (roller processing), laser processing, electric discharge processing, etching processing, lithography, etc., and the formation method is particularly limited. It is not something. Of these processing methods, plastic processing enables formation at a very low cost.
  • the dimensions and shape of the fine irregularities are an aspect ratio (height / width): 0.001 or more, a pitch: 1 ⁇ m or more, and preferably an aspect ratio of 0.1 or more and a pitch: 10 ⁇ m or more.
  • the semiconductor chip 3 is provided with the aluminum layer 3c made of the aluminum-based metal on the joint surface side as described above, but as shown in FIG. 3, the semiconductor chip body 3 made of SiC, Si, GaN or the like.
  • An adhesion layer 3a and a barrier layer 3b can be interposed between the aluminum layer 3c and the aluminum layer 3c.
  • the barrier layer 3b has a function of preventing Al from diffusing from the aluminum layer 3c into the chip body, and Ni (nickel), Rt—Ir (platinum-iridium), or the like can be applied.
  • the adhesion layer 3a has a function of improving the adhesion between the barrier layer 3b and the chip body 3, and for example, Ti (titanium), Cr (chromium), or the like can be used.
  • the insert material 4 includes a metal that causes a eutectic reaction with Al.
  • the insert material 4 has a metal (pure zinc, zinc alloy) containing Zn (zinc) as a main component, or a eutectic reaction with Zn.
  • Alloys of the resulting metal and Zn for example, alloys containing Zn and Al as main components, alloys containing Zn and Mg (magnesium) as main components, alloys containing Zn and Cu (copper) as main components, Zn and Sn (tin) ), An alloy mainly composed of Zn and Ag (silver), an alloy mainly composed of Zn, Mg and Al, an alloy mainly composed of Zn, Cu (copper) and Al, and Zn An alloy mainly composed of Sn (tin) and Al, or a thin plate or foil of an alloy mainly composed of Zn, Ag (silver), and Al can be used.
  • the “main component” means that the total content of the metals is 80% or more.
  • the semiconductor chip 3 and the wiring metal 2 are relatively pressurized, brought into close contact via the insert material 4, and heating is started while further pressing.
  • the stress at the portion where the tip of the convex portion of the fine unevenness 2r comes into contact is rapidly increased locally, and the oxide film 3f of the aluminum layer 3c is formed without increasing the applied pressure so much. It is mechanically destroyed and the new surface is exposed.
  • the oxide film 2f at the tip of the fine irregularities 2r is also destroyed, and the new surface of the wiring metal 2 is exposed.
  • the eutectic reaction melt is discharged from the bonding interface, and most of the fragments of the oxide films 3f and 2f dispersed in the liquid phase are eutectic. It is extruded from the bonding interface together with the melt, exposing a new surface of the aluminum-based metal, and causing Al diffusion reaction at the bonding interface.
  • FIG. 1E the bonding between the wiring metal 2 and the aluminum layer 3c of the semiconductor chip 3, that is, the direct bonding between the aluminum-based metals is achieved.
  • a small amount of a mixture containing eutectic reaction products, oxide films, metals derived from insert materials, etc. may remain at the bonding interface, but as long as a direct bonding portion between aluminum-based metals is formed. It will not be a problem on strength. Moreover, such a residue contributes to electric conduction and heat conduction.
  • the present invention is not limited to this, and the formation position of the fine unevenness is formed in at least one of the joining parts.
  • the fine irregularities can be formed on one side or both sides of the insert material 4, which eliminates the need to add a fine irregularity forming step for the wiring metal 2 or the semiconductor chip 3. It becomes possible.
  • the form of foil It is desirable to sandwich between the two materials.
  • the wiring metal 2 is made of an aluminum-based metal.
  • a method such as plating, sputtering, or thermal spraying can be applied. Needless to say, these methods are also applied to the formation of the aluminum layer 2 c on the semiconductor chip 3.
  • the above-described joining of the wiring metal 2 and the semiconductor chip 3 in the manufacturing method of the present invention can be performed in an inert gas atmosphere, but can be performed without any trouble even in the air.
  • it is possible to carry out in vacuum but not only vacuum equipment is required, but also the vacuum gauge and gate valve may be damaged by melting of the insert material. Therefore, it is advantageous in terms of cost.
  • means for heating or maintaining the bonding portion within a predetermined temperature range is not particularly limited.
  • high-frequency heating, infrared heating, heater heating, or the like can be used.
  • a combined method can be employed.
  • the speed is high because the interface may be oxidized and the discharge of the melt may be reduced, leading to a decrease in strength. This tendency occurs especially in the case of bonding in the atmosphere.
  • the pressurizing force at the time of joining is preferably set to 1 MPa or more and 30 MPa or less. That is, when the pressure is less than 1 MPa, the oxide film cannot be destroyed or the eutectic reaction product or the oxide film fragments can be sufficiently discharged from the joint surface. If the pressure exceeds 30 MPa, the semiconductor chip 2 may be damaged. by.
  • FIG. 4 (a) to 4 (c) are cross-sectional views showing examples of the bonding surface, particularly the wiring metal, in the manufacturing method of the present invention.
  • the semiconductor chip 3 is shown. Is provided with an aluminum layer 3c on the outermost surface of the joint, and the wiring metal 2 is entirely made of an aluminum-based metal, and has fine irregularities 2r on the joint surface, as in FIG.
  • the wiring metal 2 may be, for example, one having an aluminum layer 2c made of the above aluminum-based metal on the bonding surface of a copper substrate 2b.
  • the aluminum layer 2c can be formed by plating, sputtering, vapor deposition, or the like. According to this, the aluminum layer 2c can be disposed on the entire surface of the fine irregularities 2r formed in a relatively free shape.
  • the fine unevenness 2r can be processed. In this case, the aluminum layer is disposed on the base material in advance.
  • the selected material for example, a clad material can be used, and the range of applicable materials can be expanded.
  • the structure of the semiconductor device manufactured by the manufacturing method of the present invention is formed by bonding a semiconductor chip and a wiring metal, and the semiconductor chip includes an aluminum-based metal on the bonding surface, while the wiring metal is at least bonded.
  • the surface is provided with an aluminum-based metal, and the semiconductor chip and the aluminum-based metal of the wiring metal are directly bonded at least at a part of the bonding interface.
  • Al eutectic composition means a composition obtained by a eutectic reaction between Al and at least one metal contained in the insert material
  • Al oxide means an aluminum metal surface. This is a fragment of the oxide film generated on the surface of the insert material.
  • a semiconductor device 1 shown in FIG. 5A includes a bus bar in which a wiring metal 2 made of an aluminum-based metal is arranged on one side of an insulating ceramic substrate 12 on a cooling body (heat sink) 11.
  • the semiconductor chip 3 is bonded to the wiring metal 2 and fixed.
  • the semiconductor chip 3 is provided with an aluminum layer 3c made of an aluminum-based metal on the bonding surface thereof, and has a structure in which the aluminum-based metals are directly bonded by the method described above.
  • the semiconductor device 1 shown in FIG. 5B includes a cooling body 11 on one surface of a ceramic substrate provided with a wiring metal 2 made of an aluminum-based metal on both surfaces of an insulating ceramic substrate 12, and wiring on the other surface.
  • the metal 2 and the semiconductor chip 3 having the aluminum layer 3c on the joint surface are similarly joined.
  • the semiconductor device 1 shown in FIG. 5 (c) shows an example of a double-sided mounting type semiconductor device, whereas FIGS. 5 (a) and 5 (b) show single-sided mounting, and an aluminum layer is formed on both sides.
  • a bus bar provided with the wiring metal 2 on one side of the insulating ceramic substrate 12 is disposed together with the cooling body 11 above and below the semiconductor chip 3 provided with 3c.
  • the aluminum layer 3c provided on the upper and lower surfaces of the semiconductor chip 3 and the aluminum metal wiring metal 2 of the bus bar are directly joined by the method described above.
  • the semiconductor device 1 shown in FIG. 5 (d) is of a double-sided mounting type using a ceramic substrate provided with a wiring metal 2 made of an aluminum-based metal on both sides of an insulating ceramic substrate 12.
  • the structure is substantially the same as that shown in FIG. 5C except that a ceramic substrate is used.
  • FIG. 6A shows an example of a semiconductor device having a structure in which an element having a semiconductor chip 3 is joined on a base plate 13 on the upper surface side of a wiring metal 2 provided on both surfaces of an insulating ceramic substrate 12.
  • the same joining method can be adopted when joining the wiring metal 2 on the lower surface side of the insulating ceramic substrate 12 and the base plate 13. That is, the base plate 13 is made of an aluminum-based metal or at least a joining surface is made of an aluminum-based metal, and an insert material is interposed between them, so that fine irregularities are formed on at least a part of the joining surface of the wiring metal and the base plate, and the surface of the insert material. It can be joined by providing and causing eutectic melting.
  • Example 1 A semiconductor device using a bus bar provided with a wiring metal 2 made of high-purity aluminum having a purity of 99.99% and mounting an IGBT (insulated gate bipolar transistor) made of Si having a thickness of 170 ⁇ m on one side as a semiconductor chip 3 (See FIG. 5A).
  • IGBT insulated gate bipolar transistor
  • the outermost layer is formed in advance through an adhesion layer 3 a made of titanium having a thickness of 0.5 ⁇ m and a barrier layer 3 b made of nickel having a thickness of 1 ⁇ m.
  • An aluminum layer 3c was deposited to a thickness of 6 ⁇ m.
  • fine irregularities 2r (see FIG. 2B) having a triangular groove periodic structure with a height of 100 ⁇ m, an aspect ratio of 1.0, and a pitch of 100 ⁇ m were formed on the bonding surface of the wiring metal 2 by cutting.
  • an insert material 4 made of a Zn-3.5% Al-2.5% Mg alloy and having a thickness of 100 ⁇ m is sandwiched between the joint surfaces of the wiring metal 2 and the semiconductor chip 3, and in this state, always between the joint surfaces. Fixing was performed using a jig so that a pressure of 5 MPa was applied. And it accommodated in the brazing furnace and was hold
  • Example 2 When producing a semiconductor device mounted on one side similar to the first embodiment, the wiring metal 2 is made of a copper alloy, and after forming the fine irregularities 2r on the joint surface in the same manner as described above, the aluminum layer 2c having a thickness of 3 ⁇ m is deposited. A bus bar equipped with was used. Except for this, the wiring metal 2 and the aluminum layers 2c and 3c of the semiconductor chip 3 were joined by repeating the same operation as in the first embodiment. As a result, it was possible to obtain a mounting die-bonding structure that was similarly Pb-free, low cost, low in strength variation, excellent in high temperature strength and long-term reliability.
  • Example 3 When producing a semiconductor device mounted on one side similar to Example 1, a copper alloy is clad with high purity aluminum having a thickness of 50 ⁇ m and a purity of 99.99%, and fine irregularities 2r are formed on the copper material in the same manner as above.
  • Example 4 Using a ceramic substrate made of AlN having a thickness of 635 ⁇ m and having a wiring metal 2 made of high-purity aluminum having a thickness of 500 ⁇ m and a purity of 99.99%, fine irregularities 2r were formed on the wiring metal 2a as described above. Except for this, the same operation as in Example 1 was repeated, the wiring metal 2 and the aluminum layer 3c of the semiconductor chip 3 were joined, and a semiconductor device in which the same semiconductor chip 3 was mounted on one side on the ceramic substrate was produced. (See FIG. 5 (b)). As a result, a Pb-free, low-cost, low strength variation, high-temperature strength, and long-term reliability were successfully obtained.
  • Example 5 When manufacturing a semiconductor device mounted on one side similar to the above-described Example 4, after being formed of AlN having a thickness of 635 ⁇ m and made of a copper alloy having a thickness of 500 ⁇ m, the fine unevenness 2r is formed on the joint surface in the same manner as described above. A ceramic substrate provided with a wiring metal 2 on which an aluminum layer 2c having a thickness of 3 ⁇ m was deposited was used. Except for this, the same operation as in Example 1 was repeated to join the aluminum layer 2c of the wiring metal 2 and the aluminum layer 3c of the semiconductor chip 3 together. As a result, a Pb-free, low-cost, low strength variation, high-temperature strength, and long-term reliability were successfully obtained.
  • Example 6 A semiconductor device was produced in which the bus bar used in Example 1 above, that is, the bus bar provided with the wiring metal 2 made of aluminum metal having the same fine irregularities 2r was mounted on both sides of the semiconductor chip 3 (FIG. 5C). reference). That is, the aluminum layer 3c is vapor-deposited on the both surfaces of the semiconductor chip 3 with the same thickness through the adhesion layer 3a and the barrier layer 3b, and the above-described material is inserted into the both surfaces with the same insert material 4 on the both surfaces. Each bus bar was placed and the same operation was repeated. Thus, the aluminum layers 3c provided on both surfaces of the semiconductor chip 3 were joined to the aluminum metal wiring metal 2, respectively. As a result, a Pb-free, low-cost, low strength variation, high-temperature strength, and long-term reliability were successfully obtained.
  • Example 7 When producing a semiconductor device mounted on both sides similar to Example 6, the wiring metal 2 is made of a copper alloy, and the fine irregularities 2r similar to the above are formed on the joint surface, and then an aluminum layer 2c having a thickness of 3 ⁇ m is deposited. A bus bar similar to that in Example 2 above was used. Except for this, the same operation as in Example 6 was repeated to join the aluminum layers 3c provided on both surfaces of the semiconductor chip 3 to the aluminum layers 2c of the wiring metal 2, respectively. As a result, a Pb-free, low-cost, low strength variation, high-temperature strength, and long-term reliability were successfully obtained.
  • Example 8 When producing a semiconductor device mounted on both sides similar to that of Example 6, a copper metal is clad with an aluminum-based metal having a thickness of 50 ⁇ m and a wiring metal 2 made of a plate material in which fine irregularities 2r are similarly formed is provided on this surface.
  • the same bus bar as in Example 3 was used. Except for this, the same operation as in Example 6 was repeated to join the aluminum layers 3c provided on both surfaces of the semiconductor chip 3 to the aluminum layers 2c of the wiring metal 2, respectively. As a result, a Pb-free, low-cost, low strength variation, high-temperature strength, and long-term reliability were successfully obtained.
  • Example 9 A ceramic substrate made of AlN having a thickness of 635 ⁇ m provided with a ceramic substrate used in the above-mentioned embodiment 4 on the semiconductor chip 3, that is, a wiring metal 2 made of aluminum-based metal having a thickness of 500 ⁇ m having the same fine irregularities 2 r on the surface. was fabricated on both sides (see FIG. 5D).
  • the ceramic substrate is disposed on both sides of the semiconductor chip 3 having the adhesion layer 3a, the barrier layer 3b, and the aluminum layer 3c on both sides through the same insert material 4, and the same operation is repeated.
  • the aluminum layers 3c provided on both surfaces of the chip 3 were joined to the aluminum metal wiring metal 2, respectively.
  • a Pb-free, low-cost, low strength variation, high-temperature strength, and long-term reliability were successfully obtained.
  • Example 10 When producing a semiconductor device mounted on both sides similar to that in Example 9, the ceramic substrate used in Example 5 above, that is, made of a copper alloy having a thickness of 500 ⁇ m, is similarly formed with fine irregularities 2r on the joint surface. Then, a ceramic substrate provided with a wiring metal 2 on which an aluminum layer 2c having a thickness of 3 ⁇ m was deposited was used. Except for this, the same operation as in Example 9 was repeated, and the aluminum layers 3 c provided on both surfaces of the semiconductor chip 3 were joined to the aluminum layer 2 c of the wiring metal 2, respectively. As a result, a Pb-free, low-cost, low strength variation, high-temperature strength, and long-term reliability were successfully obtained.
  • the wiring metal 2 and the semiconductor chip 3 were brazed using Pb—Sn solder.
  • the thickness of the solder after joining was 200 micrometers.
  • the solder containing Pb (lead) since the solder containing Pb (lead) is used, it does not meet social demands from the viewpoint of environmental protection. Further, the melting point of the solder is 184 ° C., and the high temperature durability is poor. Furthermore, it was found that intermetallic compound layers and Kirkendall voids were formed at the bonding interface, and the long-term reliability was poor.
  • Comparative Example 2 When manufacturing a semiconductor device mounted on one side as shown in FIG. 5 (a), the same operation as in Comparative Example 1 was repeated except that Sn—Ag—Cu solder was used. 3 was brazed.
  • Sn—Ag—Cu solder has a melting point of 210 to 217 ° C. higher than that of Pb—Sn solder, but it has poor high-temperature durability reliability for future power modules. . Further, like the Pb—Sn solder, an intermetallic compound layer or a Kirkendall void may be generated at the interface, and the long-term reliability is poor.
  • Comparative Example 3 When producing a semiconductor device mounted on one side as shown in FIG. 5 (a), the same operation as in Comparative Example 1 was repeated, except that silver nanoparticles whose organic molecules modified the surface of the particles were used, The wiring metal 2 and the semiconductor chip 3 were joined. Bonding with silver nanoparticles may cause voids when organic molecules modified on the surface of the nanoparticles are gasified during the bonding process, and there may be variations in particle aggregation, resulting in variations in joint strength. found. In addition, since it uses Ag, which is a noble metal, and has a complicated structure that modifies organic molecules, it is expensive and unsuitable for mass production.
  • Comparative Example 4 When manufacturing a semiconductor device mounted on one side as shown in FIG. 5A, the same operation as in Comparative Example 1 was repeated except that Ag—Ge solder was used, and the wiring metal 2 and the semiconductor chip 3 Brazed. Since Ag—Ge solder contains Au, which is a noble metal, it is expensive and unsuitable for industrial applications involving mass production. Further, in the same manner as the Pb—Sn solder and Sn—Ag—Cu solder, an intermetallic compound layer is formed at the joint interface or a Kirkendall void is generated, so that long-term reliability is poor.
  • Table 1 summarizes the combinations of materials and structures in this example and comparative example.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Die Bonding (AREA)

Abstract

Selon la présente invention, un matériau de pièce rapportée (4) qui contient un métal qui forme une réaction eutectique avec de l'aluminium est inséré entre un métal à base d'aluminium (3c) disposé sur une surface de jonction d'une puce semi-conductrice (3) et un métal de câblage (2) fait d'un métal à base d'aluminium. De minuscules creux et bosses (2r) sont également formés sur la surface de jonction du métal de câblage (2). La puce semi-conductrice (3) et le métal de câblage (2) sont chauffés tout en étant appuyés l'un contre l'autre, et des films d'oxyde (3f, 2f) sur les surfaces métalliques à base d'aluminium sont rompus par les minuscules creux et bosses (2r). De la matière en fusion provenant de la réaction eutectique se produisant sur l'interface de jonction est éliminée au même titre que les films d'oxyde, et le métal à base d'aluminium de la puce semi-conductrice (3) et le métal de câblage (2) sont directement joints l'un à l'autre.
PCT/JP2013/054323 2012-02-28 2013-02-21 Procédé de fabrication d'un dispositif semi-conducteur WO2013129229A1 (fr)

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WO2015019677A1 (fr) * 2013-08-09 2015-02-12 日産自動車株式会社 Procédé de fabrication de dispositif semi-conducteur
JP2015185688A (ja) * 2014-03-24 2015-10-22 日産自動車株式会社 半導体装置及びその製造方法

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JPH07169875A (ja) * 1993-03-11 1995-07-04 Toshiba Corp 電子回路装置及びその製造方法及び回路基板及び液晶表示装置及びサーマルヘッド及びプリンタ
JPH11111761A (ja) * 1997-10-08 1999-04-23 Fujitsu Ltd 半導体チップ部品の実装体
JP2005183650A (ja) * 2003-12-19 2005-07-07 Hitachi Ltd 半導体装置およびその製造方法
JP2011124015A (ja) * 2009-12-08 2011-06-23 Mitsubishi Electric Corp 金属部材の接合方法、金属部材および電力用半導体装置

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Publication number Priority date Publication date Assignee Title
JPH07169875A (ja) * 1993-03-11 1995-07-04 Toshiba Corp 電子回路装置及びその製造方法及び回路基板及び液晶表示装置及びサーマルヘッド及びプリンタ
JPH11111761A (ja) * 1997-10-08 1999-04-23 Fujitsu Ltd 半導体チップ部品の実装体
JP2005183650A (ja) * 2003-12-19 2005-07-07 Hitachi Ltd 半導体装置およびその製造方法
JP2011124015A (ja) * 2009-12-08 2011-06-23 Mitsubishi Electric Corp 金属部材の接合方法、金属部材および電力用半導体装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015019677A1 (fr) * 2013-08-09 2015-02-12 日産自動車株式会社 Procédé de fabrication de dispositif semi-conducteur
JP2015185688A (ja) * 2014-03-24 2015-10-22 日産自動車株式会社 半導体装置及びその製造方法

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