WO2015014066A1 - 显示面板及其封装方法、液晶显示器件 - Google Patents

显示面板及其封装方法、液晶显示器件 Download PDF

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Publication number
WO2015014066A1
WO2015014066A1 PCT/CN2013/089004 CN2013089004W WO2015014066A1 WO 2015014066 A1 WO2015014066 A1 WO 2015014066A1 CN 2013089004 W CN2013089004 W CN 2013089004W WO 2015014066 A1 WO2015014066 A1 WO 2015014066A1
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WIPO (PCT)
Prior art keywords
area
array substrate
sealant
display panel
display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2013/089004
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English (en)
French (fr)
Inventor
姜清华
秦锋
李小和
刘永
邵贤杰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Hefei BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US14/384,969 priority Critical patent/US9933664B2/en
Publication of WO2015014066A1 publication Critical patent/WO2015014066A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133388—Constructional arrangements; Manufacturing methods with constructional differences between the display region and the peripheral region
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/16—Materials and properties conductive

Definitions

  • Embodiments of the present invention relate to a display panel, a packaging method thereof, and a liquid crystal display device. Background technique
  • a gate drive circuit is usually fabricated on a TFT substrate. This eliminates the need for a gate drive chip (IC) and allows the bezel to be narrow.
  • the display frame using the gate driver chip IC is generally 5 mm or more, and the display frame of the TFT substrate driven by the GOA is generally 3 mm or less.
  • the structure of the TFT display panel using the GOA driver can be as shown in FIG. 1 , wherein the TFT substrate 1 is at the bottom layer, and a signal line driver chip IC is solder-bonded thereon, and the color film (CF) substrate 2 is at the top layer, and the middle layer is interposed.
  • a layer of liquid crystal (not shown in Figure 1).
  • the solid frame AA is an effective display area, and the TFT substrate 1 and the CF substrate 2 are bonded together by a layer of sealant 11 to prevent leakage of the internal liquid crystal, and there are two inside the frame seal 11
  • the group of GOA circuits 12, the two sets of GOA circuits 12 are symmetrically disposed on both sides of the AA area for progressive scanning of the gate lines in the display area, wherein in order to further reduce the width of the frame of the display panel, as shown in FIG. It is shown that the distance between the sealant 11 and the edge of the panel and the distance between the sealant 11 and the GOA circuit 12 are usually small.
  • the surface of the CF substrate adjacent to the liquid crystal layer has a conductive ITO film layer as a common electrode, and the common electrode and the pixel electrode on the surface of the TFT substrate form an electric field structure, thereby driving the two
  • the liquid crystal is deflected.
  • the charge of the common electrode on the CF substrate is usually transmitted by the conductive particles in the sealant.
  • the GOA circuit structure there are some connections between the gate lines and the data lines.
  • the cross-sectional view is as shown in FIG. 2, where 21 is the gate line metal, 22 is the gate insulating layer, 23 is the semiconductor layer, and 24 is the data line.
  • the layer metal, 25 is a passivation layer
  • 26 is a pixel electrode ITO layer
  • the via HI connects the pixel electrode ITO layer 26 with the data line layer metal 24
  • the via hole H2 connects the pixel electrode ITO layer 26 with the gate line layer metal 21,
  • the gate line layer metal 21 and the data line layer metal 24 can be realized. Connection. Because there are some such vias on the GON of the TN liquid crystal display panel, the sealant attached to the TFT substrate and the CF substrate must be isolated from the GOA circuit, otherwise the conductive particles in the sealant will pass through the common electrode on the CF substrate. ITO shorts all of the ITO layers in the GOA, as shown in Figure 3.
  • the embodiment of the present invention provides a display panel including an array substrate and a color filter substrate.
  • the array substrate and the color filter substrate are joined by a sealant, and the array substrate includes a display area and surrounding the display area.
  • the sealant member comprises an insulating sealant and a conductive sealant and is disposed on a peripheral region of the array substrate, and a gate drive GOA circuit is disposed in a peripheral region of the array substrate, and the gate
  • the driving GOA circuit and the conductive sealant are not located in a peripheral region on the same side of the display area.
  • the peripheral region includes a first package region adjacent to a first side of the display region and a second package region adjacent to a second side of the display region different from the first side, the gate driving GOA
  • the circuit is disposed in the first package area, and the conductive sealant is disposed in the second package area.
  • the first side and the second side of the display area abut each other.
  • the insulating sealant is formed in the first package region and/or the second package region.
  • the insulating frame seal is formed directly on the surface of the GOA circuit. In one example, the insulating sealant is formed to surround the display area, and the insulating sealant is not in contact with the display area.
  • the conductive sealant is formed on the surface of the insulating sealant in the second package region; or, in the second package region, the conductive sealant is formed in the In one example, the array substrate includes a driving chip disposed in the second package region; and the conductive sealing glue is formed between the display region and the driving chip.
  • Another embodiment of the present invention provides a liquid crystal display device including any of the display panels described above.
  • a further embodiment of the present invention provides a display panel packaging method, including:
  • the array substrate comprising a display area and a peripheral area surrounding the display area, wherein a gate driving GOA circuit is disposed in a peripheral area of the array substrate; and in the array substrate or Providing a conductive film sealant and an insulating sealant member for bonding the array substrate and the color filter substrate, wherein the sealant member is disposed to correspond to a peripheral region of the array substrate, wherein The conductive sealant electrically connects the array substrate and the color filter substrate, and is not located on the same side of the display area as the gate drive GOA circuit.
  • providing a conductive sealant and an insulating sealant member on the array substrate and/or the color filter substrate for bonding the array substrate and the color filter substrate comprises: insulating the The sealant is formed directly on the surface of the GOA circuit region.
  • the insulating sealant is formed to surround the display area, and the insulating sealant is not in contact with the display area.
  • the peripheral region of the array substrate includes a first package region adjacent to a first side of the display region and a second package region adjacent to a second side of the display region different from the first side
  • the gate driving GOA circuit is disposed in the first package region
  • the conductive sealant is disposed on the second package region
  • the providing on the array substrate and/or the color filter substrate includes conducting
  • the sealant and the insulating sealant member are used for bonding the array substrate and the color filter substrate.
  • the conductive sealant is formed on the surface of the insulating sealant in the second package region of the array substrate.
  • the array substrate includes a driving chip disposed in the second package region, in the array
  • Providing the substrate and/or the color film substrate with a conductive sealant and an insulating sealant member for bonding the array substrate and the color filter substrate comprises: forming the conductive sealant in the It shows a region between the driver chip.
  • FIG. 1 is a schematic structural view of a display panel in the prior art
  • FIG. 2 is a schematic cross-sectional view of an array substrate of a display panel in the prior art
  • FIG. 3 is a schematic view showing a short circuit of a conventional display panel
  • FIG. 4 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural view of an array substrate in which a sealant is not formed in the display panel of FIG. 4;
  • FIG. 6 is a schematic structural view of an array substrate in another display panel according to an embodiment of the present invention;
  • One of the technologies to be solved by the embodiments of the present invention is to provide a display panel, a packaging method thereof, and a liquid crystal display device, which can avoid short circuit between electrodes and realize a narrow bezel design of the display panel.
  • the display panel provided by the embodiment of the present invention includes: an array substrate 41 and a color filter substrate 42.
  • the array substrate 41 and the color filter substrate 42 are bonded by a sealant member 43.
  • the array substrate 41 includes a display area.
  • a gate driving GOA circuit 412 located outside the display area 411.
  • the sealing frame member 43 includes: an insulating sealant 431 formed on the first package area A and/or the second package area B, and formed A conductive sealant 432 for electrically connecting the array substrate 41 and the color filter substrate 42 in the second package region B.
  • the array substrate 41 is in a peripheral region other than the display region 411 and the display region 411.
  • the peripheral area includes a first package area A in which the GOA circuit 412 is disposed and a second package area in which the GOA circuit 412 is not disposed.
  • the display panel of the present invention includes an array substrate and a color filter substrate.
  • the array substrate and the color filter substrate are bonded by a sealant, wherein the array substrate includes a display area and a gate drive located outside the display area.
  • GOA circuit In the process of encapsulating the display panel, respectively, a first package region and/or a second package region shape in which a GOA circuit is disposed outside the display region The insulating frame sealant is formed, and the second package area of the GOA circuit is not disposed outside the display area to form a conductive sealant.
  • the electrodes on the color film substrate can be powered by the conductive frame glue, and the conductive frame sealant and the GOA circuit are disposed in different regions, thereby effectively avoiding the occurrence of the electrode short circuit phenomenon and significantly improving the display effect of the display panel. .
  • the display panel according to the embodiment of the present invention may include, for example, various display panels that drive liquid crystal molecules by a vertical electric field, such as a TN type display panel.
  • the TN-type display panel is taken as an example.
  • the TN-type display panel usually includes an array substrate and a color filter substrate disposed opposite to each other, and the liquid crystal layer is filled between the array substrate and the color filter substrate.
  • the surface of the array substrate adjacent to the liquid crystal layer has a pixel electrode ITO
  • the surface of the color film substrate adjacent to the liquid crystal layer has a common electrode ITO
  • the common electrode ITO and the pixel electrode ITO form an electric field structure.
  • the liquid crystal molecules between the driving electric fields are deflected.
  • the common electrode ITO on the color film substrate is electrically connected to the circuit on the array substrate through the conductive sealant.
  • an insulating sealant 431 may be formed on the surface of the area of the GOA circuit 412.
  • the insulating sealant has a width between 0.6 and 1.0 mm, which is less than the width of the GOA circuit area.
  • the insulating sealant 431 is directly formed on the surface of the GOA circuit 412 in this example, neither An additional sealant coating area is reserved outside the GOA circuit area. It is also possible to omit the above-mentioned interval of 0.2-0.4 mm, so that the width of the single-sided frame can be reduced by 0.8-1.4 mm, thereby effectively achieving narrow frame of various display panels including the frame TN type.
  • the insulating sealant 431 may also be continuously formed in the peripheral region of the periphery of the display region 411, and the insulating sealant 431 is not in contact with the display region.
  • the insulating sealant 431 region may be a box region that is equally spaced around the display region 411.
  • Such a sealant coating method can be realized by existing equipment production, so that the production difficulty of such a display panel can be reduced to some extent.
  • the display panel according to an embodiment of the present invention may be provided with at least one set of GOA circuits to implement scan driving of the pixel circuits.
  • the display panel may include only one set of GOA circuits disposed on the left or right side of the display area, thereby minimizing the frame design of the display panel while implementing pixel circuit scan driving; or
  • the display panel may include two sets of GOA circuits respectively disposed on the left and right sides of the display area, left side
  • the GOA circuit can be used to scan the gate lines of the odd rows, and the GOA circuit on the right side can be used to scan the gate lines of the even rows, so as to avoid the adjacent two rows of the GOA circuit being too dense, thereby effectively improving the display panel. quality.
  • the description is made by taking two sets of GOA circuits symmetrically disposed on the left and right sides of the display area.
  • the insulating sealant 431 when the insulating sealant 431 is continuously formed around the display region 411, the insulating sealant 431 will be formed in the second package region B.
  • a conductive sealant 432 may be formed on the surface of the insulating sealant 431 in the second package region B.
  • the conductive sealant 432 with conductive particles is directly formed on the insulating sealant 431 without conductive particles, which may cause poor conduction and the like, thereby affecting the ITO electrode on the color filter substrate. Power supply.
  • a via hole may be disposed in the second encapsulation region B under the conductive sealant 432, or a connection circuit may be additionally provided, so that the conductive sealant 432
  • the connection circuit on the array substrate is connected through a via or an additional connection circuit.
  • the display panel provided by the embodiment of the present invention may be as shown in FIG. 6 , in order to avoid the problem that the conductive sealant 432 with the conductive particles is directly formed on the insulating sealant 431 without the conductive particles.
  • the conductive sealant 432 may be formed on the outer side of the insulating sealant 431 in the second package region B.
  • a conductive seal having charged particles may be formed on the upper and lower sides of the display panel where the GOA circuit is not disposed.
  • the sealant 432 can be formed adjacent to the outer side of the insulating sealant 431, or the conductive sealant 432 can be spaced apart from the insulating sealant 431. In such a display panel, the positions of the insulating sealant 431 and the conductive sealant 432 do not overlap, so that the conductive particles can be used to supply power to the ITO electrodes on the color filter substrate without short-circuiting the GOA circuits on both sides. phenomenon.
  • the array substrate 41 further includes a driving chip 60 disposed in the second package region B.
  • a conductive sealant 432 may be formed between the display region 411 and the driving chip 60.
  • a signal line driving chip 60 is mainly soldered in a peripheral region of the display region 411 where the GOA circuit 412 is not disposed, and the driving chip 60 is mainly used for controlling gate lines or data lines. signal input.
  • the peripheral region near the side of the driving chip 60 has a plurality of designs such as fan-shaped traces, thereby having a large width, and the opposite sides thereof are generally required to satisfy the requirements of the narrow bezel. The area is limited.
  • the conductive sealant 432 with conductive particles may be formed only on the side of the driving chip 60, and the conductive sealant 432 may be located in the region between the display region 411 and the driving chip 60, and the other three sides are No conductive sealant with conductive particles was formed.
  • the energization of the ITO electrode on the color filter substrate can be performed, and the conductive particles can be used to supply power to the ITO electrode on the color filter substrate without short-circuiting on both sides of the GOA circuit, and at the same time, the maximum avoidance can be avoided.
  • the increase in the size of the display panel border further improves the quality of the display panel.
  • the liquid crystal display device provided by the embodiment of the present invention includes any of the display panels as described above, and the liquid crystal display device may be any product or component having a display function such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone or a tablet computer.
  • the display panel may include, for example, various display panels that drive liquid crystal molecules by a vertical electric field, such as a TN type display panel.
  • the TN-type display panel is taken as an example.
  • the TN-type display panel usually includes an array substrate and a color filter substrate disposed opposite to each other, and the liquid crystal layer is filled between the array substrate and the color filter substrate.
  • the surface of the array substrate adjacent to the liquid crystal layer has a pixel electrode ITO
  • the surface of the color film substrate adjacent to the liquid crystal layer has a common electrode ITO
  • the common electrode ITO and the pixel electrode ITO form an electric field structure.
  • the liquid crystal molecules between the driving electric fields are deflected.
  • the common electrode ITO on the color filter substrate is electrically connected to the circuit on the array substrate through the conductive sealant.
  • the liquid crystal display device provided by the embodiment of the present invention includes a display panel, and the display panel includes an array substrate and a color filter substrate.
  • the array substrate and the color filter substrate are bonded by a sealant, wherein the array substrate includes a display area and is located in the display area.
  • the outer gate drives the GOA circuit.
  • an insulating sealant is formed by a first package region and/or a second package region provided with a GOA circuit outside the display region, and a second package region of the GOA circuit is not disposed outside the display region.
  • Form a conductive frame sealant is formed by a first package region and/or a second package region provided with a GOA circuit outside the display region, and a second package region of the GOA circuit is not disposed outside the display region.
  • the electrodes on the color film substrate can be powered by the conductive sealant, and the conductive sealant and the GOA circuit are disposed in different regions, thereby effectively avoiding The appearance of the short circuit of the electrode significantly improves the display effect of the display panel.
  • An embodiment of the present invention provides a display panel packaging method, which is applicable to the display panel of any of the above, the method comprising:
  • the array substrate includes a display area and a gate driving GOA circuit located outside the display area.
  • the insulating encapsulation glue is formed by the first encapsulation area and/or the second encapsulation area provided with the GOA circuit outside the display area, respectively.
  • a second package area outside the display area where the GOA circuit is not disposed forms a conductive sealant.
  • the display panel may include, for example, various display panels that drive liquid crystal molecules by a vertical electric field, such as a TN type display panel.
  • the TN-type display panel is taken as an example.
  • the TN-type display panel usually includes an array substrate and a color filter substrate disposed opposite to each other, and the liquid crystal layer is filled between the array substrate and the color filter substrate.
  • the surface of the array substrate adjacent to the liquid crystal layer has a pixel electrode ITO
  • the surface of the color film substrate adjacent to the liquid crystal layer has a common electrode ITO
  • the common electrode ITO and the pixel electrode ITO form an electric field structure.
  • the liquid crystal molecules between the driving electric fields are deflected.
  • the common electrode ITO on the color filter substrate is electrically connected to the circuit on the array substrate through the conductive sealant.
  • insulating sealant in the first package region and/or the second package region of the array substrate may specifically include:
  • An insulating sealant is formed on the surface of the GOA circuit.
  • the insulating sealant has a width between 0.6 and 1.0 mm, which is less than the width of the GOA circuit area.
  • the insulating sealant 431 is directly formed in the present example.
  • the surface of the GOA circuit 412 does not require additional masking coating areas to be reserved outside of the GOA circuit area. It is also possible to omit the above-described interval of 0.2-0.4 mm, so that the width of the single-sided frame can be reduced by 0.8-1.4 mm, thereby effectively achieving narrow frame formation of various display panels including the frame TN type.
  • the insulating sealant 431 may also be continuously formed around the display area, and the insulating sealant is not in contact with the display area.
  • Such a sealant coating method can be realized by existing equipment production, so that the production difficulty of such a display panel can be reduced to some extent.
  • the array substrate of the display panel may be provided with at least one set of GOA circuits in the peripheral area to implement scan driving of the pixel circuits.
  • the display panel may include a set of GOA circuits disposed on the left or right side of the display area, so that the frame design of the display panel may be minimized while the pixel circuit scan driving is implemented, or the display panel may further include Two sets of GOA circuits on the left and right sides of the display area, the GOA circuit on the left side can be used to scan the gate lines of odd rows, and the GOA circuit on the right side can be used to scan the gate lines of even lines, thus avoiding GOA The two adjacent lines of the circuit are too dense, which effectively improves the quality of the display panel.
  • the two sets of GOA circuits are symmetrically disposed on the left and right sides of the display area as an example.
  • forming a conductive sealant for electrically connecting the array substrate and the color filter substrate to the second package region of the array substrate may include:
  • a conductive sealant is formed on the surface of the insulating sealant in the second package region of the array substrate.
  • the frame width of the display panel can be further reduced since a new sealant coating area is not added.
  • the disadvantage is that the conductive frame sealant with conductive particles is directly formed on the insulating sealant without conductive particles, which may cause poor conduction and the like, thereby affecting the power supply of the ITO electrode on the color filter substrate. .
  • a via hole may be provided for the insulating sealant in the second package region, or a connection circuit may be additionally provided, so that the conductive sealant passes through the via hole or the additionally provided connection circuit and the control circuit on the array substrate. Connected.
  • a conductive sealant may be formed on the outer side of the insulating sealant in the second package region of the array substrate.
  • Such a display panel insulating frame sealant does not overlap with the position of the conductive sealant, so that the conductive particles can be used to supply power to the ITO electrode on the color filter substrate without causing short circuit on both sides of the GOA circuit.
  • the array substrate may further include a driving chip disposed in the second package region;
  • forming a conductive sealant for electrically connecting the array substrate and the color filter substrate to the second package region of the array substrate may include: forming a conductive sealant only on the display region and the driving chip. between.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Mathematical Physics (AREA)
  • Liquid Crystal (AREA)
  • Engineering & Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)

Abstract

提供了一种显示面板及其封装方法、液晶显示器件，显示面板包括：阵列基板（41）和彩膜基板（42），阵列基板（41）和彩膜基板（42）通过封框胶构件（43）接合，阵列基板（41）包括显示区域（411）以及围绕显示区域（411）的周边区域，封框胶构件（43）包括绝缘封框胶（431）和导电封框胶（432）且设置于阵列基板（41）的周边区域，栅极驱动GOA电路（412）设置在阵列基板（41）的周边区域，且栅极驱动GOA电路（412）与导电封框胶（432）不位于显示区域（411）的同一侧的外围区域。

Description

显示面板及其封装方法、 液晶显示器件 技术领域
本发明实施例涉及显示面板及其封装方法、 液晶显示器件。 背景技术
随着 TFT-LCD ( Thin Film Transistor-Liquid Crystal Display, 薄月莫场效应 晶体管液晶显示器 )的不断发展，人们对于显示器窄边框的要求也越来越高。 为了进一步降低显示器边框的宽度， 目前业界通常将栅极驱动电路（ Gate On Array, 筒称 GOA )制作在 TFT基板上。 这样既不需要栅极驱动芯片 （ IC ) , 还可以把边框做到很窄。 使用栅极驱动芯片 IC的显示器边框一般在 5mm以 上， 而采用 GOA驱动的 TFT基板的显示器边框一般在 3mm以下。
使用 GOA驱动的 TFT显示面板的结构可以如图 1所示，其中 TFT基板 1在最底层， 其上有压焊一颗信号线驱动芯片 IC, 彩膜（ CF )基板 2在最顶 层， 中间夹杂一层液晶层（图 1中未示出） 。 实线框 AA为有效显示区域， TFT基板 1与 CF基板 2之间由一层封框胶 11将其贴合，以防止内部的液晶 发生外泄， 在封框胶 11所围区域内部有两组 GOA电路 12, 这两组 GOA电 路 12对称的设置于 AA区域的两侧，用于对显示区域内的栅线进行逐行扫描， 其中为了进一步减小显示面板的边框宽度，如图 1所示，封框胶 11与面板边 缘的距离以及封框胶 11与 GOA电路 12的距离通常很小。
对于有源矩阵驱动型显示面板而言， CF基板贴近液晶层的表面有一层导 电的 ITO薄膜层作为公共电极，该公共电极与 TFT基板表面的像素电极组成 一电场结构， 从而驱动两者之间的液晶发生偏转。 需要特别说明的是， CF 基板上的公共电极的电荷通常是通过框胶内的导电粒子将 TFT基板上的电 荷传递过去的。 然而， 在 GOA电路结构中有一些栅线与数据线间的连接， 其截面图如图 2所示， 其中 21为栅线层金属， 22为栅绝缘层， 23为半导体 层， 24为数据线层金属， 25为钝化层， 26为像素电极 ITO层， 过孔 HI将 像素电极 ITO层 26与数据线层金属 24连接，过孔 H2将像素电极 ITO层 26 与栅线层金属 21连接， 这样就可以实现栅线层金属 21与数据线层金属 24 的连接。 正因为 TN型液晶显示面板 GOA上有一些这样的过孔， 因而贴合 TFT基板与 CF基板的封框胶必须与 GOA电路隔离，不然封框胶内的导电粒 子会通过 CF基板上的公共电极 ITO将 GOA内的 ITO层全部短路在一块， 如图 3所示。 在窄边框 TN型显示面板的制作过程中， 由于封框胶与 GOA 电路之间的间距过小， 现有工艺难以将封框胶与 GOA电路完全隔离， 从而 难以避免电极短路现象的出现， 影响显示面板的显示效果， 严重制约 TN型 显示面板的窄边框设计。 发明内容
本发明实施例的提供一种显示面板， 包括阵列基板和彩膜基板， 所述阵 列基板和所述彩膜基板通过封框胶构件接合， 所述阵列基板包括显示区域以 及围绕所述显示区域的周边区域， 所述封框胶构件包括绝缘封框胶和导电封 框胶且设置于所述阵列基板的周边区域， 栅极驱动 GOA电路设置在所述阵 列基板的周边区域， 且所述栅极驱动 GOA电路与所述导电封框胶不位于所 述显示区域的同一侧的外围区域。
在一个示例中， 所述周边区域包括靠近所述显示区域的第一侧的第一封 装区域和靠近所述显示区域的不同于第一侧的第二侧的第二封装区域， 栅极 驱动 GOA电路设置在所述第一封装区域内， 所述导电封框胶设置在所述第 二封装区域。
在一个示例中， 所述显示区域的第一侧与第二侧彼此邻接。
在一个示例中， 所述绝缘封框胶形成于第一封装区域和 /或第二封装区 域。
在一个示例中， 所述绝缘封框胶形直接成于所述 GOA电路的表面上。 在一个示例中， 所述绝缘封框胶形成为围绕所述显示区域， 且所述绝缘 封框胶不与所述显示区域相接触。
在一个示例中， 在所述第二封装区域内， 所述导电封框胶形成于所述绝 缘封框胶的表面； 或， 在所述第二封装区域， 所述导电封框胶形成于所述绝 在一个示例中， 所述阵列基板包括设置于所述第二封装区域内的驱动芯 片； 且所述导电封框胶形成于所述显示区域与所述驱动芯片之间。 本发明的另一实施例提供一种液晶显示器件， 包括以上所述的任一显示 面板。
本发明的又一实施例提供一种显示面板封装方法， 包括：
提供阵列基板和彩膜基板， 所述阵列基板包括显示区域以及围绕所述显 示区域周边区域， 其中， 栅极驱动 GOA电路设置在所述阵列基板的外围区 域中； 以及在所述阵列基板或所述彩膜基板上提供包括导电封框胶和绝缘封 框胶构件用于接合所述阵列基板与所述彩膜基板， 所述封框胶构件设置为对 应所述阵列基板的周边区域， 其中所述导电封框胶将所述阵列基板和所述彩 膜基板电连接， 并且与所述栅极驱动 GOA电路不位于所述显示区域的同一 侧。
在一个示例中，在所述阵列基板和 /或所述彩膜基板上提供包括导电封框 胶和绝缘封框胶构件用于接合所述阵列基板与所述彩膜基板包括： 将所述绝 缘封框胶直接形成于所述 GOA电路区域的表面。
在一个示例中， 所述绝缘封框胶形成为围绕所述显示区域， 且所述绝缘 封框胶不与所述显示区域相接触。
在一个示例中， 所述阵列基板的周边区域包括靠近所述显示区域的第一 侧的第一封装区域和靠近所述显示区域的不同于第一侧的第二侧的第二封装 区域， 所述栅极驱动 GOA电路设置在所述第一封装区域内， 所述导电封框 胶设置在所述第二封装区域，所述在所述阵列基板和 /或所述彩膜基板上提供 包括导电封框胶和绝缘封框胶构件用于接合所述阵列基板与所述彩膜基板包 括： 在所述阵列基板的第二封装区域， 将导电封框胶形成于所述绝缘封框胶 的表面； 或， 在所述阵列基板的第二封装区域， 将导电封框胶形成于所述绝 在一个示例中，所述阵列基板包括设置于所述第二封装区域的驱动芯片， 在所述阵列基板和 /或所述彩膜基板上提供包括导电封框胶和绝缘封框胶构 件用于接合所述阵列基板与所述彩膜基板包括： 将所述导电封框胶形成于所 述显示区域与所述驱动芯片之间。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例或现有技 术描述中所需要使用的附图作筒单地介绍， 显而易见地， 下面描述中的附图 仅仅涉及本发明的一些实施例， 并非对本发明的限制。
图 1为现有技术中一种显示面板的结构示意图；
图 2为现有技术中一种显示面板的阵列基板的截面结构示意图； 图 3为现有的显示面板发生短路情况的示意图；
图 4为本发明实施例提供的一种显示面板的结构示意图；
图 5为图 4的显示面板中的未形成有封框胶的阵列基板的结构示意图； 图 6为本发明实施例提供的另一显示面板中的阵列基板的结构示意图； 图 7为本发明实施例提供的又一显示面板中的阵列基板的结构示意图。 具体实施方式
下面将结合本发明实施例中的附图， 对本发明实施例中的技术方案进行 清楚、 完整地描述， 显然， 所描述的实施例仅仅是本发明一部分实施例， 而 不是全部的实施例。 基于本发明中的实施例， 本领域普通技术人员所获得的 所有其他实施例， 都属于本发明保护的范围。
本发明的实施例要解决的技术之一是提供一种显示面板及其封装方法、 液晶显示器件， 能够避免电极之间发生短路， 实现显示面板的窄边框设计。
本发明实施例提供的显示面板，如图 4所示， 包括： 阵列基板 41和彩膜 基板 42, 该阵列基板 41和彩膜基板 42通过封框胶构件 43粘合， 阵列基板 41 包括显示区域 411 以及位于该显示区域 411外侧的栅极驱动 GOA电路 412, 进一步地，封框胶构件 43包括： 形成于第一封装区域 A和 /或第二封装 区域 B的绝缘封框胶 431 ,以及形成于第二封装区域 B的用于将阵列基板 41 和彩膜基板 42电连接的导电封框胶 432。
在一个示例中，如图 5所示，阵列基板 41在显示区域 411以及显示区域 411之外的周边区域。在周边区域包括其中设置有 GOA电路 412第一封装区 域 A和其中未设置有 GOA电路 412的第二封装区域
本发明实施例提供的显示面板， 该显示面板包括阵列基板和彩膜基板， 该阵列基板和彩膜基板通过封框胶粘合， 其中， 阵列基板包括显示区域以及 位于显示区域外侧的栅极驱动 GOA电路。 在封装该显示面板的过程中， 分 别通过在显示区域外设置有 GOA电路的第一封装区域和 /或第二封装区域形 成绝缘封框胶， 在显示区域外未设置 GOA电路的第二封装区域形成导电封 框胶。 这样一来， 彩膜基板上的电极可以通过导电封框胶供电， 该导电封框 胶与 GOA电路设置于不同的区域，从而可以有效避免电极短路现象的出现， 显著提高了显示面板的显示效果。
需要说明的是， 根据本发明实施例的显示面板例如可以包括 TN型显示 面板在内的各种通过竖直电场驱动液晶分子的显示面板。在本发明实施例中， 是以 TN型显示面板为例进行的说明，其中， TN型显示面板通常包括相对设 置的阵列基板和彩膜基板， 该阵列基板和彩膜基板之间填充有液晶层， 为了 驱动液晶分子发生偏转，阵列基板靠近液晶层一侧的表面具有像素电极 ITO, 彩膜基板靠近液晶层一侧的表面具有公共电极 ITO, 该公共电极 ITO与像素 电极 ITO组成一电场结构， 驱动电场之间的液晶分子发生偏转。 其中， 彩膜 基板上的公共电极 ITO通过导电封框胶与阵列基板上的电路电连接。
进一步地，在如图 4所示的显示面板中，绝缘封框胶 431可以形成于 GOA 电路 412区域的表面。
在一个示例中，绝缘封框胶的宽度在 0.6-1.0mm之间，这一宽度小于 GOA 电路区域的宽度。 相比于在第一封装区域 A中将绝缘封框胶与 GOA电路以 0.2-0.4mm的间隔并排设置的情况， 本示例中将绝缘封框胶 431直接形成于 GOA电路 412的表面， 既无需在 GOA电路区域之外再额外预留封框胶涂布 区域。 也可以省略上述 0.2-0.4mm 的间隔， 因此可以将单侧边框宽度降低 0.8- 1.4mm, 从而有效实现了边框 TN型在内的多种显示面板的窄边框化。
在一个示例中， 绝缘封框胶 431还可以连续形成于显示区域 411的四周 的周边区域内， 且绝缘封框胶 431不与显示区域相接触。 如图 4所示， 绝缘 封框胶 431区域可以是围绕显示区域 411四周等间距分布的方框区域。 这样 一种封框胶涂布方式可以通过现有的设备生产实现， 从而可以在一定程度上 降低这样一种显示面板的生产难度。
需要说明的是，根据本发明实施例的显示面板可以设置有至少一组 GOA 电路以实现像素电路的扫描驱动。 例如， 在一个示例中， 显示面板可以仅包 括一组设置于显示区域左侧或右侧的 GOA电路， 从而可以在实现像素电路 扫描驱动的同时最大限度地降低显示面板的边框设计； 或者在另一示例中， 显示面板可以包括分别设置于显示区域左侧和右侧的两组 GOA电路， 左侧 的 GOA电路可以用于扫描奇数行的栅线，右侧的 GOA电路则可以用于扫描 偶数行的栅线， 这样一来可以避免 GOA电路相邻两行过于密集， 从而有效 提高了显示面板的质量。 在本发明实施例中， 如图 4至 7所示， 均是以两组 GOA电路对称设置于显示区域左右两侧为例进行的说明。
进一步地， 如图 4所示， 当绝缘封框胶 431连续形成于显示区域 411的 四周时， 绝缘封框胶 431将会形成在第二封装区域 B内。 在此情况下， 在该 第二封装区域 B内，可以将导电封框胶 432形成于该绝缘封框胶 431的表面。 采用这样一种导电封框胶 432的结构设计， 由于并未增加新的封框胶涂布区 域用于涂布导电封框胶 432, 因此可以进一步减小显示面板的边框宽度。 但 其不足之处在于， 将带导电粒子的导电封框胶 432直接形成在没有带导电粒 子的绝缘封框胶 431之上可能出现导通不良等不良现象， 从而影响彩膜基板 上的 ITO电极的供电。
在一个示例中， 为了避免上述不良发生， 可以对第二封装区域 B内的位 于导电封框胶 432下方的绝缘封框胶 431设置过孔，或者额外设置连接电路， 从而使得导电封框胶 432通过过孔或额外设置的连接电路与阵列基板上的控 制电路相连接。
为避免将带导电粒子的导电封框胶 432直接形成在没有带导电粒子的绝 缘封框胶 431之上出现导通不良等不良现象， 本发明实施例提供的显示面板 可以如图 6所示， 其中， 在第二封装区域 B内， 可以将导电封框胶 432形成 于绝缘封框胶 431的外侧。
例如， 如图 5所示， 当在显示面板上形成完没有导电粒子的方框形状的 绝缘封框胶 431后， 可以在显示面板的未设置 GOA电路的上下两侧形成具 有带电粒子的导电封框胶 432, 该导电封框胶 432可以相邻的形成于绝缘封 框胶 431的外侧， 或者导电封框胶 432可以与绝缘封框胶 431之间具有一定 的间隔。 这样一种显示面板中， 绝缘封框胶 431与导电封框胶 432的位置不 重叠， 这样既可以通过导电粒子给彩膜基板上的 ITO电极供电， 又不会使两 侧 GOA电路出现短路的现象。
在一个示例中，如图 7所示， 阵列基板 41还包括设置于第二封装区域 B 的驱动芯片 60。 导电封框胶 432可以形成于显示区域 411与驱动芯片 60之 间。 例如在如图 7所示的显示面板中， 显示区域 411的下方未设置 GOA电 路 412的外围区域内压焊有一颗信号线驱动芯片 60, 该驱动芯片 60主要用 于控制栅线或数据线的信号输入。在一个示例中，在显示面板的阵列基板上， 靠近驱动芯片 60的一侧的周边区域具有扇形走线等诸多设计，从而具有较大 的宽度， 而其相对侧为了满足窄边框的要求， 通常区域面积有限。 在此情况 下， 可以只在驱动芯片 60—侧形成带有导电粒子的导电封框胶 432, 该导电 封框胶 432可以位于显示区域 411与驱动芯片 60之间的区域，而其余三侧均 没有形成带导电粒子的导电封框胶。 以这种方式来实现彩膜基板上的 ITO电 极的通电， 既可以通过导电粒子给彩膜基板上的 ITO 电极供电， 又不会使 GOA电路两侧出现短路的现象，同时能够最大限度地避免显示面板边框尺寸 的增加， 从而进一步提高了显示面板的质量。
本发明实施例提供的液晶显示器件， 包括如上所述的任一种显示面板， 该液晶显示器件可以为液晶显示器、 液晶电视、 数码相框、 手机或平板电脑 等任何具有显示功能的产品或者部件。
需要说明的是， 显示面板例如可以包括 TN型显示面板在内的各种通过 竖直电场驱动液晶分子的显示面板。 在本发明实施例中， 是以 TN型显示面 板为例进行的说明， 其中， TN型显示面板通常包括相对设置的阵列基板和 彩膜基板， 该阵列基板和彩膜基板之间填充有液晶层， 为了驱动液晶分子发 生偏转， 阵列基板靠近液晶层一侧的表面具有像素电极 ITO, 彩膜基板靠近 液晶层一侧的表面具有公共电极 ITO,该公共电极 ITO与像素电极 ITO组成 一电场结构， 驱动电场之间的液晶分子发生偏转。 其中， 彩膜基板上的公共 电极 ITO通过导电封框胶与阵列基板上的电路电连接。
显示面板的结构在前述实施例中已做了详细的描述， 此处不做赘述。 本发明实施例提供的液晶显示器件， 包括显示面板， 该显示面板包括阵 列基板和彩膜基板， 该阵列基板和彩膜基板通过封框胶粘合， 其中， 阵列基 板包括显示区域以及位于显示区域外侧的栅极驱动 GOA电路。 在封装该显 示面板的过程中， 分别通过在显示区域外设置有 GOA电路的第一封装区域 和 /或第二封装区域形成绝缘封框胶， 在显示区域外未设置 GOA电路的第二 封装区域形成导电封框胶。 这样一来， 彩膜基板上的电极可以通过导电封框 胶供电， 该导电封框胶与 GOA电路设置于不同的区域， 从而可以有效避免 电极短路现象的出现， 显著提高了显示面板的显示效果。
本发明实施例提供一种显示面板封装方法， 适用于如上任一所述的显示 面板， 该方法包括：
5101、 提供阵列基板和彩膜基板， 该阵列基板包括显示区域以及位于该 显示区域外侧的栅极驱动 GOA电路。
5102、 在阵列基板的第一封装区域和 /或第二封装区域形成绝缘封框胶， 该第一封装区域包括显示区域外设置有 GOA电路的至少一侧区域。
5103、 在阵列基板的第二封装区域形成用于将阵列基板和彩膜基板电连 接的导电封框胶， 该第二封装区域包括显示区域外未设置 GOA电路的区域。
S104、 利用该导电封框胶和该绝缘封框胶将彩膜基板与阵列基板粘合。 根据本发明实施例提供的显示面板封装方法， 在封装该显示面板的过程 中， 分别通过在显示区域外设置有 GOA电路的第一封装区域和 /或第二封装 区域形成绝缘封框胶， 在显示区域外未设置 GOA电路的第二封装区域形成 导电封框胶。 这样一来， 彩膜基板上的电极可以通过导电封框胶供电， 该导 电封框胶与 GOA电路设置于不同的区域， 从而可以有效避免电极短路现象 的出现， 显著提高了显示面板的显示效果。
需要说明的是， 显示面板例如可以包括 TN型显示面板在内的各种通过 竖直电场驱动液晶分子的显示面板。 在本发明实施例中， 是以 TN型显示面 板为例进行的说明， 其中， TN型显示面板通常包括相对设置的阵列基板和 彩膜基板， 该阵列基板和彩膜基板之间填充有液晶层， 为了驱动液晶分子发 生偏转， 阵列基板靠近液晶层一侧的表面具有像素电极 ITO, 彩膜基板靠近 液晶层一侧的表面具有公共电极 ITO,该公共电极 ITO与像素电极 ITO组成 一电场结构， 驱动电场之间的液晶分子发生偏转。 其中， 彩膜基板上的公共 电极 ITO通过导电封框胶与阵列基板上的电路电连接。
进一步地，在阵列基板的第一封装区域和 /或第二封装区域形成绝缘封框 胶具体可以包括：
将绝缘封框胶形成于 GOA电路的表面。
在一个示例中，绝缘封框胶的宽度在 0.6-1.0mm之间，这一宽度小于 GOA 电路区域的宽度。 相比于第一封装区域 A 中将绝缘封框胶与 GOA 电路以 0.2-0.4mm的间隔并排设置的情况， 本示例中将绝缘封框胶 431直接形成于 GOA电路 412的表面， 既无需在 GOA电路区域之外再额外预留封框胶涂布 区域。 也可以省略上述 0.2-0.4mm 的间隔， 因此可以将单侧边框宽度降低 0.8-1.4mm, 从而有效实现了边框 TN型在内的多种显示面板的窄边框化。
在一个示例中， 绝缘封框胶 431还可以连续形成于显示区域的四周， 且 绝缘封框胶不与显示区域相接触。 这样一种封框胶涂布方式可以通过现有的 设备生产实现， 从而可以在一定程度上降低这样一种显示面板的生产难度。
需要说明的是， 显示面板的阵列基板在周边区域内可以设置有至少一组 GOA电路以实现像素电路的扫描驱动。例如，显示面板可以包括一组设置于 显示区域左侧或右侧的 GOA电路， 从而可以在实现像素电路扫描驱动的同 时最大限度地降低显示面板的边框设计， 或者显示面板还可以包括分别设置 于显示区域左侧和右侧的两组 GOA电路，左侧的 GOA电路可以用于扫描奇 数行的栅线， 右侧的 GOA电路则可以用于扫描偶数行的栅线， 这样一来可 以避免 GOA电路相邻两行过于密集， 从而有效提高了显示面板的质量。 在 本发明实施例中， 均是以两组 GOA电路对称设置于显示区域左右两侧为例 进行的说明。
进一步地， 在阵列基板的第二封装区域形成用于将阵列基板和彩膜基板 电连接的导电封框胶例如可以包括：
在阵列基板的第二封装区域， 将导电封框胶形成于绝缘封框胶的表面。 采用这样一种导电封框胶的结构设计， 由于并未增加新的封框胶涂布区 域， 因此可以进一步减小显示面板的边框宽度。 但其不足之处在于， 将带导 电粒子的导电封框胶直接形成在没有带导电粒子的绝缘封框胶之上可能出现 导通不良等不良现象， 从而影响彩膜基板上的 ITO电极的供电。 为了避免上 述不良发生， 可以对第二封装区域内的绝缘封框胶设置过孔， 或者额外设置 连接电路， 从而使得导电封框胶通过过孔或额外设置的连接电路与阵列基板 上的控制电路相连接。
在一个示例中， 还可以在阵列基板的第二封装区域， 将导电封框胶形成 于所述绝缘封框胶的外侧。 这样一种显示面板绝缘封框胶与导电封框胶的位 置不重叠， 这样既可以通过导电粒子给彩膜基板上的 ITO电极供电， 又不会 使 GOA电路两侧出现短路的现象。
在一个示例中， 阵列基板还可以包括设置于第二封装区域的驱动芯片； 在此情况下， 在阵列基板的第二封装区域形成用于将阵列基板和彩膜基板电 连接的导电封框胶例如可以包括： 将导电封框胶仅形成于显示区域与所述驱 动芯片之间。这样一来，既可以通过导电粒子给彩膜基板上的 ΙΤΟ电极供电， 又不会使 GOA电路两侧出现短路的现象， 同时能够最大限度地避免显示面 板边框尺寸的增加， 从而进一步提高了显示面板的质量。
虽然上文中已经用一般性说明及具体实施方式， 对本发明作了详尽的描 述， 但在本发明基础上， 可以对之作一些修改或改进， 这对本领域技术人员 而言是显而易见的。 因此， 在不偏离本发明精神的基础上所做的这些修改或 改进， 均属于本发明要求保护的范围。

Claims

权利要求书
1、一种显示面板， 包括阵列基板和彩膜基板， 所述阵列基板和所述彩膜 基板通过封框胶构件接合， 所述阵列基板包括显示区域以及围绕所述显示区 域的周边区域， 所述封框胶构件包括绝缘封框胶和导电封框胶且设置于所述 阵列基板的周边区域，栅极驱动 GOA电路设置在所述阵列基板的周边区域， 且所述栅极驱动 GOA电路与所述导电封框胶不位于所述显示区域的同一侧 的外围区域。
2、根据权利要求 1所述的显示面板， 其中， 所述周边区域包括靠近所述 显示区域的第一侧的第一封装区域和靠近所述显示区域的不同于第一侧的第 二侧的第二封装区域， 栅极驱动 GOA电路设置在所述第一封装区域内， 所 述导电封框胶设置在所述第二封装区域。
3、根据权利要求 2所述的显示面板， 其中， 所述显示区域的第一侧与第
4、根据权利要求 2或 3所述的显示面板， 其中， 所述绝缘封框胶形成于 第一封装区域和 /或第二封装区域。
5、根据权利要求 1至 4中任一项所述的显示面板， 其中， 所述绝缘封框 胶形直接成于所述 GOA电路的表面上。
6、根据权利要求 1至 5中任一项所述的显示面板， 其中， 所述绝缘封框 胶形成为围绕所述显示区域， 且所述绝缘封框胶不与所述显示区域相接触。
7、根据权利要求 2至 6中任一项所述的显示面板， 其中， 在所述第二封 装区域内， 所述导电封框胶形成于所述绝缘封框胶的表面； 或，
在所述第二封装区域， 所述导电封框胶形成于所述绝缘封框胶的外侧。
8、根据权利要求 2至 7中任一项所述的显示面板， 其中， 所述阵列基板 包括设置于所述第二封装区域内的驱动芯片； 且所述导电封框胶形成于所述 显示区域与所述驱动芯片之间。
9、 一种液晶显示器件， 包括如权利要求 1至 8中任一所述的显示面板。
10、 一种显示面板的封装方法， 包括：
提供阵列基板和彩膜基板， 所述阵列基板包括显示区域以及围绕所述显 示区域周边区域， 其中， 栅极驱动 GOA电路设置在所述阵列基板的外围区 域中； 以及
在所述阵列基板或所述彩膜基板上提供包括导电封框胶和绝缘封框胶构 件用于接合所述阵列基板与所述彩膜基板， 所述封框胶构件设置为对应所述 阵列基板的周边区域， 其中所述导电封框胶将所述阵列基板和所述彩膜基板 电连接， 并且与所述栅极驱动 GOA电路不位于所述显示区域的同一侧。
11、根据权利要求 10所述的显示面板封装方法， 其中，在所述阵列基板 和 /或所述彩膜基板上提供包括导电封框胶和绝缘封框胶构件用于接合所述 阵列基板与所述彩膜基板包括：
将所述绝缘封框胶直接形成于所述 GOA电路区域的表面。
12、 根据权利要求 10或 11所述的显示面板封装方法， 其中， 所述绝缘 封框胶形成为围绕所述显示区域， 且所述绝缘封框胶不与所述显示区域相接 触。
13、 根据权利要求 10至 12中任一项所述的显示面板封装方法， 其中， 所述阵列基板的周边区域包括靠近所述显示区域的第一侧的第一封装区域和 靠近所述显示区域的不同于第一侧的第二侧的第二封装区域， 所述栅极驱动 GOA电路设置在所述第一封装区域内，所述导电封框胶设置在所述第二封装 区域，所述在所述阵列基板和 /或所述彩膜基板上提供包括导电封框胶和绝缘 封框胶构件用于接合所述阵列基板与所述彩膜基板包括：
在所述阵列基板的第二封装区域， 将导电封框胶形成于所述绝缘封框胶 的表面； 或，
在所述阵列基板的第二封装区域， 将导电封框胶形成于所述绝缘封框胶 的外侧。
14、 根据权利要求 10至 13中任一项所述的显示面板封装方法， 其中， 所述阵列基板包括设置于所述第二封装区域的驱动芯片，在所述阵列基板和 / 或所述彩膜基板上提供包括导电封框胶和绝缘封框胶构件用于接合所述阵列 基板与所述彩膜基板包括：
将所述导电封框胶形成于所述显示区域与所述驱动芯片之间。
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