Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
  • H10D12/411—Insulated-gate bipolar transistors [IGBT]
  • H10D12/441—Vertical IGBTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
  • H10D12/01—Manufacture or treatment
  • H10D12/031—Manufacture or treatment of IGBTs
  • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
  • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
  • H10D12/411—Insulated-gate bipolar transistors [IGBT]
  • H10D12/441—Vertical IGBTs
  • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
  • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
  • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
  • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
  • H10D62/126—Top-view geometrical layouts of the regions or the junctions
  • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
  • H10D62/393—Body regions of DMOS transistors or IGBTs 
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/111—Field plates
  • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
  • H10D84/131—Thyristors having built-in components

Definitions

• This invention relates to a MOS-bipolar device and, more particularly, to a Clustered Insulated Gate Bipolar Transistor (CIGBT) and a process for fabrication thereof.
• CIGBT Clustered Insulated Gate Bipolar Transistor
• IGBTs Insulated Gate Bipolar Transistors
• MOS Gated Thyristor (MGT) devices have been identified as a promising alternative to transistor based devices as they exhibit a lower forward voltage drop and improved current densities.
• the CIGBT described in International Patent Application No. WO01/18876 is a MOS gated thyristor device that exhibits a unique self-clamping feature that protects cathode cells from high anode voltages under all operating conditions.
• the self-clamping feature also enables current saturation at high gate biases and provides low switching losses, and its low on-state voltage and high voltage blocking capabilities make the CIGBT highly suitable as an alternative to the IGBT. It is an object of the present invention to provide a cathode cell structure, and method of fabricating the same, using CIGBT technology.
• a semiconductor device comprising at least one cell comprising a base region of a first conductivity type having disposed therein at least one cathode region of a first and second conductivity type, connected together through a conductive contact; a first well region of a second conductivity type; a second well region of a first conductivity type; a drift region of a second conductivity type; a anode region of a first conductivity type; and an anode contact; in which each cell is disposed within the first well region and the first well region is disposed within the second well region; wherein the device comprises an elongate trench that longitudinally intersects the second well region and the drift region and laterally intersects the base region and the first well region, wherein an insulating film is provided to substantially cover the inner surface of the trench and wherein a gate is provided on the insulating film so as to substantially fill the trench; and in which the device is configured such that during operation of the device a depletion region at a junction between the
• the trench is configured to laterally intersect the first and second wells, in which case, the trench can extend through the full thickness of the second well region into the drift region, or not, as required.
• the trench may not extend into the second well at all, but if it does, it may terminate within the second well or it may extend through the full thickness of the second well into the drift region. This is dependent on, for example, required device characteristics and processing constraints.
• a method of manufacturing a semiconductor device comprising the steps of forming the second well region within a semiconductor layer of the second conductivity type, such that the remaining semiconductor layer forms the drift region, forming the first well region within the second well region, forming the base region within the first well region, and forming the cathode region; the method further comprising forming an elongate trench such that it longitudinally intersects the second well region and the drift region, and laterally intersects the base region and first well region.
• the method further comprises the steps of forming a plurality of semiconductor devices according to claim 1 on a semiconductor substrate, the devices being arranged in one or more substantially parallel rows, and forming a plurality of elongate trenches in substantially parallel rows which run substantially perpendicular to the row or rows of semiconductor devices, such that each trench longitudinally intersects the second well region and drift region, and laterally intersects the base region and first well region of at least one semiconductor device.
• the or each trench may be configured to laterally intersect the first and second well regions of the respective semiconductor device, but preferably the or each trench does not extend through the full thickness of the second cell region.
• the method may further comprise the step of forming an insulating layer on the inner surface of the or each trench, and forming a gate configured to substantially fill the respective trench.
• each device of the or each row of devices may be configured to be operative.
• each device of alternate rows of devices may be configured to be operative, with the devices of the remaining rows being designated as dummy cells.
• the present invention extends to a semiconductor structure comprising a plurality of semiconductor devices as defined above, arranged in substantially parallel rows of devices, and including a plurality of trenches arranged in substantially parallel rows, substantially perpendicular to the rows of semiconductor devices, each trench being configured to longitudinally intersect the second well and drift regions, and laterally intersect the base, first well and second well regions, of a device on each row devices; and wherein an insulating film is provided to substantially cover the inner surface of at least one of the trenches, with a gate being formed on the insulating film so as to substantially fill the or each said trench.
• Figure 1 a is a schematic partial front cross-sectional view of a cathode structure in accordance with an exemplary embodiment of the present invention
• Figure 1 b is a schematic partial side cross-sectional view of a cathode structure, including dummy trenches, in accordance with an exemplary embodiment of the present invention
• Figure 1 c is a schematic plan view of a structure carrying a plurality of cathode cells
• Figures 2a to 2e are plan schematic views of cathode geometries in accordance with respective exemplary embodiments of the present invention.
• Figure 2f is a plan view of a structure carrying a plurality of cathode cells illustrating how they can be built together on a single substrate;
• Figure 2g is a plan view of the geometry of Figure 2a, with the connecting trenches omitted for clarity;
• Figures 3a to 3e are schematic cross sectional views illustrating the various stages in the fabrication process of a device according to an exemplary embodiment of the present invention;
• Figure 3f is a schematic plan view of a single cell of a device according to an exemplary embodiment of the invention to illustrate the configuration of a trench;
• Figure 4 illustrates the comparative doping profile of a device according to an exemplary embodiment of the present invention.
• Figure 5 illustrates a structure according to an exemplary embodiment of the present invention, illustrating the use of planar gates to connect the clusters.
• Figure 1 a shows a portion 10 of a body of semiconductor material, typically monocrystalline silicon.
• the device is an NPT (non-punch through) device fabricated from N type silicon through which diffusions are made to provide a pattern of cathode cells at the upper surface.
• PT punch through
• FS Field Stop
• the device structure comprises an N drift region 24 into which a P well 20 is diffused.
• the device further includes an N well 22 diffused into the P well 20, so as to lie within the P well both vertically and laterally, thereby leaving a P region 20a which will lie in the main current path, in use.
• the region 20b provides a channel overlaid by a MOSFET gate 140.
• gate oxide is shown as black.
• each cell comprises a shallow P base 32 diffused into N well 22.
• a comparative doping profile for a device according to an exemplary embodiment of the invention is illustrated in Figure 4 of the drawings.
• All the diffusions are made through upper surface using, for example, a plurality of conventional lithography stages.
• the particular process used to achieve these diffusions is not critical to the invention, any known process for effecting diffusion regions may be used, and this process will, therefore, not be described further in any detail.
• the N well contains a cluster of cathode cells, each cell being of the same symmetric construction.
• the cells are formed in a single P base region 32 which is intersected by the gate structure of each cell.
• the gate structure comprises a trench 40, etched from surface 26, and extending from that surface into the P well region 20.
• the trench 40 may extend only into the N well region, or extend all the way through the thickness of the P well into the drain region 20.
• a polysilicon gate 38 is located in the trench and isolated from the adjacent silicon material by gate oxide 33.
• a P+ region 34 is selectively diffused into the P base 32, and then the N+ cathode regions 36 are diffused into the P+ region 34, the cathode regions forming a non-rectifying junction with the P+ base region 34.
• the P+ region 34 and the cathode regions 36 may be formed before the trenches 40 are formed, such that the trenches are formed so as to extend through the P+ and cathode regions 34, 36, as well as the P base region 32 and the N well 22.
• N+ regions 36 are formed within the base material 32.
• the regions 132a and 132b provide respective channels of MOSFETs, each having a source 36 and a drain at the portions 122 of the P well 20 by the gate.
• the gate controls the conduction from the cathode/source contact metallisation (140, Figure 3a) to the P well.
• the cathode contacts are provided by metallisation extending to each source region 36 and it will be noted that at the surface 26 the contacts bridge the PN junctions between the N+ regions 36 and the P base 34.
• a P+ anode region 14 is formed on the lower surface of the drift region 24, to which the anode contact 16 is made.
• dummy cells within the structure, in order to increase the spacing between the N well of a cathode cell and that of adjacent cells. This can be achieved simply by including a cell such as that shown in Figure 1 b, but which is left to float or connected to ground and, thus, non-operational. In a dummy cell, there is no n+ region. Thus a dummy cell can be connected to the cathode or not. These dummy cells can be dispersed independently within the cluster. Furthermore, some of the trenches 40a in an operational cell may be designated as "dummy trenches".
• FIG. 2a illustrates a striped design in which there is 100% contact and no dummy cells are provided along the axis, such that all cathode cells are "live" components. This is shown more clearly in Figure 2g of the drawings, in which the connecting trenches (to other cathode clusters) are omitted.
• Figure 2b illustrates the case where there is one dummy cell per active cell, wherein the black areas 300 between trenches 40 are the dummy areas.
• Figure 2c illustrates the case where there are two dummies per unit trench
• Figure 2d illustrates the case where there are three dummies per unit trench
• Figure 2e illustrates the case where there are dummies 300 located perpendicular to the trenches 40.
• the cathode clusters can be built together. Referring, for example, to Figures 1 c and 2f of the drawings, a striped configuration is illustrated in which there are a plurality of parallel "stripes" or trenches 40, between blocks 100 of cathode cells, wherein each cell is provided with a set of gate contacts (not shown) and connected thereby, via trenches 102, to the power supply. It will be appreciated that these connecting trenches do not need to be configured in the manner shown, i.e. longitudinally and/or horizontally across the device - a large number of alternative configurations is envisaged, for example, a zig-zag pattern, and the present invention is in no way intended to be limited in this regard.
• a number of trench gates can be dispersed between the clusters, depending upon the loading conditions of specific equipment used.
• FIG 2b there are wider spaces between “live” blocks, and in Figures 2c and 2d, these spaces are wider again.
• the same trench longitudinally intersects the drift and P well regions of each device, as well as laterally intersecting the base, N well and P well regions, as shown in Figure 1 b.
• planar gates can be used for connecting the cluster cells, as shown in Figure 5 of the drawings.
• the N well 22 is tied to the cathode potential through the accumulation region formed in the N well region and inverted channels in the P base region 32. With increase in the potential differences of the P well and N well junction above its built-in potential, results in the firing ON of the thyristor.
• the N well/P well (22/20) potential increases with further increase in the anode voltage.
• This increase in the potential leads to the enhancement of the P base 32/N well 22 depletion region.
• the concentration of the N well 22 is lower than that of the P base 32, the depletion region predominantly moves into the N well region.
• the depletion touches the P well/N well junction 23 and at that point the device becomes clamped.
• the self clamping feature ensures that any further increase in the anode potential is dropped only across the P well/N drift (20/24) region.
• the device turn-off performance is similar to that of the IGBT.
• the control gate is turned off, the potential across the P base/N well (32/22) increases until self-clamping occurs. Once it is clamped, the wide nature of the P well 20 enables the holes to be collected to the P base region 32, 34 effectively.
• FIG. 3a the process starts with a prepared n-type semiconductor 200 having an upper surface 201 and an opposing lower surface 202.
• the P well layer 220 is formed through the upper surface 201 of the n-type semiconductor 200 by, for example, photolithography and ion implantation, as shown in Figure 3b.
• the N well layer 222 is formed within the P well layer 220, again through the upper surface 201 of the structure by, for example, photolithography and ion implantation.
• the P base layer 232 is seen to have been formed within the N well layer 222, again through the upper surface and again by means of, for example, photolithography and ion implantation.
• the trenches 240 which will serve as gates are selectively formed by, for example, dry etching. These trenches 240 are formed so as to laterally intersect the P base layer 232, the N well layer 222 and the P well layer 220, although the trenches may terminate within the N well region 222 or extend through the P well region 220 into the drift region. The trenches also longitudinally intersect the substrate 200, the P well layer 220 and the N well layer 222, as shown in the schematic plan view of Figure 3f. In one exemplary embodiment, the P+ layer 234 and cathode layer 236 are selectively formed after the trench gates have been formed, although these layers may be formed prior to the formation of the trenches.
• the inner surfaces of the trenches 240 are covered with a gate oxide (insulating film 240, and the gate electrodes 244 are formed on the gate oxide film 242 so as to fill the trenches.
• the gate electrodes 244 may be formed of, for example, doped polysilicon by any suitable process known to a person skilled in the art such as, for example, chemical vapour deposition (CVD).
• An insulating film (not shown) is selectively formed over the trench openings and then the cathode electrode (not shown) is formed over the upper surface of the structure.
• the N+ buffer layer (not shown), if required, and the P anode layer are formed on the lower side 202 of the n-type substrate 200. It will be appreciated, however, the the buffer layer is not required in NPT technology.

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• Thyristors (AREA)
• Electrodes Of Semiconductors (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

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• 2013
  • 2013-07-23 GB GBGB1313126.3A patent/GB201313126D0/en not_active Ceased
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• 2014
  • 2014-07-02 AU AU2014294820A patent/AU2014294820B2/en active Active
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  • 2014-07-02 CA CA2918848A patent/CA2918848A1/en not_active Abandoned
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