WO2015010427A1 - 阵列基板及其制作方法和显示装置 - Google Patents

阵列基板及其制作方法和显示装置 Download PDF

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Publication number
WO2015010427A1
WO2015010427A1 PCT/CN2013/089674 CN2013089674W WO2015010427A1 WO 2015010427 A1 WO2015010427 A1 WO 2015010427A1 CN 2013089674 W CN2013089674 W CN 2013089674W WO 2015010427 A1 WO2015010427 A1 WO 2015010427A1
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Prior art keywords
oxide semiconductor
layer
metal oxide
semiconductor layer
array substrate
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PCT/CN2013/089674
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English (en)
French (fr)
Inventor
闫梁臣
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京东方科技集团股份有限公司
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Priority to US14/381,646 priority Critical patent/US9646997B2/en
Publication of WO2015010427A1 publication Critical patent/WO2015010427A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate, a method for fabricating the same, and a display device.
  • an array substrate a method for fabricating the same
  • a display device a display device.
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • LCD Thin Film Transistor-Liquid Crystal Display
  • the performance of the TFT determines the display quality of the liquid crystal display.
  • Amorphous silicon is often used as an active layer in mass production, but amorphous silicon has more defects and a lower mobility.
  • the actual carrier mobility of an amorphous silicon TFT is approximately 10 cm 2 /(V*s), but since the number of defects is too large, most of the charge attracted by the gate electrode is taken in the defect and cannot provide conductivity.
  • the equivalent carrier mobility is only less than I cm 2 /(V*s), which does not meet the needs of large-size display products.
  • the prior art uses a metal oxide semiconductor to form an active layer, but some metal oxide semiconductors have a low mobility, and some metal oxide semiconductors have a relatively high mobility, but are leaky.
  • the current is relatively large, which will affect the performance of the TFT, causing the display to not display properly.
  • the technical problem to be solved by the present invention is to provide an array substrate, a manufacturing method thereof and a display device, the active layer of the array substrate having good and stable performance and high mobility.
  • an array substrate wherein an active layer of the array substrate is composed of at least two metal oxide semiconductor layers, wherein the at least two metal oxide semiconductor layers comprise a first metal oxide semiconductor layer and a first a second metal oxide semiconductor layer, the first metal oxide semiconductor layer is formed on the gate insulating layer, and the second metal oxide semiconductor layer is formed with an etch barrier layer, the first metal oxide semiconductor layer
  • the mobility is greater than the mobility of the second metal oxide semiconductor layer, and the mobility of the first metal oxide semiconductor layer is greater than the mobility of the second metal oxide semiconductor layer.
  • the migration rate of the second bismuth metal oxysulfide semi-conductive conductor layer is 88 1100 ccmm 22 //VV**ss. .
  • Step by step, in the above-mentioned above-mentioned solution, the thickness of the first gold metal oxy-oxide hydride semi-conductive conductor layer is
  • the thickness of the second semi-gold metal oxy-oxide former semi-conductive conductor layer is 1100nnmm-5500nnmmoo
  • the first gold metal oxy-oxide hydride semi-conductive conductor layer is ⁇
  • the second bismuth metal is an oxy oxidized material semi-conductive conductor layer is IIGGZZOO. .
  • the specific array of the array substrate substrate has a body package including: on the substrate substrate of the substrate a gate electrode electrode and a gate grid line on the board;
  • a gate insulating layer on the gate-gate electrical electrode and the gate-grid line
  • the active source layer on the insulating gate layer of the gate grid
  • drain-leakage electrode electrode a source electrode electrode, and a drain electrode formed of the source-drain metal layer layer on the etching etch barrier layer layer
  • the data is based on the drain electrode, the source electrode, and a passivation layer on the data line, and the passivation layer includes a via corresponding to the drain electrode;
  • the pixel electrode being electrically connected to the drain electrode through the via hole.
  • Embodiments of the present invention also provide a display device including the array substrate as described above.
  • the embodiment of the invention further provides a method for fabricating an array substrate, comprising forming an active layer composed of at least two metal oxide semiconductor layers.
  • the at least two metal oxide semiconductor layers comprise a first metal oxide semiconductor layer and a second metal oxide semiconductor layer, the first metal oxide semiconductor layer being formed on the gate insulating layer, the second metal An etch stop layer is formed on the oxide semiconductor layer, a mobility of the first metal oxide semiconductor layer is greater than a mobility of the second metal oxide semiconductor layer, and a mobility of the first metal oxide semiconductor layer Greater than the mobility of the second metal oxide semiconductor layer.
  • the manufacturing method specifically includes:
  • the pattern of the passivation layer including a via corresponding to the drain electrode;
  • a pattern of pixel electrodes is formed on the base substrate on which the passivation layer is formed, and the pixel electrode is electrically connected to the drain electrode through the via holes.
  • the pattern of forming the active layer on the base substrate on which the gate insulating layer is formed includes:
  • the first metal oxide semiconductor layer is: ⁇
  • the second metal oxide semiconductor layer is IGZO.
  • the active layer of the array substrate is composed of at least two metal oxide semiconductor layers, wherein the at least two metal oxide semiconductor layers comprise a first metal oxide semiconductor layer and a second metal oxide semiconductor layer, first a metal oxide semiconductor layer is formed on the gate insulating layer, and an etch barrier layer is formed on the second metal oxide semiconductor layer, and a mobility of the first metal oxide semiconductor layer is greater than a mobility of the second metal oxide semiconductor layer, and It plays a role in reducing leakage current and stabilizing TFT characteristics.
  • the at least two metal oxide semiconductor layers it is finally possible to prepare an active layer which is excellent in performance, stable, and has high mobility.
  • FIG. 1 is a schematic cross-sectional view showing a gate electrode and a gate line formed on an array substrate according to an embodiment of the present invention
  • FIG. 2 is a schematic cross-sectional view showing a gate insulating layer formed on an array substrate according to an embodiment of the present invention; Forming a first metal oxide semiconductor layer and a second on the array substrate A schematic cross-sectional view of the metal oxide semiconductor layer;
  • FIG. 4 is a schematic cross-sectional view showing a pattern of an active layer formed on an array substrate according to an embodiment of the present invention
  • FIG. 5 is a schematic cross-sectional view showing a pattern of an etch stop layer formed on an array substrate according to an embodiment of the present invention
  • FIG. 6 is a cross-sectional view showing a source electrode, a drain electrode, and a data line formed on an array substrate according to an embodiment of the present invention
  • FIG. 7 is a schematic cross-sectional view showing a pattern of a passivation layer formed on an array substrate according to an embodiment of the present invention
  • FIG. 8 is a schematic cross-sectional view showing a pixel electrode formed on an array substrate according to an embodiment of the present invention.
  • Embodiments of the present invention provide an array substrate, a method of fabricating the same, and a display device capable of producing an active layer having good performance, stability, and high mobility.
  • An embodiment of the present invention provides an array substrate, wherein an active layer of the array substrate is composed of at least two metal oxide semiconductor layers, wherein at least two metal oxide semiconductor layers include a first metal oxide semiconductor layer and a first a second metal oxide semiconductor layer, the first metal oxide semiconductor layer is formed on the gate insulating layer, and the second metal oxide semiconductor layer is formed with an etch barrier layer, and the mobility of the first metal oxide semiconductor layer is greater than that of the second metal The mobility of the oxide semiconductor layer.
  • the first metal oxide semiconductor layer has a higher mobility as a carrier transport layer
  • the second metal oxide semiconductor layer has a lower mobility as a relatively high resistance layer, which can Reduce the leakage current and stabilize the characteristics of the TFT.
  • the array substrate of the present invention is not limited to being formed by using two metal oxide semiconductor layers.
  • the active layer may have a structure of three or more layers, and it is only necessary to ensure a high mobility of the metal oxide semiconductor layer on the gate insulating layer, and the metal oxide layer on which the etch barrier layer is formed has a higher Low mobility is fine.
  • two metal oxide semiconductor layers are generally used to form the active layer.
  • the mobility of the first metal oxide semiconductor layer used is greater than 30 em 2 /V*s; in order to ensure the performance of the prepared active layer Good, stable, and generally, the mobility of the second metal oxide semiconductor layer used is 8 10 cm 2 /V*S o
  • the first metal oxide semiconductor layer may have a thickness of 10 nm to 50 nm
  • the second metal oxide semiconductor layer may have a thickness of 10 nm to 50 nm.
  • the first metal oxide semiconductor layer can adopt ITZO
  • the second metal oxide semiconductor layer can adopt a mobility of ffi IGZOoIGZO of about 10 cm 2 /V*s, and the mobility of ITZO can be Up to 30 cm 2 /V*s or more, but the leakage current of ITZO is relatively large, so that ITZO is disposed as a first metal oxide semiconductor layer on the gate insulating layer, which can be used as a carrier because of its high mobility.
  • IGZO is disposed as a second metal oxide semiconductor layer under the source/drain metal layer and the etch barrier layer, and has a lower mobility as a relatively high resistance layer, thereby reducing leakage current and stabilizing the TFT The role of the feature.
  • the array substrate of the present invention may include:
  • the gate insulating layer on the gate electrode and the gate line;
  • the active layer on the gate insulating layer is the active layer on the gate insulating layer
  • the passivation layer on the drain electrode, the source electrode, and the data line, the passivation layer including a via corresponding to the drain electrode;
  • the embodiment of the invention further provides a display device comprising the array substrate according to any of the above embodiments.
  • the structure of the array substrate is the same as the above embodiment, and details are not described herein again.
  • the structure of other parts of the display device can refer to the prior art, which will not be described in detail herein.
  • the display device can be: a product or a component having any display function such as a liquid crystal panel, an electronic paper, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, or the like.
  • the embodiment of the invention further provides a method for fabricating an array substrate, comprising: forming an active layer composed of at least two metal oxide semiconductor layers,
  • the at least two metal oxide semiconductor layers comprise a first metal oxide semiconductor layer and a second metal oxide semiconductor layer, the first metal oxide semiconductor layer being formed on the gate insulating layer, the second metal An etch barrier layer is formed on the oxide semiconductor layer, and a mobility of the first metal oxide semiconductor layer is greater than a mobility of the second metal oxide semiconductor layer.
  • the first metal oxide semiconductor layer has a higher mobility as a carrier transport layer
  • the second metal oxide semiconductor layer has a lower mobility as a relatively high resistance layer, and can A method of reducing leakage current and stabilizing TFT characteristics.
  • the fabrication method of the present invention is not limited to the formation of an active layer using two metal oxide semiconductor layers, and it is also possible to form an active layer by using more than one metal oxide semiconductor layer, and it is only necessary to ensure that on the gate insulating layer.
  • a metal oxide semiconductor layer has a high mobility, and the metal oxide semiconductor layer on which the etch barrier layer is formed has a low mobility.
  • two metal oxide semiconductor layers are generally used to form the active layer.
  • the mobility of the first metal oxide semiconductor layer used is greater than 30 C m 2 /V* S; in order to ensure active preparation The layer properties are good and stable.
  • the mobility of the second metal oxide semiconductor layer used is 8-10 cm V*S o
  • the manufacturing method may include:
  • the pattern of the passivation layer including a via corresponding to the drain electrode;
  • a pattern of pixel electrodes is formed on the base substrate on which the passivation layer is formed, and the pixel electrode is electrically connected to the drain electrode through the via holes.
  • the forming the pattern of the active layer on the base substrate on which the gate insulating layer is formed comprises:
  • ITZO may be employed as the first metal oxide semiconductor layer
  • IGZO may be employed as the second metal oxide semiconductor layer.
  • the mobility of IGZO is around i0 cm 2 /V*s, and the mobility of ITZO can reach 30 em 2 /V*s or more.
  • the leakage current of the IGZO is relatively large, so that ⁇ is arranged as the first metal oxide semiconductor layer.
  • the gate insulating layer can serve as a carrier transport layer because of its high mobility;
  • IGZO is disposed as a second metal oxide semiconductor layer under the source/drain metal layer and the etch barrier layer, since it has The lower mobility can be used as a relatively high-resistance layer to reduce leakage current and stabilize TFT characteristics.
  • the method for fabricating the array substrate of the embodiment is further carried out in combination with a specific process flow.
  • the method for fabricating the array substrate of the present invention comprises the following steps: Step a, providing a substrate, forming a gate electrode composed of a gate metal layer on the substrate, and as shown in FIG. It is to be noted that a pattern including a gate electrode 2 and a gate line connected to the gate electrode 2 composed of a gate metal layer is first formed on the base substrate i by one patterning process.
  • the base substrate 1 can be Glass substrate or quartz substrate.
  • a gate metal layer may be deposited on the base substrate 1 by sputtering or thermal evaporation.
  • the material of the gate metal layer may be a metal such as Cr, W, Ti, Ta, Mo, Ai, Cu or the like and an alloy thereof, and the gate metal layer may also be composed of a plurality of metal thin films.
  • a photoresist is coated on the gate metal layer, and the photoresist is exposed by a mask to form a photoresist unretained region and a photoresist retention region, wherein the photoresist retention region Corresponding to the region where the pattern of the gate line and the gate electrode 2 is located, the photoresist unretained region corresponds to a region other than the above-mentioned pattern; the development process is performed, the photoresist in the unretained region of the photoresist is completely removed, and the photoresist remaining region The thickness of the photoresist remains unchanged; the gate metal film of the unretained region of the photoresist is completely etched away by an etching process to form a pattern of the gate line and the gate electrode 2; and the remaining photoresist is stripped.
  • Step b as shown in FIG. 2, forming a gate insulating layer 3 on the substrate substrate on which the gate electrode 2 and the gate line are formed;
  • a gate insulating layer 3 may be formed by depositing a gate insulating layer material having a thickness of 1000 A to 4000 A on the substrate of the step a by a plasma enhanced chemical vapor deposition (PECVD) method.
  • the gate insulating layer material may be an oxide or a nitride or an oxynitride
  • the gate insulating layer may be a single layer, a double layer or a multilayer structure.
  • ITZO may be first deposited as a first metal oxide semiconductor layer 4 by magnetron sputtering, thermal evaporation or other film formation method on the substrate substrate subjected to the step b, specifically, ITZO
  • the thickness may be from 10 nm to 50 nm, after which IGZO may be further deposited as the second metal oxide semiconductor layer 5, and the thickness of the IGZO may be iOnm 50 nm.
  • Step d forming a pattern of the active layer on the base substrate on which the first metal oxide semiconductor layer 4 and the second metal oxide semiconductor layer 5 are formed as shown in FIG. 4;
  • a photoresist is coated on the second metal oxide semiconductor layer 5, and the photoresist is exposed to form a photoresist unretained region and a photoresist remaining region; and then development processing is performed.
  • the photoresist in the unreserved region of the photoresist is completely removed, and the thickness of the photoresist in the photoresist remaining region remains unchanged;
  • the first metal oxide semiconductor layer in the unreserved region of the photoresist is completely etched away by an etching process and a second metal oxide semiconductor layer, forming a pattern of the active layer; stripping the photoresist retention region
  • Step e forming a pattern of the etch stop layer 6 on the base substrate on which the pattern of the active layer is formed, as shown in FIG. 5;
  • the etch barrier material is deposited on the substrate substrate subjected to the step d by magnetron sputtering, thermal evaporation or other film formation methods, wherein the etch barrier material may be an oxide or a nitride.
  • the region corresponds to the region where the pattern of the etch barrier layer 6 is located, and the photoresist unretained region corresponds to the region other than the above-mentioned pattern; while the development process is performed, the photoresist in the unreserved region of the photoresist is completely removed, and the photoresist is retained.
  • the thickness of the photoresist in the region remains unchanged; the etch barrier material of the unretained region of the photoresist is completely etched away by an etching process to form a pattern of the etch barrier layer 6; the remaining photoresist is stripped.
  • Step f as shown in FIG. 6, a pattern of a source electrode, a drain electrode and a data line composed of a source/drain metal layer 7 is formed on a base substrate on which a pattern of the etch barrier layer 6 is formed;
  • a source/drain metal layer 7 is deposited by magnetron sputtering, thermal evaporation or other film formation method on the substrate substrate subjected to the step e.
  • the material of the source/drain metal layer 7 may be a metal such as Gr, W, ⁇ ⁇ 3 ⁇ 4, ⁇ , AL Cii or the like, and the source/drain metal layer 7 may also be composed of a plurality of metal thin films.
  • a layer of photoresist is coated on the source/drain metal layer 7, and the photoresist is exposed by a mask to form a photoresist unretained region and a photoresist retention region, wherein the photoresist
  • the reserved area corresponds to the area where the pattern of the source electrode, the drain electrode and the data line is located, and the unretained area of the photoresist corresponds to the area other than the above-mentioned pattern; the development process is performed, and the photoresist in the unretained area of the photoresist is completely removed, the light is completely removed.
  • the thickness of the photoresist in the adhesive-retained area remains unchanged; the source-drain metal film in the unreserved region of the photoresist is completely etched by the etching process to form a pattern of the source electrode, the drain electrode and the data line; gum.
  • Step g as shown in FIG. , a pattern of the passivation layer 8 is formed on the substrate substrate on which the patterns of the active electrode, the drain electrode and the data line are formed;
  • a passivation layer material having a thickness of 1000A to 4500A is deposited by ffi magnetron sputtering, thermal evaporation or other film formation method on the substrate substrate subjected to the step f, wherein the passivation layer material may be an oxide or Nitride or composite structural layer.
  • the photoresist retention area corresponds to the region of the pattern of the passivation layer
  • the photoresist unretained area corresponds to the area other than the above-mentioned pattern
  • the thickness of the photoresist in the glue-retained region remains unchanged; the passivation layer material of the unretained region of the photoresist is completely etched away by an etching process to form a pattern of the passivation layer 8 including the via corresponding to the drain electrode; The remaining photoresist is stripped.
  • Step h As shown in Fig. 8, a pattern of the pixel electrode 9 is formed on the base substrate on which the passivation layer 8 is formed, and the pixel electrode 9 is connected to the drain electrode through the via hole.
  • a transparent conductive layer having a thickness of 300 A 600 A is deposited on the substrate substrate subjected to the step g by magnetron sputtering, thermal evaporation or other film forming method, wherein the transparent conductive layer may be indium tin oxide (yttrium). Materials such as oxidized radium zinc ( ⁇ ).
  • Coating a layer of photoresist on the transparent conductive layer exposing the photoresist by using a mask to form a photoresist unretained region and a photoresist retention region, wherein the photoresist retention region corresponds to In the region where the pattern of the pixel electrode 9 is located, the photoresist unretained region corresponds to a region other than the above-mentioned pattern; the development process is performed, the photoresist in the unretained region of the photoresist is completely removed, and the photoresist in the photoresist-retained region is removed. The thickness remains unchanged; the transparent conductive layer of the unretained area of the photoresist is completely etched away by an etching process to form a pattern of the pixel electrode 9; the remaining photoresist is stripped.
  • the array substrate of the embodiment shown in FIG. 8 can be obtained.
  • the technical solution of the embodiment adopts two metal oxide semiconductor layers to prepare an active layer, wherein the first metal oxide semiconductor layer
  • the carrier transport layer has a higher mobility
  • the second metal oxide semiconductor layer has a lower mobility as a relatively high-resistance layer, and functions to reduce leakage current and stabilize TFT characteristics.

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Abstract

一种阵列基板，阵列基板的有源层由至少两个金属氧化物半导体层（4，5）组成，其中，至少两个金属氧化物半导体层（4，5）包括第一金属氧化物半导体层（4）和第二金属氧化物半导体层（5），第一金属氧化物半导体层（4）形成于栅绝缘层（3）上，第二金属氧化物半导体层（5）上形成有刻蚀阻挡层（6），第一金属氧化物半导体层（4）的迀移率大于第二金属氧化物半导体层（5）的迀移率。还提供阵列基板的制作方法和显示装置。

Description

阵列基板及其制作方法和显示装置 本发明涉及显示技术领域， 特别涉及一种阵列基板及其制作方法和显示 装置 随着科技的不断进步， 用户对液晶显示设备的需求日益增加，
TFT-LCD(Thin Film Transistor-Liquid Crystal Display, 薄膜场效应晶体管液晶 显示器） 也成为了手机、 平板电脑等产品中使用的主流显示器。 此外， 随着 显示设备的普及， 用户对大尺寸显示产品的需求也越来越普遍。
TFT的性能决定了液晶显示器的显示品质。 量产中常常采用非晶硅作为 有源层， 但非晶硅具有较多的缺陷， 并且迁移率较低。 非晶硅 TFT的载流子 实际迁移率大致在 10cm2/(V*s)左右， 但由于缺陷数目太多， 栅电极所吸引的 大部分电荷被攫取在缺陷中而无法提供导电能力， 使得等效载流子迁移率仅 仅剩下不到 I cm2/(V*s)， 不能满足大尺寸显示产品的需求。
为了提高有源层的迁移率，现有技术采用金属氧化物半导体制作有源层， 但有的金属氧化物半导体的迁移率不够高， 而有的金属氧化物半导体虽然迁 移率比较高， 但是漏电流比较大， 将会影响 TFT的性能， 导致显示器不能正 常显示。 本发明要解决的技术问题是提供一种阵列基板及其制作方法和显示装 置， 该阵列基板的有源层具有良好的、 稳定的性能， 且具有高迁移率。
为解决上述技术问题， 本发明的实施例提供技术方案如下：
一方面， 提供一种阵列基板， 所述阵列基板的有源层由至少两个金属氧 化物半导体层组成， 其中， 所述至少两个金属氧化物半导体层包括第一金属 氧化物半导体层和第二金属氧化物半导体层， 所述第一金属氧化物半导体层 形成于栅绝缘层上， 所述第二金属氧化物半导体层上形成有刻蚀阻挡层， 所 述第一金属氧化物半导体层的迁移率大于所述第二金属氧化物半导体层的迁 移率， 所述第一金属氧化物半导体层的迁移率大于所述第二金属氧化物半导 体层的迁移率。 迸迸一一步步地地，， 上上述述方方案案中中，， 所所述述第第一一金金属属氧氧化化物物半半导导体体层层的的迁迁移移率率大大于于
3300ccmm2277VV**ss,, 所所述述第第二二金金属属氧氧化化物物半半导导体体层层的的迁迁移移率率为为 88 1100 ccmm22//VV**ss。。
迸迸一一步步地地，， 上上述述方方案案中中，， 所所述述第第一一金金属属氧氧化化物物半半导导体体层层的的厚厚度度为为
11 OOnnmm--SSOOnnmm,, 所所述述第第二二金金属属氧氧化化物物半半导导体体层层的的厚厚度度为为 1100nnmm--5500nnmmoo
迸迸一一步步地地，， 上上述述方方案案中中，， 所所述述第第一一金金属属氧氧化化物物半半导导体体层层为为 ΙΙΤΤΖΖΟΟ,, 所所述述第第 二二金金属属氧氧化化物物半半导导体体层层为为 IIGGZZOO。。
迸迸一一步步地地，， 上上述述方方案案中中，， 所所述述阵阵列列基基板板具具体体包包括括：： 在在所所述述衬衬底底基基板板上上的的栅栅电电极极和和栅栅线线；；
在在所所述述栅栅电电极极和和所所述述栅栅线线上上的的所所述述栅栅绝绝缘缘层层；；
在在所所述述栅栅绝绝缘缘层层上上的的所所述述有有源源层层；；
Figure imgf000003_0001
在在所所述述刻刻蚀蚀阻阻挡挡层层上上的的由由所所述述源源漏漏金金属属层层构构成成的的漏漏电电极极、、 源源电电极极和和数数据据 在所述漏电极、 所述源电极和所述数据线上的钝化层， 所述钝化层包括 对应所述漏电极的过孔；
在所述钝化层上的像素电极， 所述像素电极遥过所述过孔与所述漏电极 电连接。
本发明实施例还提供了一种显示装置， 包括如上所述的阵列基板。
本发明实施例还提供了一种阵列基板的制作方法， 包括形成由至少两个 金属氧化物半导体层组成的有源层，
其中， 所述至少两个金属氧化物半导体层包括第一金属氧化物半导体层 和第二金属氧化物半导体层， 所述第一金属氧化物半导体层形成于栅绝缘层 上， 所述第二金属氧化物半导体层上形成有刻蚀阻挡层， 所述第一金属氧化 物半导体层的迁移率大于所述第二金属氧化物半导体层的迁移率， 所述第一 金属氧化物半导体层的迁移率大于所述第二金属氧化物半导体层的迁移率。
迸一歩地， 上述方案中， 所述制作方法具体包括：
在衬底基板上形成栅电极和栅线的图案， 然后形成栅绝缘层；
在形成有所述栅绝缘层的衬底基板上形成所述有源层的图案； 在形成有所述有源层的衬底基板上形成刻蚀阻挡层的图案； 在形成有所述刻蚀阻挡层的衬底基板上形成数据线、 源电极和漏电极的 图案；
在形成有所述数据线、 所述源电极和所述漏电极的衬底基板上形成钝化 层的图案， 所述钝化层的图案包括有对应所述漏电极的过孔；
在形成有所述钝化层的衬底基板上形成像素电极的图案， 所述像素电极 通过所述过孔与所述漏电极电连接。
进一步地， 上述方案中， 所述在形成有所述栅绝缘层的衬底基板上形成 所述有源层的图案包括：
在形成有所述栅绝缘层的衬底基板上沉积所述第一金属氧化物半导体 层；
在所述第一金属氧化物半导体层上沉积所述第二金属氧化物半导体层； 在所述第二金属氧化物半导体层上涂覆光刻胶， 通过构图工艺， 形成由 所述第一金属氧化物半导体层和所述第二金属氧化物半导体层组成的有源层 的图案。
进一步地， 上述方案中， 所述第一金属氧化物半导体层为: ίΤΖΟ， 所述第 二金属氧化物半导体层为 IGZO。
本发明的实施例具有以下有益效果：
上述方案中， 阵列基板的有源层由至少两个金属氧化物半导体层组成， 其中， 至少两个金属氧化物半导体层包括第一金属氧化物半导体层和第二金 属氧化物半导体层， 第一金属氧化物半导体层形成于栅绝缘层上， 第二金属 氧化物半导体层上形成有刻蚀阻挡层， 第一金属氧化物半导体层的迁移率大 于第二金属氧化物半导体层的迁移率， 可以起到降低漏电流、 稳定 TFT特性 的作用。 这样通过至少两个金属氧化物半导体层组合， 最终可以制备性能良 好、 稳定且具有高迁移率的有源层。 图 1为本发明实施例在阵列基板上形成栅电极和栅线后的截面示意图； 图 2为本发明实施例在阵列基板上形成栅绝缘层后的截面示意图； 图 3为本发明实施例在阵列基板上形成第一金属氧化物半导体层和第二 金属氧化物半导体层后的截面示意图；
图 4为本发明实施例在阵列基板上形成有源层的图案后的截面示意图； 图 5为本发明实施例在阵列基板上形成刻蚀阻挡层的图案后的截面示意 图；
图 6为本发明实施例在阵列基板上形成源电极、 漏电极和数据线后的截 面示意图；
图 7为本发明实施例在阵列基板上形成钝化层的图案后的截面示意图； 图 8为本发明实施例在阵列基板上形成像素电极后的截面示意图。
附图标记
1 衬底基板 2 栅电极 3 栅绝缘层
4第一金属氧化物半导体层 5 第二金属氧化物半导体层
6 刻蚀阻挡层 7 源漏金属层 8 钝化层
9 像素电极 为使本发明的实施例要解决的技术问题、 技术方案和优点更加清楚， 下 面将结合附图及具体实施例进行详细描述。
本发明的实施例提供一种阵列基板及其制作方法和显示装置， 能够制备 性能良好、 稳定且具有高迁移率的有源层。
本发明实施例提供了一种阵列基板， 所述阵列基板的有源层由至少两个 金属氧化物半导体层组成， 其中， 至少两个金属氧化物半导体层包括第一金 属氧化物半导体层和第二金属氧化物半导体层， 第一金属氧化物半导体层形 成于栅绝缘层上， 第二金属氧化物半导体层上形成有刻蚀阻挡层， 第一金属 氧化物半导体层的迁移率大于第二金属氧化物半导体层的迁移率。
本发明的阵列基板中， 第一金属氧化物半导体层作为载流子传输层具有 较高的迁移率， 而第二金属氧化物半导体层作为相对高电阻层具有较低的迁 移率， 可以起到降低漏电流、 稳定 TFT特性的作用。 这样通过至少两个金属 氧化物半导体层组合， 最终可以制备性能良好、 稳定—且.具有高迁移率的有源 层
本发明的阵列基板并不局限于采用两个金属氧化物半导体层形成有源 层， 有源层还可以具有三层以上的结构， 只需要保证在栅绝缘层上的金属氧 化物半导体层具有较高的迁移率， 在其上形成刻蚀阻挡层的金属氧化物层具 有较低的迁移率即可。 在实际生产中， 为了简化生产流程和节省生产成本， 一般采用两个金属氧化物半导体层形成有源层。
迸一步地， 为了保证制备的有源层具有较高的迁移率， 一般地， 所采用 的第一金属氧化物半导体层的迁移率大于 30em2/V*s;为了保证制备的有源层 性能良好、稳定，一般地，所采用的第二金属氧化物半导体层的迁移率为 8 10 cm2/V*S o
迸一步地， 所述第一金属氧化物半导体层的厚度可以为 10nm-50nm， 所 述第二金属氧化物半导体层的厚度可以为 10nm-50nm。
具体地，本发明的阵列基板中，第一金属氧化物半导体层可以采用 ITZO, 第二金属氧化物半导体层可以采 ffi IGZOoIGZO的迁移率在 10 cm2/V*s左右， ITZO的迁移率可以达到 30 cm2/V*s以上， 但是 ITZO的漏电流比较大， 这样 将 ITZO作为第一金属氧化物半导体层布置在栅绝缘层之上， 由于其具有较 高的迁移率可以作为载流子传输层； 将 IGZO作为第二金属氧化物半导体层 布置在源漏金属层和刻蚀阻挡层之下， 由于其具有较低的迁移率可以作为相 对高电阻层， 起到降低漏电流、 稳定 TFT特性的作用。
具体地， 本发明的阵列基板可以包括：
衬底基板； 在所述栅电极和所述栅线上的所述栅绝缘层；
在所述栅绝缘层上的所述有源层；
在所述有源层上的刻蚀阻挡层；
在所述刻蚀阻挡层上的由所述源漏金属层构成的漏电极、 源电极和数据 线；
在所述漏电极、 所述源电极和所述数据线上的钝化层， 所述钝化层包括 对应所述漏电极的过孔；
在所述钝化层上的像素电极， 所述像素电极通过所述过孔与所述漏电极 电连接。 本发明实施例还提供了一种显示装置， 包括如上任一实施例所述的阵列 基板。 其中， 阵列基板的结构同上述实施例， 在此不再赘述。 另外， 显示装 置其他部分的结构可以参考现有技术， 对此本文不再详细描述。 该显示装置 可以为： 液晶面板、 电子纸、 液晶电视、 液晶显示器、 数码相框、 手机、 平 板电脑等具有任何显示功能的产品或部件。
本发明实施例还提供了一种阵列基板的制作方法， 包括： 形成由至少两 个金属氧化物半导体层组成的有源层，
其中， 所述至少两个金属氧化物半导体层包括第一金属氧化物半导体层 和第二金属氧化物半导体层， 所述第一金属氧化物半导体层形成于栅绝缘层 上， 所述第二金属氧化物半导体层上形成有刻蚀阻挡层， 所述第一金属氧化 物半导体层的迁移率大于所述第二金属氧化物半导体层的迁移率。
本发明制作的阵列基板， 第一金属氧化物半导体层作为载流子传输层具 有较高的迁移率， 而第二金属氧化物半导体层作为相对高电阻层具有较低的 迁移率， 可以起到降低漏电流、 稳定 TFT特性的作^。 这样通过至少两个金 属氧化物半导体层组合， 最终可以制备性能良好、 稳定且具有高迁移率的有 源层。
本发明的制作方法并不局限于采用两个金属氧化物半导体层形成有源 层， 还可以利 ffi≡个以上的金属氧化物半导体层形成有源层， 只需要保证在 栅绝缘层上的那一层金属氧化物半导体层具有较高的迁移率， 在其上形成刻 蚀阻挡层的那一层金属氧化物半导体层具有较低的迁移率即可。 在实际生产 中， 为了简化生产流程和节省生产成本， 一般采用两个金属氧化物半导体层 形成有源层。
迸一步地， 为了保证制备的有源层具有较高的迁移率， 一般地， 所采用 的第一金属氧化物半导体层的迁移率大于 30Cm2/V*S;为了保证制备的有源层 性能良好、稳定，一般地，所采用的第二金属氧化物半导体层的迁移率为 8-10 cm V*S o
具体地， 所述制作方法可以包括：
在衬底基板上形成栅电极和栅线的图案， 然后形成栅绝缘层；
在形成有所述栅绝缘层的衬底基板上形成所述有源层的图案； 在形成有所述有源层的衬底基板上形成刻蚀阻挡层的图案； 在形成有所述刻蚀阻挡层的衬底基板上形成数据线、 源电极和漏电极的 图案；
在形成有所述数据线、 所述源电极和所述漏电极的衬底基板上形成钝化 层的图案， 所述钝化层的图案包括有对应所述漏电极的过孔；
在形成有所述钝化层的衬底基板上形成像素电极的图案， 所述像素电极 通过所述过孔与所述漏电极电连接。
其中， 所述在形成有所述栅绝缘层的衬底基板上形成所述有源层的图案 包括：
在形成有所述栅绝缘层的衬底基板上沉积所述第一金属氧化物半导体 层；
在所述第一金属氧化物半导体层上沉积所述第二金属氧化物半导体层； 在所述第二金属氧化物半导体层上涂覆光刻胶， 通过构图工艺， 形成由 所述第一金属氧化物半导体层和所述第二金属氧化物半导体层组成的有源层 的图案。
具体地， 本发明的制作方法中， 可以采用 ITZO作为第一金属氧化物半 导体层， 可以采用 IGZO作为第二金属氧化物半导体层。 IGZO 的迁移率在 i0 cm2/V*s左右， ITZO的迁移率可以达到 30 em2/V*s以上， 但是: ίΤΖΟ的漏 电流比较大， 这样将 ΙΤΖΟ 作为第一金属氧化物半导体层布置在栅绝缘层之 上， 由于其具有较高的迁移率可以作为载流子传输层； 将 IGZO作为第二金 属氧化物半导体层布置在源漏金属层和刻蚀阻挡层之下， 由于其具有较低的 迁移率可以作为相对高电阻层， 起到降低漏电流、 稳定 TFT特性的作用。
下面结合具体的工艺流程对本实施例的阵列基板的制作方法进行进一步
如图 i〜图 8所示， 本发明的阵列基板的制作方法包括以下步骤： 歩骤 a、提供一衬底基板，在衬底基板上形成由栅金属层组成的栅电极和 如图 1所示， 首先通过一次构图工艺在衬底基板 i上形成由栅金属层组 成的包括栅电极 2和与栅电极 2连接的栅线的图案。 其中， 衬底基板 1可为 玻璃基板或石英基板。
具体地， 可以采用溅射或热蒸发的方法在衬底基板 1上沉积一层栅金属 层。 栅金属层的材料可以是 Cr、 W、 Ti、 Ta, Mo、 Ai、 Cu等金属及其合金， 栅金属层也可以是由多层金属薄膜组成。 在栅金属层上涂覆一层光刻胶， 采 用掩膜板对光刻胶迸行曝光， 使光刻胶形成光刻胶未保留区域和光刻胶保留 区域， 其中， 光刻胶保留区域对应于栅线和栅电极 2的图案所在区域， 光刻 胶未保留区域对应于上述图案以外的区域； 进行显影处理， 光刻胶未保留区 域的光刻胶被完全去除， 光刻胶保留区域的光刻胶厚度保持不变； 通过刻蚀 工艺完全刻蚀掉光刻胶未保留区域的栅金属薄膜， 形成栅线和栅电极 2的图 案； 剥离剩余的光刻胶。
步骤 b: 如图 2所示， 在形成有栅电极 2和栅线的衬底基板上形成栅绝 缘层 3;
具体地， 可以采 ^等离子体增强化学气相沉积 （PECVD) 方法， 在经过 步骤 a的衬底基板上沉积厚度为 1000 A〜4000A的栅绝缘层材料，形成栅绝缘 层 3。 其中， 栅绝缘层材料可以选用氧化物或者氮化物或者氮氧化物， 栅绝 缘层可以为单层、 双层或多层结构。
步骤 在形成有栅绝缘层 3的衬底基板上沉积第一金属氧化物半导体层 4和第二金属氧化物半导体层 5;
具体地， 如图 3所示， 可以先在经过歩骤 b的衬底基板上采用磁控溅射、 热蒸发或其它成膜方法沉积 ITZO作为第一金属氧化物半导体层 4, 具体地， ITZO的厚度可以为 10nm- 50nm,之后可以再沉积 IGZO作为第二金属氧化物 半导体层 5， IGZO的厚度可以为 iOnm 50nm。
步骤 d: 如图 4所示， 在形成有第一金属氧化物半导体层 4和第二金属 氧化物半导体层 5的衬底基板上形成有源层的图案；
具体地， 在第二金属氧化物半导体层 5上涂覆光刻胶， 对光刻胶进行曝 光， 使光刻胶形成光刻胶未保留区域和光刻胶保留区域； 之后进行显影处理， 光刻胶未保留区域的光刻胶被完全去除， 光刻胶保留区域的光刻胶厚度保持 不变； 通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的第一金属氧化物半导体 层和第二金属氧化物半导体层， 形成有源层的图案； 剥离光刻胶保留区域的 步骤 e:如图 5所示，在形成有源层的图案的衬底基板上形成刻蚀阻挡层 6的图案；
具体地， 在经过步骤 d的衬底基板上采用磁控溅射、 热蒸发或其它成膜 方法沉积刻蚀阻挡层材料， 其中， 刻蚀阻挡层材料可以选用氧化物或者氮化 物。 在刻蚀阻挡层材料上涂覆一层光刻胶， 采用掩膜板对光刻胶进行曝光， 使光刻胶形成光刻胶未保留区域和光刻胶保留区域， 其中， 光刻胶保留区域 对应于刻蚀阻挡层 6的图案所在区域， 光刻胶未保留区域对应于上述图案以 外的区域； 迸行显影处理， 光刻胶未保留区域的光刻胶被完全去除， 光刻胶 保留区域的光刻胶厚度保持不变； 通过刻蚀工艺完全刻蚀掉光刻胶未保留区 域的刻蚀阻挡层材料， 形成刻蚀阻挡层 6的图案； 剥离剩余的光刻胶。
歩骤 f: 如图 6所示， 在形成有刻蚀阻挡层 6的图案的衬底基板上形成由 源漏金属层 7构成的源电极、 漏电极和数据线的图案；
具体地， 在经过歩骤 e的衬底基板上采用磁控溅射、 热蒸发或其它成膜 方法沉积一层源漏金属层 7。 源漏金属层 7的材料可以是 Gr、 W、 Τ Τ¾、 Μο、 AL Cii等金属及其合金， 源漏金属层 7也可以是由多层金属薄膜组成。 在源漏金属层 7上涂覆一层光刻胶， 采用掩膜板对光刻胶迸行曝光， 使光刻 胶形成光刻胶未保留区域和光刻胶保留区域， 其中， 光刻胶保留区域对应于 源电极、 漏电极和数据线的图案所在区域， 光刻胶未保留区域对应于上述图 案以外的区域； 进行显影处理， 光刻胶未保留区域的光刻胶被完全去除， 光 刻胶保留区域的光刻胶厚度保持不变； 通过刻蚀工艺完全刻蚀掉光刻胶未保 留区域的源漏金属薄膜， 形成源电极、 漏电极和数据线的图案； 剥离剩余的 光刻胶。
歩骤 g: 如图 Ί所示， 在形成有源电极、 漏电极和数据线的图案的衬底 基板上形成钝化层 8的图案；
具体地， 在经过歩骤 f 的衬底基板上采 ffi磁控溅射、 热蒸发或其它成膜 方法沉积厚度为 1000A〜4500A的钝化层材料， 其中， 钝化层材料可以选用氧 化物或者氮化物或者复合结构层。 在钝化层材料上涂敷一层光刻胶； 采用掩 膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶保留区域, 其中， 光刻胶保留区域对应于钝化层的图案所在区域， 光刻胶未保留区域对 应于上述图案以外的区域； 进行显影处理， 光刻胶未保留区域的光刻胶被完 全去除， 光刻胶保留区域的光刻胶厚度保持不变； 通过刻蚀工艺完全刻蚀掉 光刻胶未保留区域的钝化层材料， 形成包括对应于漏电极的过孔的钝化层 8 的图案； 剥离剩余的光刻胶。
步骤 h: 如图 8所示， 在形成有钝化层 8的衬底基板上形成像素电极 9 的图案， 像素电极 9通过过孔与漏电极连接。
具体地， 在经过步骤 g的衬底基板上采用磁控溅射、 热蒸发或其它成膜 方法沉积厚度为 300A〜600A的透明导电层， 其中， 透明导电层可以采用氧化 铟锡 （ΙΤΟ)、 氧化镭锌 （ΙΖΟ) 等材料。 在透明导电层上涂敷一层光刻胶； 采用掩膜板对光刻胶进行曝光， 使光刻胶形成光刻胶未保留区域和光刻胶保 留区域， 其中， 光刻胶保留区域对应于像素电极 9的图案所在区域， 光刻胶 未保留区域对应于上述图案以外的区域； 进行显影处理， 光刻胶未保留区域 的光刻胶被完全去除， 光刻胶保留区域的光刻胶厚度保持不变； 通过刻蚀工 艺完全刻蚀掉光刻胶未保留区域的透明导电层， 形成像素电极 9的图案； 剥 离剩余的光刻胶。
经过上述步骤 a- h即可得到如图 8所示的本实施例的阵列基板， 本实施 例的技术方案采用两个金属氧化物半导体层制备有源层， 其中， 第一金属氧 化物半导体层作为载流子传输层具有较高的迁移率， 而第二金属氧化物半导 体层作为相对高电阻层具有较低的迁移率， 可以起到降低漏电流、 稳定 TFT 特性的作用。 这样通过至少两个金属氧化物半导体层组合， 最终可以制备性 能良好、 稳定且具有高迁移率的有源层。
以上所述是本发明的优选实施方式， 应当指出， 对于本技术领域的普通 技术人员来说， 在不脱离本发明所述原理的前提下， 还可以作出若干改进和 润饰， 这些改进和润饰也应视为本发明的保护范围。

Claims

1、 一种阵列基板， 其特征在于， 所述阵列基板的有源层由至少两个金属 氧化物半导体层组成， 其中， 所述至少两个金属氧化物半导体层包括第一金 属氧化物半导体层和第二金属氧化物半导体层， 所述第一金属氧化物半导体 层形成于栅绝缘层上， 所述第二金属氧化物半导体层上形成有刻蚀阻挡层， 所述第一金属氧化物半导体层的迁移率大于所述第二金属氧化物半导体层的 迁移率。
2、 根据权利要求 1所述的阵列基板， 其特征在于， 所述第一金属氧化物 半导体层的迁移率大于 30cm2/V*S，所述第二金属氧化物半导体层的迁移率为 8- i0 cm2/V*s。
3、 根据权利要求 2所述的阵列基板， 其特征在于， 所述第一金属氧化物 半导体层的厚度为 iOnm- 50nm， 所述第二金属氧化物半导体层的厚度为 iOnm- 50nm。
4、 根据权利要求 2所述的阵列基板， 其特征在于， 所述第一金属氧化物 半导体层为 ITZO, 所述第二金属氧化物半导体层为 IGZO。
5、 根据权利要求 1-4中任一项所述的阵列基板， 其特征在于， 所述阵列 基板具体包括：
衬底基板； 在所述栅电极和所述栅线上的所述栅绝缘层；
在所述栅绝缘层上的所述有源层；
在所述有源层上的刻蚀阻挡层；
在所述刻蚀阻挡层上的由所述源漏金属层构成的漏电极、 源电极和数据 线；
在所述漏电极、 所述源电极和所述数据线上的钝化层， 所述钝化层包括 对应所述漏电极的过孔；
在所述钝化层上的像素电极， 所述像素电极通过所述过孔与所述漏电极 电连接。
6、 一种显示装置， 其特征在于， 包括如权利要求] ί 5中任一项所述的阵 列基板。
7、 一种阵列基板的制作方法， 其特征在于， 包括形成由至少两个金属氧 化物半导体层组成的有源层，
其中， 所述至少两个金属氧化物半导体层包括第一金属氧化物半导体层 和第二金属氧化物半导体层， 所述第一金属氧化物半导体层形成于栅绝缘层 上， 所述第二金属氧化物半导体层上形成有刻蚀阻挡层， 所述第一金属氧化 物半导体层的迁移率大于所述第二金属氧化物半导体层的迁移率。
8、 根据权利要求 7所述的阵列基板的制作方法， 其特征在于， 所述制作 方法具体包括：
在衬底基板上形成栅电极和栅线的图案， 然后形成栅绝缘层；
在形成有所述栅绝缘层的衬底基板上形成所述有源层的图案，； 在形成有所述有源层的衬底基板上形成刻蚀阻挡层的图案；
在形成有所述刻蚀阻挡层的衬底基板上形成数据线、 源电极和漏电极的 图案；
在形成有所述数据线、 所述源电极和所述漏电极的衬底基板上形成钝化 层的图案， 所述钝化层的图案包括有对应所述漏电极的过孔；
在形成有所述钝化层的衬底基板上形成像素电极的图案， 所述像素电极 遥过所述过孔与所述漏电极电连接。
9、 根据权利要求 8所述的阵列基板的制作方法， 其特征在于， 所述在形 成有所述栅绝缘层的衬底基板上形成所述有源层的图案包括：
在形成有所述栅绝缘层的衬底基板上沉积所述第一金属氧化物半导体 层；
在所述第一金属氧化物半导体层上沉积所述第二金属氧化物半导体层； 在所述第二金属氧化物半导体层上涂覆光刻胶， 通过构图工艺， 形成由 所述第一金属氧化物半导体层和所述第二金属氧化物半导体层组成的有源层 的图案。
10、 根据权利要求 7-9 中任一项所述的阵列基板的制作方法， 其特征在 于， 所述第一金属氧化物半导体层为 ITZO, 所述第二金属氧化物半导体层为
〇ZDI。
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CN202957251U (zh) * 2012-12-13 2013-05-29 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板和显示装置
CN103412450A (zh) * 2013-07-26 2013-11-27 京东方科技集团股份有限公司 阵列基板及其制作方法和显示装置
CN203351574U (zh) * 2013-07-26 2013-12-18 京东方科技集团股份有限公司 阵列基板和显示装置

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