WO2014172227A1 - Parallel memories for multidimensional data access - Google Patents

Parallel memories for multidimensional data access Download PDF

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Publication number
WO2014172227A1
WO2014172227A1 PCT/US2014/033915 US2014033915W WO2014172227A1 WO 2014172227 A1 WO2014172227 A1 WO 2014172227A1 US 2014033915 W US2014033915 W US 2014033915W WO 2014172227 A1 WO2014172227 A1 WO 2014172227A1
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WO
WIPO (PCT)
Prior art keywords
data
memories
patch
multidimensional
window
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2014/033915
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English (en)
French (fr)
Inventor
Kenneth Hiroshi Eguro
Ray A. Bittner, Jr.
George E. Smith
Shawn Michael Swilley
Rehan Ahmed
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microsoft Corp
Original Assignee
Microsoft Corp
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Filing date
Publication date
Application filed by Microsoft Corp filed Critical Microsoft Corp
Priority to CN201480021493.5A priority Critical patent/CN105229696A/zh
Priority to EP14723271.4A priority patent/EP2987131A1/en
Publication of WO2014172227A1 publication Critical patent/WO2014172227A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Definitions

  • Standard image and signal processing algorithms generally process data within a sample window (e.g. a Gaussian blur). If this window "slides" neatly in raster order, producing this sample window is relatively straightforward and, to a large degree, does not become markedly more difficult as the sample window increases in size (e.g. larger radius Gaussian blurs).
  • a sample window e.g. a Gaussian blur
  • sample windows that are computed upon are generally arbitrarily-located windows within a larger search space.
  • a similar situation occurs if the analysis is data-dependent. Producing sample windows for these more advanced algorithms is a much more difficult problem.
  • One solution stores the data representing the larger search space in a buffer and uses a series of random memory accesses into that buffer to gradually construct the required sample.
  • this solution creates a bottleneck at the memory, limiting the speed of computation. This is because real memory has limited I/O capacity (i.e.
  • An alternative solution avoids the memory bottleneck by creating multiple identical copies of the larger search space using multiple buffers. In this way, parallel data items are produced within the requested window, only limited by the number of parallel buffers. This solution is amenable to a direct hardware implementation. However, having multiple copies comes at a significant resource cost, as essentially the amount of memories needed is proportional to the window size if normalized to a constant performance requirement.
  • one or more of various aspects of the subject matter described herein are directed towards distributing multidimensional data among memories such that a patch / window of the multidimensional data is able to filled in parallel data read operations.
  • the number of memories is determined based upon a product of a length of each dimension of the patch that is used in processing the multidimensional data.
  • the memories are read to fill a positioned patch of data with the multidimensional data associated with a position of the patch via a parallel read of each of the memories.
  • a distribution process is configured to determine a number of memories based upon multidimensional patch dimensions.
  • the distribution process loads the memories with data from a multidimensional array in an interleaved manner, in which the interleaving provides that any patch of data (that corresponds to the multidimensional patch dimensions) that is filled by reading the memories has each data access unit (one or more items read or written together as a unit) read from a different memory.
  • One or more aspects are directed towards loading multidimensional data into a plurality of memories, determining addresses in each of the memories based upon a position of a window, and filling a data window with a single parallel read of the plurality of memories.
  • Data corresponding to the window data is output, and the process repeated for different window positions.
  • the window data may be rotated to provide the data corresponding to the window data.
  • FIGURE 1 is a block diagram representing example components that may be used to load multidimensional data for parallel reading, including into and from field programmable gate array (FPGA) memories, according to one or more example implementations .
  • FIGS. 2A and 2B are representations of how data may be loaded into memories in an interleaved manner for subsequent parallel reading, according to one or more example implementations.
  • FIG. 3 is a representation of a window of data being filled by parallel memory reads, according to one or more example implementations.
  • FIG. 4 is a representation of a window of data being filled by parallel memory reads, in which horizontal rotation of the data is performed based upon the window position to provide a consistent return pattern, according to one or more example implementations .
  • FIG. 5 is a representation of a window of data being filled by parallel memory reads, in which horizontal and vertical rotation of the data is performed based upon the window position to provide a consistent return pattern, according to one or more example implementations .
  • FIG. 6 is a representation of how a subset of multidimensional data may be buffered, according to one or more example implementations.
  • FIG. 7 is a representation of how memories may be arranged with section-based offsets, according to one or more example implementations.
  • FIG. 8 is a representation of how two lines of a memory may be read, according to one or more example implementations.
  • FIG. 9 is a flow diagram representing example steps taken to load memories in an interleaved manner for parallel reading, according to one or more example
  • FIG. 10 is a flow diagram representing example steps taken to read patch / window data in parallel and if necessary rotate the data, according to one or more example implementations.
  • FIG. 11 is a block diagram representing an exemplary non-limiting computing system or operating environment, in the form of a gaming system, into which one or more aspects of various embodiments described herein can be implemented.
  • Various aspects of the technology described herein are generally directed towards dividing data to be processed among separate memories (comprising a "patch cache"), each memory holding a different, but interleaved, portion of the data.
  • the interleaving is based upon the data to be processed (such as image data or other real-world sampled data) being physically or time adjacent, e.g., pixels in an image are adjacent other ones.
  • the division and interleaving are based upon the dimensions of the patch (e.g., window size in two-dimensional data processing).
  • the data are arranged such that each access into the "patch cache" needs to get one and only one value from each memory within the cache. This provides fast single- cycle access and a large degree of aggregate parallel bandwidth.
  • the technology described herein provides a memory architecture that capitalizes on the natural physical spatial locality of the image or other real-world data to maintain high performance without duplication. This allows extremely high performance with little resource overhead.
  • any of the examples herein are non-limiting. For instance, benefits are readily apparent in hardware / FPGA / ASIC scenarios, however the technology may be used in other scenarios. Further, two-dimensional image data are used in some of the examples to help convey the concepts in a way that is relatively easy to understand, however image data is only one type of data, and other types of data, including in more than two dimensions, may benefit from the technology described herein. As such, the present invention is not limited to any particular embodiments, aspects, concepts, structures, functionalities or examples described herein. Rather, any of the embodiments, aspects, concepts, structures, functionalities or examples described herein are non-limiting, and the present invention may be used various ways that provide benefits and advantages in data processing and/or connected components in general.
  • FIG. 1 shows an example system in which a multidimensional array 102 of data to be processed, (e.g., two-dimensional image data) is processed by an array processing component 104.
  • the array processing component 104 is coupled to a data distributing process 106 that writes the array data into a plurality of independent (e.g., FPGA) memories 108(1) - 108(4), e.g., collectively arranged as a patch cache 110.
  • the distributing process is shown as being coded into the cache 110, but may be a separate process, and may be incorporated into the array processing component. Note that only four independent memories 108(1) - 108(4,) are shown in FIG. 1, but that any practical number may be used, and that the number depends on the dimensions of the patch.
  • the array processing component 104 is coupled to a data fetching process 112 that reads a patch of data in parallel from the patch cache 110 / independent memories 108(1) - 108(4).
  • the array processing component 104 processes each patch, and uses the processing on one or more patches to ultimately provide results 114.
  • the array processing component also may be in hardware, e.g., the patch cache.
  • the data is divided among separate memories, each holding a different, but interleaved, portion of the data.
  • the total memory is thus divided among the separate memories; e.g., if a single, serially accessed memory held the data in D space, each of the divided, parallel memories hold D / P ofthe data.
  • the dimensions of the data may be enumerated as N, N', N' ' and so forth, up to the number of data dimensions.
  • Each of the dimensions of the patch may be enumerated as P, P', P" and so forth.
  • the patch cache 110 is organized as an array of independent memories.
  • the number of independent memories (M) is the product of each of the lengths of dimensions in the patch.
  • FIG. 2A shows an arrangement to produce a 2x2 patch into a two-dimensional 4x4 space. That is, the patch has dimensions P and P' (each of length two), while the data has dimensions N and N' (each of length four).
  • the sixteen data items are alphabetically represented in FIG. 2A by letters A through P, and by the array indices (0, 0) to (3, 3).
  • Data may be written into the cache in raster order, organized by some dimension from N to N' to N" and so forth. These writes are generally low width (e.g., in FIG. 2A only one value wide), but wider data may be accepted.
  • data may come in as one-dimensional strips.
  • a system may accept small length strips; this may be expanded to full-width N length strips or even higher order multi-dimensional strips.
  • the cache 110 accepts the data and writes it in a round-robin style by dimension. For example, if data arrives in raster-order, first along dimension N, then by dimension N', and so forth, the data for each dimension is written into each of the dimensions in the patch array in turn. This proceeds in a round-robin manner among the first dimension of the patch array across the entire length of first data dimension, wrapping on the first dimension of the patch array. Subsequent data along progressively higher dimensions of the data are distributed round-robin across progressively higher dimensions of the patch array, again wrapping each dimension of the patch array. If the dimension order of the data is higher than the dimension order of the patch, the round-robin ordering restarts at the first dimension of the patch.
  • This distribution (e.g., for three dimensions) may be represented as:
  • the MemW and MemX memories are in the first row of the dimension PxP' array (along the P dimension) and the MemY and MemZ memories are in the second row of the dimension PxP' array (again, along the P dimension but this time in the next P' dimension row).
  • the first two data points A and B enter the cache and are placed into the MemW and MemX memories, respectively.
  • the third data point C enters the cache, the length of the P dimension has been exhausted, but the N dimension has not.
  • the P dimension will wrap around and the third and fourth data points C and D are placed in the MemW and MemX memories, respectively.
  • the second, third and so forth time slices across the N" dimensions wrap back to the first P dimension in the same MemW, MemX, MemW, MemX, MemY, MemZ, MemY, MemZ, MemW, MemX ... arrangement.
  • the output from each memory can be re-arranged along each dimension to a consistent orientation.
  • the top left pixel in any 2x2 patch (represented by the dashed boxes) may come from any of the four memories in the array.
  • the order does not correspond to the patch order.
  • B, C, F, G is desired as the patch data, however the order corresponding to MemW, MemX, MemY and MemZ is C, B, G and F.
  • the order is irrelevant, e.g., if the array processing component 104 is simply summing the returned values.
  • other applications expect the data to be returned in a consistent manner, e.g., top left, top right, and lower left, lower right.
  • the data 330 from the patch 332 in FIG. 3 needs no reordering.
  • the data 440 from the patch 442 in FIG. 4 needs a horizontal shift of each row to obtain the ordered data 444, namely B, C, F, G.
  • the data 550 in patch 552 in FIG. 5 needs both horizontal shifting (data 554) and vertical shifting (data 556) to get F, G, J, and K.
  • the row data in FIG. 5 needs to be accessed via an offset to account for the next vertical row, e.g., memory MemW is arranged as A (0,0), C (2, 0), I (0, 2) and K (2,2).
  • MemW is considered as having two sections that correspond to this offset, namely section 0 containing A (0,0) and C (2, 0), and section 1 containing I (0, 2) and K (2,2). This section-based offset addressing allows the patch window to be filled with the correct data when positioned at any row, as in FIG. 5.
  • Rotation may be efficiently accomplished by a series of shift registers.
  • the rotations e.g., in two dimensions
  • any patch (window) dimensions are determined according to: X Rot - X % A-wX
  • a w x and A W Y define the access window, that is, the patch dimensions, and X and Y are the starting coordinates of the patch.
  • An entire array (e.g., a full set of image data) need not be put into the cache at the same time.
  • a part (e.g., a band) of an image 660 may be written to the memories, and read back and processed.
  • the band being read is between YLOW and YHIGH, indicated by the dashed horizontal lines.
  • the patch / access window 662 needs to be able to be positioned (aligned on pixels) anywhere in the band, and is defined by A w x (patch width) and A W Y (patch height), which, for example, may be the 2x2 window in the above examples.
  • one part of the memories may be written while reading from another part. Thus, as a line is freed, it may be written while the next line is being processed.
  • the reading needs to pause when new writes are needed.
  • dual ported memory there may be times when both ports are being used for reads; if this is not the case, reads and writes can occur on the same cycle. However, this opportunity may not occur, or the writes may fall behind the reads, whereby some pausing of the reads needs to occur.
  • FIG. 7 shows each memory is divided into sections, e.g., sec 0 or sec 1, to provide the offset into the data to match the patch's vertical row position as described above.
  • the section number is calculated from the 7-coordinate in order to give the starting address for the part of the memory that contains the line being accessed.
  • FIG. 8 shows another alternative, in which instead of one item of data (e.g., pixel) being returned for a read, two pixels are returned as a unit. This may be because the pixels are eight bits wide and the memory is sixteen bits wide, for example, so two pixels are read at once.
  • the term "access unit” refers to whatever reading and writing scheme is in place, e.g., one-byte reads, two-byte reads, four-byte reads and so on. Note that the scheme in use affects the number of memories needed; for example, if the patch is 4x4 and each memory provides two pixels, then two memories across and four memories down are needed.
  • FIG. 9 is a flow diagram showing example steps for interleaving data among memories based upon a window (patch) size.
  • FIG. 9 is generally described with respect to two dimensions, and assumes that the data will fit in the memories (whether as a whole or via a band at a time as described above).
  • Step 902 obtains the patch dimensions, e.g., as part of a setup process performed by the array processing algorithm.
  • Step 904 represents allocating memories according to the patch dimensions, e.g., a 2x2 patch has four memories, a 3x3 nine, a 4x4 sixteen, and so on.
  • Step 906 selects the first dimension of data, e.g., the X-dimension starting at coordinate zero.
  • Step 908 selects the memories based upon the X- dimension, such as the first two of four memories for a 2x2 patch, the first three for a 3x3 patch, and so on.
  • Step 910 represents the interleaving of the data along the X-axis among the selected memories, e.g., alternating between them. Note that the data wraps in the selected memories as needed, as described above. This continues until the first dimension is exhausted, that is, the entire line is placed in the selected memories.
  • step 914 evaluates whether the second dimension is exhausted, e.g., the last row has been placed into the memories. If not, at step 916 the first dimension is "reset" (e.g., the X-coordinate returns to zero) and the next dimension incremented, e.g., the 7-coordinate is moved to the next line.
  • Step 908 selects the next memories, e.g., not the ones used previously. For example, with a 2x2 patch, every other row is placed into a different pair of the memories; for a 3x3 patch, every third row into a different set of three memories, and so on. In this way, every value in a window is in a different memory.
  • FIG. 10 represents reading the data, beginning at step 1002 where the window data (e.g., the starting coordinate and size) are received. Note that in a sliding window scenario, the logic of FIG. 10 may simply receive a "next position" command and move the window horizontally until it needs to move down to the next line.
  • the window data e.g., the starting coordinate and size
  • Step 1004 represents computing the address in each memory for the data points in the access window, e.g., using the address computations described above. Note that rather than the full computation, in a sliding window scenario the previous computation may be used to determine the next location in each memory because the window position and underlying memory changes regularly.
  • Step 1006 reads the memories at their respective addresses, in parallel, into a set of shift registers or the like. As described above, step 1008 performs any needed X rotation, and step 1010 any needed 7 rotation. At this time, the window is output, filled with the correct data in the correct order.
  • FIG. 11 illustrates an example of a suitable computing and networking environment / system 1100 into which computer-related examples and implementations described herein may be implemented, for example.
  • the computing and networking environment 1100 may program an FPGA with data and/or logic to perform multidimensional array processing as described herein, provide input data (e.g., capture images), receive output data, and so forth.
  • the computing and networking environment 1100 also may implement the technology described in FIGS. 1 - 10 in software, at least in part.
  • FIG. 11 is a functional block diagram of an example gaming and media system 1100 and shows functional components in more detail.
  • Console 1101 has a central processing unit (CPU) 1102, and a memory controller 1103 that facilitates processor access to various types of memory, including a flash Read Only Memory (ROM) 1104, a Random Access Memory (RAM) 1106, a hard disk drive 1108, and portable media drive 1109.
  • the CPU 1102 includes a level 1 cache 1110, and a level 2 cache 1112 to temporarily store data and hence reduce the number of memory access cycles made to the hard drive, thereby improving processing speed and throughput.
  • the CPU 1102, the memory controller 1103, and various memory devices are interconnected via one or more buses (not shown).
  • the details of the bus that is used in this implementation are not particularly relevant to understanding the subject matter of interest being discussed herein.
  • a bus may include one or more of serial and parallel buses, a memory bus, a peripheral bus, and a processor or local bus, using any of a variety of bus architectures.
  • bus architectures can include an Industry Standard Architecture (ISA) bus, a Micro Channel Architecture (MCA) bus, an Enhanced ISA (EISA) bus, a Video Electronics
  • VESA Standards Association
  • PCI Peripheral Component Interconnects
  • the CPU 1102, the memory controller 1103, the ROM 1104, and the RAM 1106 are integrated onto a common module 1114. In this
  • the ROM 1104 is configured as a flash ROM that is connected to the memory controller 1103 via a Peripheral Component Interconnect (PCI) bus or the like and a ROM bus or the like (neither of which are shown).
  • the RAM 1106 may be configured as multiple Double Data Rate Synchronous Dynamic RAM (DDR SDRAM) modules that are independently controlled by the memory controller 1103 via separate buses (not shown).
  • DDR SDRAM Double Data Rate Synchronous Dynamic RAM
  • the hard disk drive 1108 and the portable media drive 1109 are shown connected to the memory controller 1103 via the PCI bus and an AT Attachment (ATA) bus 1116.
  • ATA AT Attachment
  • dedicated data bus structures of different types can also be applied in the alternative.
  • a three-dimensional graphics processing unit 1120 and a video encoder 1122 form a video processing pipeline for high speed and high resolution (e.g., High Definition) graphics processing. Data are carried from the graphics processing unit 1120 to the video encoder 1122 via a digital video bus (not shown).
  • An audio processing unit 1124 and an audio codec (coder/decoder) 1126 form a corresponding audio processing pipeline for multi-channel audio processing of various digital audio formats. Audio data are carried between the audio processing unit 1124 and the audio codec 1126 via a communication link (not shown).
  • the video and audio processing pipelines output data to an A/V
  • (audio/video) port 1128 for transmission to a television or other display / speakers.
  • the video and audio processing components 1120, 1122, 1124, 1126 and 1128 are mounted on the module 1114.
  • FIG. 11 shows the module 1114 including a USB host controller 1130 and a network interface (NW I/F) 1132, which may include wired and/or wireless components.
  • the USB host controller 1130 is shown in communication with the CPU 1102 and the memory controller 1103 via a bus (e.g., PCI bus) and serves as host for peripheral controllers 1134.
  • the network interface 1132 provides access to a network (e.g., Internet, home network, etc.) and may be any of a wide variety of various wire or wireless interface components including an Ethernet card or interface module, a modem, a Bluetooth module, a cable modem, and the like.
  • the console 1101 includes a controller support subassembly 1140, for supporting four game controllers 1141(1) - 1141(4).
  • the controller support subassembly 1140 includes any hardware and software components needed to support wired and/or wireless operation with an external control device, such as for example, a media and game controller.
  • a front panel I/O subassembly 1142 supports the multiple functionalities of a power button 1143, an eject button 1144, as well as any other buttons and any LEDs (light emitting diodes) or other indicators exposed on the outer surface of the console 1101.
  • the subassemblies 1140 and 1142 are in communication with the module 1114 via one or more cable assemblies 1146 or the like.
  • the console 1101 can include additional controller
  • the illustrated implementation also shows an optical I/O interface 1148 that is configured to send and receive signals (e.g., from a remote control 1149) that can be communicated to the module 1114.
  • signals e.g., from a remote control 1149
  • Memory units (MUs) 1150(1) and 1150(2) are illustrated as being connectable to MU ports "A" 1152(1) and "B" 1152(2), respectively.
  • Each MU 1150 offers additional storage on which games, game parameters, and other data may be stored.
  • the other data can include one or more of a digital game component, an executable gaming application, an instruction set for expanding a gaming application, and a media file.
  • each MU 1150 can be accessed by the memory controller 1103.
  • a system power supply module 1154 provides power to the components of the gaming system 1100.
  • a fan 1156 cools the circuitry within the console 1101.
  • An application 1160 comprising machine instructions is typically stored on the hard disk drive 1108.
  • various portions of the application 1160 are loaded into the RAM 1106, and/or the caches 1110 and 1112, for execution on the CPU 1102.
  • the application 1160 can include one or more program modules for performing various display functions, such as controlling dialog screens for presentation on a display (e.g., high definition monitor), controlling transactions based on user inputs and controlling data transmission and reception between the console 1101 and externally connected devices.
  • the gaming system 1100 may be operated as a standalone system by connecting the system to high definition monitor, a television, a video projector, or other display device. In this standalone mode, the gaming system 1100 enables one or more players to play games, or enjoy digital media, e.g., by watching movies, or listening to music.
  • gaming system 1100 may further be operated as a participating component in a larger network gaming community or system.

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