Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/0008—Arrangements for reducing power consumption
  • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
  • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
  • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
  • H03K19/17748—Structural details of configuration resources
  • H03K19/1776—Structural details of configuration resources for memories

Definitions

• One embodiment of the present invention relates to semiconductor devices.
• one embodiment of the present invention relates to storage devices and semiconductor devices including the storage devices.
• Patent Document 1 discloses the structure of a memory element for retaining data in a node that becomes floating by turning off such a transistor.
• Patent Document 1 Japanese Published Patent Application No. 2011 -171702
• a high-level potential applied to a node in a memory cell of a storage device through an n-channel transistor is decreased by the threshold voltage of the transistor.
• the potential of the node in the memory cell of the storage device becomes too low, so that the logic level of a signal output from the memory cell is changed. Consequently, data reliability is likely to be decreased.
• data is written to a storage device by accumulating electric charge in a node through a first transistor.
• Supply of a first signal to a gate of the first transistor is controlled by a second transistor.
• the first transistor is turned on or off in accordance with the potential of the first signal.
• the potential of a second signal including the data is input to a logic element having low current supply capability, and a potential output from the logic element is supplied to one of a source and a drain of the first transistor.
• a potential that is higher than a potential obtained by addition of the threshold voltage of the second transistor to the second potential is supplied to a gate of the second transistor.
• the second transistor is on; thus, the potential of the first signal is supplied to the gate of the first transistor through the second transistor.
• the potential of one of the source and the drain of the first transistor is increased from the third potential to the first potential in a state where the potential is supplied to the gate of the second transistor, the second transistor is turned off; thus, the gate of the first transistor becomes floating.
• the potential of the gate of the first transistor can be increased by the above operation even when the potential of the gate of the first transistor is decreased from the potential by the threshold voltage of the second transistor. Accordingly, the first transistor can be turned on reliably. Consequently, in the storage device according to one embodiment of the present invention, data can be written to the node at high speed even when power supply voltage supplied to the storage device is decreased, and it is possible to prevent a potential supplied to the node in data writing from being decreased by the threshold voltage of the first transistor.
• a storage device includes a first transistor, a second transistor, a logic element, and a semiconductor element.
• the second transistor controls supply of a first signal to a gate of the first transistor.
• the logic element changes the potential of one of a source and a drain of the first transistor from a third potential that is lower than the second potential into the first potential after the logic element changes the potential of one of the source and the drain of the first transistor from the second potential into the third potential.
• the semiconductor element has a function of making the other of the source and the drain of the first transistor floating.
• the first transistor has lower off-state current than a transistor including a channel formation region in a silicon film or a silicon substrate.
• a transistor including a channel formation region in a film of a semiconductor having a wider band gap and lower intrinsic carrier density than silicon can have significantly lower off-state current than a transistor including a channel formation region in a normal semiconductor such as silicon or germanium.
• a transistor having a wider band gap and lower intrinsic carrier density than silicon are an oxide semiconductor, silicon carbide, and gallium nitride whose bandgap is 2 or more times that of silicon.
• the node becomes floating, i.e., has extremely high insulating properties with another electrode or a wiring when the first transistor is off.
• the potential of the signal including the data is held in the node.
• a low-power storage device in which operation speed can be maintained.
• a low-power storage device that can operate correctly.
• a low-power semiconductor device in which operation speed can be maintained.
• a low-power semiconductor device that can operate correctly.
• FIG. 1 illustrates a storage device structure
• FIGS. 2A and 2B illustrate storage device operation
• FIG. 3 is a timing chart of a storage device
• FIGS. 4A and 4B each illustrate a storage device structure
• FIG. 5 illustrates a cell array structure
• FIG. 6 is a timing chart of a cell array
• FIG. 7 illustrates a PLD structure
• FIGS. 8A to 8C each illustrate a logic block structure
• FIG. 9A illustrates part of a PLD structure
• FIG. 9B illustrates a switch circuit structure
• FIG. 10 illustrates a PLD entire structure
• FIG. 1 1 is a cell cross-sectional view
• FIGS. 12A to 12F each illustrate an electronic device
• FIG. 13 shows potential waveforms obtained by calculation. BEST MODE FOR CARRYING OUT THE INVENTION
• a semiconductor device includes, in its category, a variety of semiconductor integrated circuits formed using semiconductor elements, such as microprocessors, image processing circuits, controllers for semiconductor display devices, digital signal processors (DSP), microcontrollers, control circuits for batteries such as secondary batteries, and protection circuits.
• the semiconductor device includes, in its category, a variety of devices such as RF tags formed using any of the semiconductor integrated circuits and semiconductor display devices.
• the semiconductor display device includes, in its category, liquid crystal display devices, light-emitting devices in which a light-emitting element typified by an organic light-emitting element is provided in each pixel, electronic paper, digital micromirror devices (DMD), plasma display panels (PDP), field emission displays (FED), and other semiconductor display devices in which semiconductor elements are included in driver circuits.
• liquid crystal display devices light-emitting devices in which a light-emitting element typified by an organic light-emitting element is provided in each pixel
• electronic paper digital micromirror devices (DMD), plasma display panels (PDP), field emission displays (FED), and other semiconductor display devices in which semiconductor elements are included in driver circuits.
• DMD digital micromirror devices
• PDP plasma display panels
• FED field emission displays
• FIG. 1 illustrates the structure of a storage device 10 according to one embodiment of the present invention.
• the storage device 10 includes one or more groups each including at least a transistor 1 1, a transistor 12, and a logic element 13.
• FIG. 1 illustrates a structure example of the storage device 10 that includes one memory cell 14 as the group.
• the storage device 10 in FIG. 1 further includes a semiconductor element 16 supplied with a potential output from the memory cell 14. A potential output from the semiconductor element 16 is applied to a wiring 17. Note that in the structure of the storage device 10 in FIG. 1 , the semiconductor element 16 is not included in the memory cell 14; however, the semiconductor element 16 may be included in the memory cell 14.
• the transistor 11 has a function of controlling the electrical connection between a node NDl and a node ND3 in the memory cell 14 in accordance with the potential of a node ND2. Specifically, one of a source and a drain of the transistor 1 1 corresponds to the node NDl , the other of the source and the drain of the transistor 1 1 corresponds to the node ND3, and a gate of the transistor 1 1 corresponds to the node ND2.
• the potential of a signal including data that is output from the logic element 13 is supplied to the node NDl .
• electric charge corresponding to the potential is accumulated in the node ND3 and data is written to the memory cell 14.
• the memory cell 14 includes a capacitor 15 connected to the node ND3, and the potential of the node ND3 is held by the capacitor 15.
• connection means an electrical connection and corresponds to a state where current, voltage, or a potential can be supplied or transmitted. Accordingly, a connection state does not always mean a direct connection state but includes an electrical connection state through a circuit element such as a wiring, a resistor, a diode, or a transistor so that current, voltage, or a potential can be supplied or transmitted.
• a source of a transistor means a source region that is part of a semiconductor film functioning as an active layer or a source electrode that is electrically connected to the semiconductor film.
• a drain of a transistor means a drain region that is part of a semiconductor film functioning as an active layer or a drain electrode that is electrically connected to the semiconductor film.
• a gate means a gate electrode.
• source and drain of a transistor interchange with each other depending on the conductivity type of the transistor or levels of potentials applied to terminals.
• a terminal to which a low potential is applied is called a source
• a terminal to which a high potential is applied is called a drain.
• a terminal to which a low potential is applied is called a drain
• a terminal to which a high potential is applied is called a source.
• the transistor 1 1 has extremely low off-state current.
• a transistor including a channel formation region in a film of a semiconductor having a wider band gap and lower intrinsic carrier density than silicon can have significantly lower off-state current than a transistor including a channel formation region in a normal semiconductor such as silicon or germanium.
• a transistor including a channel formation region in a normal semiconductor such as silicon or germanium.
• a transistor is suitable for the transistor 11 .
• Examples of such a semiconductor are an oxide semiconductor and gallium nitride whose bandgap is 2 or more times that of silicon.
• the off-state current of the transistor 1 1 is extremely low, the other of the source and the drain of the transistor 11 becomes floating, i.e., has extremely high insulating properties with another electrode or a wiring when the transistor 1 1 is off. Accordingly, electric charge held in the node ND3 can be prevented from leaking, and the potential of the signal including data is held in the node ND3.
• off-state current in this specification means current that flows in a cut-off region between a source and a drain of a transistor.
• the transistor 12 has a function of controlling supply of a signal from a wiring WL to the gate of the transistor 1 1 , i.e., the node ND2.
• the transistor 11 is turned on or off in accordance with the potential of the signal.
• one of a source and a drain of the transistor 12 is connected to the wiring WL supplied with the signal, the other of the source and the drain of the transistor 12 is connected to the gate of the transistor 11, and a gate of the transistor 12 is connected to a wiring VL.
• the semiconductor element 16 has a function of making the other of the source and the drain of the transistor 11 , i.e., the node ND3 floating.
• a transistor, a capacitor, or the like can be used as the semiconductor element 16.
• a gate of the transistor is connected to the node ND3.
• a capacitor is used as the semiconductor element 16 one of a pair of electrodes of the capacitor is connected to the node ND3.
• the logic element 13 has functions of inverting the polarity of the potential of the signal including data after the signal is input and supplying the inverted signal to one of the source and the drain of the transistor 1 1 , i.e., the node ND l .
• an inverter or the like can be used as the logic element 13.
• the logic element 13 preferably has low current supply capability.
• the logic element 13 preferably has low current supply capability such that when the potential of a signal input to the logic element 1 3 is changed from a first potential into a second potential that is lower than the first potential, the potential of the node ND l is changed from a third potential that is lower than the second potential into the first potential after the potential of the node NDl is changed from the second potential into the third potential.
• an input terminal of the logic element 13 is connected to a wiring DL, and an output terminal of the logic element 13 is connected to one of the source and the drain of the transistor 1 1 , i.e., the node NDl .
• FIGS. 2A and 2B schematically illustrate the operation example of the storage device 10 in FIG. 1 .
• an n-channel transistor 16t is used as the semiconductor element 16 and the node ND3 is connected to a gate of the transistor 16t.
• one of a source and a drain of the transistor 16t is connected to a wiring 1 7a (example of the wiring 17), and the other of the source and the drain of the transistor 16t is connected to a wiring 17b (example of the wiring 17).
• FIG. 3 is an example of a timing chart showing potentials of the wiring WL, the wiring DL, the node NDl , the node ND2, and the node ND3.
• a high-level potential (VDD) is supplied to the wiring WL.
• a high-level potential (e.g., VDD) that is higher than a potential obtained by addition of the threshold voltage of the transistor 12 to a low-level potential (e.g., a ground potential GND) is supplied to the wiring VL.
• the transistor 12 is on, so that a potential (VDD - Vth) obtained by subtraction of the threshold voltage Vth of the transistor 12 from the high-level potential (VDD) is supplied to the gate of the transistor 1 1, i.e., the node ND2 through the transistor 12.
• the high-level potential (VDD) is supplied to the wiring DL, so that the low-level potential (GND) is supplied from the logic element 13 to one of the source and the drain of the transistor 11 , i.e., the node NDl .
• the low-level potential (GND) is applied to the node ND3 through the transistor 1 1.
• the transistor 16t can be turned off and the wiring 17a can be electrically isolated from the wiring 17b.
• a potential supplied to the wiring DL is decreased from the high-level potential (VDD) to the low-level potential (GND). Since the logic element 13 has low current supply capability, with the decrease in potential supplied to the wiring DL, the potential of the node NDl is decreased because of capacitance between the input terminal and the output terminal of the logic element 13. In FIG. 2B and FIG. 3, the potential of the node NDl is decreased from the low-level potential (GND) to a lower-level potential (-VDD).
• the transistor 12 is on at the beginning of the period t2, so that the potential (VDD - Vth) is continuously supplied to the gate of the transistor 11 , i.e., the node ND2.
• the logic element 13 increases the potential of the node NDl from the low-level potential (-VDD) to the high-level potential (VDD).
• the potential of the gate of the transistor 11 i.e., the node ND2 is started to be increased because of the capacitance Cs formed between the source and the gate of the transistor 11.
• the potential of the other of the source and the drain of the transistor 12 that is connected to the node ND2 becomes higher than the potential (VDD - Vth), so that the transistor 12 is turned off. Consequently, the gate of the transistor 1 1 , i.e., the node ND2 becomes floating.
• the potential of the node ND2 is continuously increased.
• the potential of the node ND2 is increased to a potential (3VDD - Vth) obtained by addition of a difference between the low-level potential (-VDD) and the high-level potential (VDD) to the potential (VDD - Vth).
• the gate potential of the transistor 1 1 can be increased by the above operation in the period t2.
• the potential (VDD) supplied to the node ND 1 in data writing can be prevented from being decreased by the threshold voltage of the transistor 1 1 , the potential (VDD) can be supplied to the node ND3, and data can be written to the node ND3 at high speed.
• the transistor 16t Since the high-level potential (VDD) is supplied to the node ND3 in the period t2, the transistor 16t is turned on and the wiring 17a is electrically connected to the wiring 17b.
• the potential supplied to the wiring DL is decreased from the high-level potential (VDD) to the low-level potential (GND), and the high-level potential (VDD) corresponding to a logical value "1 " is supplied to the node ND3.
• the potential supplied to the wiring DL in the period t2, can be kept at the high-level potential (VDD), and the low-level potential (GND) corresponding to a logical value "0" can be supplied to the node ND3.
• the low-level potential (GND) is supplied to the wiring WL.
• the high-level potential e.g., VDD
• VDD high-level potential
• the transistor 12 is on, so that the low-level potential (GND) is supplied to the gate of the transistor 1 1 , i.e., the node ND2 through the transistor 12. Accordingly, the transistor 1 1 is turned off and the potential (VDD) supplied in the period t2 is held in the node ND3. Consequently, the transistor 16t is kept on and the wiring 17a is kept electrically connected to the wiring 17b.
• the node ND1 has the potential (GND).
• FIG. 4A illustrates the structure of the storage device 10 that includes an inverter as the logic element 13.
• the logic element 13 included in the storage device 10 in FIG. 4A includes a p-channel transistor 18 and an n-channel transistor 19. Gates of the transistors 18 and 19 are connected to the wiring DL. One of a source and a drain of the transistor 18 is connected to a wiring 20 supplied with a high-level potential, and one of a source and a drain of the transistor 19 is connected to a wiring 21 supplied with a low-level potential. The other of the source and the drain of the transistor 18 and the other of the source and the drain of the transistor 19 are connected to one of the source and the drain of the transistor 1 1 , i.e., the node ND1.
• FIG. 4B illustrates another structure example of the storage device 10 that includes an inverter as the logic element 13.
• the storage device 10 in FIG. 4B is obtained by addition of an inverter 22 to the storage device 10 in FIG. 4A.
• the wiring WL is connected to the wiring DL
• the wiring DL is connected to an input terminal of the inverter 22 and one of the source and the drain of the transistor 12.
• FIG. 4B does not illustrate the wiring WL but illustrates only the wiring DL.
• an output terminal of the inverter 22 is connected to the input terminal (node ND4) of the logic element 13.
• FIGS. 4A and 4B when a data retention period becomes longer, a potential between a high-level potential and a low-level potential is applied to the semiconductor element 16 for a long time in some cases.
• a potential between a high-level potential and a low-level potential is applied to the semiconductor element 16 for a long time in some cases.
• the logic element 1 3 preferably has low current supply capability such that when the potential of a signal input to the logic element 13 is changed from a first potential into a second potential that is lower than the first potential, the potential of the node ND 1 is changed from a third potential that is lower than the second potential into the first potential after the potential of the node ND1 is changed from the second potential into the third potential.
• the channel length of each of the transistors 18 and 19 is preferably large. Specific channel length is described below. Note that in the following description, for easy understanding, the source of the transistor 18 is connected to the wiring 20, the source of the transistor 1 9 is connected to the wiring 21 , and the drains of the transistors 18 and 19 are connected to the node ND1.
• a channel formation region is formed in each of the transistors 18 and 19 included in the logic element 13.
• the channel formation region means a region of a semiconductor film of a transistor or a semiconductor substrate that overlaps with a gate electrode and is sandwiched between a source electrode or a source region and a drain region or a drain electrode.
• the capacitance Cs and the capacitance Cd are represented by Equation (1 ).
• the channel length and the channel width of the transistor 19 are denoted by Li and Wn, respectively.
• the channel length and the channel width of the transistor 1 8 are denoted by Li and Wp, respectively.
• a proportional constant is denoted by o.
• a fixed potential is applied to each of the wiring 20 connected to the source of the transistor 18 and the wiring 21 connected to the source of the transistor 19. If the channel formation region of the transistor 1 1 has high resistance and the transistor 12 is off when the potential, of the input terminal of the logic element 13 is decreased from the high-level potential (VDD) to the low-level potential (GND), the drain of the transistor 1 8 and the drain of the transistor 19 can be regarded as being floating.
• Equation (2) If sink current supplied from the output terminal of the inverter 22 to the input terminal of the logic element 13 is denoted by Is, the capacitance Cs of the logic element 13 is charged by the sink current Is; thus, the falling time constant ri of the potential of the input terminal of the logic element 13 is represented by Equation (2).
• the channel length and the channel width of each transistor included in the inverter 22 are denoted by L and W, respectively.
• the minimum channel length and the minimum channel width that are determined by a process are used as the channel length L and the channel width W, respectively.
• the channel width Wn of the transistor 19 in the logic element 13 is equal to the channel width W.
• the channel width Wp of the transistor 18 is adjusted so that the same drain current flows through the transistors 18 and 19 in consideration of a mobility difference between the p-channel transistor 1 8 and the n-channel transistor 19.
• the capacitance Cd of the logic element 13 is charged by the current / flowing to the transistors 18 and 19 in the logic element 13; thus, the rising time constant TO of the potential in the node ND 1 is represented by Equation (4).
• the logic element 13 preferably has low current supply capability.
• the time constant TO is preferably larger than the time constant ⁇ . In other words, to meet the above condition, it is necessary to satisfy Equation (5) derived from Equation (2) and Equation (4).
• Equation (6) can be derived from Equation (5).
• the channel length Li of the transistor included in the logic element 13 is preferably more than twice the channel length L of the transistor included in the inverter 22.
• Equation (V) the falling time constant ⁇ of the potential of the input terminal of the logic element 13 is represented by Equation (V).
• Equation (4) the rising time constant TO of the potential in the node ND 1 in the case of FIG. 4A is represented by Equation (4).
• Equation (8) the time constant TO is larger than the time constant ⁇ .
• Equation (9) can be derived from Equation (8).
• the channel length L of the transistor included in the logic element 13 is preferably significantly larger than the channel length L of another transistor such that Equation (9) is satisfied.
• FIG. 13 shows potential waveforms of wirings and nodes in the storage device 10 in FIG. 4B that are obtained by calculation.
• the calculation was conducted under a condition that a low-level potential and a high-level potential were 0 V and 1 V, respectively.
• the potential of the input terminal of the logic element 13 i.e., the node ND4 was decreased from 1 V to 0 V.
• the potential of the input terminal of the logic element 13 inverter having sufficiently high current supply capability
• the potential of the node ND4 was decreased, the potential of the node ND1 was temporarily decreased from 0 V to approximately -1 V because of capacitance between the input terminal and the output terminal of the logic element 13, and then, was increased to 1 V over time.
• the potential of the node ND2 was started to be increased. Then, when the gate voltage of the transistor 12 became close to the threshold voltage, the drain current of the transistor 12 was decreased, and the potential of the node ND2 stopped increasing after it became approximately 0.6 to 0.7 V without reaching 1 V. After the potential of the node ND2 reached the above potential, the potential of the node ND1 was decreased from 0 V to approximately -I V. At that time, the potential of the node ND2 was almost decreased because of the capacitance Cs of the transistor 1 1 ; however, the potential of the node ND2 was hardly decreased because 1 V was supplied from the wiring DL to the node ND2 through the transistor 12.
• the transistor 12 was turned off; thus, the potential of the node ND2 was increased to higher than 2 V because of the capacitance Cs of the transistor 11. Since the potential of the node ND2 was sufficiently increased, it was confirmed that a desired potential 1 V was able to be written to the node ND3 without a decrease in potential of the node ND3 by the threshold voltage of the transistor 11 .
• the potential of the node ND2 is not increased to higher than 2 V though it might be increased to higher than 1 V because of the capacitance Cs of the transistor 1 1.
• the potential of the output terminal of the logic element 13 is increased after it is decreased temporarily, the potential of the node ND2, i.e., the gate potential of the transistor 1 1 can be high compared with the case where the logic element 13 has sufficiently high current supply capability. Consequently, it is possible to write a desired potential to the node ND3 in the memory cell 14 without an increase in the number of power supply potentials.
• FIG. 5 is an example of a circuit diagram of a cell array 30 including the plurality of memory cells 14. Unlike FIG. 1, FIG. 5 illustrates the case where the semiconductor element 16 is included in the memory cell 14 and a transistor 16t is used as the semiconductor element 16.
• a variety of wirings such as the plurality of wirings WL, the plurality of wirings DL, the plurality of wirings VL, a plurality of wirings CL, and a plurality of wirings SL are provided, and a signal or a potential from a driver circuit is supplied to each memory cell 14 through the wirings.
• the number of wirings can be determined by the number and arrangement of the memory cells 14. Specifically, in the case of the cell array 30 in FIG. 5, the memory cells 14 in y rows and x columns (each of x and y is a natural number of 2 or more) are connected in matrix, and wirings WL1 to WLy corresponding to the plurality of wirings WL, wirings DLl to OLx corresponding to the plurality of wirings DL, wirings VL1 to VLy corresponding to the plurality of wirings VL, wirings CL 1 to CL corresponding to the plurality of wirings CL, and wirings SL1 to SLy corresponding to the plurality of wirings SL are provided in the cell array 30.
• the input terminal of the logic element 13 is connected to one of the wirings DL, and the output terminal of the logic element 13 is connected to one of the source and the drain of the transistor 1 1.
• the gate of the transistor 12 is connected to one of the wirings VL, one of the source and the drain of the transistor 12 is connected to the wiring WL, and the other of the source and the drain of the transistor 12 is connected to the gate of the transistor 1 1.
• the other of the source and the drain of the transistor 1 1 is connected to the gate of the transistor 16t and one electrode of the capacitor 15.
• the other electrode of the capacitor 15 is connected to one of the wirings CL.
• One of the source and the drain of the transistor 16t is connected to one of the wirings DL, and the other of the source and the drain of the transistor 16t is connected to one of the wirings SL.
• the transistor 1 1 and the transistor 12 are n-channel transistors, and the transistor 16t is a p-channel transistor.
• One of the wiring DL and the wiring SL corresponds to the wiring 17a (example of the wiring 17 in FIG. 1 ), and the other of the wiring DL and the wiring SL corresponds to the wiring 17b (example of the wiring 17 in FIG. 1 ).
• FIG. 6 illustrates the case where data writing, data retention, and data reading are performed on the memory cell 14 in a first row and a first column, the memory cell 14 in the first row and an x-th column, the memory cell 14 in a y-th row and the first column, and the memory cell 14 in the y-th row and the x-th column.
• ground potential (GND) is used as a low-level potential.
• the wiring WL 1 and the wiring CL1 included in the memory cells 14 in the first row are selected.
• the high-level potential (VDD) is supplied to the wiring WL 1
• the low-level potential (GND) is supplied to the wirings WL2 to WLy.
• the potential (VDD) is supplied to the wiring SL and the wiring VL.
• the transistors 11 included in the memory cells 14 in the first row are selectively turned on.
• the potential (GND) is supplied to the wiring CL1
• the potential (VDD) is supplied to the wirings CL2 to CLy.
• FIG. 6 illustrates the case where the potential (GND) is supplied to the wiring DL l and the potential (VDD) is supplied to the wiring DLx.
• the polarities of the potentials supplied to the wirings DL l and DLx are inverted by the logic elements 1 3, and then the inverted potentials are supplied to the gates of the transistors 16t, i.e., the nodes ND3 through the transistors 1 1 that are on.
• the amount of electrical charge accumulated in the nodes ND3 is controlled in accordance with the supplied potentials, data is written to the memory cell 14 in the first row and the first column and the memory cell 14 in the first row and the x-th column.
• the logic element 13 since the logic element 13 has low current supply capability, with the decrease in potential supplied to the wiring DL l in the period T l , the potential of the node ND 1 in the memory cell 14 connected to the wiring DL l and the wiring WL l is decreased because of the capacitance of the logic element 13.
• the potential of the gate of the transistor 1 1 i.e., the node ND2 is started to be increased because of the capacitance Cs formed between the source and the gate of the transistor 1 1 .
• the potential of the other of the source and the drain of the transistor 12 that is connected to the node ND2 becomes higher than the potential (VDD - Vth), so that the transistor 12 is turned off.
• the gate of the transistor 1 1 i.e., the node ND2 becomes floating. Even after the node ND2 becomes floating, the potential of the node ND2 is continuously increased.
• the potential of the node ND2 can be increased to the potential (3VDD - Vth) obtained by addition of a difference between the low-level potential (-VDD) and the high-level potential (VDD) to the potential (VDD - Vth). Consequently, the potential (VDD) supplied to the node ND1 in data writing can be prevented from being decreased by the threshold voltage of the transistor 1 1 , the potential (VDD) can be supplied to the node ND3, and data can be written to the node ND3 at high speed.
• the potential (GND) is supplied to the wiring WL l , so that the transistors 1 1 included in the memory cells 14 in the first row are turned off. Furthermore, the potential (VDD) is supplied to the wiring CL 1, so that the potentials of the nodes ND3 are increased. Accordingly, the transistors 16t are turned off regardless of data written to the nodes ND3. [0088]
• the wiring WLy and the wiring CLy included in the memory cells 14 in the y-t row are selected.
• the potential (VDD) is supplied to the wiring WLy, and the potential (GND) is supplied to the wirings WL l to WL(y-l ).
• the potential (VDD) is supplied to the wiring SL and the wiring VL.
• the transistors 1 1 included in the memory cells 14 in the "-th row are selectively turned on.
• the potential (GND) is supplied to the wiring CLy, and the potential (VDD) is supplied to the wirings CL 1 to CL(y-l ).
• FIG. 6 illustrates the case where the potential (VDD) is supplied to the wiring DL 1 and the potential (GND) is supplied to the wiring DLx.
• VDD potential
• GND potential
• the polarities of the potentials supplied to the wirings DL1 and DLx are inverted by the logic elements 13, and then the inverted potentials are supplied to the gates of the transistors 16t, i.e., the nodes ND3 through the transistors 11 that are on.
• the potential of the gate of the transistor 11 i.e., the node ND2 can be increased to the potential (3VDD - Vth) ideally. Consequently, the potential (VDD) supplied to the node ND1 in data writing can be prevented from being decreased by the threshold voltage of the transistor 1 1, the potential (VDD) can be supplied to the node ND3, and data can be written to the node ND3 at high speed.
• the potential (GND) is supplied to the wiring WLy, so that the transistors 1 1 included in the memory cells 14 in the y-th row are turned off. Furthermore, the potential (VDD) is supplied to the wiring CLy, so that the potentials of the nodes ND3 are increased. Accordingly, the transistors 16t are turned off regardless of data written to the nodes ND3.
• the transistor 1 1 has extremely low off-state current as described above.
• the off-state current of the transistor 1 1 is low, electric charge accumulated in the node ND3 is less likely to leak; thus, data can be retained for a long time.
• the wiring CL1 included in the memory cells 14 in the first row are selected.
• the potential (GND) is supplied to the wiring CL1
• the high-level potential (VDD) is supplied to the wirings CL2 to CLy.
• none of the wirings WL is selected by supply of the potential (GND).
• the potential (VDD) is supplied to the wiring SL and the wiring VL.
• Resistance between the source and the drain of the transistor 16t depends on the amount of electrical charge accumulated in the node ND3.
• a potential based on the amount of electrical charge accumulated in the node ND3 is supplied to the wirings DL1 and DLx. Then, by reading a difference in the amount of electrical charge from the potential, data can be read from the memory cell 14 in the first row and the first column and the memory cell 14 in the first row and the x-th column.
• the wiring CLy included in the memory cells 14 in the -th row are selected. Specifically, in FIG. 6, the potential (GND) is supplied to the wiring CLy, and the high-level potential (VDD) is supplied to the wirings CL1 to CL(y-l). In the period T4, none of the wirings WL is selected by supply of the potential (GND). Furthermore, in a period during which the wiring CLy is selected, the potential (VDD) is supplied to the wiring SL and the wiring VL. [0097]
• the resistance between the source and the drain of the transistor 16t depends on the amount of electrical charge accumulated in the node ND3.
• a potential based on the amount of electrical charge accumulated in the node ND3 is supplied to the wirings DL 1 and DLx. Then, by reading a difference in the amount of electrical charge from the potential, data can be read from the memory cell 14 in the y-th row and the first column and the memory cell 14 in the y-th row and the -th column.
• a reading circuit is connected to an end of each wiring DL, and a signal output from the reading circuit includes data actually read from the cell array 30.
• a logic circuit is formed using adequate-scale programmable logic blocks (PLE), and the functions of the logic blocks and the connection between the logic blocks can be changed (configured) after manufacture.
• the PLD includes a plurality of logic blocks and a routing resource for controlling the connection between the logic blocks.
• the functions of the logic blocks and the connection between the logic blocks formed using a routing resource are defined by configuration data, and the configuration data is stored in a storage device included in each logic block or a storage device included in the routing resource.
• FIG. 7 illustrates a PLD structure example in which a switch is used as the semiconductor element 16 included in the storage device 10 in FIG. 1 and the electrical connection between a plurality of logic blocks 41 is controlled by the semiconductor element 16.
• FIG. 7 illustrates the semiconductor element 16 formed using a transistor functioning as a switch that is turned on or off in accordance with data retained in the storage device 10 and logic blocks 41 - 1 and 41 -2.
• the electrical connection between the logic blocks 41 -1 and 41 -2 is controlled by the semiconductor element 16.
• the logic blocks 41 -1 and 41-2 are examples of the plurality of logic blocks (LB) 41.
• the logic blocks 41 - 1 and 41 -2 are electrically connected to each other.
• the logic blocks 41 -1 and 41 -2 are electrically isolated from each other.
• the storage device 10 for detection may be provided in the PLD.
• the storage device 10 for detection can have a structure in which an inverter is used as the semiconductor element 16 in the storage device 10 in FIG. 4B, for example.
• Capacitance of the capacitor 15 connected to the node ND3 and another parasitic capacitance of the storage device 10 for detection are preferably set higher than those of the storage device 10 used as a configuration memory.
• the potential of the wiring DL is set high and a high-level potential is written to the node ND3.
• FIG. 8A illustrates one mode of the logic block (LB) 41.
• the logic block 41 in FIG. 8A includes a look-up table (LUT) 42, a flip-flop 43, and the storage device 10.
• Logical operation of the LUT 42 is determined in accordance with configuration data of the storage device 10. Specifically, one output value of the LUT 42 with respect to input values of a plurality of input signals supplied to input terminals 44 is determined. Then, the LUT 42 outputs a signal including the output value.
• the flip-flop 43 holds the signal output from the LUT 42 and outputs an output signal corresponding to the signal from a first output terminal 45 and a second output terminal 46 in synchronization with a clock signal CL .
• the logic block 41 may further include a multiplexer circuit.
• the multiplexer circuit can select whether the output signal from the LUT 160 goes through the flip-flop 43.
• the type of the flip-flop 43 may be determined by the configuration data.
• the flip-flop 43 may have a function of any of a D flip-flop, a T flip-flop, a JK flip-flop, and an RS flip-flop depending on the configuration data.
• FIG. 8B illustrates another mode of the logic block 41.
• the logic block 41 in FIG. 8B has a structure in which an AND circuit 47 is added to the logic block 41 in FIG. 8A.
• a signal from the flip-flop 43 is supplied as a positive logic input, and a signal INIT is supplied as a negative logic input.
• the potential of a wiring supplied with a signal output from the logic block 41 can be initialized. Consequently, a large amount of current can be prevented from flowing between the logic blocks 41, so that breakage of the PLD can be prevented.
• FIG. 8C illustrates another mode of the logic block 41 .
• FIG. 8C has a structure in which a multiplexer 48 is added to the logic block 41 in FIG. 8A.
• the logic block 41 in FIG. 8C further includes two storage devices 10 (storage devices 10a and 10b).
• Logical operation of the LUT 42 is determined in accordance with configuration data of the storage device 10a.
• a signal output from the LUT 42 and a signal output from the flip-flop 43 are input to the multiplexer 48.
• the multiplexer 48 has functions of selecting and outputting one of the two output signals in accordance with configuration data stored in the storage device 10b.
• the signal output from the multiplexer 48 is output from the first output terminal 45 and the second output terminal 46.
• FIG. 9A schematically illustrates part of the structure of a PLD 40.
• the PLD 40 in FIG. 9A includes the plurality of logic blocks (LB) 41 , a wiring group 121 connected to any of the plurality of logic blocks 41 , and switch circuits 122 for controlling the connection between the wirings included in the wiring group 121.
• the wiring group 121 and the switch circuits 122 correspond to a routing resource 123.
• the connection between the wirings controlled by the switch circuits 122 are determined by the configuration data of the storage device 10.
• FIG. 9B illustrates a structure example of the switch circuit 122.
• the switch circuit 122 in FIG. 9B has a function of controlling the connection between a wiring 125 and a wiring 126 included in the wiring group 121 .
• the switch circuit 122 includes transistors 127 to 132.
• the transistors 127 to 132 each correspond to the semiconductor element 16 included in the storage device 10.
• the switch circuit 122 and the storage device 10 share the transistors 127 to 132.
• the transistors 127 to 132 are connected to the nodes ND3 of the plurality of storage devices 10. Selection (switching) of the on state or off state of each of the transistors 127 to 132 is determined by data retained in the node ND3 of the storage device 10.
• the transistor 127 has a function of controlling the electrical connection between a point A of the wiring 125 and a point C of the wiring 126.
• the transistor 128 has a function of controlling the electrical connection between a point B of the wiring 125 and the point C of the wiring 126.
• the transistor 129 has a function of controlling the electrical connection between the point A of the wiring 125 and a point D of the wiring 126.
• the transistor 130 has a function of controlling the electrical connection between the point B of the wiring 125 and the point D of the wiring 126.
• the transistor 131 has a function of controlling the electrical connection between the point A and the point B of the wiring 125.
• the transistor 132 has a function of controlling the electrical connection between the point C and the point D of the wiring [0113]
• the switch circuits 122 also have a function of controlling the electrical connection between the wiring group 121 and output terminals 124 of the PLD 40.
• FIG. 10 illustrates a structure example of the entire PLD 40.
• I/O elements 140 phase lock loops (PLL) 141 , a RAM 142, and a multiplier 143 are provided in the PLD 40.
• the I/O element 140 functions as an interface that controls input and output of signals from and to an external circuit of the PLD 40.
• the PLL 141 has a function of generating a signal C .
• the RAM 142 has a function of storing data used for logical operation.
• the multiplier 143 corresponds to a logic circuit for multiplication. When the PLD 40 has a function of executing multiplication, the multiplier 143 is not necessarily provided.
• FIG. 11 illustrates a cross-sectional structure example of the transistor 1 1 , the transistor 12, the transistor 18, the transistor 19, and the capacitor 1 included in the storage device 10 in FIG. 4A.
• the p-channel transistor 18, the n-channel transistor 19, and the n-channel transistor 12 are formed in a silicon on insulator (SOI) substrate, and the transistor 11 formed using an oxide semiconductor film is formed above the transistors 18, 19, and 12.
• the transistors 18, 19, and 12 may each include a semiconductor thin film of silicon, germanium, or the like in an amorphous, microcrystalline, polycrystalline, or single crystal state.
• the transistors 18, 19, and 12 may each include an oxide semiconductor film.
• the transistor 11 is not necessarily stacked above the transistors 18, 19, and 12, and the transistors 1 1 , 18, 19, and 12 may be formed over the same insulating surface.
• the transistors 18, 19, and 12 may be formed using a single crystal silicon substrate. Note that to prevent latch up when a negative potential is supplied to the node ND1 , in one embodiment of the present invention, it is preferable to form the transistors 18, 19, and 12 by using a semiconductor thin film provided over the insulating surface. [01 17]
• any of the following may be used: amorphous silicon formed by sputtering or vapor phase growth such as plasma-enhanced CVD; polycrystalline silicon obtained by crystallization of amorphous silicon by treatment such as laser annealing; and the like.
• the transistors 1 8, 19, and 12 are formed over a substrate 400 provided with an insulating film 401 .
• the substrate 400 Although there is no particular limitation on a material that can be used as the substrate 400, it is necessary that the material have at least heat resistance high enough to withstand heat treatment to be performed later.
• a glass substrate formed by a fusion process or a float process, a quartz substrate, a semiconductor substrate, a ceramic substrate, or the like can be used as the substrate 400.
• a glass substrate whose strain point is 730 °C or higher is preferably used as a glass substrate.
• a semiconductor substrate of single crystal silicon is preferably used as the substrate 400.
• a single crystal semiconductor substrate has higher surface flatness than a glass substrate. Accordingly, variation in thickness of an insulating film, a conductive film, or the like due to surface unevenness of the substrate can be prevented; thus, electrical characteristics of semiconductor elements such as transistors can be uniform even when the semiconductor elements are downsized.
• the transistor 18 includes, over the insulating film 401 , a crystalline semiconductor film 402, a gate insulating film 403 over the semiconductor film 402, and a gate electrode 404 overlapping with the semiconductor film 402 with the gate insulating film 403 positioned therebetween.
• the semiconductor film 402 includes a first region 405 functioning as a channel formation region and second regions 406 and 407 that have p-type conductivity and function as a source and a drain. The first region 405 is sandwiched between the second regions 406 and 407.
• the transistor 19 includes, over the insulating film 401 , a crystalline semiconductor film 408, a gate insulating film 409 over the semiconductor film 408, and a gate electrode 410 overlapping with the semiconductor film 408 with the gate insulating film 409 positioned therebetween.
• the semiconductor film 408 includes a first region 41 1 functioning as a channel formation region and second regions 412 and 413 that have n-type conductivity and function as a source and a drain.
• the first region 41 1 is sandwiched between the second regions 412 and 413.
• the transistor 12 includes, over the insulating film 401 , a crystalline semiconductor film 414, a gate insulating film 415 over the semiconductor film 414, and a gate electrode 416 overlapping with the semiconductor film 414 with the gate insulating film 415 positioned therebetween.
• the semiconductor film 414 includes a first region 41 7 functioning as a channel formation region and second regions 418 and 419 that have n-type conductivity and function as a source and a drain.
• the first region 417 is sandwiched between the second regions 418 and 419.
• An insulating film 420 is provided on the transistors 1 8, 19, and 12. Openings are formed in the insulating film 420. Through the openings, a wiring 423 connected to the second region 406, a wiring 424 connected to the second regions 407 and 412, a wiring 425 connected to the second region 413, a wiring 426 connected to the second region 41 8, and a wiring 427 connected to the second region 419 are formed on the insulating film 420.
• An insulating film 430 is formed over the wirings 423 to 427.
• the transistor 1 1 , the capacitor 15, and a wiring 445 are formed over the insulating film 430.
• the transistor 1 1 includes, over the insulating film 430, a semiconductor film 431 including an oxide semiconductor; conductive films 432 and 433 that are provided over the semiconductor film 431 and function as source and drain electrodes; a gate insulating film 434 over the semiconductor film 431 and the conductive films 432 and 433; and a gate electrode 435 that overlaps with the semiconductor film 431 in a region between the conductive films 432 and 433 with the gate insulating film 434 positioned between the gate electrode 435 and the semiconductor film 431.
• the conductive film 432 is connected to the wiring 424 through the opening formed in the insulating film 430.
• the wiring 445 is connected to the wiring 426 through the opening formed in the insulating film 430.
• a conductive film 436 is provided over the gate insulating film 43 1 to overlap with the conductive film 433. A portion where the conductive films 433 and 436 overlap with each other with the gate insulating film 434 positioned therebetween functions as the capacitor 15.
• FIG. 1 1 illustrates an example in which the capacitor 1 5 is provided over the insulating film 430 together with the transistor 11 .
• the capacitor 15 may be provided below the insulating film 430 together with the transistors 1 8, 19, and 12.
• the insulating film 441 and an insulating film 442 are stacked in that order over the transistor 1 1 and the capacitor 15.
• the insulating film 441 is preferably an insulating film of silicon nitride or the like that can prevent hydrogen released from the insulating film 442 from entering the semiconductor film 431.
• Openings are formed in the insulating films 441 and 442 and the gate insulating film 434.
• a conductive film 443 that is connected to the gate electrode 435 and the wiring 445 through the openings is provided over the insulating film 442.
• the transistor 11 includes the gate electrode 435 on at least one side of the semiconductor film 431.
• the transistor 11 may include a pair of gate electrodes with the semiconductor film 43 1 positioned therebetween.
• a signal for controlling an on state or an off state may be supplied to one of the gate electrodes, and the other of the gate electrodes may be supplied with a potential from another element.
• potentials at the same level may be supplied to the pair of gate electrodes, or a fixed potential such as a ground potential may be supplied only to the other of the gate electrodes.
• the transistor 1 1 has a single-gate structure where one channel formation region corresponding to one gate electrode 435 is provided.
• the transistor 1 1 may have a multi-gate structure where a plurality of channel formation regions are formed in one active layer by providing a plurality of gate electrodes electrically connected to each other.
• a highly-purified oxide semiconductor (purified oxide semiconductor) obtained by reduction of impurities such as moisture or hydrogen that serve as electron donors (donors) and reduction of oxygen vacancies is an intrinsic (i-type) semiconductor or a substantially intrinsic semiconductor.
• a transistor including a channel formation region in a highly-purified oxide semiconductor film has extremely low off-state current and high reliability.
• off-state current can be lower than or equal to the measurement limit of a semiconductor parameter analyzer, i.e., lower than or equal to 1 x 10 ⁇ 13 A, at a voltage (drain voltage) between a source electrode and a drain electrode of 1 to 10 V.
• a semiconductor parameter analyzer i.e., lower than or equal to 1 x 10 ⁇ 13 A
• drain voltage a voltage between a source electrode and a drain electrode of 1 to 10 V.
• off-state current standardized on the channel width of the transistor is lower than or equal to 100 ⁇ / ⁇ .
• a capacitor and a transistor were connected to each other and off-state current was measured using a circuit in which electric charge flowing to or from the capacitor is controlled by the transistor.
• a highly-purified oxide semiconductor film was used in the channel formation region of the transistor, and the off-state current of the transistor was measured from a change in the amount of electric charge of the capacitor per unit hour.
• the transistor including the highly-purified oxide semiconductor film in the channel formation region has much lower off-state current than a crystalline silicon transistor.
• an oxide semiconductor preferably contains at least indium (In) or zinc (Zn).
• the oxide semiconductor preferably contains gallium (Ga) in addition to In and Zn.
• Tin (Sn) is preferably contained as a stabilizer.
• Hafnium (Hf) is preferably contained as a stabilizer.
• Aluminum (Al) is preferably contained as a stabilizer.
• Zirconium (Zr) is preferably contained as a stabilizer.
• an In-Ga-Zn-based oxide, an In-Sn-Zn-based oxide, or the like has an advantage of high mass productivity because a transistor with favorable electrical characteristics can be formed by sputtering or a wet process.
• a transistor with favorable electrical characteristics can be formed over a glass substrate. Furthermore, a larger substrate can be used.
• one or more kinds of lanthanoid such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), or lutetium (Lu) may be contained.
• La lanthanum
• Ce cerium
• Pr praseodymium
• Nd neodymium
• Sm samarium
• Eu europium
• Gd gadolinium
• Tb terbium
• Dy dysprosium
• Ho holmium
• Er erbium
• Tm thulium
• Yb ytterbium
• Lu lutetium
• In-Zn-based oxide a Sn-Zn-based oxide, an Al-Zn-based oxide, a Zn-Mg-based oxide, a Sn-Mg-based oxide, an In-Mg-based oxide, an In-Ga-based oxide, an In-Ga-Zn-based oxide (also referred to as IGZO), an In-Al-Zn-based oxide, an In-Sn-Zn-based oxide, a Sn-Ga-Zn-based oxide, an Al-Ga-Zn-based oxide, a Sn-Al-Zn-based oxide, an In-Hf-Zn-based oxide, an In-La-Zn-based oxide, an In-Pr-Zn-based oxide, an In-Nd-Zn-based oxide, an In-Ce-Zn-based oxide, an In-Sm-Zn-based oxide, an ln-Eu-Zn-based oxide, an In-Gd-Zn-based oxide, an In-T
• an In-Ga-Zn-based oxide means an oxide containing In, Ga, and Zn, and there is no limitation on the ratio of In, Ga, and Zn.
• the In-Ga-Zn-based oxide may contain a metal element other than In, Ga, and Zn.
• the In-Ga-Zn-based oxide has sufficiently high resistance when no electric field is applied thereto, so that off-state current can be sufficiently reduced.
• the In-Ga-Zn-based oxide has high mobility.
• the structure of the oxide semiconductor film is described below.
• An oxide semiconductor film is roughly classified into a single-crystal oxide semiconductor film and a non-single-crystal oxide semiconductor film.
• the non-single-crystal oxide semiconductor film means any of an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, a polycrystalline oxide semiconductor film, a c-axis aligned crystalline oxide semiconductor (CAAC-OS) film, and the like.
• the amorphous oxide semiconductor film has disordered atomic arrangement and no crystalline component.
• a typical example of the amorphous oxide semiconductor film is an oxide semiconductor film in which no crystal part exists even in a microscopic region, and the whole of the film is amorphous.
• the microcrystalline oxide semiconductor film includes a microcrystal (also referred to as nanocrystal) of greater than or equal to 1 nm and less than 10 nm, for example.
• the microcrystalline oxide semiconductor film has higher degree of atomic order than the amorphous oxide semiconductor film.
• the density of defect states of the microcrystalline oxide semiconductor film is lower than that of the amorphous oxide semiconductor film.
• the CAAC-OS film is one of oxide semiconductor films including a plurality of crystal parts, and most of the crystal parts each fit into a cube whose one side is less than 100 nm. Thus, there is a case where a crystal part included in the CAAC-OS film fits into a cube whose one side is less than 10 nm, less than 5 nm, or less than 3 nm. The density of defect states of the CAAC-OS film is lower than that of the microcrystalline oxide semiconductor film.
• the CAAC-OS film is described in detail below.
• TEM transmission electron microscope
• metal atoms are arranged in a layered manner in the crystal parts.
• Each metal atom layer has a morphology reflected by a surface over which the CAAC-OS film is formed (hereinafter, a surface over which the CAAC-OS film is formed is referred to as a formation surface) or a top surface of the CAAC-OS film, and is arranged in parallel to the formation surface or the top surface of the CAAC-OS film.
• parallel indicates that an angle formed between two straight lines is -10 to 10°, and accordingly includes the case where the angle is -5 to 5°.
• perpendicular indicates that an angle formed between two straight lines is 80 to 100°, and accordingly includes the case where the angle is 85 to 95°.
• metal atoms are arranged in a triangular or hexagonal configuration in the crystal parts.
• a CAAC-OS film is subjected to structural analysis with an X-ray diffraction (XRD) apparatus.
• XRD X-ray diffraction
• each metal atom layer which is arranged in a layered manner and observed in the cross-sectional TEM image corresponds to a plane parallel to the a-b plane of the crystal.
• the crystal part is formed concurrently with deposition of the CAAC-OS film or is formed through crystallization treatment such as heat treatment.
• the c-axis of the crystal is aligned in a direction parallel to a normal vector of a formation surface or a normal vector of a top surface.
• the c-axis might not be necessarily parallel to a normal vector of a formation surface or a normal vector of a top surface of the CAAC-OS film.
• the crystallinity in the CAAC-OS film is not necessarily uniform.
• the crystallinity in the vicinity of the top surface is higher than that in the vicinity of the formation surface in some cases.
• the crystallinity in a region to which the impurity is added is changed, and the crystallinity in the CAAC-OS film varies depending on regions.
• a peak of 20 may also be observed at around 36°, in addition to the peak of 20 at around 31 °.
• the peak of 2 ⁇ at around 36° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS film. It is preferable that in the CAAC-OS film, a peak of 2 ⁇ 9 appear at around 31 ° and a peak of 20 do not appear at around 36°.
• the transistor In a transistor including the CAAC-OS film, changes in electrical characteristics of the transistor due to irradiation with visible light or ultraviolet light are small. Thus, the transistor has high reliability.
• an oxide semiconductor film may be a stacked film including two or more films of an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, and a CAAC-OS film, for example.
• a storage device or semiconductor device can be used for display devices, personal computers, or image reproducing devices provided with recording media (typically, devices that reproduce the content of recording media such as digital versatile discs (DVD) and have displays for displaying the reproduced images).
• recording media typically, devices that reproduce the content of recording media such as digital versatile discs (DVD) and have displays for displaying the reproduced images.
• electronic devices that can include the storage device or semiconductor device according to one embodiment of the present invention, cellular phones, game machines (including portable game machines), portable information terminals, e-book readers, cameras such as video cameras and digital still cameras, goggle-type displays (head mounted displays), navigation systems, audio reproducing devices (e.g., car audio systems and digital audio players), copiers, facsimiles, printers, multifunction printers, automated teller machines (ATM), vending machines, and the like can be given.
• FIGS. 12A to 12F illustrate specific examples of these electronic devices.
• FIG. 12A illustrates a portable game machine, which includes a housing 5001 , a housing 5002, a display portion 5003, a display portion 5004, a microphone 5005, speakers 5006, an operation key 5007, a stylus 5008, and the like. Note that although the portable game machine in FIG. 12A has the two display portions 5003 and 5004, the number of display portions included in the portable game machine is not limited thereto.
• FIG. 12B illustrates a portable information terminal, which includes a first housing 5601 , a second housing 5602, a first display portion 5603, a second display portion 5604, a joint 5605, an operation key 5606, and the like.
• the first display portion 5603 is provided in the first housing 5601
• the second display portion 5604 is provided in the second housing 5602.
• the first housing 5601 and the second housing 5602 are connected to each other with the joint 5605, and an angle between the first housing 5601 and the second housing 5602 can be changed with the joint 5605.
• An image on the first display portion 5603 may be switched depending on the angle between the first housing 5601 and the second housing 5602 at the joint 5605.
• a display device with a position input function may be used as at least one of the first display portion 5603 and the second display portion 5604.
• the position input function can be added by providing a touch panel in a display device.
• the position input function can be added by providing a photoelectric conversion element called a photosensor in a pixel portion of a display device.
• FIG. 12C illustrates a laptop, which includes a housing 5401 , a display portion 5402, a keyboard 5403, a pointing device 5404, and the like.
• FIG. 12D illustrates an electric refrigerator-freezer, which includes a housing 5301 , a refrigerator door 5302, a freezer door 5303, and the like.
• FIG. 12E illustrates a video camera, which includes a first housing 5801 , a second housing 5802, a display portion 5803, operation keys 5804, a lens 5805, a joint 5806, and the like.
• the operation keys 5804 and the lens 5805 are provided in the first housing 5801
• the display portion 5803 is provided in the second housing 5802.
• the first housing 5801 and the second housing 5802 are connected to each other with the joint 5806, and an angle between the first housing 5801 and the second housing 5802 can be changed with the joint 5806.
• An image on the display portion 5803 may be switched depending on the angle between the first housing 5801 and the second housing 5802 at the joint 5806.
• FIG. 12F illustrates an ordinary motor vehicle, which includes a car body 5101 , wheels 5 102, a dashboard 5103, lights 5104, and the like.
• 10 storage device, 10a: storage device, 10b: storage device, 1 1 : transistor, 12: transistor, 13: logic element, 14: memory cell, 1 5: capacitor, 16: semiconductor element, 16t: transistor, 17: wiring, 17a: wiring, 17b: wiring, 18: transistor, 19: transistor, 20: wiring, 21 : wiring, 22: inverter, 30: cell array, 40: PLD, 41 : logic block, 41 - 1 : logic block, 41-2: logic block, 42: LUT, 43: flip-flop, 44: input terminal, 45: output terminal, 46: output terminal, 47: AND circuit, 48: multiplexer, 121 : wiring group, 122: switch circuit, 123: routing resource, 124: output terminal, 125: wiring, 126: wiring, 127: transistor, 128: transistor, 129: transistor, 130: transistor, 131 : transistor, 132: transistor, 140: I/O element, 141 : PLL, 142: RAM, 143: multiplier, 400: substrate, 401 :

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