WO2014146370A1 - 阵列基板、显示面板和显示装置 - Google Patents

阵列基板、显示面板和显示装置 Download PDF

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Publication number
WO2014146370A1
WO2014146370A1 PCT/CN2013/077961 CN2013077961W WO2014146370A1 WO 2014146370 A1 WO2014146370 A1 WO 2014146370A1 CN 2013077961 W CN2013077961 W CN 2013077961W WO 2014146370 A1 WO2014146370 A1 WO 2014146370A1
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Prior art keywords
pixel electrode
layer
electrode layer
array substrate
pixel
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Ceased
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PCT/CN2013/077961
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English (en)
French (fr)
Inventor
姜文博
陈小川
李月
薛海林
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Priority to US14/355,244 priority Critical patent/US9841639B2/en
Publication of WO2014146370A1 publication Critical patent/WO2014146370A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto

Definitions

  • Embodiments of the present invention relate to an array substrate, a display panel, and a display device. Background technique
  • the aperture ratio of the liquid crystal display refers to the ratio of the area of the light passing portion after removing the wiring portion and the transistor portion (usually hidden by the black matrix) of each pixel to the entire area of each pixel. The higher the aperture ratio, the more efficient the light passes through.
  • the pixel electrode layer in a liquid crystal display is realized by a sputtering process after forming a passivation layer. All of the pixel electrode layers are in the same plane, that is, belong to the same layer.
  • 1 is a schematic view showing a pixel structure of an array substrate in a conventional art.
  • 101 is a gate line layer
  • 102 is a data line layer
  • 103 is a pixel electrode layer.
  • the pixel electrode layers 103 in Fig. 1 are all in the same plane, i.e., belong to the same layer.
  • the cross-sectional structure of the area a in FIG. 1 is as shown in FIG. 2, and the gate line layer 101, the gate insulating layer 104, the active layer 105, and the data line layer 102 (including the source 1021 and the drain 1022) are blunt from bottom to top.
  • the layer 106, the pixel electrode layer 103, wherein the pixel electrode layer 103 and the data line layer 102 are connected through via holes of the passivation layer 106.
  • the cross-sectional structure of the region b in Fig. 1 is as shown in Fig. 3. From the bottom to the top, the gate insulating layer 104, the data line layer 102, the passivation layer 106, and the pixel electrode layer 103 are sequentially arranged.
  • the pixel electrodes in adjacent pixels cannot be too close in the manufacturing process, otherwise
  • the pixel electrodes of adjacent pixels are not etched due to the limitation of the precision of the etching device, so that there is a connection between the pixel electrodes of adjacent pixels. If there is no etching between the pixel electrodes of adjacent pixels and there is a connection between the pixel electrodes of the adjacent pixels, the pixel electrode material at the connection also emits light when actually displayed, resulting in display of bright spots. At present, generally, a large gap is left between the pixel electrodes of adjacent pixels (determined according to the precision of the etching device). Although the above problem can be solved, the area of the pixel electrode is reduced, thereby causing the display area to shrink. And further cause the aperture ratio to drop ⁇ Summary of the invention
  • Embodiments of the present invention provide an array substrate.
  • the array substrate includes a pixel electrode layer.
  • the pixel electrode layer includes a first pixel electrode layer, a second pixel electrode layer, and an insulating layer, the insulating layer being located between the first pixel electrode layer and the second pixel electrode layer to make the first pixel electrode layer
  • the second pixel electrode layer is insulated from the second pixel electrode layer, and the pixel electrode of the first pixel electrode layer and the pixel electrode of the second pixel electrode layer are alternately arranged.
  • Embodiments of the present invention also provide a display panel including the array substrate.
  • Embodiments of the present invention also provide a display device including the display panel.
  • the two pixel electrode layers are used, and the two pixel electrode layers are not in the same layer, so that the area of the pixel electrode can be increased, thereby increasing the pixel aperture ratio as much as possible.
  • the storage capacitor has been greatly improved, and the elimination of undesirable phenomena such as flicker has played an important role.
  • FIG. 1 is a schematic view showing a pixel structure of an array substrate in a conventional art
  • FIG. 2 is a schematic cross-sectional structural view of a region a in FIG. 1;
  • FIG. 3 is a schematic cross-sectional structural view of a region b in FIG. 1;
  • FIG. 4 is a schematic diagram of a pixel structure of an array substrate according to an embodiment of the invention.
  • Figure 5 is a schematic cross-sectional view of the area A in Figure 4.
  • Figure 6 is a schematic cross-sectional view of a region B in Figure 4.
  • Figure 7 is a cross-sectional structural view of a region C in Figure 4.
  • Figure 8 is a schematic cross-sectional view of the area A in Figure 4.
  • Figure 9 is a cross-sectional structural view of a region B in Figure 4.
  • Figure 10 is a cross-sectional structural view of a region C in Figure 4.
  • FIG. 11 is a schematic diagram of alternate arrangement of pixel electrodes in accordance with an embodiment of the present invention. detailed description
  • Embodiments of the present invention provide an array substrate including a pixel electrode layer including a first pixel electrode layer, a second pixel electrode layer, and an insulating layer, wherein the insulating layer is located at the first pixel electrode layer
  • the first pixel electrode layer and the second pixel electrode layer are insulated from each other between the second pixel electrode layer, and the pixel electrode of the first pixel electrode layer and the pixel electrode of the second pixel electrode layer are alternately arranged.
  • FIG. 11 is a schematic diagram showing the pixel electrodes of the first pixel electrode layer and the pixel electrodes of the second pixel electrode layer being alternately arranged, in which 1031 represents the pixel electrode of the first pixel electrode layer, and 1032 represents the second pixel electrode.
  • the pixel electrodes of the layers, 1031 and 1032, are located in different layers. It should be noted that the embodiments of the present invention are not limited to the alternate arrangement shown in FIG. 11. The alternate arrangement described in the embodiments of the present invention needs to ensure that adjacent pixel electrodes are respectively located in different pixel electrode layers. .
  • the array substrate of the embodiment of the present invention further includes a gate insulating layer and a passivation layer.
  • the insulating layer between the first pixel electrode layer and the second pixel electrode layer comprises a first insulating layer and a second insulating layer, and the first insulating layer is adjacent to the first pixel electrode layer and has the same material as the gate insulating layer
  • the second insulating layer is adjacent to the second pixel electrode layer and is the same material as the passivation layer.
  • the array substrate of the embodiment of the present invention further includes a plurality of thin film transistors having a drain, and the pixel electrode of the first pixel electrode layer is connected to the drain of the thin film transistor through a via penetrating through the gate insulating layer, and second The pixel electrode of the pixel electrode layer is connected to the drain of the thin film transistor through a via penetrating through the passivation layer.
  • the insulating layer material between the first pixel electrode layer and the second pixel electrode layer is the same as the material of the passivation layer.
  • the technical solution of the embodiment of the present invention is applicable not only to the array substrate fabricated by the 5mask and 6mask processes, but also to the array substrate fabricated by other feasible number of mask processes.
  • the subsequent embodiment of the present invention is described by taking an array substrate fabricated by a 6mask process as an example, but this does not constitute a limitation of the present invention. Other feasible array substrates fabricated by the mask process are also applicable.
  • FIG. 4 is a schematic diagram of a pixel structure of an array substrate according to an embodiment of the present invention.
  • 101 is a gate line layer
  • 102 is a data line layer
  • 1031 is a pixel electrode of a first pixel electrode layer
  • 1032 is a pixel electrode of a second pixel electrode layer.
  • the cross-sectional structure of the region A in FIG. 4 is as shown in FIG. 5. From the bottom to the top, the gate line layer 101, the pixel electrode 1031 of the first pixel electrode layer, the gate insulating layer 104, the active layer 105, and the data line layer 102 are A source electrode 1021, a drain 1022), and a passivation layer 106 are included.
  • the pixel electrode 1031 of the first pixel electrode layer is located under the gate insulating layer 104 of the array substrate, and the pixel electrode 1031 of the first pixel electrode layer and the gate line layer 101 of the array substrate are separated by a gate insulating layer 104, the first pixel
  • the pixel electrode 1031 of the electrode layer is connected to the drain 1022 of the thin film transistor through a via penetrating through the gate insulating layer 104.
  • the cross-sectional structure of the region B in FIG. 4 is as shown in FIG. 6.
  • the gate line layer 101, the gate insulating layer 104, the active layer 105, and the data line layer 102 are The passivation layer 106 and the pixel electrode 1032 of the second pixel electrode layer.
  • the pixel electrode 1032 of the second pixel electrode layer is located above the passivation layer 106 of the array substrate, and the pixel electrode 1032 of the second pixel electrode layer is connected to the drain electrode 1022 of the thin film transistor through a via penetrating through the passivation layer 106.
  • the cross-sectional structure of the region C in FIG. 4 is as shown in FIG. 7.
  • the pixel electrode 1031, the gate insulating layer 104, the data line layer 102, the passivation layer 106, and the second pixel electrode layer of the first pixel electrode layer are sequentially in order from bottom to top.
  • the pixel electrode 1031 of the first pixel electrode layer is located under the gate insulating layer 104
  • the pixel electrode 1032 of the second pixel electrode layer is located above the passivation layer 106.
  • the first pixel electrode layer is located above the first passivation layer of the array substrate, below the second passivation layer
  • the second pixel electrode layer is located above the second passivation layer of the array substrate.
  • Embodiments of the present invention also provide a method of fabricating an array substrate.
  • the method includes: forming a first pixel electrode layer and a second pixel electrode layer on the array substrate, respectively.
  • the first pixel electrode layer and the second pixel electrode layer are located in different layers, and an insulating layer is formed between the first pixel electrode layer and the second pixel electrode layer, and the pixel electrode of the first pixel electrode layer and the pixel of the second pixel electrode layer
  • the electrodes are arranged alternately.
  • the first pixel electrode layer and the second pixel electrode layer are formed by a sputtering process.
  • the second pixel electrode layer may be formed after the passivation layer is formed on the array substrate.
  • the first pixel electrode layer may be connected to the drain of the thin film transistor through a via penetrating the gate insulating layer, and the second pixel electrode layer may be connected to the drain of the thin film transistor through a via of the passivation layer.
  • a first pixel electrode layer may be formed after the first passivation layer is formed on the array substrate and before the first passivation layer is formed, and a second layer is formed on the array substrate After the passivation layer, a second pixel electrode layer is formed.
  • each layer is sequentially a gate line layer, a first pixel electrode layer, a gate insulating layer, an active layer, a data line layer, a passivation layer, and a second pixel. Electrode layer.
  • the order of formation of each layer is sequentially a gate line layer, a gate insulating layer, an active layer, a data line layer, and a first passivation. a layer, a first pixel electrode layer, a second passivation layer, and a second pixel electrode layer.
  • the pixel structure of the array substrate using the double passivation layer can also be seen in FIG.
  • the cross-sectional structure of the region A in FIG. 4 is as shown in FIG. 8. From the bottom to the top, the gate line layer 101, the gate insulating layer 104, the active layer 105, and the data line layer 102 (including the source 1021 and the drain 1022) are The first passivation layer 1061 and the pixel electrode 1031 of the first pixel electrode layer.
  • the pixel electrode 1031 of the first pixel electrode layer is located above the first passivation layer 1061 and is connected to the drain electrode 1022 of the thin film transistor through a via hole penetrating through the first passivation layer 1061.
  • the cross-sectional structure of the region B in FIG. 4 is as shown in FIG. 9.
  • the gate line layer 101, the gate insulating layer 104, the active layer 105, and the data line layer 102 are sequentially arranged from bottom to top.
  • the pixel electrode 1032 of the second pixel electrode layer is connected to the drain electrode 1022 of the thin film transistor through a via penetrating through the first passivation layer 1061 and the second passivation layer 1062.
  • the cross-sectional structure of the region C in FIG. 4 is as shown in FIG. 10.
  • the gate insulating layer 104 From the bottom to the top, the gate insulating layer 104, the data line layer 102, the first passivation layer 1061, the pixel electrode 1031 of the first pixel electrode layer, and the second blunt The layer 1062 and the pixel electrode 1032 of the second pixel electrode layer.
  • the pixel electrode 1031 of the first pixel electrode layer is located above the first passivation layer 1061 of the array substrate and below the second passivation layer 1062, and the second pixel electrode layer
  • the pixel electrode 1032 is located above the second passivation layer 1062 of the array substrate.
  • a pixel electrode (including a pixel electrode and a second image of the first pixel electrode layer) in the embodiment of the present invention
  • the pixel electrode of the element electrode layer In addition to indium tin oxide (ITO, Indium Tin Oxide), other alternative materials can be used.
  • ITO Indium Tin Oxide
  • the array substrate of the embodiment of the invention may be formed based on a conventional glass substrate, or may be formed based on other feasible flexible materials.
  • the embodiment of the invention adopts two layers of pixel electrodes, and the two layers of pixel electrodes are not in the same layer, so the area of the pixel electrodes can be increased, so that there is no need to worry about the connection between the pixel electrodes in the case of increasing the pixel aperture ratio as much as possible. produce.
  • the area of the pixel electrode on the array substrate increases, the area of the corresponding black matrix on the opposite substrate also needs to be correspondingly reduced.
  • the embodiment of the present invention also greatly increases the storage capacitance, and plays an important role in avoiding undesirable phenomena such as flicker.

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  • Physics & Mathematics (AREA)
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Abstract

一种阵列基板、显示面板和显示装置。该阵列基板包括像素电极层，所述像素电极层包括第一像素电极层、第二像素电极层和绝缘层（104），所述绝缘层（104）位于所述第一像素电极层和第二像素电极层之间以使所述第一像素电极层和第二像素电极层之间绝缘，且所述第一像素电极层的像素电极（1031）和所述第二像素电极层的像素电极（1032）交替排列。

Description

阵列基板、 显示面板和显示装置 技术领域
本发明的实施例涉及一种阵列基板、 显示面板和显示装置。 背景技术
随着液晶显示器的广泛推广和应用， 人们对液晶显示器提出了越来越高 的要求， 尤其是对于提高开口率提出了很高的要求。 所谓液晶显示器的开口 率， 是指除去每一个像素的配线部、 晶体管部（通常采用黑矩阵隐藏）后的 光线通过部分的面积与每一个像素整体面积的比值。 开口率越高， 光线通过 的效率越高。
目前， 液晶显示器中的像素电极层是在形成钝化层之后通过溅射工艺来 实现的。 所有的像素电极层都在同一平面， 即属于同一层。 图 1为传统技术 中阵列基板的像素结构的示意图。在图 1中， 101为栅线层， 102为数据线层， 103为像素电极层。 图 1中的像素电极层 103都在同一平面， 即属于同一层。
图 1中区域 a的剖面结构如图 2所示， 从下至上依次为栅线层 101、 栅 绝缘层 104、 有源层 105、 数据线层 102 (包括源极 1021、 漏极 1022 ) 、 钝 化层 106、像素电极层 103 ,其中像素电极层 103与数据线层 102通过钝化层 106的过孔相连。 图 1中区域 b的剖面结构如图 3所示， 从下至上依次为栅 绝缘层 104、 数据线层 102、 钝化层 106、 像素电极层 103。
在如上所述的传统的显示装置中， 由于像素电极都是在同一平面 （即， 只有一层像素电极层） ， 因此在制作过程中相邻像素中的像素电极不能离得 太近， 否则就会因为受限于刻蚀设备的精度而导致相邻像素的像素电极刻蚀 不干净， 进而使得相邻像素的像素电极之间存在连接。 如果相邻像素的像素 电极之间没有刻蚀干净而使得相邻像素的像素电极之间存在连接， 则在实际 显示时连接处的像素电极材料也会发光， 导致显示亮点。 目前， 通常在相邻 像素的像素电极之间留有较大空隙 （根据刻蚀设备的精度来确定） ， 虽然能 够解决以上问题， 但会造成像素电极的面积缩小， 由此导致显示区域缩小， 并进而导致开口率降^^ 发明内容
本发明的实施例提供一种阵列基板。 该阵列基板包括像素电极层。 所述 像素电极层包括第一像素电极层、 第二像素电极层和绝缘层， 所述绝缘层位 于所述第一像素电极层和第二像素电极层之间以使所述第一像素电极层和第 二像素电极层之间绝缘， 且所述第一像素电极层的像素电极和所述第二像素 电极层的像素电极呈交替排列。
本发明的实施例还提供一种显示面板， 包括所述的阵列基板。
本发明的实施例还提供一种显示装置， 包括所述的显示面板。
在根据本发明实施例的阵列基板、 显示面板和显示装置中， 采用两层像 素电极层， 这两像素电极层不在同一层， 因此可以增大像素电极的面积， 从 而在尽量增大像素开口率的情况下不必担心会有像素电极之间的连接产生。 此外， 存储电容也得到了大幅提升， 对闪烁 （flicker )等不良现象的避免起 到了重要作用。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为传统技术中阵列基板的像素结构的示意图；
图 2为图 1中的区域 a的剖面结构示意图；
图 3为图 1中的区域 b的剖面结构示意图；
图 4为根据本发明实施例的阵列基板的像素结构的示意图；
图 5为图 4中的区域 A的剖面结构示意图；
图 6为图 4中的区域 B的剖面结构示意图；
图 7为图 4中的区域 C的剖面结构示意图；
图 8为图 4中的区域 A的剖面结构示意图；
图 9为图 4中的区域 B的剖面结构示意图；
图 10为图 4中的区域 C的剖面结构示意图；
图 11为根据本发明实施例的像素电极交替排列的示意图。 具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合附图， 对本发明实施例的技术方案进行清楚、 完整地描述。 显然， 所描述的实施例 是本发明的一部分实施例， 而不是全部的实施例。 基于所描述的本发明的实 施例， 本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实 施例， 都属于本发明保护的范围。
本发明的实施例提供了一种阵列基板， 该阵列基板包括像素电极层， 该 像素电极层包括第一像素电极层、 第二像素电极层和绝缘层， 所述绝缘层位 于第一像素电极层和第二像素电极层之间以使第一像素电极层和第二像素电 极层之间绝缘， 且第一像素电极层的像素电极和第二像素电极层的像素电极 呈交替排列。作为示例， 图 11示出了第一像素电极层的像素电极和第二像素 电极层的像素电极呈交替排列的示意图，图中 1031表示第一像素电极层的像 素电极， 1032表示第二像素电极层的像素电极， 1031和 1032位于不同层。 需要说明的是， 本发明实施例并非仅限于图 11所示的这一种交替排列方式， 本发明实施例中所述的交替排列需要尽量保证让相邻的像素电极分别位于不 同的像素电极层。
例如， 本发明实施例的阵列基板还包括栅绝缘层和钝化层。 相应的， 位 于第一像素电极层和第二像素电极层之间的绝缘层包括第一绝缘层和第二绝 缘层， 且第一绝缘层靠近第一像素电极层并与栅绝缘层的材料相同， 第二绝 缘层靠近第二像素电极层并与钝化层的材料相同。
例如， 本发明实施例的阵列基板还包括多个薄膜晶体管， 所述薄膜晶体 管具有漏极， 第一像素电极层的像素电极通过贯穿栅绝缘层的过孔与薄膜晶 体管的漏极相连， 第二像素电极层的像素电极通过贯穿钝化层的过孔与薄膜 晶体管的漏极相连。
例如， 位于第一像素电极层和第二像素电极层之间的绝缘层材料与钝化 层的材料相同。
需要说明的是，本发明实施例的技术方案不仅适用于通过 5mask、 6mask 工艺制作的阵列基板， 也适用于其他可行数量的 mask工艺制作的阵列基板。 本发明的后续实施例以 6mask工艺制作的阵列基板为例进行说明， 但这并不 构成对本发明的限定， 其他可行数量的 mask工艺制作的阵列基板同样适用 于本发明实施例的技术方案。
图 4为根据本发明实施例的阵列基板的像素结构的示意图。 在图 4中， 101为栅线层， 102为数据线层， 1031为第一像素电极层的像素电极， 1032 为第二像素电极层的像素电极。
图 4中的区域 A的剖面结构如图 5所示， 从下至上依次为栅线层 101、 第一像素电极层的像素电极 1031、栅绝缘层 104、有源层 105、数据线层 102 (包括源极 1021、漏极 1022 )、钝化层 106。第一像素电极层的像素电极 1031 位于阵列基板的栅绝缘层 104下方，且第一像素电极层的像素电极 1031与阵 列基板的栅线层 101之间通过栅绝缘层 104隔开， 第一像素电极层的像素电 极 1031通过贯穿栅绝缘层 104的过孔与薄膜晶体管的漏极 1022相连。
图 4中的区域 B的剖面结构如图 6所示， 从下至上依次为栅线层 101、 栅绝缘层 104、 有源层 105、 数据线层 102 (包括源极 1021 , 漏极 1022 ) 、 钝化层 106、 第二像素电极层的像素电极 1032。 第二像素电极层的像素电极 1032位于阵列基板的钝化层 106上方， 且第二像素电极层的像素电极 1032 通过贯穿钝化层 106的过孔与薄膜晶体管的漏极 1022相连。
图 4中的区域 C的剖面结构如图 7所示，从下至上依次为第一像素电极 层的像素电极 1031、栅绝缘层 104、数据线层 102、钝化层 106、 第二像素电 极层的像素电极 1032。 从图 7中也能够明显看出， 第一像素电极层的像素电 极 1031位于栅绝缘层 104下方， 第二像素电极层的像素电极 1032位于钝化 层 106上方。 形下， 第一像素电极层位于阵列基板的第一钝化层上方、 第二钝化层下方， 所述第二像素电极层位于阵列基板的第二钝化层上方。
本发明的实施例还提供了一种阵列基板的制作方法。 该方法包括： 在阵 列基板上分别形成第一像素电极层和第二像素电极层。 第一像素电极层和第 二像素电极层位于不同层， 第一像素电极层与第二像素电极层之间形成有绝 缘层， 且第一像素电极层的像素电极和第二像素电极层的像素电极呈交替排 列。
例如， 第一像素电极层和第二像素电极层通过溅射工艺形成。
例如， 可以在于阵列基板上形成栅线层之后且在形成栅绝缘层之前， 形 成第一像素电极层， 且将第一像素电极层与阵列基板的栅线层通过栅绝缘层 隔开。 例如， 可以在于阵列基板上形成钝化层之后， 形成第二像素电极层。
例如， 可以将第一像素电极层通过贯穿栅绝缘层的过孔与薄膜晶体管的 漏极相连， 第二像素电极层通过钝化层的过孔与薄膜晶体管的漏极相连。
例如， 在具有双钝化层的阵列基板中， 可以在于阵列基板上形成第一钝 化层之后且在形成第一钝化层之前， 形成第一像素电极层， 并且在于阵列基 板上形成第二钝化层之后， 形成第二像素电极层。
例如， 在制作根据本发明实施例的阵列基板时， 各层的形成顺序依次为 栅线层、 第一像素电极层、 栅绝缘层、 有源层、 数据线层、 钝化层、 第二像 素电极层。
在阵列基板采用双钝化层的情形下，在制作本发明实施例的阵列基板时， 各层的形成顺序依次为栅线层、栅绝缘层、有源层、数据线层、 第一钝化层、 第一像素电极层、 第二钝化层、 第二像素电极层。
采用双钝化层的阵列基板的像素结构也可以参见图 4。 图 4中的区域 A 的剖面结构如图 8所示，从下至上依次为栅线层 101、栅绝缘层 104、有源层 105、 数据线层 102 (包括源极 1021 , 漏极 1022 ) 、 第一钝化层 1061、 第一 像素电极层的像素电极 1031。 第一像素电极层的像素电极 1031位于第一钝 化层 1061 上方， 并通过贯穿第一钝化层 1061 的过孔与薄膜晶体管的漏极 1022相连。 图 4中的区域 B的剖面结构如图 9所示，从下至上依次为栅线层 101、栅绝缘层 104、有源层 105、数据线层 102 (包括源极 1021 ,漏极 1022 )、 第一钝化层 1061、 第二钝化层 1062、 第二像素电极层的像素电极 1032。 第 二像素电极层的像素电极 1032通过贯穿第一钝化层 1061和第二钝化层 1062 的过孔与薄膜晶体管的漏极 1022相连。 图 4中的区域 C的剖面结构如图 10 所示， 从下至上依次为栅绝缘层 104、 数据线层 102、 第一钝化层 1061、 第 一像素电极层的像素电极 1031、 第二钝化层 1062和第二像素电极层的像素 电极 1032。
可以看出， 在采用双钝化层的阵列基板中， 第一像素电极层的像素电极 1031位于阵列基板的第一钝化层 1061上方及第二钝化层 1062下方，第二像 素电极层的像素电极 1032位于阵列基板的第二钝化层 1062上方。
本发明实施例中的像素电极（包括第一像素电极层的像素电极和第二像 素电极层的像素电极） 除了可以采用铟锡氧化物 （ITO, Indium Tin Oxide ) 外， 还可以采用其他替代材料。 本发明实施例的阵列基板可以基于传统的玻 璃基板制作形成， 也可以基于其他可行的柔性材料制作形成。
本发明的实施例采用两层像素电极， 这两层像素电极不在同一层， 因此 可以增大像素电极的面积， 从而在尽量增大像素开口率的情况下不必担心会 有像素电极之间的连接产生。 此外， 当阵列基板上的像素电极的面积的增大 时， 对向基板上的对应的黑矩阵的面积也需要相应缩小。 此外， 本发明的实 施例还使得存储电容也得到了大幅提升， 对闪烁 （flicker )等不良现象的避 免起到了重要作用。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种阵列基板， 包括像素电极层，
其中所述像素电极层包括第一像素电极层、 第二像素电极层和绝缘层， 所述绝缘层位于所述第一像素电极层和第二像素电极层之间以使所述第一像 素电极层和第二像素电极层之间绝缘， 且所述第一像素电极层的像素电极和 所述第二像素电极层的像素电极呈交替排列。
2、根据权利要求 1所述的阵列基板，其中所述阵列基板还包括栅绝缘层 和钝化层， 所述绝缘层包括第一绝缘层和第二绝缘层， 所述第一绝缘层靠近 所述第一像素电极层且与所述栅绝缘层材料相同， 所述第二绝缘层靠近所述 第二像素电极层且与所述钝化层材料相同。
3、根据权利要求 2所述的阵列基板，其中所述阵列基板还包括多个薄膜 晶体管， 所述薄膜晶体管具有漏极， 所述第一像素电极层的像素电极通过贯 穿所述栅绝缘层的过孔与所述薄膜晶体管的漏极相连， 所述第二像素电极层 的像素电极通过贯穿所述钝化层的过孔与薄膜晶体管的漏极相连。
4、根据权利要求 1所述的阵列基板，其中所述阵列基板还包括第一钝化 层和第二钝化层， 第一像素电极层位于第一钝化层上方、 第二钝化层下方， 第二像素电极层位于第二钝化层上方。
5、根据权利要求 4所述的阵列基板，其中所述阵列基板还包括多个薄膜 晶体管， 所述薄膜晶体管具有漏极， 第一像素电极层的像素电极通过贯穿第 一钝化层的过孔与薄膜晶体管的漏极相连， 第二像素电极层的像素电极通过 贯穿第一钝化层和第二钝化层的过孔与薄膜晶体管的漏极相连。
6、 一种显示面板， 包括权利要求 1~5任一项所述的阵列基板。
7、 一种显示装置， 包括权利要求 6所述的显示面板。
PCT/CN2013/077961 2013-03-19 2013-06-26 阵列基板、显示面板和显示装置 Ceased WO2014146370A1 (zh)

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