WO2014126201A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2014126201A1 WO2014126201A1 PCT/JP2014/053479 JP2014053479W WO2014126201A1 WO 2014126201 A1 WO2014126201 A1 WO 2014126201A1 JP 2014053479 W JP2014053479 W JP 2014053479W WO 2014126201 A1 WO2014126201 A1 WO 2014126201A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/50—Peripheral circuit region structures
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments
Definitions
- the present invention is based on the priority claim of Japanese Patent Application No. 2013-027793 (filed on Feb. 15, 2013), the entire contents of which are incorporated herein by reference. Shall.
- the present invention relates to a semiconductor device.
- standby current standby current
- Icc2ps correlates with the leakage current when the transistor is off
- the subthreshold current current that flows before the channel is turned on by applying a voltage to the gate
- GIDL Gate-Induced-Drain-Leakage current; gate induced drain leakage current
- the applied voltage Vpp is high (about 2.5 to 3 V), so that the leakage component due to GIDL increases.
- the same conductivity type as that of the first diffusion layers 51a, 51b and the second diffusion layer 51c is provided between the first diffusion layers 51a and 51b and the second diffusion layer 51c and the channel.
- the extension region 110 having a lower impurity concentration than the first diffusion layers 51a and 51b and the second diffusion layer 51c is provided, and the first diffusion layers 51a and 51b and the second diffusion layer 51c are formed deeper in the extension region 110.
- the extension region 110 is ion-implanted at a tilt angle (angle at which the normal of the main surface of the semiconductor substrate 101 intersects the ion beam) 0 deg, and the pocket-implanted region 111 is often ion-implanted at a desired tilt angle.
- the ion concentration in the extension region 110 is reduced, and thus the parasitic resistance increases and the on-current Ion decreases.
- the diffusion coefficient of boron B used for ion implantation of the extension region 110 of the pMOS transistor, the first diffusion layers 51a and 51b, and the second diffusion layer 51c is large, and the junction is deep. Therefore, the short channel effect tends to increase, and the threshold voltage Vt tends to decrease, making it difficult to form a transistor with a short gate length.
- an LDD (Lightly Doped Drain) region that is thinner than the ion concentration of the extension region 110 is used, and carbon C is implanted into the LDD region.
- this method is difficult to use in the pMOS transistor of the sub-word driver SWD because GIDL increases due to crystal defects and electric field strength generated in the semiconductor substrate (silicon substrate).
- the gate length of the pMOS transistor of the sub-word driver SWD must be increased inevitably, which hinders chip size reduction.
- both ends of the outer periphery of the element isolation region formed on the semiconductor substrate and the active region sandwiched between the element isolation regions extend on the element isolation region.
- an active region of the unit transistors adjacent to each other in the first direction the plurality of unit transistors having an inner periphery arranged to close the active region and a gate electrode formed in a frame shape are electrically isolated by the element isolation region, and the active regions of the unit transistors adjacent to each other in the second direction intersecting the first direction are connected.
- GIDL can be reduced while maintaining the on-current Ion in the unit transistor. Further, since the gate length of the gate electrode can be shortened, the chip size can be reduced.
- FIG. 3 is a diagram schematically illustrating an example of a partial arrangement of a memory cell array and peripheral circuits in the semiconductor device according to the first embodiment of the present invention.
- FIG. 3 is a diagram schematically showing an example of the arrangement of bit lines and word lines in the memory cell array in the semiconductor device according to the first embodiment of the present invention.
- FIG. 3 is a diagram schematically illustrating an example of a circuit configuration of a sub word line driver of a peripheral circuit in the semiconductor device according to the first embodiment of the present invention.
- FIG. 3 is a diagram schematically illustrating an example of a layout of pMOS transistors in a sub word line driver of a peripheral circuit in the semiconductor device according to the first exemplary embodiment of the present invention.
- FIG. 5 is a diagram corresponding to FIG.
- FIG. 4 illustrating an example of a connection between a pMOS transistor and a wiring in a sub-word line driver of a peripheral circuit in the semiconductor device according to the first exemplary embodiment of the present invention.
- FIG. 6 is a view corresponding to FIG. 5 schematically showing an example of a wiring layout in a sub-word line driver of a peripheral circuit in the semiconductor device according to the first embodiment of the present invention.
- 5 schematically shows an example of the configuration of the pMOS transistor in the sub-word line driver of the peripheral circuit in the semiconductor device according to the first embodiment of the present invention, between (a) AA ′ and (b) between BB ′ in FIG. (C) It is sectional drawing between CC '.
- FIG. 5 schematically shows an example of the configuration of the pMOS transistor in the sub-word line driver of the peripheral circuit in the semiconductor device according to the first embodiment of the present invention, between (a) AA ′ and (b) between BB ′ in FIG. (C) It is sectional drawing
- FIG. 6 is a process cross-sectional view corresponding to section AA ′ of FIG. 5 schematically showing an example of a method for manufacturing a pMOS transistor in a sub-word line driver of a peripheral circuit in the semiconductor device according to the first embodiment of the present invention.
- 5A and 5B schematically showing an example of the configuration of the pMOS transistor in the sub-word line driver of the peripheral circuit in the semiconductor device according to the second embodiment of the present invention.
- (C) is a cross-sectional view corresponding to CC ′.
- FIG. 10 is a process cross-sectional view corresponding to AA ′ of FIG.
- FIG. 5 schematically showing an example of a method for manufacturing a pMOS transistor in a sub-word line driver of a peripheral circuit in a semiconductor device according to Embodiment 2 of the present invention.
- 5A and 5B schematically showing an example of the configuration of the pMOS transistor in the sub-word line driver of the peripheral circuit in the semiconductor device according to the third embodiment of the present invention.
- (C) is a cross-sectional view corresponding to CC ′.
- FIG. 10 is a process cross-sectional view corresponding to AA ′ in FIG. 5 schematically showing an example of a method for manufacturing a pMOS transistor in a sub-word line driver of a peripheral circuit in a semiconductor device according to Embodiment 3 of the present invention.
- FIG. 5A and 5B schematically showing an example of the configuration of the pMOS transistor in the sub-word line driver of the peripheral circuit in the semiconductor device according to the fourth embodiment of the present invention.
- (C) is a cross-sectional view corresponding to CC ′.
- FIG. 10 is a process cross-sectional view corresponding to AA ′ of FIG. 5 schematically showing an example of a method for manufacturing a pMOS transistor in a sub-word line driver of a peripheral circuit in a semiconductor device according to Embodiment 4 of the present invention. It is the figure which showed an example of the connection of the pMOS transistor and wiring in the subword line driver of the peripheral circuit in the semiconductor device which concerns on a prior art example.
- 15A and 15B schematically showing an example of the configuration of the pMOS transistor in the sub-word line driver of the peripheral circuit in the semiconductor device according to the conventional example, (b) BB ′, (c) It is sectional drawing between CC '.
- FIG. 1 is a diagram schematically showing an example of a partial arrangement of a memory cell array and peripheral circuits in a semiconductor device according to Embodiment 1 of the present invention.
- FIG. 2 is a diagram schematically showing an example of the arrangement of bit lines and word lines of the memory cell array in the semiconductor device according to the first embodiment of the present invention.
- the semiconductor device is a semiconductor memory device (semiconductor memory) capable of storing information in a circuit configured by semiconductor elements.
- the semiconductor device includes a memory cell array MCA, and includes a row decoder Xdec, a main word driver MWD, a sub word driver SWD, a column decoder Ydec, and a sense amplifier array SAA as peripheral circuits of the memory cell array MCA (see FIG. 1).
- the memory cell array MCA is an array in which memory cells MC are arranged in a matrix of a plurality of rows and a plurality of columns (see FIGS. 1 and 2).
- the memory cell array MCA itself is also arranged in a matrix of a plurality of rows and a plurality of columns.
- the memory cell array MCA includes memory cells MC, sub word lines SWL, and bit lines BL.
- the memory cell MC is a cell constituting a circuit necessary for storing 1-bit information (see FIG. 2).
- the memory cell MC is provided at each intersection (or near the intersection) of the sub word line SWL and the bit line BL.
- a selection transistor (not shown) and a storage element (not shown, a capacitor, a resistance change element) are connected in series between a common source line (not shown) and the bit line BL.
- An electrode that is electrically connected and the gate electrode of the selection transistor is electrically connected to the sub word line SWL can be used.
- Memory cell MC is electrically connected to corresponding sub-word line SWL and bit line BL. Note that.
- the common source line supplies a common reference potential to the memory cells MC.
- the sub word lines SWL are provided so as to extend in the X direction and to be aligned in the Y direction (see FIG. 2).
- Each sub word line SWL is electrically connected to a corresponding sub word line driver SWLD in one of the sub word drivers SWD arranged on both sides in the X direction of the memory cell array MCA.
- the bit lines BL extend in the Y direction and are arranged side by side in the X direction (see FIG. 2). Each bit line BL is electrically connected to a corresponding sense amplifier SA in one of the sense amplifier arrays SAA arranged on both sides in the Y direction of the memory cell array MCA.
- the row decoder Xdec is a circuit that decodes signals (encoded row addresses) from an array control circuit (not shown) and a row address buffer (not shown) (see FIG. 1).
- the row decoder Xdec outputs the decoded signal (row address) to the main word driver MWD.
- the main word driver MWD is a circuit for selecting the sub word driver SWD belonging to the signal (row address) from the row decoder Xdec (see FIG. 1).
- the main word driver MWD selects a corresponding sub word driver SWD based on a signal (row address) from the row decoder Xdec, and outputs a signal (row address) toward the selected sub word driver SWD.
- the sub word driver SWD is a circuit for selecting memory cells belonging to a predetermined row in the memory cell array MCA (see FIGS. 1 and 2).
- the sub word drivers SWD are arranged on both sides in the X direction of the memory cell array MCA.
- the sub word driver SWD has a plurality of sub word line drivers SWLD.
- the sub word line driver SWLD is electrically connected to the corresponding sub word line SWL.
- the sub word driver SWD activates the sub word line driver SWLD corresponding to the row address, and sets the row (row) address in the memory cell array MCA via the corresponding sub word line SWL. select. Details of the configuration of the sub word driver SWD and the sub word line driver SWLD will be described later.
- the column decoder Ydec is a circuit that decodes signals (encoded column addresses) from an array control circuit (not shown) and a column address buffer (not shown) (see FIG. 1).
- the column decoder Ydec activates the corresponding bit line BL based on the column address, and selects a column (column) address in the memory cell array MCA via the bit line BL.
- the sense amplifier array SAA is an array in which a plurality of sense amplifiers SA are arranged (see FIGS. 1 and 2).
- the sense amplifier array SAA is arranged on both sides in the Y direction of the memory cell array MCA.
- the sense amplifier SA is a circuit that amplifies the potential of data read from the memory cell array MCA via the selected bit line BL.
- the sense amplifier SA outputs the potential-amplified data toward a determination circuit (not shown).
- FIG. 3 is a diagram schematically showing an example of the circuit configuration of the sub-word line driver of the peripheral circuit in the semiconductor device according to Embodiment 1 of the present invention.
- a plurality of sub word line drivers SWLD0 to SWLD7 are arranged in a matrix of a plurality of rows and a plurality of columns.
- the pMOS transistor Q00 and the nMOS transistor Q10 are electrically connected in series between the output signal line AAFXT0 and the reference potential line Vkk (0 to ⁇ 0.5 V), and the pMOS transistor An nMOS transistor Q10 and an nMOS transistor Q20 are electrically connected in parallel between Q00 and the reference potential line Vkk.
- the gate electrodes of the pMOS transistor Q00 and the nMOS transistor Q10 are electrically connected to an address MWLB0 (row address) signal line from the main word driver MWD.
- the gate electrode of the nMOS transistor Q20 is electrically connected to the complementary output signal line ARFXB0.
- a sub word line SWL0 is electrically connected to the source terminal of the pMOS transistor Q00, the drain terminal of the nMOS transistor Q10, and the drain terminal of the nMOS transistor Q20. The same applies to the other sub word line drivers SWLD1 to SWLD7.
- the address MWLB0 signal line is electrically connected in common by the sub word line drivers SWLD0 to SWLD3.
- the address MWLB1 signal line is also electrically connected in common by the sub word line drivers SWLD4 to SWLD7.
- the output signal line AAFXT0 and the complementary output signal line ARFXB0 are electrically connected in common by the sub word line driver SWLD0 and the sub word line driver SWLD4.
- the output signal line AAFXT1 and the complementary output signal line ARFXB1 are also electrically connected in common by the sub word line driver SWLD1 and the sub word line driver SWLD5.
- the output signal line AAFXT2 and the complementary output signal line ARFXB2 are electrically connected in common by the sub word line driver SWLD2 and the sub word line driver SWLD6.
- the output signal line AAFXT3 and the complementary output signal line ARFXB3 are electrically connected in common by the sub word line driver SWLD3 and the sub word line driver SWLD7.
- the configuration of the pMOS transistors Q00 to Q07 of the sub word line drivers SWLD0 to SWLD7 will be described later.
- FIG. 4 is a diagram schematically showing an example of the layout of the pMOS transistors in the sub-word line driver of the peripheral circuit in the semiconductor device according to the first embodiment of the present invention.
- FIG. 5 is a diagram corresponding to FIG. 4 showing an example of the connection between the pMOS transistor and the wiring in the sub word line driver of the peripheral circuit in the semiconductor device according to the first embodiment of the present invention.
- FIG. 6 is a diagram corresponding to FIG. 5 schematically showing an example of a wiring layout in the sub-word line driver of the peripheral circuit in the semiconductor device according to the first embodiment of the present invention.
- FIG. 7 schematically illustrates an example of the configuration of the pMOS transistor in the sub-word line driver of the peripheral circuit in the semiconductor device according to the first embodiment of the present invention, between (a) AA ′ and (b) B in FIG.
- FIG. 4B is a cross-sectional view between -B ′ and (c) CC ′.
- the pMOS transistors Q00 to Q07 of the sub word line drivers SWLD0 to SWLD7 in FIG. 3 are formed on the n well 102 formed on the semiconductor substrate 101 as shown in FIG.
- An element isolation region 103 in which an insulator (for example, a silicon oxide film) is embedded in a groove formed in a line shape is formed at a predetermined position of the n-well 102.
- the element isolation region 103 is disposed in a region between the active regions 11 shown in FIG.
- a gate electrode 12 for example, titanium nitride
- a gate insulating film 105 for example, a silicon oxide film
- the gate electrode 12 extends on the active region sandwiched between the element isolation regions 103, and both ends of the outer periphery extend on the element isolation region 103.
- the gate electrode is arranged so as to close the active region, is formed in a frame shape (frame shape), is connected to the gate electrode 12 adjacent in the Y direction so as to be shifted in the X direction, and is adjacent to the Y direction. 12 is separated.
- the gate electrode 12 has a first channel portion 12a and a second channel portion 12b on both sides in the X direction with respect to the second diffusion layer 11b on the inner side of the frame shape, and in the Y direction with respect to the second diffusion layer 11b on the inner side of the frame shape.
- the portions on both sides become the first connection portion 12c and the second connection portion 12d. That is, the first connection portion 12c and the second connection portion 12d connect both ends of the first channel portion 12a and the second channel portion 12b in the Y direction.
- An interval S1 between the gate electrodes in the X direction inside the frame shape of the gate electrode 12 is the same as an interval S2 between the gate electrodes in the X direction outside the frame shape of the gate electrode 12 (see FIG. 7).
- the gate electrode 12 is electrically connected to a wiring to which a corresponding address signal MWLBn is input (see FIGS. 5 and 6). Note that the width L in the X direction of the unit transistor 10 is the width of eight sub-word lines SWL (see FIG. 4).
- a first diffusion layer 11a (p-type diffusion layer; for example, a layer in which boron B is diffused) is formed in a frame-shaped inner region of the gate electrode 12 on the n-well 102.
- a second diffusion layer 11b (p-type diffusion layer; for example, a layer in which boron B is diffused) is formed (see FIGS. 4 and 7).
- the distance in the X direction between the center of the first diffusion layer 11a and the center of the second diffusion layer 11b is one half (L / 2) of the width L in the X direction of the unit transistor 10 (see FIG. 4). ).
- the extension region 110 is a region in which impurities (for example, boron B) having the same conductivity type as the first diffusion layer 11a and the second diffusion layer 11b and having a lower concentration than the first diffusion layer 11a and the second diffusion layer 11b are diffused. .
- impurities for example, boron B
- the pocket implantation region 111 is a region having a conductivity type opposite to that of the first diffusion layer 11a and the second diffusion layer 11b and an impurity (for example, phosphorus) having a concentration higher than that of the n-well 102 is implanted and diffused.
- the extension region 110 and the pocket implantation region 111 are disposed below or in the vicinity of the sidewall spacer 107.
- An interlayer insulating film 115 (for example, a silicon oxide film) is formed on the entire surface of the substrate including the gate electrode 12, the sidewall spacer 107, the first diffusion layer 11a, and the second diffusion layer 11b.
- a hole leading to the first diffusion layer 11a is formed in the interlayer insulating film 115, and a contact plug 13a (for example, DOPOS, doped polysilicon) is embedded in the hole.
- a hole communicating with the second diffusion layer 11b is formed in the interlayer insulating film 115, and a contact plug 13b (for example, DOPOS, doped polysilicon) is embedded in the hole.
- a wiring 117 (for example, a laminated film of tungsten nitride / tungsten) is formed at a predetermined position on the interlayer insulating film 115 including the contact plugs 13a and 13b.
- the wiring electrically connected to the sub word lines SWL0 to SWL7 is connected to the corresponding contact plug 13a (see FIGS. 5 and 6).
- the wiring connected to the output signal AAFXTn is connected to the corresponding contact plug 13b (see FIGS. 5 and 6).
- An interlayer insulating film 120 (for example, a silicon oxide film) is formed on the interlayer insulating film 115 including the wiring 117.
- the interlayer insulating film 120 is formed with a hole communicating with the wiring 117 connected to the output signal AAFXTn, and a contact plug 121 (for example, DOPOS, doped polysilicon) is embedded in the hole.
- a wiring 122 connected to the output signal AAFXTn is formed on the interlayer insulating film 120 including the contact plug 121.
- the wiring 122 is electrically connected to the second diffusion layer 11b through the contact plug 121, the wiring 117, and the contact plug 13b.
- FIG. 8 is a process cross-sectional view corresponding to the line AA ′ of FIG. 5 schematically showing an example of the method for manufacturing the pMOS transistor in the sub-word line driver of the peripheral circuit in the semiconductor device according to the first embodiment of the present invention. is there.
- an n-well 102 (for example, a region where phosphorus is diffused) is formed on a semiconductor substrate 101 (for example, a silicon substrate), and then a gate insulating film 105 (for example, a silicon oxide film) is formed on the n-well 102.
- a gate electrode 12 (for example, titanium nitride) is formed, and then a part of the gate electrode 12 and the gate insulating film 105 is removed by lithography and dry etching techniques (step A1).
- an extension region 110 is formed by implanting impurities (for example, boron B) at a tilt angle of 0 deg into the exposed n-well 102 (step A2; see FIG. 8A).
- impurities for example, boron B
- a pocket implantation region 111 is formed by implanting impurities (for example, phosphorus) at a desired tilt angle into the n-well 102 located deeper than the extension region 110 (step A3; see FIG. 8B).
- impurities for example, phosphorus
- an insulating film for example, a silicon nitride film for the sidewall spacer 107 is formed on the entire surface of the substrate including the extension region 110, the gate electrode 12, and the gate insulating film 105, and then the insulating film is etched back.
- sidewall spacers 107 are formed on the side wall surfaces of the frame-shaped inner periphery and the frame-shaped outer periphery of the gate electrode 12 and the gate insulating film 105, and then the exposed extension region 110 is tilted to the n-well 102.
- impurities for example, boron B
- step A5 an interlayer insulating film, contact plugs, and wiring are formed by using a conventional method. Thereby, the pMOS transistor in the sub word line driver as shown in FIG. 7 can be manufactured.
- GIDL can be reduced while maintaining the on-current Ion of the pMOS transistors Q00 to Q07. Further, since the gate length of the sub word driver SWD can be scaled (reduced), the chip size can be reduced.
- the pocket injection region 111 is formed in the first diffusion layer 11 a and the second diffusion layer 11 b on both the frame-shaped inner side and the frame-shaped outer side of the gate electrode 12, thereby reducing the short channel effect.
- This makes it possible to suppress pMOS transistors with shorter gate lengths and reduce the chip area. That is, by reducing the area occupied by the sub word driver SWD in the chip, the chip area of the DRAM can be reduced and the performance of the pMOS transistor can be improved.
- the extension region 110 and the pocket implantation region 111 can be formed by the same ion implantation, and the capability of the pMOS transistor can be maintained without increasing the cost. It becomes.
- the cost is not increased.
- FIG. 9 schematically shows an example of the configuration of the pMOS transistor in the sub-word line driver of the peripheral circuit in the semiconductor device according to the second embodiment of the present invention, between (a) AA ′ in FIG. 5 and (b) B
- FIG. 4 is a cross-sectional view corresponding to the line between -B ′ and (c) CC ′.
- the second embodiment is a modification of the first embodiment, in which the extension region 110 and the pocket injection region 111 are not formed around the first diffusion layer 11a of the pMOS transistor in the sub word line driver SWD, and the second diffusion layer 11b is surrounded.
- the extension region 110 and the pocket implantation region 111 are formed only in the pMOS transistor so that the impurity profile is asymmetric.
- Other configurations are the same as those of the first embodiment.
- FIG. 10 is a process cross-sectional view corresponding to section AA ′ of FIG. 5 schematically showing an example of a method for manufacturing a pMOS transistor in the sub-word line driver of the peripheral circuit in the semiconductor device according to the second embodiment of the present invention. is there.
- an n-well 102 (for example, a region where phosphorus is diffused) is formed on a semiconductor substrate 101 (for example, a silicon substrate), and then a gate insulating film 105 (for example, a silicon oxide film) is formed on the n-well 102.
- a gate electrode 12 (for example, titanium nitride) is formed, and then part of the gate electrode 12 and the gate insulating film 105 is removed by lithography and dry etching techniques (step B1).
- a resist 125 is formed to cover a region where the first diffusion layer (11a in FIG. 10) is to be formed.
- the exposed n-well 102 is doped with impurities (for example, with a tilt angle of 0 deg.
- the extension region 110 is formed only in the region where the second diffusion layer (11b in FIG. 10) is to be formed (step B2; see FIG. 10A).
- an impurity for example, phosphorus
- a second diffusion layer 11b in FIG. 10
- the pocket injection region 111 is formed only in the region to be changed (step B3; see FIG. 10B).
- an insulating film for example, silicon nitride
- the sidewall spacer 107 is formed on each of the sidewall surfaces of the frame-shaped inner periphery and the frame-shaped outer periphery of the gate electrode 12 and the gate insulating film 105 by etching back the insulating film.
- an impurity for example, boron B
- boron B is implanted from the exposed n well 102 and the extension region 110 into the n well 102 at a tilt angle of 0 deg, thereby forming the first diffusion layer 11a and the second diffusion layer 11b.
- step B5 an interlayer insulating film, contact plugs, and wiring are formed by using a conventional method.
- a pMOS transistor in which the profiles of the extension region 110 and the pocket implantation region 111 are asymmetric in the sub-word line driver as shown in FIG. 9 can be manufactured.
- the first diffusion layer 11a inside the frame shape of the gate electrode 12 does not have the extension region 110 and the pocket implantation region 111, and the extension region 110 and pocket implantation are not present in the second diffusion layer 11b outside the frame shape.
- a pMOS transistor having a region 111 having an asymmetric impurity profile is formed in the sub-word driver SWD using the resist 125, and at the same time, a transistor having a symmetric impurity profile can be formed in the peripheral circuit portion.
- GIDL generated in the first diffusion layer 11a inside the frame shape can be reduced.
- the extension region 110 and the pocket implantation region 111 can be formed by the same ion implantation, and the capability of the transistor can be maintained without increasing the cost. Become.
- FIG. 11 schematically shows an example of the configuration of the pMOS transistor in the sub-word line driver of the peripheral circuit in the semiconductor device according to the third embodiment of the present invention, between (a) AA ′ and (b) B in FIG.
- FIG. 6 is a cross-sectional view corresponding to a line between ⁇ B ′ and (c) CC ′.
- the third embodiment is a modification of the second embodiment, and the interval S1 between the gate electrodes in the X direction inside the frame shape of the gate electrode 12 is set between the gate electrodes in the X direction outside the frame shape of the gate electrode 12.
- the distance is smaller than the interval S2
- the width of the first diffusion layer 11a is smaller than the width of the second diffusion layer 11b.
- the extension region 110 and the pocket implantation region 111 are formed only around the second diffusion layer 11b to form a pMOS transistor having an asymmetric impurity profile, similar to the second embodiment.
- Other configurations are the same as those in the second embodiment.
- FIG. 12 is a process cross-sectional view corresponding to the section AA ′ of FIG. 5 schematically showing an example of a method for manufacturing a pMOS transistor in the sub-word line driver of the peripheral circuit in the semiconductor device according to the third embodiment of the present invention. is there.
- an n-well 102 (for example, a region where phosphorus is diffused) is formed on a semiconductor substrate 101 (for example, a silicon substrate), and then a gate insulating film 105 (for example, a silicon oxide film) is formed on the n-well 102.
- a gate electrode 12 (for example, titanium nitride) is formed, and then a part of the gate electrode 12 and the gate insulating film 105 is removed by lithography and dry etching techniques. Thereafter, the n well 102, the gate electrode 12, and the gate insulating film are removed.
- An insulating film for example, a silicon nitride film for the sidewall spacer 107 is formed on the entire surface of the substrate including 105, and then the insulating film is etched back to thereby form the frame shape of the gate electrode 12 and the gate insulating film 105.
- Side wall spacers 107 on the respective side wall surfaces of the inner periphery and the outer periphery of the frame shape. Forming (step C1).
- a resist 125 is formed to cover a region where the first diffusion layer (11a in FIG. 12) is to be formed.
- the exposed n-well 102 is doped with impurities (for example, with a tilt angle of 0 deg.
- the extension region 110 is formed only in the region where the second diffusion layer (11b in FIG. 12) is to be formed (step C2; see FIG. 12A).
- an impurity for example, phosphorus
- a second diffusion layer 11b in FIG. 12
- the pocket injection region 111 is formed only in the region to be changed (step C3; see FIG. 12B).
- step C4 see FIG. 12C.
- step C5 an interlayer insulating film, a contact plug, and a wiring are formed using a conventional method.
- a pMOS transistor in which the width of the first diffusion layer 11a is smaller than the width of the second diffusion layer 11b and the profiles of the extension region 110 and the pocket injection region 111 are asymmetric in the sub-word line driver as shown in FIG. can do.
- FIG. 6 is a cross-sectional view corresponding to a line between ⁇ B ′ and (c) CC ′.
- Embodiment 4 is a modification of Embodiment 3, in which a pocket injection region 111 is formed around the first diffusion layer 11a.
- the interval S1 between the gate electrodes in the X direction inside the frame shape of the gate electrode 12 is made smaller than the interval S2 between the gate electrodes in the X direction outside the frame shape of the gate electrode 12, and the width of the first diffusion layer 11a Is the same as that of the third embodiment in that it is smaller than the width of the second diffusion layer 11b.
- the extension region 110 and the pocket implantation region 111 are formed around the second diffusion layer 11b to form a pMOS transistor having an asymmetric impurity profile. Other configurations are the same as those in the third embodiment.
- FIG. 14 is a process cross-sectional view corresponding to the line AA ′ of FIG. 5 schematically showing an example of a method for manufacturing a pMOS transistor in the sub-word line driver of the peripheral circuit in the semiconductor device according to the fourth embodiment of the present invention. is there.
- an n-well 102 (for example, a region where phosphorus is diffused) is formed on a semiconductor substrate 101 (for example, a silicon substrate), and then a gate insulating film 105 (for example, a silicon oxide film) is formed on the n-well 102.
- a gate electrode 12 (for example, titanium nitride) is formed, and then a part of the gate electrode 12 and the gate insulating film 105 is removed by lithography and dry etching techniques. Thereafter, the n well 102, the gate electrode 12, and the gate insulating film are removed.
- An insulating film for example, a silicon nitride film for the sidewall spacer 107 is formed on the entire surface of the substrate including 105, and then the insulating film is etched back to thereby form the frame shape of the gate electrode 12 and the gate insulating film 105.
- Side wall spacers 107 on the respective side wall surfaces of the inner periphery and the outer periphery of the frame shape. Forming (step D1).
- an impurity for example, boron B
- boron B is implanted into the exposed n-well 102 at a predetermined tilt angle, so that the extension region 110 is formed only in a region where the second diffusion layer (11b in FIG. 14) is to be formed.
- carbon C is injected into the extension region 110 only at a predetermined tilt angle (step D2; see FIG. 14A).
- the predetermined tilt angle when forming the extension region 110 is such that the extension region 110 is formed only in the region where the second diffusion layer (11b in FIG. 14) is to be formed, but the first diffusion layer ( In the region where 11a in FIG. 14 is to be formed, the angle at which the extension region 110 is not formed (or the impurity concentration of the extension region 110 related to the first diffusion layer (11a in FIG. 14) is the second diffusion layer (FIG. 14). 11b) may be an angle that is thinner than the impurity concentration of the extension region 110).
- the predetermined tilt angle when carbon C is implanted is such that carbon C is not implanted into a region where the first diffusion layer (11a in FIG. 14) is to be formed (or a significant dose of the extension region 110). And the angle at which carbon C is implanted into the extension region 110 (or the second diffusion layer (11b in FIG. 14)) for the region that will form the second diffusion layer (11b in FIG. 14). ) May be an angle that is significantly darker than the region that will form. Since the gate interval of the peripheral circuit portion is set wider than the interval S1 between the gate electrodes in the X direction inside the frame shape of the gate electrode 12, the transistor in the peripheral circuit portion is extended to both the source and drain. Carbon C into the region is implanted symmetrically.
- an impurity for example, phosphorus
- an impurity for example, phosphorus
- the pocket implantation region 111 is implanted at a tilt angle of 0 deg because pocket implantation is performed in a region where both the first diffusion layer (11b in FIG. 14) and the second diffusion layer (11b in FIG. 14) are to be formed. This is because the region 111 is formed.
- an impurity for example, boron B
- boron B is implanted from the exposed extension region 110 and pocket implantation region 111 into the n-well 102 at a tilt angle of 0 deg, thereby forming the first diffusion layer 11a and the second diffusion layer 11b (see FIG. Step D4; see FIG. 14 (c)).
- step C5 an interlayer insulating film, a contact plug, and a wiring are formed using a conventional method.
- a pMOS transistor in which the width of the first diffusion layer 11a is smaller than the width of the second diffusion layer 11b and the profile of the extension region 110 is asymmetric in the sub-word line driver as shown in FIG. 13 can be manufactured.
- GIDL can be reduced while maintaining the on-current Ion of the pMOS transistor. Further, since the gate length of the sub word driver SWD can be reduced, the chip size can be reduced.
- the first diffusion layer 11a inside the frame shape of the gate electrode 12 has a low concentration (carbon C) in the extension region 111, and the second diffusion layer 11b outside the frame shape has a high concentration (carbon C) in the extension region.
- a transistor having an asymmetric profile can be formed in the sub-word driver SWD by self-alignment, and at the same time, a transistor having a symmetrical impurity profile can be formed in the peripheral circuit portion without increasing the number of masks for ion implantation.
- GIDL generated in the diffusion layers 11a and 11b inside the frame shape is reduced.
- the short channel effect can be suppressed by forming the pocket injection regions 111 in the diffusion layers 11a and 11b on both the frame-shaped inner side and the frame-shaped outer side of the gate electrode 12.
- a transistor with a shorter gate length can be obtained, and the chip area can be reduced. That is, by reducing the area occupied by the sub word driver SWD in the chip, the chip area of the DRAM can be reduced and the performance of the transistor can be improved.
- the extension region 111 and the pocket implantation region 110 can be formed by the same ion implantation, and the capability of the transistor can be maintained without increasing the cost. Become.
- the cost is not increased.
- both ends of the outer periphery of the element isolation region formed on the semiconductor substrate and the active region sandwiched between the element isolation regions extend on the element isolation region.
- an active region of the unit transistors adjacent to each other in the first direction the inner region having a plurality of unit transistors, the inner periphery of the unit transistors having a gate electrode formed in a frame shape, the inner region being disposed so as to close the active region Are electrically isolated by the element isolation region, and the active regions of the unit transistors adjacent to each other in the second direction intersecting the first direction are connected.
- the gate electrodes are arranged on the element isolation region so that the gate electrodes adjacent to each other in the first direction are in contact with each other and adjacent to the second direction.
- the gate electrode is arranged at a predetermined interval from the matching gate electrode.
- an interval between the gate electrodes in the second direction on the inner side of the frame shape of the gate electrode is the gate in the second direction on the outer side of the frame shape of the gate electrode. It is the same as the distance between the electrodes.
- an interval between the gate electrodes in the second direction on the inner side of the frame shape of the gate electrode is the gate in the second direction on the outer side of the frame shape of the gate electrode. Narrower than the distance between the electrodes.
- the semiconductor device includes sidewall spacers formed on respective sidewall surfaces of the frame-shaped inner periphery and the frame-shaped outer periphery of the gate electrode.
- the first conductivity type well formed on the semiconductor substrate is opposite to the first conductivity type formed on the well in the inner region of the frame shape of the gate electrode.
- the semiconductor device is disposed in contact with the second diffusion layer in a region between the channel of the unit transistor and the second diffusion layer, and has an impurity concentration lower than that of the second diffusion layer.
- the second diffusion layer and the second extension region at a position deeper than the second extension region in the second extension region of the second conductivity type and a region between the channel of the unit transistor and the second diffusion layer.
- a second pocket implantation region of the first conductivity type having an impurity concentration higher than that of the well.
- an impurity concentration is lower than that of the first diffusion layer while being in contact with the first diffusion layer in a region between the channel of the unit transistor and the first diffusion layer.
- the first diffusion region and the first extension region at a position deeper than the first extension region in the first extension region of the second conductivity type and the region between the channel of the unit transistor and the first diffusion layer.
- a first pocket implantation region of the first conductivity type having an impurity concentration higher than that of the well.
- the first transistor having an impurity concentration higher than that of the well is disposed in contact with the first diffusion layer in a region between the channel of the unit transistor and the first diffusion layer.
- a first pocket implantation region of a conductive type is provided.
- the semiconductor device of the present invention includes a plurality of word drivers including a plurality of the unit transistors, and a plurality of word lines electrically connected to the word drivers.
- the first diffusion layer is electrically connected to a corresponding word line
- the second diffusion layer is electrically connected to a corresponding output signal line
- the gate electrode is It is electrically connected to the corresponding address signal line.
- the word line extends in the first direction and is arranged side by side in the second direction, and the word driver includes the first direction and the second direction. Arranged side by side.
- the word drivers arranged in the first direction are electrically connected to the common address signal line.
- the word drivers arranged in the second direction are electrically connected to the common output signal line.
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Abstract
Description
本発明は、日本国特許出願:特願2013-027793号(2013年02月15日出願)の優先権主張に基づくものであり、同出願の全記載内容は引用をもって本書に組み込み記載されているものとする。
本発明は、半導体装置に関する。
以下の分析は、本願発明者により与えられる。
本発明の実施形態1に係る半導体装置について図面を用いて説明する。図1は、本発明の実施形態1に係る半導体装置におけるメモリセルアレイ及び周辺回路の一部の配置の一例を模式的に示した図である。図2は、本発明の実施形態1に係る半導体装置におけるメモリセルアレイのビット線及びワード線の配置の一例を模式的に示した図である。
本発明の実施形態2に係る半導体装置について図面を用いて説明する。図9は、本発明の実施形態2に係る半導体装置における周辺回路のサブワード線ドライバにおけるpMOSトランジスタの構成の一例を模式的に示した図5の(a)A-A´間、(b)B-B´間、(c)C-C´間に相当する断面図である。
本発明の実施形態3に係る半導体装置について図面を用いて説明する。図11は、本発明の実施形態3に係る半導体装置における周辺回路のサブワード線ドライバにおけるpMOSトランジスタの構成の一例を模式的に示した図5の(a)A-A´間、(b)B-B´間、(c)C-C´間に相当する断面図である。
本発明の実施形態4に係る半導体装置について図面を用いて説明する。図13は、本発明の実施形態4に係る半導体装置における周辺回路のサブワード線ドライバにおけるpMOSトランジスタの構成の一例を模式的に示した図5の(a)A-A´間、(b)B-B´間、(c)C-C´間に相当する断面図である。
本発明の一視点においては、半導体装置において、半導体基板上に形成された素子分離領域と、前記素子分離領域に挟まれた活性領域上に、その外周の両端が前記素子分離領域上に延在し、内周が前記活性領域を閉じるように配置されるとともに、フレーム形に形成されたゲート電極と、を有する複数の単位トランジスタを備え、第1の方向に隣り合う前記単位トランジスタの前記活性領域は、前記素子分離領域によって電気的に分離され、前記第1の方向と交差する第2の方向に隣り合う前記単位トランジスタの前記活性領域は、繋がっている。
11 活性領域
11a 第1拡散層
11b 第2拡散層
12 ゲート電極
12a 第1チャネル部
12b 第2チャネル部
12c 第1接続部
12d 第2接続部
13、13a、13b コンタクトプラグ
50a 第1単位トランジスタ
50b 第2単位トランジスタ
51 活性領域
51a、51b 第1拡散層
51c 第2拡散層
52a、52b ゲート電極
53a、53b、53c コンタクトプラグ
101 半導体基板
102 nウェル(第1導電型)
103 素子分離領域
105 ゲート絶縁膜
107 サイドウォールスペーサ
110 エクステンション領域
111 ポケット注入領域(第1導電型)
115 第1層間絶縁膜
117 配線
120 第2層間絶縁膜
121 コンタクトプラグ
122 配線
125 レジスト
MCA メモリセルアレイ
MC メモリセル
Xdec ロウデコーダ
MWD メインワードドライバ
SWD サブワードドライバ
SWLD、SWLD0~7 サブワード線ドライバ
SWL、SWL0~7 サブワード線
Ydec カラムデコーダ
SAA センスアンプアレイ
SA センスアンプ
BL ビット線
MWLB0~1 アドレス信号
AAFXT0~3 出力信号
ARFXB0~3 相補出力信号
Q00~07 pMOSトランジスタ
Q10~17 nMOSトランジスタ
Q20~27 nMOSトランジスタ
Claims (14)
- 半導体基板上に形成された素子分離領域と、
前記素子分離領域に挟まれた活性領域上に、その外周の両端が前記素子分離領域上に延在し、内周が前記活性領域を閉じるように配置されるとともに、フレーム形に形成されたゲート電極と、
を有する複数の単位トランジスタを備え、
第1の方向に隣り合う前記単位トランジスタの前記活性領域は、前記素子分離領域によって電気的に分離され、
前記第1の方向と交差する第2の方向に隣り合う前記単位トランジスタの前記活性領域は、繋がっている半導体装置。 - 前記ゲート電極は、前記素子分離領域上で前記第1の方向に互いに隣り合うゲート電極同士が接するように少なくとも4つ配置されるとともに、前記第2の方向に隣り合うゲート電極と所定の間隔をおいて配置される請求項1記載の半導体装置。
- 前記ゲート電極のフレーム形状の内側での前記第2の方向の前記ゲート電極間の間隔は、前記ゲート電極のフレーム形状の外側での前記第2の方向の前記ゲート電極間の間隔と同一である請求項2記載の半導体装置。
- 前記ゲート電極のフレーム形状の内側での前記第2の方向の前記ゲート電極間の間隔は、前記ゲート電極のフレーム形状の外側での前記第2の方向の前記ゲート電極間の間隔より狭い請求項2記載の半導体装置。
- 前記ゲート電極のフレーム形状の内周及びフレーム形状の外周のそれぞれの側壁面上に形成されたサイドウォールスペーサを備える請求項1乃至4のいずれか一に記載の半導体装置。
- 半導体基板上に形成された第1導電型のウェルと、
前記ゲート電極のフレーム形状の内側の領域の前記ウェル上に形成された前記第1導電型とは反対の第2導電型の第1拡散層と、
前記ゲート電極のフレーム形状の外側の領域の前記ウェル上に形成された前記第2導電型の第2拡散層と、
を備える請求項1乃至5のいずれか一に記載の半導体装置。 - 前記単位トランジスタのチャネルと前記第2拡散層との間の領域にて前記第2拡散層と接して配されるとともに、前記第2拡散層よりも不純物濃度が低い前記第2導電型の第2エクステンション領域と、
前記単位トランジスタのチャネルと前記第2拡散層との間の領域の前記第2エクステンション領域より深い位置にて前記第2拡散層及び前記第2エクステンション領域と接して配されるとともに、前記ウェルよりも不純物濃度が高い前記第1導電型の第2ポケット注入領域と、
を備える請求項6記載の半導体装置。 - 前記単位トランジスタのチャネルと前記第1拡散層との間の領域にて前記第1拡散層と接して配されるとともに、前記第1拡散層よりも不純物濃度が低い前記第2導電型の第1エクステンション領域と、
前記単位トランジスタのチャネルと前記第1拡散層との間の領域の前記第1エクステンション領域より深い位置にて前記第1拡散層及び前記第1エクステンション領域と接して配されるとともに、前記ウェルよりも不純物濃度が高い前記第1導電型の第1ポケット注入領域と、
を備える請求項7記載の半導体装置。 - 前記単位トランジスタのチャネルと前記第1拡散層との間の領域にて前記第1拡散層と接して配されるとともに、前記ウェルよりも不純物濃度が高い前記第1導電型の第1ポケット注入領域を備える請求項7記載の半導体装置。
- 複数の前記単位トランジスタを備える複数のワードドライバと、
前記ワードドライバに電気的に接続される複数のワード線と、
を備える請求項6乃至9のいずれか一に記載の半導体装置。 - 前記第1拡散層は、対応するワード線と電気的に接続され、
前記第2拡散層は、対応する出力信号線と電気的に接続され、
前記ゲート電極は、対応するアドレス信号線と電気的に接続される請求項10記載の半導体装置。 - 前記ワード線は、前記第1の方向に延在するとともに前記第2の方向に並んで配置され、
前記ワードドライバは、前記第1の方向及び前記第2の方向に並んで配置される請求項10又は11記載の半導体装置。 - 前記第1の方向に並んだ各前記ワードドライバは、共通の前記アドレス信号線に電気的に接続される請求項12記載の半導体装置。
- 前記第2の方向に並んだ各前記ワードドライバは、共通の前記出力信号線に電気的に接続される請求項12又は13記載の半導体装置。
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JP2000156419A (ja) * | 1998-09-04 | 2000-06-06 | Hitachi Ltd | 半導体装置の製造方法および半導体装置 |
JP2000236074A (ja) * | 1998-12-17 | 2000-08-29 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JP2002100746A (ja) * | 2000-09-21 | 2002-04-05 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JP2011233765A (ja) * | 2010-04-28 | 2011-11-17 | Elpida Memory Inc | 半導体装置及び半導体装置の製造方法 |
JP2013254860A (ja) * | 2012-06-07 | 2013-12-19 | Ps4 Luxco S A R L | 半導体装置の製造方法 |
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JP2012054502A (ja) * | 2010-09-03 | 2012-03-15 | Elpida Memory Inc | 半導体装置 |
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JP2000156419A (ja) * | 1998-09-04 | 2000-06-06 | Hitachi Ltd | 半導体装置の製造方法および半導体装置 |
JP2000236074A (ja) * | 1998-12-17 | 2000-08-29 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JP2002100746A (ja) * | 2000-09-21 | 2002-04-05 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JP2011233765A (ja) * | 2010-04-28 | 2011-11-17 | Elpida Memory Inc | 半導体装置及び半導体装置の製造方法 |
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