WO2014121710A1 - 一种氮化物功率器件及其制造方法 - Google Patents

一种氮化物功率器件及其制造方法 Download PDF

Info

Publication number
WO2014121710A1
WO2014121710A1 PCT/CN2014/071559 CN2014071559W WO2014121710A1 WO 2014121710 A1 WO2014121710 A1 WO 2014121710A1 CN 2014071559 W CN2014071559 W CN 2014071559W WO 2014121710 A1 WO2014121710 A1 WO 2014121710A1
Authority
WO
WIPO (PCT)
Prior art keywords
nitride
layer
power device
multilayer structure
semiconductor
Prior art date
Application number
PCT/CN2014/071559
Other languages
English (en)
French (fr)
Inventor
程凯
Original Assignee
苏州晶湛半导体有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 苏州晶湛半导体有限公司 filed Critical 苏州晶湛半导体有限公司
Priority to JP2015556386A priority Critical patent/JP6588340B2/ja
Priority to EP14748959.5A priority patent/EP2955757B1/en
Priority to DK14748959T priority patent/DK2955757T3/da
Publication of WO2014121710A1 publication Critical patent/WO2014121710A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66522—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with an active layer made of a group 13/15 material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity

Definitions

  • the invention belongs to the field of microelectronics, and relates to a nitride power device, and a method for manufacturing the nitride power device, in particular, by introducing a semiconductor doped multilayer capable of forming a thick space charge depletion region in a Si village substrate.
  • the structure can withstand a large applied voltage, thereby increasing the breakdown voltage of the device.
  • gallium nitride The third-generation semiconductor material, gallium nitride (GaN), has become a research hotspot due to its large forbidden band width, high electron saturation drift speed, high breakdown field strength and good thermal conductivity.
  • gallium nitride materials are more suitable for manufacturing high temperature, high frequency, high voltage and high power devices than silicon and gallium arsenide. Therefore, gallium nitride based electronic devices have a good application prospect.
  • GaN power devices were fabricated on sapphire or silicon carbide substrates. Due to the particularity and process difficulty of GaN heterojunction conductive channels, GaN power devices are basically planar structures. Because the bottom of the village is 4 ⁇ thick and the breakdown electric field is high, the device is generally laterally broken. The planar breakdown voltage can be improved by some planar optimization techniques such as field plate structure, increasing gate and drain distance, and the like. However, the sapphire and silicon carbide substrate materials are relatively expensive and it is difficult to realize large-sized substrate materials and epitaxial layers. Therefore, the cost of GaN power devices is high and difficult to market.
  • FIG. 1A The structure is as shown in FIG. 1A, including a silicon substrate 1, a nitride nucleation layer 2, a nitride buffer layer 3, a nitride channel layer 4, a nitride barrier layer 5, a dielectric passivation layer 9, and a source including 6.
  • the silicon-based gallium nitride power device Due to the conductivity of the silicon material itself and the low critical electric field, the silicon-based gallium nitride power device has a saturation breakdown voltage which is determined by the thickness of the nitride epitaxial layer grown on the silicon substrate.
  • the grounding of the village is an inevitable choice, which leads to the breakdown voltage Vbrl of the silicon-based GaN power device when the ground is grounded than the floating breakdown.
  • the voltage Vbr2 is reduced by half. As shown in Fig.
  • the resistivity is usually not more than 10 4 Ohm.cm, which is much smaller than the nitride resistivity (>10 9 Ohm.cm). Play a role in partial pressure. Therefore, it is an urgent problem to improve the breakdown voltage of the nitride power device on the silicon village.
  • the breakdown voltage of the silicon nitride high-voltage device can be improved.
  • the technology for growing the nitride epitaxial layer on the silicon material is becoming more and more mature, there is a huge difference between the silicon material and the nitride.
  • Lattice mismatch and thermal mismatch the thickness of the grown nitride epitaxial layer is greatly limited, generally about 2um to 4um, the growth of the thick nitride epitaxial layer will not only take longer, increase the cost Reduce the productivity, and the quality of the epitaxial layer will be deteriorated, it will be easy to warp or crack, increase the difficulty of the process, reduce the yield and so on.
  • the breakdown voltage of the device is also affected by longitudinal breakdown.
  • This longitudinal breakdown voltage is determined by the tolerable voltage of the epitaxial layer and the withstand voltage of the silicon substrate. Therefore, the total longitudinal breakdown voltage can be improved by improving the pressure resistance of the silicon substrate.
  • the thickness of the silicon substrate is generally fixed. Too thick will increase the cost, and affect the quality of the nitride epitaxial layer on the silicon, which will increase the process difficulty. Therefore, it is not feasible to increase the silicon village bottom pressure resistance by increasing the thickness of the village bottom. .
  • PN diodes made of silicon can withstand high reverse applied voltages.
  • an N-type doped region and a P-type doped region are formed by doping in the bottom of the silicon village, and a PN junction is formed inside the two doped regions to form a space charge depletion region, and a conductive electron inside the space charge region
  • the hole is very small, close to zero, similar to a high-resistance zone, the breakdown electric field is relatively high, and can withstand a certain applied voltage.
  • the voltage that the space charge region can withstand is related to its width. The wider the space charge region, the greater the voltage that can withstand, that is, the breakdown voltage of the PN diode.
  • the width of the space charge region is affected by the doping concentration and the applied voltage. Generally, the width of the space charge region becomes larger as the applied voltage increases. When the doping concentration is higher, the space charge region is narrower than the same voltage. When the concentration is low, the space charge region is wide and can withstand higher applied voltage. Space charge when electrons and holes inside the N-type doped region and the P-type doped region are completely depleted The width of the area will not expand any more. Continue to increase the applied voltage space and the charge area will break down. Because the silicon doping process is mature and stable, different structures and different concentrations of doping profiles can be formed, so that PN diodes capable of withstanding different voltages are generated. Summary of the invention
  • a thinner lateral P-type doped semiconductor layer and an N-type doped semiconductor layer, a P-type doped semiconductor layer and an N-type doping may be introduced into the silicon substrate by epitaxial or ion implantation.
  • a space charge region is formed inside the semiconductor layer, and the conductive electrons and holes inside the space charge region are completely depleted, and the space charge region is substantially insulated, which is similar to a high resistance region, and the breakdown electric field is relatively high, and can withstand a certain applied voltage.
  • the voltage that the space charge region can withstand is related to the width of the space charge region, and the wider the space charge region, the greater the voltage that can withstand.
  • the space charge region is continuously widened, and the voltage that can be withstood is also increasing. Because the semiconductor doping layer is thin, the electrons and holes inside the entire doped semiconductor layer are Completely depleted, the entire doped semiconducting region becomes a high-resistance region that can withstand higher applied voltages. If there are multiple layers of N-type semiconductor layers and P-type semiconductor layers, a multi-layer space charge depletion region is formed, and a thick space charge depletion region is formed, which can withstand a high applied voltage, in practice The structure of the specifically doped semiconductor layer is determined according to the voltage that the device is required to withstand.
  • the space charge region formed by the P-type doped semiconductor layer and the N-type doped semiconductor layer introduced in the silicon substrate is equivalent to inserting a high voltage withstand layer in the conductive silicon substrate to improve the resistance of the silicon substrate.
  • the compressive property increases the breakdown voltage of the entire device, especially in the case where the silicon substrate is grounded, greatly increasing the longitudinal breakdown voltage between the drain and the bottom electrode.
  • a semiconductor doped multilayer structure capable of forming a space charge depletion region by introducing a thinner n-type silicon layer and a p-type silicon layer by introducing a space charge depletion region in a silicon substrate.
  • a nitride power device comprising: a silicon substrate comprising a semiconductor doped multilayer structure capable of forming a space charge depletion region; an epitaxy on the silicon substrate a multilayer structure comprising at least a nitride nucleation layer, a nitride buffer layer formed on the nitride nucleation layer, and a nitride channel layer formed on the nitride buffer layer; An electrode formed on the epitaxial multilayer structure, wherein the nitride power device is a triode structure, the electrode includes a source and a drain, and a gate between the source and the drain; the nitride When the power device is a diode structure, the electrode includes a positive electrode and a negative electrode.
  • the semiconductor doped multilayer structure may be a pn structure composed of an n-type semiconductor layer and a p-type semiconductor layer, and includes a space depletion region; or an n-type semiconductor
  • the multilayer structure in which the layer and the p-type semiconductor layer are alternately alternately includes a plurality of pn junctions, that is, a plurality of spatial depletion regions.
  • the nitride power device can apply forward bias or reverse bias, and the single-layer n-type semiconductor and the single-layer p-type semiconductor cannot bear the bidirectional voltage drop. Therefore, a practical village bottom structure needs to be composed of a plurality of layers of n-type and p-type semiconductor layers.
  • the n-type semiconductor layer and the p-type semiconductor layer in the semiconductor doped multilayer structure have a thickness greater than 2 nm, and the n-type semiconductor layer and the p-type semiconductor layer in the semiconductor doped multilayer structure
  • the n- and p-type semiconductors are respectively; the number, thickness and doping concentration of the entire semiconductor doped multilayer structure can be adjusted according to the voltage tolerated.
  • the semiconductor doped multilayer structure is prepared by epitaxial growth or ion implantation.
  • the above semiconductor doped multilayer structure may be formed on the top or inner or back side of the silicon substrate, or any combination thereof.
  • the semiconductor in the semiconductor doped multilayer structure may be any one of silicon, germanium, silicon, silicon carbide, m-v compound or any combination thereof.
  • a nitride barrier layer is provided on the nitride channel layer, and a two-dimensional electron gas is formed at an interface between the nitride channel layer and the nitride barrier layer.
  • a dielectric layer on the barrier layer is further included.
  • the dielectric layer includes one of SiN, Si0 2 , SiON, A1 2 0 3 , Hf0 2 , HfAlOx, or any combination thereof.
  • a gallium nitride layer on the barrier layer is further included.
  • an A1N interposer layer between the barrier layer and the channel layer is further included.
  • an AlGaN back barrier layer between the buffer layer and the channel layer is further included.
  • a dielectric layer is formed under the gate.
  • the gate electrode has a gate field plate and/or a source having a source field plate.
  • a method for fabricating a nitride power device comprising the steps of: forming a semiconductor doped multilayer structure capable of forming a space charge depletion region in a silicon substrate; a nitride nucleation layer on a silicon substrate containing a semiconductor doped multilayer structure; a nitride buffer layer grown on the nitride nucleation layer; a nitride channel layer grown on the nitride buffer layer; Forming a contact electrode on the compound channel layer, wherein the nitride power device is a triode structure, the electrode includes a source and a drain, and a gate between the source and the drain; the nitride power device is a diode In the structure, the electrode includes a positive electrode and a negative electrode.
  • the above-described method of fabricating the semiconductor doped multi-layer structure is epitaxial growth or ion implantation.
  • 1A is a schematic structural view of a nitride device on a Si Si village
  • Figure 1B shows the breakdown voltage of a silicon nitride power device in the case of floating and village grounding
  • FIG. 2A is a schematic structural view of a nitride power device according to a first embodiment of the present invention
  • FIG. 2B is a modified structure of the first embodiment of the present invention
  • 2C is another modified structure of the first embodiment of the present invention
  • Figure 5 is another modified structure of the first embodiment of the present invention.
  • FIG. 6 is a schematic structural view of a silicon nitride power device on a silicon substrate according to a second embodiment of the present invention
  • FIG. 7 is a schematic structural view of a silicon nitride power device on a silicon substrate according to a third embodiment of the present invention
  • FIG. 9 is a schematic structural view of a nitride power device on a silicon substrate according to a fifth embodiment of the present invention
  • FIG. 10 is a schematic diagram of a nitride on a silicon substrate according to a sixth embodiment of the present invention
  • FIG. 11 is a schematic structural view of a nitride power device on a silicon substrate according to a seventh embodiment of the present invention
  • FIG. 12 is a schematic structural view of a silicon nitride power device on a silicon substrate according to an eighth embodiment of the present invention.
  • the present invention proposes a nitride power device capable of withstanding a high breakdown voltage, and the nitride power device fabricates a p-type silicon layer and an n-type silicon layer alternately arranged on the silicon substrate. Knot. When an applied voltage is applied to the nitride power device, each pn junction forms a space charge depletion region, and the breakdown voltage of the entire device is greatly increased by the superposition of one or more space charge depletion regions. Reduces the risk of voltage breakdown of the device.
  • FIG. 2A is a schematic structural diagram of a silicon nitride power device on a silicon substrate according to a first embodiment of the present invention.
  • a field effect transistor having a triode structure is described.
  • the nitride power device includes: a silicon substrate 1 including a semiconductor doped multilayer structure 10 capable of forming a space charge depletion region.
  • the epitaxial multilayer structure comprises: a nitride nucleation layer 2 and a buffer layer 3, and the buffer layer 3 comprises GaN or AlN or other nitrides to match the substrate material And the effect of a high-quality nitride epitaxial layer, affecting the crystal quality, surface morphology and electrical properties of the heterojunction composed of gallium nitride/aluminum gallium nitride a parameter; a channel layer 4 is grown on the buffer layer 3, the channel layer comprises a non-doped GaN layer; a barrier layer 5 is grown on the channel layer 4, the barrier layer comprises AlGaN or other nitride; 4 and the barrier layer 5 together form a semiconductor heterojunction structure, forming a high concentration two-dimensional electron gas at the interface, and generating a conductive channel at the heterojunction interface of the GaN channel layer; depositing on the barrier layer 5
  • the dielectric layer 9 is passivated to the surface of the material,
  • a lateral semiconductor doped multilayer structure 10 capable of forming a space charge depletion region is introduced on a silicon substrate
  • the semiconductor doped multilayer structure 10 is an innovation of the present invention, which is a pn junction composed of a semiconductor layer and an n-type semiconductor layer, or a plurality of pn junctions which are repeatedly composed of a plurality of p-type semiconductor layers and an n-type semiconductor layer
  • the semiconductor layer 4 is thin, generally thicker than 2 nm, and can be epitaxially grown Or ion implantation, the number of layers, thickness and doping concentration of the entire semiconductor doped multilayer structure can be adjusted according to the voltage tolerated, and the doping concentration of the n-type and p-type semiconductors can be low, that is, if and p are formed.
  • the power device exemplified in this embodiment is a field effect transistor. Therefore, the epitaxial multilayer structure on the substrate layer includes a barrier layer on the channel layer and a dielectric layer on the surface of the barrier layer. The power device may also be a semiconductor device of other functions. Therefore, for the present invention, the epitaxial multilayer structure is only a semiconductor device that realizes a specific function, and at least includes a nucleation layer, a buffer layer, and a nitride channel layer.
  • FIG. 2B is a modification of the first embodiment of the present invention.
  • the silicon substrate 1 is composed of lightly doped P-silicon and n-type silicon.
  • the bottom of the silicon village 1 is similar to a reverse biased PN junction, forming a space charge depletion region, which can withstand a certain voltage drop and increase the breakdown voltage of the device.
  • FIG. 2C is another variation of the first embodiment of the present invention.
  • the silicon substrate 1 has a three-layer structure composed of heavily doped p+ silicon and lightly doped.
  • the composition of the hetero-P-silicon and n-type silicon, the role of the silicon substrate 1 and the role of the silicon substrate 1 in FIG. 2A and FIG. 2B The same, will not be described here.
  • 3 is a modification of the first embodiment of the present invention, directly performing epitaxial growth or doping process on the top layer of the silicon substrate, so that the semiconductor doped multilayer structure is located on the top layer of the silicon substrate, the nitride nucleation layer 2 and the buffer Layer 3 or the like can be grown directly on the semiconductor doped multilayer structure, which is relatively cylindrical compared to the semiconductor doped multilayer structure located inside the silicon substrate in FIG.
  • FIG. 4 is another modification of the first embodiment of the present invention, directly performing epitaxial growth or doping process on the back side of the silicon substrate, so that the semiconductor doped multi-layer structure is located on the back side of the silicon substrate, compared to the silicon in FIG.
  • the semiconductor doped multi-layer structure on the top layer of the village bottom reduces the difficulty in the growth of the nitride nucleation layer 2 and the buffer layer 3 directly on the semiconductor doped multilayer structure.
  • FIG. 5 is another variation of the first embodiment of the present invention.
  • the number and thickness of the general semiconductor doped multilayer structure are determined by the voltage to be withstood. When the applied voltage is not very high, the semiconductor doped multilayer structure It is not required to be too thick, and the process can be tubular.
  • the semiconductor doped multilayer structure 10 is composed of an n-type semiconductor and a p-type semiconductor, wherein the n-type semiconductor layer is located at the topmost layer near the nitride epitaxy.
  • the n-type semiconductor layer may be a relatively thick lightly doped semiconductor layer
  • the p-type semiconductor layer may be a relatively thin heavily doped semiconductor layer.
  • the semiconductor doped double layer When the drain is positively pressurized and the substrate is grounded, the semiconductor doped double layer
  • the structure is similar to a reverse biased PN junction, forming a space charge depletion region, which can withstand a certain voltage drop and increase the breakdown voltage of the device.
  • the semiconductor doped double layer structure can also be located on the top or back of the silicon substrate.
  • the method includes the steps of:
  • the semiconductor doped multilayer structure can be formed on the inner, top or back surface of the silicon substrate by epitaxial growth or ion implantation, and the number of breakdown voltages is determined according to the required breakdown voltage. The number of layers and the thickness of the semiconductor doped multilayer structure.
  • FIG. 6 is a schematic structural view of a silicon nitride power device on a silicon substrate according to a second embodiment of the present invention.
  • a diode device having a diode structure is employed as an explanation.
  • the semiconductor device of the diode device is incorporated into a semiconductor doped multilayer structure, which can enhance the reverse breakdown voltage of the diode, wherein the electrode 8 is a Schottky junction, as the anode of the diode, and the electrode 7 is an ohmic contact, as a diode negative electrode.
  • FIG. 7 is a schematic structural view of a silicon nitride power device on a silicon substrate according to a third embodiment of the present invention.
  • a MOSFET device of another triode structure is used as an illustration.
  • the MOSFET device is a nitride n-channel MOSFET device, and a semiconductor doped multilayer structure is introduced in the silicon substrate of the device, and the breakdown voltage of the device is greatly improved.
  • the underlying regions of the source and the drain of the nitride channel layer are n-type heavily doped regions, generally doped with silicon, and the lower portion of the gate is p-type lightly doped, generally doped with magnesium, and the dielectric layer under the gate metal is generally Si0. 2 , SiN, A1N, A1 2 0 3 or other insulating dielectric layer.
  • FIG. 8 is a schematic structural view of a silicon nitride power device on a silicon substrate according to a fourth embodiment of the present invention.
  • the GaN layer 11 is grown on the barrier layer. Due to the defects on the surface of the AlGaN barrier layer and the high density of surface states, more than 4 electrons are trapped, which affects the two-dimensional electron gas in the channel, reducing device characteristics and reliability.
  • a layer of GaN as a protective layer on the surface of the barrier layer the defects of the surface of the barrier layer and the influence of the surface state on the device characteristics can be effectively reduced.
  • FIG. 9 is a schematic structural view of a silicon nitride power device on a silicon substrate according to a fifth embodiment of the present invention.
  • Introducing the A1N insertion layer 12 between the barrier layer and the channel layer because the forbidden band width of A1N is very high, the electrons can be more effectively confined in the heterojunction well, and the concentration of the two-dimensional electron gas is increased;
  • A1N insertion The layer also isolates the conductive channel from the AlGaN barrier layer, reducing the scattering effect of the barrier layer on electrons, thereby increasing the mobility of the electrons and improving the overall characteristics of the device.
  • FIG. 10 is a schematic structural view of a silicon nitride power device on a silicon substrate according to a sixth embodiment of the present invention.
  • An AlGaN back barrier layer 13 is introduced between the buffer layer and the channel layer. Under a certain applied voltage, electrons in the channel enter the buffer layer, especially in short channel devices, which makes the gate The control of the channel electrons is relatively weak, and the short channel effect occurs. In addition, there are many defects and impurities in the buffer layer, which may affect the two-dimensional electron gas in the channel, such as causing current collapse.
  • the channel electrons can be isolated from the buffer layer, effectively confining the two-dimensional electron gas in the channel layer, and improving the short channel effect and the current collapse effect.
  • FIG. 11 is a view showing the structure of a nitride power device on a silicon substrate according to a seventh embodiment of the present invention; Intention.
  • An insulating dielectric layer 14 is inserted under the gate to form a MISFET structure. This layer of insulating dielectric serves as both a passivation layer and a gate insulating layer, which can effectively reduce the gate leakage current.
  • the insulating dielectric layer 14 includes one of SiN, Si0 2 , SiON, A1 2 0 3 , Hf0 2 , HfAlOx, or any combination thereof.
  • Fig. 12 is a view showing the structure of a silicon nitride power device on a silicon substrate according to an eighth embodiment of the present invention.
  • a gate field plate 15 and/or a source field plate 16 are further provided on the gate 8 and/or source 6 of the nitride power device.
  • a nitride power device enhanced device can also be realized by changing the structure or device manufacturing process of the nitride channel layer or the barrier layer on the silicon substrate, such as bombarding the material region under the gate metal with fluorine ions. Forming an enhanced device or the like.
  • the present invention provides a silicon-based nitride power device and a method for fabricating the same, by introducing a semiconductor doped multilayer composed of an n-type silicon layer and a p-type silicon layer repeatedly alternating on a silicon substrate.
  • the structure forms a space charge depletion region, which increases the breakdown voltage of the device and reduces the risk of voltage breakdown of the device.
  • the nitride power device of the present invention and the method for fabricating the nitride power device have been described in detail by way of some exemplary embodiments, the above embodiments are not exhaustive, and those skilled in the art may Various changes and modifications are realized within the spirit and scope of the invention. Therefore, the invention is not limited to the embodiments, and the scope of the invention is only limited by the appended claims.
  • the above description has been made by taking a semiconductor doped multilayer structure in which a n-type silicon layer and a p-type silicon layer are alternately alternately formed in a silicon substrate, it should be understood that other structures known to those skilled in the art may be used. Or materials to improve the pressure resistance of the village bottom, the present invention does not have any limitation.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Manufacturing & Machinery (AREA)
  • Materials Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本发明提供了一种氮化物功率器件及其制造方法。该氮化物功率器件在现有器件结构的基础上，在硅村底上制作出p型硅层和n型硅层交替排列的半导体掺杂多层结构，当有外加电压加载到氮化物功率器件上时，每层半导体掺杂结构都会形成一个空间电荷耗尽区，通过一个或多个空间电荷耗尽区的叠加，使得整个器件的击穿电压大大提高，从而降低了器件被电压击穿的风险。同时本发明也提出了上述氮化物功率器件的制作方法。

Description

一种氮化物功率器件及其制造方法 本申请要求于 2013 年 02 月 07 日提交中国专利局、 申请号为 201310049854.4、 发明名称为"一种氮化物功率器件及其制造方法"的中国 专利申请的优先权， 其全部内容通过引用结合在本申请中。 技术领域
本发明属于微电子技术领域， 涉及一种氮化物功率器件， 以及该氮化 物功率器件的制造方法， 尤其是通过在 Si村底中引入可以形成较厚空间电 荷耗尽区的半导体掺杂多层结构， 可以承受较大的外加电压， 从而提高器 件击穿电压。 背景技术
第三代半导体材料氮化镓（GaN ) 由于具有禁带宽度大、 电子饱和漂 移速度高、 击穿场强高、 导热性能好等特点， 已经成为目前的研究热点。 在电子器件方面， 氮化镓材料比硅和砷化镓更适合于制造高温、 高频、 高 压和大功率器件， 因此氮化镓基电子器件具有 4艮好的应用前景。
以往氮化镓功率器件都是在蓝宝石或碳化硅村底上制成的， 由于氮化 镓异质结导电沟道的特殊性及工艺难度所限， 氮化镓功率器件基本都是平 面结构， 因为村底 4艮厚且击穿电场较高， 所以器件一般是横向击穿， 通过 一些平面优化技术， 如场板结构、 增加栅极与漏极距离等可以提高器件的 击穿电压。 但是蓝宝石和碳化硅村底材料比较贵且难以实现大尺寸的村底 材料和外延层， 所以氮化镓功率器件成本^艮高， 难以市场化。
目前在大尺寸硅村底上生长氮化镓功率器件的技术日趋成熟， 并且成 本较低， 是推动氮化镓功率器件市场化的主流方向， 以三极管结构的氮化 镓功率器件为例， 其结构如图 1A所示， 包括硅村底 1、 氮化物成核层 2、 氮 化物緩沖层 3、 氮化物沟道层 4、 氮化物势垒层 5、 介质钝化层 9, 以及包括 源极 6、漏极 7和栅极 8的三个电极。 由于硅材料本身的导电性和低的临界电 场， 硅基氮化镓功率器件都存在一个饱和击穿电压， 该饱和击穿电压由硅 村底上生长的氮化物外延层厚度来决定。 此外， 为了避免器件中静电的积 累而导致 ESD (静电放电）和为了在电路中实现电压匹配， 村底接地是必 不可免的选择， 这导致硅基氮化镓功率器件村底接地时的击穿电压 Vbrl比 浮地击穿电压 Vbr2减小了一半， 如图 1B所示， 即使采用高阻区熔硅， 其电 阻率通常也不超过 104 Ohm.cm, 远小于氮化物电阻率 (>109 Ohm.cm), 无法 起到分压的作用。 所以提高硅村底上氮化物功率器件的击穿电压是目前急 需解决的问题。
通过增加外延层厚度的方法可以提高硅村底氮化物高压器件的击穿电 压， 尽管目前在硅材料上生长氮化物外延层的技术正日趋成熟， 但是因为 硅材料和氮化物之间存在巨大的晶格失配和热失配， 生长的氮化物外延层 厚度受到极大的限制，一般来说大约在 2um至 4um左右，生长过厚的氮化物 外延层不仅会需要更长的时间， 提高成本、 降低产能， 而且外延层的质量 会变差， 容易翘曲或龟裂， 增加工艺难度， 降低成品率等等。
村底接地后， 器件的击穿电压也为纵向击穿所影响。 此纵向击穿电压 由外延层的可耐受电压和硅村底的可耐受电压决定。 所以， 总的纵向击穿 电压可通过改善硅村底的耐压性来提高。
硅村底的厚度一般是固定的， 过厚会增加成本， 并且影响硅上氮化物 外延层的质量， 也会增加工艺难度， 所以通过增加村底厚度来提高硅村底 耐压性并不可行。
在硅半导体器件中，用硅材料制作的 PN二极管可以承受很高的反向外 加电压。 一般是在硅村底中通过掺杂形成 N型掺杂区域和 P型掺杂区域， 两 个掺杂区域内部会形成一个 PN结， 形成空间电荷耗尽区， 空间电荷区内部 导电的电子和空穴非常少， 近似于零， 类似于一个高阻区， 击穿电场比较 高， 可以承受一定的外加电压。 空间电荷区可耐受的电压与其宽度有关， 空间电荷区越宽， 所能耐受的电压越大， 即 PN二极管的击穿电压就越大。 空间电荷区的宽度受掺杂浓度和外加电压的影响， 一般随着外加电压的增 加空间电荷区的宽度逐渐变大， 掺杂浓度较高时空间电荷区较窄， 相比同 样电压下掺杂浓度较低时空间电荷区宽度较宽，可以承受更高的外加电压。 当 N型掺杂区域和 P型掺杂区域内部的电子和空穴被完全耗尽时， 空间电荷 区的宽度便不会再扩展， 继续增加外加电压空间电荷区就会击穿。 因为硅 掺杂工艺成熟稳定， 可以形成不同结构、 不同浓度的掺杂分布， 所以产生 了能够耐受不同电压的 PN二极管。 发明内容
有鉴于此， 可以通过外延掺杂或离子注入的方法在硅村底内部引入厚 度较薄的横向 P型掺杂半导体层和 N型掺杂半导体层， P型掺杂半导体层和 N型掺杂半导体层内部会形成空间电荷区， 空间电荷区内部的导电电子和 空穴被完全耗尽， 空间电荷区基本绝缘， 近似于一个高阻区， 击穿电场比 较高， 可以承受一定的外加电压。 空间电荷区所能耐受的电压与空间电荷 区的宽度有关， 空间电荷区越宽， 可以耐受的电压越大。 随着反向外加电 压的增加， 空间电荷区不断增宽， 所能耐受的电压也不断增大， 因为半导 体掺杂层很薄，所以整个掺杂半导层内部的电子和空穴都会被完全被耗尽， 整个掺杂半导区域都会成为一个高阻区， 可以承受较高的外加电压。 如果 有多层 N型半导体层和 P型半导体层， 就会形成多层的空间电荷耗尽区， 并 且组成一个较厚的空间电荷耗尽区， 可以耐受很高的外加电压， 实际中可 以根据器件所需耐受的电压来决定具体掺杂半导体层的结构。
硅村底中引入的 P型掺杂半导体层和 N型掺杂半导体层所形成的空间 电荷区相当于在导电硅村底中插入了一层高电压耐受层， 提高了硅村底的 耐压性，进而提高了整个器件的击穿电压，尤其是在硅村底接地的情况下， 大大提高了漏极与村底电极之间的纵向击穿电压。
本发明的目的在于提供一种通过在硅村底中引入可以形成空间电荷耗 尽区的半导体掺杂多层结构， 该半导体掺杂多层结构由较薄的 n型硅层和 p 型硅层反复交替组成， 在一定外加电压下， 每一层半导体掺杂层都产生空 间电荷耗尽区， 整个半导体掺杂多层结构形成一个厚的空间电荷耗尽区， 可以承受较大外加电压， 半导体掺杂多层结构越厚， 所形成的空间电荷区 越厚， 可承受的压降越高。 通过这种方法， 可以实现耐高击穿电压的氮化 物功率器件。 另外， 本发明的另一目的在于还提出了上述氮化物功率器件 的制造方法。 根据本发明的一个方面， 提供了一种氮化物功率器件， 包括： 硅村底， 该硅村底包括可以形成空间电荷耗尽区的半导体掺杂多层结构； 在上述硅 村底上的外延多层结构， 该外延多层结构至少包括氮化物成核层、 形成于 所述氮化物成核层上的氮化物緩沖层和形成于所述氮化物緩沖层上的氮化 物沟道层； 以及形成于所述外延多层结构上的电极， 其中所述氮化物功率 器件为三极管结构时， 所述电极包括源极和漏极， 以及源极和漏极之间的 栅极； 所述氮化物功率器件为二极管结构时， 所述电极包括正极和负极。
优选的， 在上述氮化物功率器件中， 上述半导体掺杂多层结构可以是 一层 n型半导体层和一层 p型半导体层组成的 pn结构，含有一个空间耗尽 区； 或者是 n型半导体层和 p型半导体层反复交替组成的多层结构， 含有 多个 pn结， 即多个空间耗尽区。
考虑到硅村底接地时， 氮化物功率器件可以施加正向偏压， 也可以施 加反向偏压， 由单层的 n-型半导体和单层的 p型半导体无法承担双向的电 压压降。 因此， 实用的村底结构需要由多层 n型和 p型半导体层组成。
优选， 在上述氮化物功率器件中， 上述半导体掺杂多层结构中的 n型 半导体层和 p型半导体层厚度大于 2nm, 该半导体掺杂多层结构中的 n型 半导体层和 p型半导体层分别为 n-和 p-型半导体； 整个半导体掺杂多层结 构的层数、 厚度及掺杂浓度可根据所需要耐受的电压调节。
优选， 在上述氮化物功率器件中， 上述半导体掺杂多层结构的制备方 法为外延生长或离子注入。
优选， 在上述氮化物功率器件中， 上述半导体掺杂多层结构可在硅村 底顶层或者内部或者背面形成， 或者是其任意组合。
优选， 在上述氮化物功率器件中， 上述半导体掺杂多层结构中的半导 体， 可以是硅、 锗、 错硅、 碳化硅、 m-v族化合物中的任意一种或其任意 组合。
优选， 在上述氮化物功率器件中， 上述氮化物沟道层上， 设有氮化物 势垒层， 在氮化物沟道层和氮化物势垒层的界面处形成二维电子气。
优选， 在上述氮化物功率器件中， 还包括在上述势垒层上的介质层。 优选， 在上述氮化物功率器件中， 上述介质层包括 SiN、 Si02、 SiON、 A1203、 Hf02、 HfAlOx中的一种， 或者是其任意组合。
优选， 在上述氮化物功率器件中， 还包括在上述势垒层上的氮化镓冒 层。
优选， 在上述氮化物功率器件中， 还包括在上述势垒层和沟道层之间 的 A1N插入层。
优选， 在上述氮化物功率器件中， 还包括在上述緩沖层和沟道层之间 的 AlGaN背势垒层。
优选， 在上述氮化物功率器件中， 上述栅极下有介质层。
优选， 在上述氮化物功率器件中， 上述栅极具有栅场板和 /或源极具有 源场板。
根据本发明的一个方面，提供了一种用于制造氮化物功率器件的方法， 包括以下步骤： 在硅村底中弓 I入可以形成空间电荷耗尽区的半导体掺杂多 层结构； 在上述含有半导体掺杂多层结构的硅村底上生长氮化物成核层； 在上述氮化物成核层上生长氮化物緩沖层； 在上述氮化物緩沖层上生长氮 化物沟道层； 在上述氮化物沟道层上形成接触电极其中所述氮化物功率器 件为三极管结构时， 所述电极包括源极和漏极， 以及源极和漏极之间的栅 极； 所述氮化物功率器件为二极管结构时， 所述电极包括正极和负极。
优选， 在上述用于制造氮化物功率器件的方法中， 上述半导体掺杂多 层结构的制备方法为外延生长或离子注入。 附图说明
相信通过以下结合附图对本发明具体实施方式的说明， 能够使人们更 好地了解本发明上述的特点、 优点和目的， 其中：
图 1A为现有的 Si村底上氮化物功率器件结构示意图；
图 1B 为硅上氮化物功率器件在浮地和村底接地两种情况下的击穿电 压；
图 2A为本发明第一实施方式的氮化物功率器件结构示意图； 图 2B为本发明第一实施方式的一种变形结构； 图 2C为本发明第一实施方式的另一种变形结构；
图 3为本发明第一实施方式的一种变形结构；
图 4为本发明第一实施方式的另一种变形结构；
图 5为本发明第一实施方式的另一种变形结构；
图 6为本发明第二实施方式的硅村底上氮化物功率器件结构示意图； 图 7为本发明第三实施方式的硅村底上氮化物功率器件结构示意图； 图 8为本发明第四实施方式的硅村底上氮化物功率器件结构示意图； 图 9为本发明第五实施方式的硅村底上氮化物功率器件结构示意图； 图 10为本发明第六实施方式的硅村底上氮化物功率器件结构示意图； 图 11为本发明第七实施方式的硅村底上氮化物功率器件结构示意图； 图 12为本发明第八实施方式的硅村底上氮化物功率器件结构示意图。 具体实施方式
如背景技术中所述， 现有的硅村底氮化物功率器件， 由于硅村底接地 后， 整个器件的纵向击穿电压减为原来的一半， 大大加大了器件的电压击 穿几率。
本发明根据现有技术的不足， 提出了一种可以耐高击穿电压的氮化物 功率器件， 该氮化物功率器件在硅村底上制作出 p型硅层和 n型硅层交替 排列的 pn结。 当有外加电压加载到氮化物功率器件上时， 每个 pn结都会 形成一个空间电荷耗尽区， 通过一个或多个空间电荷耗尽区的叠加， 使得 整个器件的击穿电压大大提高， 从而降低了器件被电压击穿的风险。
下面就结合附图对本发明的技术方案做详细介绍。
请参见图 2A, 图 2A为本发明第一实施方式的硅村底上氮化物功率器 件结构示意图。 在本实施方式中， 采用具有三极管结构的场效应管作为说 明， 该氮化物功率器件包括： 硅村底 1 , 该硅村底 1 包括可以形成空间电 荷耗尽区的半导体掺杂多层结构 10; 在上述硅村底 1上的外延多层结构， 该外延多层结构包括； 氮化物成核层 2和緩沖层 3, 緩沖层 3包括 GaN或 A1N或其他氮化物， 起到匹配村底材料和高质量氮化物外延层的作用， 影 响上方由氮化镓 /铝镓氮构成的异质结的晶体质量、表面形貌以及电学性质 等参数； 在緩沖层 3上生长沟道层 4, 沟道层包含非的掺杂 GaN层； 在沟 道层 4上生长势垒层 5, 势垒层包含 AlGaN或其他氮化物； 沟道层 4和势 垒层 5—起组成半导体异质结结构， 在界面处形成高浓度二维电子气， 并 在 GaN沟道层的异质结界面处产生导电沟道； 在势垒层 5上沉积介质层 9 对材料表面进行钝化保护， 介质层包括 SiN、 Si02、 SiON、 A1203、 Hf02、 HfAlOx中的一种， 或者是其任意组合； 在源极 6和漏极 7之间的区域， 介 质层被刻蚀出凹槽， 然后沉积金属形成栅极 8。 在本发明中， 在硅村底上 引入了可以形成空间电荷耗尽区的横向半导体掺杂多层结构 10, 该半导体 掺杂多层结构 10是本发明的一个创新之处，它是由 p型半导体层和 n型半 导体层组成的 pn结，或者由多层 p型半导体层和 n型半导体层反复交替组 成的多个 pn结， 半导体层 4艮薄， 厚度一般大于 2nm, 可通过外延生长或者 离子注入形成， 整个半导体掺杂多层结构的层数、 厚度及掺杂浓度可根据 所需要耐受的电压调节， n型和 p型半导体的掺杂浓度可以很低， 即形成 if和 p-型半导体。 当漏极外加正向电压， 村底接地时， 每一个 pn结都产生 空间电荷耗尽区， 整个半导体掺杂多层结构形成一个 4艮厚的空间电荷耗尽 区， 可以承受很大的压降， 通过这种方法， 器件的击穿电压大大增加。 需 要指出的是， 该实施方式例举的功率器件为场效应管， 因此在村底上的外 延多层结构包括了在沟道层上的势垒层以及势垒层表面的介质层等， 然而 功率器件也可以是其它功能的半导体器件， 因此对于本发明来说， 外延多 层结构仅为实现特定功能的半导体器件时， 最少包括成核层、 緩沖层以及 氮化物沟道层。
图 2B为本发明第一实施方式的一种变形，与图 2A不同之处在于硅村 底 1 , 该硅村底 1由轻掺杂的 P-硅和 n型硅组成， 当漏极加正压， 村底接 地时， 该硅村底 1类似于一个反偏 PN结， 形成空间电荷耗尽区， 可以承 受一定的压降， 提高器件的击穿电压。
图 2C为本发明第一实施方式的另一种变形， 与图 2A和图 2B不同之 处在于硅村底 1 , 该硅村底 1具有三层结构， 由重掺杂的 p+硅、 轻掺杂的 P-硅和 n型硅组成， 该硅村底 1的作用与图 2A和图 2B中硅村底 1的作用 相同， 在此不再赘述。
图 3为本发明第一实施方式的一种变形， 直接在硅村底顶层进行外延 生长或掺杂工艺， 使得半导体掺杂多层结构位于硅村底的顶层， 氮化物成 核层 2和緩沖层 3等可以直接在半导体掺杂多层结构上进行生长， 相比图 2中位于硅村底内部的半导体掺杂多层结构， 该结构制造工艺相对筒化。
图 4为本发明第一实施方式的另一种变形， 直接在硅村底背面进行外 延生长或掺杂工艺， 使得半导体掺杂多层结构位于硅村底的背面， 相比图 3 中位于硅村底顶层的半导体掺杂多层结构， 降低了氮化物成核层 2和緩 沖层 3等直接在半导体掺杂多层结构上进行生长的工艺难度。
图 5为本发明第一实施方式的另一种变形， 一般半导体掺杂多层结构 的层数及厚度由所需要耐受的电压决定， 当外加电压不是很高时， 半导体 掺杂多层结构不需要太厚， 工艺可以筒化， 如图 5所示， 该半导体掺杂多 层结构 10由一层 n型半导体和一层 p型半导体组成，其中 n型半导体层位 于最顶层靠近氮化物外延层， n型半导体层可以是比较厚的轻掺杂半导体 层， p 型半导体层可以是比较薄的重掺杂半导体层， 当漏极加正压， 村底 接地时， 该半导体掺杂双层结构类似于一个反偏 PN结， 形成空间电荷耗 尽区， 可以承受一定的压降， 提高器件的击穿电压， 该半导体掺杂双层结 构也可以位于硅村底的顶层或背面。
制作该第一实施方式的氮化物功率器件时， 包括步骤：
在硅村底中引入可以形成空间电荷耗尽区的半导体掺杂多层结构； 在 上述含有半导体掺杂多层结构的硅村底上生长氮化物成核层； 在上述氮化 物成核层上生长氮化物緩沖层；在上述氮化物緩沖层上生长氮化物沟道层； 在上述氮化物沟道层上形成接触电极。
对于半导体掺杂多层结构， 可以通过外延生长或离子注入， 可以将该 半导体掺杂多层结构制作在硅村底的内部、 顶表面或者背面， 且根据所需 击穿电压的多少， 决定该半导体掺杂多层结构的层数以及厚度。
图 6为本发明第二实施方式的硅村底上氮化物功率器件结构示意图。 在该实施方式中， 采用具有二极管结构的二极管器件作为说明。 在氮化物 二极管器件的硅村底中弓 )入半导体掺杂多层结构， 可以增强二极管的反向 击穿电压， 其中电极 8为肖特基结， 作为二极管的正极， 电极 7为欧姆接 触， 作为二极管的负极。
图 7为本发明第三实施方式的硅村底上氮化物功率器件结构示意图。 在该实施方式中， 采用另一种三极管结构的 MOSFET 器件作为说明。 该 MOSFET器件为氮化物 n沟道 MOSFET器件， 在该器件的硅村底中引入 半导体掺杂多层结构， 器件击穿电压大大提高。 在氮化物沟道层的源极和 漏极下方区域为 n型重掺杂区域，一般掺硅，栅极下方区域为 p型轻掺杂， 一般掺镁， 栅金属下的介质层一般为 Si02、 SiN、 A1N、 A1203或其他绝缘 介质层。
图 8为本发明第四实施方式的硅村底上氮化物功率器件结构示意图。 在势垒层上生长 GaN冒层 11 , 由于 AlGaN势垒层材料表面的缺陷和表面 态密度较大， 会俘获 4艮多电子， 会对沟道中的二维电子气产生影响， 降低 器件特性及可靠性。通过在势垒层表面生长一层 GaN作为保护层可以有效 减小势垒层材料表面的缺陷和表面态对器件特性的影响。
图 9为本发明第五实施方式的硅村底上氮化物功率器件结构示意图。 在势垒层和沟道层之间引入 A1N插入层 12, 因为 A1N的禁带宽度非常高， 可以更有效地将电子限制在异质结势井中，提高了二维电子气的浓度； A1N 插入层还将导电沟道与 AlGaN势垒层隔离开，减小了势垒层对电子的散射 效应， 从而提高电子的迁移率， 使得器件整体特性得以提高。
图 10为本发明第六实施方式的硅村底上氮化物功率器件结构示意图。 在緩沖层和沟道层之间引入 AlGaN背势垒层 13, 在一定外加电压下， 沟 道中的电子会进入緩沖层， 尤其是在短沟道器件中这种现象更为严重， 使 得栅极对沟道电子的控制相对变弱， 出现短沟道效应； 加上緩沖层中的缺 陷和杂质比较多， 会对沟道中的二维电子气产生影响， 如产生电流崩塌。 通过引入 AlGaN背势垒层可以将沟道电子与緩沖层隔离开，将二维电子气 有效地限制在沟道层中， 改善短沟道效应及电流崩塌效应。
图 11 示出了本发明第七实施方式的硅村底上氮化物功率器件结构示 意图。 栅极下方插入绝缘介质层 14, 形成 MISFET结构， 这一层绝缘介质 既作为器件的钝化层， 又是栅极绝缘层， 可有效降低栅极漏电电流。 绝缘 介质层 14包括 SiN、 Si02、 SiON、 A1203、 Hf02、 HfAlOx中的一种， 或者 是其任意组合。
图 12 示出了本发明第八实施方式的硅村底上氮化物功率器件结构示 意图。 该氮化物功率器件的栅极 8和 /或源极 6上进一步设有栅场板 15和 / 或源场板 16。通过在栅极和 /或源极引入场板结构， 能够降低栅极近漏端电 场强度， 减小栅极漏电电流， 进一步提高器件击穿电压。
在本发明基础上， 通过改变硅村底上氮化物沟道层或势垒层的结构或 器件制造工艺， 也可以实现氮化物功率器件增强型器件， 如用氟离子轰击 栅金属下方材料区域可以形成增强型器件等。
综上所述，本发明提出了一种硅村底上氮化物功率器件及其制作方法， 通过在硅村底上引入由 n型硅层和 p型硅层反复交替组成的半导体掺杂多 层结构， 形成了空间电荷耗尽区， 从而加大了器件的击穿电压， 降低了器 件被电压击穿的风险。
以上虽然通过一些示例性的实施例对本发明的氮化物功率器件以及用 于制造氮化物功率器件的方法进行了详细的描述， 但是以上这些实施例并 不是穷举的， 本领域技术人员可以在本发明的精神和范围内实现各种变化 和修改。 因此， 本发明并不限于这些实施例， 本发明的范围仅以所附权利 要求书为准。 例如， 以上虽然以硅村底中由 n型硅层和 p型硅层反复交替 组成的半导体掺杂多层结构为例进行了描述， 但是应该理解， 可以使用本 领域的技术人员公知的其它结构或材料来提高村底耐压性， 本发明对此没 有任何限制。

Claims

权 利 要 求
1.一种氮化物功率器件， 包括：
硅村底， 该硅村底包括可以形成空间电荷耗尽区的半导体掺杂多层结 构；
在上述硅村底上的外延多层结构， 该外延多层结构至少包括氮化物成 核层、 形成于所述氮化物成核层上的氮化物緩沖层和形成于所述氮化物緩 沖层上的氮化物沟道层； 以及
形成于所述外延多层结构上的电极， 其中所述氮化物功率器件为三极 管结构时， 所述电极包括源极和漏极， 以及源极和漏极之间的栅极； 所述 氮化物功率器件为二极管结构时， 所述电极包括正极和负极。
2. 根据权利要求 1所述的氮化物功率器件，其特征在于： 所述半导体 掺杂多层结构为一层 n型半导体层和一层 p型半导体层组成的 pn结，含有 一个空间耗尽区； 或者是 n型半导体层和 p型半导体层反复交替组成的多 层结构， 含有多个 pn结， 即多个空间耗尽区。
3. 根据权利要求 2所述的氮化物功率器件，其特征在于： 所述半导体 掺杂多层结构中的 n型半导体层和 p型半导体层的单层厚度大于 2nm; 该 半导体掺杂多层结构中的 n型半导体层和 p型半导体层分别为 n-和 p-型半 导体； 整个半导体掺杂多层结构的层数、 厚度及掺杂浓度根据所需要耐受 的电压调节。
4. 根据权利要求 1所述的氮化物功率器件，其特征在于： 所述半导体 掺杂多层结构可在硅村底顶层或者内部或者背面形成，或者是其任意组合。
5.根据权利要求 1所述的氮化物功率器件， 其特征在于： 所述半导体 掺杂多层结构中的半导体， 可以是硅、 锗、 错硅、 碳化硅、 m-v族化合物 中的任意一种或其任意组合。
6. 根据权利要求 1所述的氮化物功率器件，其特征在于： 所述氮化物 沟道层上， 进一步设有氮化物势垒层， 在氮化物沟道层和氮化物势垒层的 界面处形成二维电子气。
7. 根据权利要求 6所述的氮化物功率器件，其特征在于： 所述氮化物 势垒层上还设有介质层。
8. 根据权利要求 7所述的氮化物功率器件，其特征在于： 所述介质层 包括 SiN、 Si02、 SiON、 A1203、 Hf02、 HfAlOx中的一种， 或者是其任意 组合。
9.根据权利要求 6所述的氮化物功率器件， 其特征在于： 还包括在上 述氮化物势垒层上的氮化镓冒层。
10. 根据权利要求 6所述的氮化物功率器件，其特征在于： 还包括在 上述氮化物势垒层和氮化物沟道层之间的 A1N插入层。
11. 根据权利要求 1所述的氮化物功率器件，其特征在于： 还包括在 上述緩沖层和沟道层之间的 AlGaN背势垒层。
12. 根据权利要求 1所述的氮化物功率器件，其特征在于： 所述栅极 下方还设有绝缘介质层。
13. 根据权利要求 1所述的氮化物功率器件，其特征在于： 所述栅极 和 /或源极具有场板结构。
14. 一种用于制造氮化物功率器件的方法， 其特征在于包括以下步 骤：
在硅村底中弓 I入可以形成空间电荷耗尽区的半导体掺杂多层结构； 在上述含有半导体掺杂多层结构的硅村底上生长氮化物成核层； 在上述氮化物成核层上生长氮化物緩沖层；
在上述氮化物緩沖层上生长氮化物沟道层；
在上述氮化物沟道层上形成接触电极， 其中所述氮化物功率器件为三 极管结构时， 所述电极包括源极和漏极， 以及源极和漏极之间的栅极； 所 述氮化物功率器件为二极管结构时， 所述电极包括正极和负极。
15. 根据权利要求 14所述一种用于制造氮化物功率器件的方法， 其 特征在于： 所述半导体掺杂多层结构的制备方法为外延生长或离子注入。
PCT/CN2014/071559 2013-02-07 2014-01-27 一种氮化物功率器件及其制造方法 WO2014121710A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2015556386A JP6588340B2 (ja) 2013-02-07 2014-01-27 窒化物パワーデバイスおよびその製造方法
EP14748959.5A EP2955757B1 (en) 2013-02-07 2014-01-27 Nitride power component and manufacturing method therefor
DK14748959T DK2955757T3 (da) 2013-02-07 2014-01-27 Nitrid-effektkomponent og fremgangsmåde til fremstilling deraf

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310049854.4A CN103117303B (zh) 2013-02-07 2013-02-07 一种氮化物功率器件及其制造方法
CN201310049854.4 2013-02-07

Publications (1)

Publication Number Publication Date
WO2014121710A1 true WO2014121710A1 (zh) 2014-08-14

Family

ID=48415625

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/071559 WO2014121710A1 (zh) 2013-02-07 2014-01-27 一种氮化物功率器件及其制造方法

Country Status (5)

Country Link
EP (1) EP2955757B1 (zh)
JP (1) JP6588340B2 (zh)
CN (1) CN103117303B (zh)
DK (1) DK2955757T3 (zh)
WO (1) WO2014121710A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017524246A (ja) * 2014-09-05 2017-08-24 蘇州捷芯威半導体有限公司Ｇｐｏｗｅｒ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ，Ｉｎｃ． 電界効果ダイオード及びその製造方法

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103117303B (zh) * 2013-02-07 2016-08-17 苏州晶湛半导体有限公司 一种氮化物功率器件及其制造方法
CN104347695A (zh) * 2013-07-31 2015-02-11 浙江大学苏州工业技术研究院 一种提高器件纵向耐压能力的半导体装置
CN103500763B (zh) * 2013-10-15 2017-03-15 苏州晶湛半导体有限公司 Ⅲ族氮化物半导体器件及其制造方法
CN103531615A (zh) * 2013-10-15 2014-01-22 苏州晶湛半导体有限公司 氮化物功率晶体管及其制造方法
CN103887325A (zh) * 2013-12-18 2014-06-25 杭州恩能科技有限公司 一种提高器件耐压能力的半导体装置及其制备方法
CN103779208B (zh) * 2014-01-02 2016-04-06 中国电子科技集团公司第五十五研究所 一种低噪声GaN HEMT器件的制备方法
CN103745991B (zh) * 2014-01-22 2016-05-04 西安电子科技大学 基于超结的AlGaN/GaN高压器件及其制作方法
CN105280725B (zh) * 2015-04-17 2019-03-12 苏州捷芯威半导体有限公司 一种氮化镓二极管及其制作方法
CN112201693A (zh) * 2020-09-30 2021-01-08 锐石创芯（深圳）科技有限公司 一种氮化镓半导体器件和制造方法
CN113380877A (zh) * 2021-06-10 2021-09-10 四川美阔电子科技有限公司 一种双结型场板的功率器件

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5060030A (en) * 1990-07-18 1991-10-22 Raytheon Company Pseudomorphic HEMT having strained compensation layer
CN102299071A (zh) * 2010-06-23 2011-12-28 中国科学院微电子研究所 一种提高AlGaN/GaN HEMT频率特性的方法
CN102306659A (zh) * 2011-09-08 2012-01-04 浙江大学 一种基于体电场调制的ldmos器件
CN102903738A (zh) * 2012-09-06 2013-01-30 程凯 Ⅲ族氮化物半导体器件及其制造方法
CN103117303A (zh) * 2013-02-07 2013-05-22 苏州晶湛半导体有限公司 一种氮化物功率器件及其制造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4449467B2 (ja) * 2004-01-28 2010-04-14 サンケン電気株式会社 半導体装置
JP5041701B2 (ja) * 2005-12-07 2012-10-03 日本電信電話株式会社 ヘテロ接合型電界効果トランジスタ
JP2007250721A (ja) * 2006-03-15 2007-09-27 Matsushita Electric Ind Co Ltd 窒化物半導体電界効果トランジスタ構造
JP2007294769A (ja) * 2006-04-26 2007-11-08 Toshiba Corp 窒化物半導体素子
JP2009164158A (ja) * 2007-12-28 2009-07-23 Panasonic Corp 半導体装置及びその製造方法
JPWO2010001607A1 (ja) * 2008-07-03 2011-12-15 パナソニック株式会社 窒化物半導体装置
JP5524462B2 (ja) * 2008-08-06 2014-06-18 シャープ株式会社 半導体装置
WO2011024367A1 (ja) * 2009-08-27 2011-03-03 パナソニック株式会社 窒化物半導体装置
US8513703B2 (en) * 2010-10-20 2013-08-20 National Semiconductor Corporation Group III-nitride HEMT with multi-layered substrate having a second layer of one conductivity type touching a top surface of a first layers of different conductivity type and a method for forming the same
US8502273B2 (en) * 2010-10-20 2013-08-06 National Semiconductor Corporation Group III-nitride HEMT having a well region formed on the surface of substrate and contacted the buffer layer to increase breakdown voltage and the method for forming the same
JP5758132B2 (ja) * 2011-01-26 2015-08-05 株式会社東芝 半導体素子
JP2012231003A (ja) * 2011-04-26 2012-11-22 Advanced Power Device Research Association 半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5060030A (en) * 1990-07-18 1991-10-22 Raytheon Company Pseudomorphic HEMT having strained compensation layer
CN102299071A (zh) * 2010-06-23 2011-12-28 中国科学院微电子研究所 一种提高AlGaN/GaN HEMT频率特性的方法
CN102306659A (zh) * 2011-09-08 2012-01-04 浙江大学 一种基于体电场调制的ldmos器件
CN102903738A (zh) * 2012-09-06 2013-01-30 程凯 Ⅲ族氮化物半导体器件及其制造方法
CN103117303A (zh) * 2013-02-07 2013-05-22 苏州晶湛半导体有限公司 一种氮化物功率器件及其制造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ZHANG, BO ET AL.: "Breakdown Voltage Analysis of a REBULF LDMOS Structure with an n+ Floating Layer", CHINESE JOURNAL OF SEMICONDUCTORS, vol. 27, no. 4, 30 April 2006 (2006-04-30), pages 730, 731 AND 733, XP008181104 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017524246A (ja) * 2014-09-05 2017-08-24 蘇州捷芯威半導体有限公司Ｇｐｏｗｅｒ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ，Ｉｎｃ． 電界効果ダイオード及びその製造方法

Also Published As

Publication number Publication date
CN103117303B (zh) 2016-08-17
CN103117303A (zh) 2013-05-22
JP2016510514A (ja) 2016-04-07
EP2955757A4 (en) 2017-01-11
DK2955757T3 (da) 2019-12-02
EP2955757A1 (en) 2015-12-16
JP6588340B2 (ja) 2019-10-09
EP2955757B1 (en) 2019-09-18

Similar Documents

Publication Publication Date Title
US10985270B2 (en) Nitride power transistor and manufacturing method thereof
WO2014121710A1 (zh) 一种氮化物功率器件及其制造方法
US10026834B2 (en) Method of manufacturing enhanced device and enhanced device
JP6474881B2 (ja) ショットキーダイオード及びその製造方法
TWI759623B (zh) 用於矽上iii-v族元件的摻雜緩衝層及其形成方法
US20130240951A1 (en) Gallium nitride superjunction devices
JP5578873B2 (ja) 窒化ガリウム半導体装置及びその製造方法
CN103972284A (zh) 半导体器件
CN102916046B (zh) 硅衬底上氮化物高压器件及其制造方法
TW201306252A (zh) 氮化物半導體裝置及其製造方法
JP6834546B2 (ja) 半導体装置及びその製造方法
CN108054208B (zh) 横向型氮化镓基场效应晶体管及其制作方法
TW202129970A (zh) 縱向氮化物半導體電晶體裝置
WO2011036921A1 (ja) 半導体装置、電界効果トランジスタおよび電子装置
JP2011142358A (ja) 窒化物半導体装置
CN210897283U (zh) 一种半导体器件
CN107706238A (zh) Hemt器件及其制造方法
TWI760937B (zh) 半導體結構及其製作方法
WO2021218371A1 (zh) 一种iii族氮化物半导体集成电路结构、制造方法及其应用
WO2020216250A1 (zh) 一种增强型器件及其制备方法
TW202220216A (zh) p型氮化鎵高電子移動率電晶體
CN103887325A (zh) 一种提高器件耐压能力的半导体装置及其制备方法
WO2021184299A1 (zh) 半导体结构及其制作方法
JP7170940B2 (ja) 半導体装置
WO2024000433A1 (zh) 一种二极管及其制造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14748959

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2015556386

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 2014748959

Country of ref document: EP