WO2014121574A1 - 阵列基板及液晶显示面板 - Google Patents

阵列基板及液晶显示面板 Download PDF

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Publication number
WO2014121574A1
WO2014121574A1 PCT/CN2013/077181 CN2013077181W WO2014121574A1 WO 2014121574 A1 WO2014121574 A1 WO 2014121574A1 CN 2013077181 W CN2013077181 W CN 2013077181W WO 2014121574 A1 WO2014121574 A1 WO 2014121574A1
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Prior art keywords
sub
pixel
array substrate
electrode
common electrode
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PCT/CN2013/077181
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English (en)
French (fr)
Inventor
姜文博
薛海林
董学
车春城
陈东
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北京京东方光电科技有限公司
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Publication of WO2014121574A1 publication Critical patent/WO2014121574A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/13606—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit having means for reducing parasitic capacitance
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel

Definitions

  • Embodiments of the present invention relate to an array substrate and a liquid crystal display panel. Background technique
  • the ADS mode is a planar electric field wide viewing angle core technology. Specifically, a multi-dimensional electric field is formed by an electric field generated by the edge of the slit electrode in the same plane and an electric field generated between the slit electrode layer and the plate electrode layer, so that the slit electrode in the liquid crystal cell All of the aligned liquid crystal molecules directly above the electrode can be rotated, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency.
  • each sub-pixel unit includes one TFT 104 and one pixel electrode 105; two adjacent rows of gate lines 101 are located between adjacent two rows of sub-pixel units, and the adjacent two rows of sub-pixel units are located in the same column
  • the gates of the TFTs are staggered toward each other, and the adjacent two rows of common electrode lines 103 are separated by two rows of sub-pixel units. As shown in FIG.
  • the drain electrode of the TFT 104 of the sub-pixel unit located in the row of the same column and the first via 106 of the pixel electrode 105 are located in the region of the gate line 101 of the TFT 104 of the next row of sub-pixel units, and are transparent.
  • the projection of the first via 106 on the array substrate completely falls within the projection of the gate line 101 of the sub-pixel unit of the next row on the array substrate.
  • Such a design has a high aperture ratio, but there is a poor blinking. (flicker) phenomenon.
  • each of the TFTs and the oppositely disposed gate lines have overlapping regions on the array substrate in a vertical direction, that is, the voltage of the pixel electrodes varies with the gate line voltage as shown in FIG.
  • Embodiments of the present invention provide an array substrate and a liquid crystal display panel for solving the problem that flicker is present in an image display.
  • An array substrate provided by an embodiment of the invention includes a substrate, a data line and a gate line disposed on the substrate, and a sub-pixel unit surrounded by the data line and the gate line, and each sub-pixel unit includes a thin film transistor (TFT) And a pixel electrode, the source electrode of the TFT is connected to the data line, the drain electrode of the TFT is connected to the pixel electrode, and the gate electrode of the TFT is connected to the gate line; respectively driving the adjacent two rows of sub-pixel units
  • the gate line is located between the two rows of sub-pixel units, and the projection of the drain electrode and the gate line on the array substrate in a direction perpendicular to the array substrate has no overlapping area.
  • the gate lines of the upper row are connected to the next row of sub-pixel units, and the next row of gate lines are connected to the previous row of sub-pixel units, two The gate lines respectively drive the sub-pixel units connected thereto.
  • a TFT of each sub-pixel unit is disposed on a gate line driving the sub-pixel unit, and a drain electrode of the TFT is connected to a pixel electrode in the sub-pixel unit.
  • the pixel electrode includes a portion between the two gate lines and a portion located on both sides of the two gate lines, and the drain electrode and the pixel electrode are located between the two gate lines Partially connected.
  • the common electrode is in a different layer from the gate line and the pixel electrode, and the common electrode is located between the pixel electrode and the gate line;
  • the common electrode is located in a projection area on the array substrate in a direction perpendicular to the array substrate.
  • the drain electrode and the pixel electrode are in different layers and are electrically connected through the first via.
  • the array substrate further includes a plurality of common electrode lines spaced apart from the common electrode and insulated from the common electrode, the common electrode lines being connected to the common electrode through the second via.
  • the array substrate includes a display area and a peripheral area located around the display area, the plurality of common electrode lines are distributed in the display area and the peripheral area, and the common electrode line distributed in the peripheral area is connected to the common electrode
  • the number of second via holes is at least two.
  • the area between two gate lines between adjacent two rows of sub-pixel units is In the opaque region, the pixel electrodes of the sub-pixel units on both sides of the two gate lines extend to the opaque region, and are connected to the corresponding drains in the opaque region.
  • the pixel electrodes of the sub-pixel units of the adjacent two rows of sub-pixel units straddle the gate lines adjacent thereto and are connected to the other of the two gate lines, each The sub-pixel unit includes a common electrode and the common electrode extends between a gate line adjacent to the sub-pixel unit and a pixel electrode of the pixel unit.
  • Embodiments of the present invention provide a liquid crystal display panel including a color filter substrate disposed on a cartridge and the array substrate.
  • the color filter substrate includes a black matrix, and a projection of the gate lines on the array substrate falls within a projection of a black matrix on the array substrate on the color filter substrate.
  • the black matrix corresponding to the gate line position has the same black matrix width as the common electrode line position
  • the black matrix corresponding to the position of the gate line is different from the width of the black matrix corresponding to the position of the common electrode line.
  • An array substrate and a liquid crystal display panel provided by the embodiments of the present invention are provided with an array substrate that satisfies the following conditions: a projection of a drain electrode of the TFT and a gate line in a vertical direction on the array substrate has no overlapping area, thereby preventing image display from being defective in flicker. (flicker) problem.
  • flicker flicker
  • FIG. 1 is a top plan view showing a structure of a TFT array substrate in the prior art
  • FIG. 2 is a timing chart of operation of a gate line and a pixel electrode in the array substrate shown in FIG. 1;
  • FIG. 3 is a top plan view showing an array substrate structure using a single-type TFT according to an embodiment of the present invention
  • FIG. 4 is a schematic cross-sectional view of the array substrate of FIG. 3 taken along line A-A';
  • FIG. 5 is a partial enlarged view of the positional relationship between the first via hole and the second gate line shown in FIG. 4;
  • FIG. 6 is a plan view showing the structure of the array substrate having the second via hole according to an embodiment of the present invention;
  • FIG. 7 is a schematic plan view showing another structure of an array substrate using a single-type TFT according to an embodiment of the present invention.
  • FIG. 8 is a top plan view showing an array substrate structure using a U-shaped TFT according to an embodiment of the present invention.
  • FIG. 9 is a top plan view showing an array substrate structure using an L-type TFT according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of a black matrix setting structure on the premise of a pixel unit composed of R, G, and B sub-pixel units according to an embodiment of the present invention
  • FIG. 11 is a schematic structural diagram of a black matrix setting under the premise of a pixel unit composed of R, G, B, and W sub-pixel units according to an embodiment of the present invention. detailed description
  • the embodiment of the invention provides an array substrate and a liquid crystal display panel for solving the problem of flicker in the process of displaying an image on the liquid crystal display panel.
  • an array substrate includes: a substrate 1; a plurality of gate lines 2 and data lines 3 disposed on the substrate 1 in a horizontally and vertically intersecting manner; (FIG. 3 is a laterally disposed gate line 2 And a data line 3) disposed longitudinally; and a plurality of laterally disposed common electrode lines 4.
  • the gate line 2, the data line 3 and the common electrode line 4 enclose a sub-pixel unit; the plurality of sub-pixel units are arranged in a matrix period, and the area enclosed by the dotted line frame in FIG. 3 is a sub-pixel unit.
  • the area of the array substrate where the sub-pixel unit is located is a light-transmitting area, and the area between adjacent sub-pixel units is an opaque area, such as the area where the common electrode line 4, the data line 3, and the gate line 2 on the array substrate are not transparent. Light area.
  • two adjacent rows of sub-pixel units are provided with two gate lines 2 spaced apart by a certain distance;
  • the two gate lines 2 be a set of gate lines;
  • the common electrode line 4 is located between the adjacent two sets of gate lines. That is, in the opaque region of the substrate 1, the common electrode line 4 and the two adjacent gate lines 2 are spaced apart.
  • the common electrode line 4 is located between two adjacent sub-pixel units, and two adjacent gate lines 1 are located between the other two adjacent sub-pixel units.
  • the sub-pixel units on both sides of the two adjacent grid lines, and the sub-pixel units belonging to the same column are oppositely arranged.
  • the gate line closest to the previous row of sub-pixel units can drive the previous row of sub-pixel units, and can also drive the next row of sub-pixel units; correspondingly, the next row of gate lines is not driven.
  • the first driving method the gate line closest to the previous row of sub-pixel units corresponds to the next row of sub-pixel units, that is, the gate line closest to the previous row of sub-pixel units drives the next row of sub-pixel units.
  • the gate line closest to the next row of sub-pixel units corresponds to the previous row of sub-pixel units, that is, the gate line closest to the next row of sub-pixel units drives the previous row of sub-pixel units.
  • the second driving method the gate line closest to the previous row of sub-pixel units corresponds to the previous row of sub-pixel units, that is, the gate line closest to the previous row of sub-pixel units drives the previous row of sub-pixel units.
  • the gate line closest to the next row of sub-pixel units corresponds to the next row of sub-pixel units, that is, the gate line closest to the next row of sub-pixel units drives the previous row of sub-pixel units.
  • the gate line driving method of the array substrate shown in FIG. 3 is the above-described first driving method.
  • each sub-pixel unit includes: a TFT 5 located in the opaque region and a pixel electrode 6 located in the light-transmitting region; a source electrode of the TFT 5 is electrically connected to the data line 3, and a drain electrode and a pixel electrode 6 of the TFT 5 Electrically connected, the gate electrode of the TFT 5 is connected to the gate line 2.
  • the projection of the drain electrode and any of the gate lines in the vertical direction (the direction perpendicular to the array substrate) on the array substrate has no overlapping area.
  • the drain electrode is connected to the pixel electrode 6 at a connection region 7 as shown in FIG. 3.
  • the connection region 7 and the gate line 2 are along
  • the projection on the array substrate in the vertical direction has no overlapping area.
  • connection region 7 shown in Fig. 3 may be located in a light-transmitting region or an opaque region.
  • connection region 7 is located in the opaque region
  • the pixel electrode 6 located in the light-transmitting region further includes a convex portion located in the opaque region, and the drain electrode of the TFT 5 and the convex portion of the pixel electrode 6 located in the opaque region are electrically Sexual connection. This can avoid the problem that the aperture ratio of the pixel is lowered.
  • the convex portions on the two pixel electrodes 6 belonging to the opposite arrangement of the same column are relatively staggered.
  • the drain electrodes of the TFTs respectively connected to the adjacent two gate lines are connected to the pixel electrodes in the oppositely disposed sub-pixel units, and the connection regions of the drain electrodes and the pixel electrodes and the oppositely disposed gate lines are in the vertical direction.
  • the projections on the array substrate have no overlapping areas.
  • a region between two gate lines between adjacent two rows of sub-pixel units is an opaque region, and pixel electrodes of sub-pixel units on both sides of the two gate lines extend to the opaque region, and Connected to the corresponding drain in the opaque region.
  • FIG. 4 is a cross-sectional view of the array substrate shown in FIG. 3 taken along the line A-A'.
  • a partial cross-sectional schematic view of the array substrate includes:
  • the second gate line 22 is an upper gate line in the array substrate shown in FIG.
  • the method further includes: a gate insulating layer (GI) 8 above the first gate 21 and the second gate line 11, and an active layer 9 (ACT) located above the first gate 21, a source located above the active layer 9.
  • a drain layer 10 a resin layer 11 above the source and drain layer 10 and above the second gate line 22;
  • a first gate 21, a gate insulating layer (GI) 8, an active layer 9, and a source and drain layer 10 constitutes a TFT, that is, a TFT connected to the upper right pixel electrode shown in FIG.
  • a pixel electrode 6 located above the resin layer 11.
  • the pixel electrode 6 includes a portion located in the light transmitting region and a portion located in the opaque region.
  • the pixel electrode portion of the opaque region is electrically connected to the source and drain layer 10 located thereunder through the first via 15.
  • the TFT is located in the non-transparent area of the array substrate, and does not affect the aperture ratio of each sub-pixel unit.
  • the drain electrode of the TFT located in the non-transmissive region is electrically connected to the pixel electrode portion located in the non-transmissive region, so as to ensure that the aperture ratio of the pixel is not affected.
  • leak The projection of the electrode and the oppositely disposed gate line on the array substrate in the vertical direction has no overlapping area. In this way, it is possible to solve the problem that the display image has flicker. This is because the flicker defect is mainly due to the influence of the TFT gate line. Specifically, there is an overlap region between the pixel electrode and the gate line in the vertical direction, resulting in a certain forward capacitance between the pixel electrode and the gate line.
  • the embodiment of the present invention satisfies the following conditions by providing the array substrate: the connection area of the drain electrode and the pixel electrode and the projection of the oppositely disposed gate line on the array substrate in the vertical direction have no overlapping area. There is no positive capacitance C between the connection region of the drain electrode and the pixel electrode and the gate line, which reduces ⁇ , so that the voltage of the pixel electrode is not pulled down twice after the completion of charging, thereby solving the flicker serious problem.
  • the array substrate provided by the embodiment of the present invention further includes a common electrode 16 between the pixel electrode 6 and the resin layer 11; the common electrode 16 passes through the second via hole (not shown in FIG. 4) and FIG.
  • the common electrode lines 4 are connected.
  • a schematic cross-sectional view of a portion of the array substrate shown in FIG. 4 includes a common electrode 16 and a passivation protective layer (PVX) 17 between the common electrode 16 and the pixel electrode 6.
  • PVX passivation protective layer
  • the second gate line 22 is prevented from causing a pull-down on the operating voltage of the pixel electrode 6, which causes a flicker defect, which is provided by the embodiment of the present invention.
  • the common electrode 16 covers the entire second gate line 22, thereby preventing the influence of the second gate line 22 on the pull-down of the pixel electrode 6. That is, the common electrode 16 is located below the pixel electrode 6 and above the second gate line 22; the second gate line 22 is located at a projection area of the common electrode 16 on the array substrate in the vertical direction.
  • the pixel electrodes of the sub-pixel units in the adjacent two rows of sub-pixel units straddle the gate lines adjacent thereto, and in the two adjacent gate lines Another gate line is connected, and the common electrode 16 of each sub-pixel unit extends between the gate line 22 adjacent to the sub-pixel unit and the pixel electrode 6 of the pixel unit, so that the second gate line 22 can be opposite to the pixel electrode 6. influences.
  • FIG. 5 is a partially enlarged schematic view showing the positional relationship between the second gate line 22 and the maximum cross section of the common electrode 16 and the first via hole 15.
  • the second gate line 22 is located in the projection area of the common electrode 16 on the array substrate in the vertical direction, and the first via hole 15 is located in the second gate line 22 Outside the area where you are.
  • the common electrode lines are arranged periodically or non-periodically on the array substrate. In the array substrate shown in Fig. 3, the common electrode lines are periodically arranged on the array substrate.
  • a plurality of rows of sub-pixel units may be spaced between adjacent two rows of common electrode lines, and the number of rows of sub-pixel units between any two adjacent rows of common electrode lines may be the same or different.
  • a plurality of common electrode lines may be connected to the common electrode in the display area or in the peripheral non-display area (peripheral area).
  • connection relationship between the common electrode line and the common electrode is:
  • Each of the common electrode lines is connected to the common electrode through a second via. Specifically, the common electrode line is periodically electrically connected to the common electrode located above it through the second via hole, and the parallel resistance reduces the resistance of the common electrode.
  • Fig. 6 a schematic plan view of the common electrode line 4 on the substrate 1 and the common electrode 16 above it is connected through the second via hole 18.
  • the common electrode line 4 located only in the peripheral region is connected to the common electrode 16 through the second via hole 18.
  • the number of the second via holes 18 connected to the common electrode by each of the common electrode lines 4 is at least two.
  • the TFT array substrate shown in Fig. 3 can also be modified as shown in Fig. 7. Among them, the difference is only in the position where the TFT is located.
  • the TFTs shown in FIG. 3 and FIG. 7 are "one"-type TFTs, and the present invention is not limited to the TFTs of this structure. For example, "U"-type and “L"-type TFTs may be used, respectively. As shown in Figure 8 and Figure 9.
  • connection of the data lines in the array substrate is not limited to the connection manner in the above and the drawings, and other data line connection shapes may be adopted; the drain electrode and the pixel electrode may not pass. Hole connection, other methods can also be adopted, such as connecting by lap joint, as long as the connection is realized.
  • the above TFT array substrate is applied to a liquid crystal display panel provided by the present invention, that is, the display panel includes a color filter substrate provided on the cartridge and the array substrate.
  • the projection of the gate line on the array substrate falls within the projection of the black matrix on the array substrate on the color filter substrate.
  • the black matrix corresponding to the gate line position and the black matrix shape corresponding to the common electrode line may be the same on the color film substrate side, as the case may be.
  • the black matrix corresponding to the gate line position has the same shape as the black matrix corresponding to the common electrode line, and the horizontal streaking phenomenon can be avoided.
  • the black matrix corresponding to the gate line position has the same shape as the black matrix corresponding to the common electrode line, and horizontal crossing can be avoided. Bad pattern.
  • FIG. 10 it is a schematic diagram of an array substrate structure composed of a red sub-pixel unit (R), a green sub-pixel unit (G), and a blue sub-pixel unit (B) for one pixel unit.
  • R red sub-pixel unit
  • G green sub-pixel unit
  • B blue sub-pixel unit
  • the opaque region where the gate line 2 is located corresponds to the width of the black matrix on the color filter substrate, and the opaque region where the gate line is located corresponds to the black matrix on the color filter substrate.
  • the width is A.
  • the opaque region where the common electrode line 4 is located corresponds to the width of the black matrix on the color filter substrate, and the opaque region where the gate line is located corresponds to the width of the black matrix on the color filter substrate B.
  • A B.
  • the width of the black matrix on the corresponding area of the gate line on the color filter substrate It is equal to the width of the black matrix corresponding to the area corresponding to the common electrode line.
  • sub-pixel units of the three colors constituting one pixel unit are not limited to the above-described three types of red, green, and blue.
  • the black matrix corresponding to the gate line position is different from the black matrix shape corresponding to the common electrode line.
  • a black matrix corresponding to the gate line position and a black matrix corresponding to the common electrode line The shape is different.
  • one pixel unit (such as R, G, B, W shown in the black thick line box) is composed of four sub-pixels of R, G, B, and W located in two rows, but if it is 1, G, B, W, cause A pixel unit is formed for the upper and lower four sub-pixel units, so the BM width above the gate line (or TFT) and the BM width above the common electrode line may also be different, that is, A ⁇ B. Since R, G, B, and W are one pixel unit, no horizontal stripes appear in the pixel unit, and the arrangement between the pixel units is periodically set to be equal, and no horizontal stripes are formed between the pixel units.
  • the sub-pixel units of the four colors constituting one pixel unit are not limited to the above-mentioned four types of red, green, blue, and white.
  • the embodiment of the invention further provides a display device comprising the liquid crystal display panel.
  • the display device can be an ADS mode liquid crystal panel, a liquid crystal display, a liquid crystal television, or the like.
  • a TFT array substrate, a liquid crystal display panel, and a display device provided by the embodiments of the present invention provide an array substrate that satisfies the following conditions: the drain electrode of the TFT and the projection of the gate line on the array substrate in the vertical direction are not Overlapping areas to avoid image display of flickering flicker problems. At the same time, the influence of the gate or the gate line directly under the pixel electrode on the image display of the pixel electrode is avoided, and the occurrence of flicker defect is further avoided, and the display quality of the image is improved.

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Abstract

一种阵列基板及液晶显示面板。阵列基板包括基板（1），基板上交叉设置的数据线（3）和栅线（2），以及亚像素单元。亚像素单元由数据线（3）和栅线（2）围设而成，包括TFT（5）和像素电极（6），TFT（5）的源电极与数据线（3）连接，TFT（5）的漏电极与像素电极（6）相连，TFT（5）的栅电极与栅线（2）相连。分别驱动相邻两行相对设置的亚像素单元的栅线（2）位于两行亚像素单元之间。漏电极与像素电极（6）的连接区域（7）与栅线（2）沿垂直方向在阵列基板上的投影无重叠区域。

Description

阵列基板及液晶显示面板 技术领域
本发明的实施例涉及一种阵列基板及液晶显示面板。 背景技术
ADS模式是平面电场宽视角核心技术， 具体地， 通过同一平面内狭缝电 极边缘所产生的电场以及狭缝电极层与板状电极层间产生的电场形成多维电 场，使液晶盒内狭缝电极间、电极正上方所有取向液晶分子都能够产生旋转， 从而提高了液晶工作效率并增大了透光效率。
随着高级超维场转换技术（ Advanced Super Dimension Switch, ADS )液 晶显示产品需求量的不断增加， 高开口率， 较高良品率是每一个厂家不断追 求的目标。
参见图 1 , 为一种高开口率的阵列基板。 包括交叉设置的栅线 101和数 据线 102、 公共电极线 103以及由数据线 102和栅线 101围设形成的亚像素 单元（图 1仅示出相邻两列亚像素单元中的上下两个亚像素单元） ， 每个亚 像素单元包括一个 TFT104和一个像素电极 105; 相邻两行栅线 101位于相 邻两行亚像素单元之间，该相邻两行亚像素单元中位于同一列的 TFT的栅极 交错相向，相邻两行公共电极线 103之间相隔两行亚像素单元。如图 1所示， 位于同一列上一行的亚像素单元的 TFT104的漏电极与像素电极 105的第一 过孔 106, 位于下一行亚像素单元的 TFT104的栅线 101的区域内， 在透光 方向上， 该第一过孔 106的在阵列基板上的投影完全落在下一行的亚像素单 元的栅线 101在阵列基板上的投影内， 这样的设计方式开口率较高， 但是存 在一个闪烁不良（flicker )现象。 具体地， 每一 TFT与相对设置的栅线沿垂 直方向在阵列基板上的投影有重叠区域， 也就是说， 像素电极的电压随栅线 电压的变化如图 2所示， 像素电极的电压在第一栅线充电完成后会出现一次 下降， 这就是常说的 AVp, 但是由于像素电极与相邻的第二栅线存在垂直方 向的重叠区域， 使得相邻栅线的电压降会降影响本像素电极的电压， 会使得 电压再下拉一次。 因此会使得图像显示出现闪烁不良现象。 发明内容
本发明实施例提供了一种阵列基板及液晶显示面板， 用以解决图像显示 存在闪烁不良（flicker ) 的问题。
本发明实施例提供的一种阵列基板， 包括基板， 基板上交叉设置的数据 线和栅线， 以及由数据线和栅线围设而成的亚像素单元， 各亚像素单元包括 薄膜晶体管 （TFT )和像素电极， TFT的源电极与所述数据线连接， TFT的 漏电极与所述像素电极相连， TFT的栅电极与所述栅线相连； 分别驱动相邻 两行相对设置的亚像素单元的栅线位于所述两行亚像素单元之间， 所述漏电 极与所述栅线沿与阵列基板垂直的方向在阵列基板上的投影无重叠区域。
在一个示例中， 所述相邻两行亚像素单元之间的两条栅线中， 上一行的 栅线与下一行亚像素单元连接， 下一行栅线与上一行亚像素单元连接， 两条 栅线分别驱动与之相连的亚像素单元。
在一个示例中，所述各亚像素单元的 TFT设置在驱动该亚像素单元的栅 线上， 所述 TFT的漏电极与所述亚像素单元中的像素电极连接。
在一个示例中， 所述像素电极包括位于两条栅线之间的部分以及位于两 条栅线两侧的部分， 所述漏电极与所述像素电极中所述位于两条栅线之间的 部分连接。
在一个示例中， 还包括公共电极， 所述公共电极与所述栅线和像素电极 位于不同层且相绝缘， 所述公共电极位于所述像素电极和所述栅线之间； 所 述栅线位于所述公共电极沿与阵列基板垂直的方向在阵列基板上的投影区域 内。
在一个示例中， 所述漏电极与所述像素电极位于不同层， 且通过第一过 孔电性连接。
在一个示例中， 该阵列基板还包括与公共电极位于不同层且与公共电极 相绝缘的多条公共电极线， 所述各公共电极线通过第二过孔与所述公共电极 连接。
在一个示例中， 所述阵列基板包括显示区域以及位于显示区域周围的外 围区域， 所述多条公共电极线分布在显示区域和外围区域， 分布在外围区域 的公共电极线与公共电极连接的所述第二过孔的数量至少为两个。
在一个示例中， 位于相邻两行亚像素单元之间的两条栅线之间的区域为 不透光区域，该两条栅线两侧的亚像素单元的像素电极延伸到该不透光区域， 并且在该不透光区域内与相应的漏极连接。
在一个示例中， 所述相邻两行亚像素单元中的各亚像素单元的像素电极 跨过与之相邻的栅线， 并与所述两条栅线中的另一个栅线相连， 各亚像素单 元包括公共电极且该公共电极延伸到与该亚像素单元相邻的栅线与该像素单 元的像素电极之间。
本发明实施例提供一种液晶显示面板， 包括对盒设置的彩膜基板和所述 阵列基板。
在一个示例中， 所述彩膜基板包括黑矩阵， 所述栅线在所述阵列基板上 的投影落在所述彩膜基板上黑矩阵在所述阵列基板上的投影内。
在一个示例中， 在彩膜基板侧， 当一个像素单元由三种颜色的亚像素单 元组成时， 所述栅线位置对应的黑矩阵与所述公共电极线位置对应的黑矩阵 宽度相同；
当一个像素单元由至少四种颜色的亚像素单元组成时， 所述栅线位置对 应的黑矩阵与所述公共电极线位置对应的黑矩阵宽度不相同。
本发明实施例提供的一种阵列基板及液晶显示面板， 通过设置满足如下 条件的阵列基板： TFT的漏电极与栅线沿垂直方向在阵列基板上的投影无重 叠区域， 避免图像显示存在闪烁不良（flicker ) 的问题。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为现有技术中 TFT阵列基板结构的俯视示意图；
图 2为图 1所示的阵列基板中栅线和像素电极工作时序图；
图 3为本发明实施例提供的一种采用一字型 TFT的阵列基板结构的俯视 示意图；
图 4为图 3所述的阵列基板在 A-A'向的截面示意图；
图 5为图 4所示的第一过孔与第二栅线之间位置关系的局部放大图； 图 6 为本发明实施例提供的具有第二过孔的阵列基板结构的俯视示意 图；
图 7为本发明实施例提供的另一种采用一字型 TFT的阵列基板结构的俯 视示意图；
图 8为本发明实施例提供的一种采用 U型 TFT的阵列基板结构的俯视 示意图；
图 9为本发明实施例提供的一种采用 L型 TFT的阵列基板结构的俯视示 意图；
图 10为本发明实施例提供的由 R、 G、 B亚像素单元组成的像素单元的 前提下， 黑矩阵设置结构示意图；
图 11为本发明实施例提供的由 R、 G、 B、 W亚像素单元组成的像素单 元的前提下， 黑矩阵设置结构示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
本发明实施例提供了一种阵列基板及液晶显示面板， 用以解决液晶显示 面板在显示图像的过程中， 存在闪烁不良（flicker ) 的问题。
下面通过附图具体说明本发明实施例提供的技术方案。
参见图 3, 本发明实施例提供的阵列基板， 包括： 基板 1 , 位于基板 1 上的多条呈横纵交叉设置的栅线 2和数据线 3; (如图 3中横向设置的栅线 2 和纵向设置的数据线 3 ) ； 以及多条横向设置的公共电极线 4。
栅线 2、 数据线 3以及公共电极线 4围成一个亚像素单元； 多个亚像素 单元呈矩阵周期排列， 如图 3中虚线框所围区域为一个亚像素单元。 亚像素 单元所在阵列基板的区域为透光区域， 相邻亚像素单元之间的区域为不透光 区域， 如阵列基板上公共电极线 4、 数据线 3和栅线 2所在的区域为不透光 区域。
如图 3, 相邻两行亚像素单元之间设置有两条间隔有一定距离的栅线 2; 设这两条栅线 2为一组栅线； 公共电极线 4位于相邻的两组栅线之间。 即， 在基板 1的不透光区域， 公共电极线 4和两条紧邻的栅线 2间隔排列。 公共 电极线 4位于两行相邻的亚像素单元之间， 两条紧邻的栅线 1位于其他两行 相邻的亚像素单元之间。
如图 3 , 紧邻的两条栅线两侧的亚像素单元， 且属于同一列的亚像素单 元相对设置。
本发明实施例， 距离上一行亚像素单元最近的栅线（称为上一行栅线） 可以驱动上一行亚像素单元， 也可以驱动下一行亚像素单元； 相应地， 下一 行栅线驱动未被上一行栅线驱动的下一行亚像素单元或者上一行亚像素单 元。
即包括两种驱动方式。
第一种驱动方式： 距离上一行亚像素单元最近的栅线与下一行亚像素单 元对应， 即距离上一行亚像素单元最近的栅线驱动下一行亚像素单元。 距离 下一行亚像素单元最近的栅线（靠下的栅线）与上一行亚像素单元对应， 即， 距离下一行亚像素单元最近的栅线驱动上一行亚像素单元。
第二种驱动方式： 距离上一行亚像素单元最近的栅线与该上一行亚像素 单元对应， 即距离上一行亚像素单元最近的栅线驱动该上一行亚像素单元。 距离下一行亚像素单元最近的栅线（靠下的栅线）与该下一行亚像素单元对 应， 即， 距离该下一行亚像素单元最近的栅线驱动上一行亚像素单元。
图 3所示的阵列基板的栅线驱动方式为上述第一种驱动方式。
如图 3所示， 每一亚像素单元包括： 位于不透光区域的 TFT5和位于透 光区域的像素电极 6; TFT5的源电极与数据线 3电性连接， TFT5的漏电极 与像素电极 6电性相连， TFT5的栅电极与栅线 2相连。
漏电极与任何一条栅线沿垂直方向 （垂直于阵列基板的方向）在阵列基 板上的投影无重叠区域。
漏电极与像素电极 6连接位置如图 3所示的连接区域 7, 当漏电极与栅 线 2沿垂直方向在阵列基板上的投影无重叠区域时， 相应地， 连接区域 7与 栅线 2沿垂直方向在阵列基板上的投影无重叠区域。
例如， 图 3所示的连接区域 7可以位于透光区域或不透光区域。
如果连接区域设置在透光区域会引起像素的开口率降低的问题。 例如， 连接区域 7位于不透光区域时， 位于透光区域的像素电极 6还包 括位于不透光区域的凸起部分， TFT5的漏电极与像素电极 6位于不透光区 域的凸起部分电性连接。 这样可以避免像素的开口率降低的问题。
属于同一列相对设置的两个像素电极 6上的凸起部分相对交错设置。 例如，分别与所述相邻两条栅线连接的 TFT的漏电极与相对设置的亚像 素单元中的像素电极连接， 该漏电极与像素电极的连接区域与相对设置的栅 线沿垂直方向在阵列基板上的投影无重叠区域。
例如， 位于相邻两行亚像素单元之间的两条栅线之间的区域为不透光区 域， 该两条栅线两侧的亚像素单元的像素电极延伸到该不透光区域， 并且在 该不透光区域内与相应的漏极连接。
为了更清楚说明上述实施例提供的阵列基板上各部分之间的位置关系。 下面通过图 4说明， 图 4为图 3所示的阵列基板在 A-A'向的截面图。
参见图 4, 阵列基板的部分截面示意图包括：
基板 1;
位于基板 1上的第一栅极 21和第二栅线 22;第一栅极 21与图 3所示的 阵列基板中的靠下的一条栅线对应。第二栅线 22为图 3所示的阵列基板中的 靠上的一条栅线。
还包括： 第一栅极 21和第二栅线 11上方的栅极绝缘层（GI ) 8, 以及 位于第一栅极 21上方的有源层 9 ( ACT ) , 位于有源层 9上方的源漏极层 10,位于源漏极层 10上方的以及第二栅线 22上方的树脂层 11;第一栅极 21、 栅极绝缘层（GI ) 8、 有源层 9, 以及源漏极层 10构成一个 TFT, 也即构成 一个与图 3所示的右上方的像素电极相连的 TFT。
还包括： 位于树脂层 11上方的像素电极 6。 像素电极 6包括位于透光区 域的部分和位于不透光区域的部分。 不透光区域的像素电极部分通过第一过 孔 15与位于其下方的源漏极层 10电性相连。
本发明实施例提供的阵列基板， 相邻两行亚像素单元之间的两条栅线分 别用于驱动所述相邻的两行亚像素单元中的其中之一行。 本发明中， TFT位 于阵列基板的非透光区域， 不影响每一亚像素单元的开口率。
本发明实施例提供的阵列基板，位于非透光区域的 TFT的漏电极与位于 非透光区域的像素电极部分电性相连， 保证不影响像素的开口率。 另外， 漏 电极与相对设置的栅线沿垂直方向在阵列基板上的投影无重叠区域。 这样， 可以解决显示图像存在闪烁不良（flicker )的问题。 这是因为， flicker不良主 要是由于 TFT栅线的影响所致， 具体地， 是因为像素电极与栅线之间在垂直 方向有重叠区域， 导致像素电极与栅线之间存在一定的正向电容 C, 相应地 会使得已经充电后的电压处于一定值的像素电极的电压被拉低。 电压的拉低 产生 Δνρ, 而如果处理不好就会在显示图像产生的抖动现象， 也即图像存在 flicker的现象， 这种现象称为 flicker不良。 本发明实施例通过设置阵列基板 满足如下条件： 漏电极与像素电极的连接区域与相对设置的栅线沿垂直方向 在阵列基板上的投影无重叠区域。 实现漏电极与像素电极的连接区域与栅线 之间不存在正对电容 C, 减小了 Δνρ, 也就使得像素电极的电压在充电完成 之后不会连续两次被拉低， 从而解决了 flicker严重的问题。
参见图 4, 本发明实施例提供的阵列基板还包括位于像素电极 6与树脂 层 11之间的公共电极 16; 公共电极 16通过第二过孔（图 4中未示出）与图 3所示的公共电极线 4相连。
如图 4所示的阵列基板部分截面示意图， 包括公共电极 16, 以及位于公 共电极 16和像素电极 6之间的钝化保护层（ PVX ) 17。
例如，为了避免图 5所示像素电极 6受其下方的第二栅线 22的影响，从 而避免第二栅线 22对像素电极 6的工作电压造成下拉， 引起 flicker不良， 本发明实施例提供的公共电极 16覆盖整个第二栅线 22, 从而防止第二栅线 22对像素电极 6下拉的影响。 即公共电极 16位于像素电极 6下方以及第二 栅线 22上方；第二栅线 22位于公共电极 16沿垂直方向在阵列基板上的投影 区域。
例如， 如图 3和图 4所示， 相邻两行亚像素单元中的各亚像素单元的像 素电极跨过与之相邻的栅线，并与所述两条相邻的栅线中的另一条栅线相连， 各亚像素单元的公共电极 16延伸到与该亚像素单元相邻的栅线 22与该像素 单元的像素电极 6之间， 从而能够第二栅线 22对像素电极 6的影响。
图 4所示的第一过孔 15的最大截面沿垂直方向在阵列基板上的投影与第 二栅线 22无重叠区域。如图 5所示为第二栅线 22与公共电极 16和第一过孔 15的最大截面之间的位置关系局部放大示意图。 第二栅线 22位于公共电极 16沿垂直方向在阵列基板上的投影区域内， 且第一过孔 15位于第二栅线 22 所在的区域之外。
公共电极线位于阵列基板上周期性或者非周期性地排列。 图 3所示的阵 列基板， 公共电极线位于阵列基板上周期性排列。
也就是说， 相邻两行公共电极线之间可以间隔多行亚像素单元， 任意相 邻两行公共电极线之间的亚像素单元的行数可以相同或不同。
多条共电极线可以通过在显示区域内与公共电极连接， 也可以在周边非 显示区域（外围区域） 内连接。
公共电极线与公共电极的连接关系为：
各公共电极线通过第二过孔与所述公共电极连接。 具体地， 公共电极线 通过第二过孔周期性地和位于其上方的公共电极电性连接， 起到并联电阻减 小公共电极电阻的作用。 参见图 6, 为基板 1上的公共电极线 4与位于其上 方的公共电极 16通过第二过孔 18连接的俯视示意图。
或者仅位于外围区域的公共电极线 4通过第二过孔 18与所述公共电极 16连接。
如图 6所示， 通过过孔与公共电极相连的公共电极线中， 每一公共电极 线 4与公共电极连接的第二过孔 18的数量至少为两个。
图 3所示的 TFT阵列基板， 还可以采用如图 7所示的变形。 其中， 区别 仅在 TFT所处的位置不同。 另外， 图 3和图 7中所示的 TFT采用的是"一" 字型 TFT, 本发明并不限制与此结构的 TFT, 例如还可以采用" U"型和" L"型 的 TFT, 分别如图 8和图 9所示。
需要说明的是， 本发明实施例提供的阵列基板中数据线的连接并不限于 上述及附图中的连接方式， 也可以采用其他的数据线连接形状； 漏电极和像 素电极也可以不通过过孔连接， 也可以采取其他的方式， 如通过搭接的方式 进行连接， 只要实现连接即可。
上述 TFT阵列基板， 应用于本发明提供的一种液晶显示面板， 即该显示 面板包括对盒设置的彩膜基板和上述阵列基板。
例如， 该液晶显示面板中， 所述栅线在阵列基板上的投影落在彩膜基板 上黑矩阵在阵列基板上的投影内。
例如， 所述液晶显示面板， 在彩膜基板侧， 所述栅线位置对应的黑矩阵 与所述公共电极线对应的黑矩阵形状可以也可以相同， 视情况而论。 当一个像素单元由三个亚像素单元组成时， 栅线位置对应的黑矩阵与所 述公共电极线对应的黑矩阵形状相同， 可以避免横纹不良现象。
例如： 当一个像素单元由红（R ) 、 绿（G ) 、 蓝（B )亚像素单元组成 时， 栅线位置对应的黑矩阵与所述公共电极线对应的黑矩阵形状相同， 可以 避免横纹不良现象。
如图 10所示， 为一个像素单元由红色亚像素单元（R ) 、 绿色亚像素单 元（G )、 蓝色亚像素单元（B )组成的阵列基板结构示意图。 每一行亚像素 单元中， 相邻的三个 R、 G、 B亚像素单元组成一个像素单元。
如图 10所示，栅线 2所在的不透光区域（对应虚线框所围区域）对应彩 膜基板上的黑矩阵的宽度， 栅线所在的不透光区域对应彩膜基板上的黑矩阵 的宽度为 A。
公共电极线 4所在的不透光区域（对应虚线框所围区域）对应彩膜基板 上的黑矩阵的宽度， 栅线所在的不透光区域对应彩膜基板上的黑矩阵的宽度 为 B, 其中 A=B。
也就是说，一个像素单元由红色亚像素单元（R )、绿色亚像素单元（G )、 蓝色亚像素单元（B )组成时， 彩膜基板上的对栅线对应区域的黑矩阵的宽 度等于对公共电极线对应区域的黑矩阵的宽度。 由于上下相邻两个像素 TFT 相对， 所以黑矩阵 BM遮挡外沿和栅极线外沿平行， 常规 RGB并列排布的 方式下， 形成和公共电极线上方宽度相同的外形平整的 BM遮挡， 即 A=B, 这样所有像素的开口大小相同外观一致， 避免了相邻行 BM差异而产生的横 纹。
当然，组成一个像素单元的三种颜色的亚像素单元不限于上述的红、绿、 蓝三种。
当一个像素单元由至少四种颜色的亚像素单元组成时， 栅线位置对应的 黑矩阵与所述公共电极线对应的黑矩阵形状不相同。
例如： 当一个像素单元由红（R ) 、 绿（G ) 、 蓝（B )和白 （W ) 色亚 像素单元组成时， 栅线位置对应的黑矩阵与所述公共电极线对应的黑矩阵形 状不相同。
如图 11所示， 一个像素单元（如黑粗线框中所示的 R、 G、 B、 W ) 由 位于两行的 R、 G、 B、 W四个子像素组成时， 但如果是1 、 G、 B、 W、 因 为上下 4个亚像素单元构成了一个像素单元， 因此栅线（或者 TFT )上方 BM 宽度和公共电极线上方 BM宽度也可以不相同， 即 A≠B。 由于 R、 G、 B、 W作为一个像素单元， 该像素单元内不会出现横纹， 且像素单元之间的设置 是周期性等大设置的， 像素单元之间不会出现横纹。
同理，组成一个像素单元的四种颜色的亚像素单元不限于上述的红、绿、 蓝、 白四种。
本发明实施例还提供一种显示装置， 包括所述液晶显示面板。 显示装置 可以为 ADS模式的液晶面板、 液晶显示器、 液晶电视等。
综上所述， 本发明实施例提供的一种 TFT阵列基板、 液晶显示面板及显 示装置， 通过设置满足如下条件的阵列基板： TFT的漏电极与栅线沿垂直方 向在阵列基板上的投影无重叠区域， 来避免图像显示存在闪烁不良 flicker的 问题。同时避免了像素电极正下方的栅极或栅线对像素电极图像显示的影响， 更进一步避免了 flicker不良的发生， 提高图像的显示质量。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种阵列基板， 包括基板， 基板上交叉设置的数据线和栅线， 以及由 数据线和栅线围设而成的亚像素单元， 各亚像素单元包括薄膜晶体管（TFT ) 和像素电极， TFT的源电极与所述数据线连接， TFT的漏电极与所述像素电 极相连， TFT的栅电极与所述栅线相连， 其中，
分别驱动相邻两行相对设置的亚像素单元的栅线位于所述两行亚像素单 元之间，
所述漏电极与所述栅线沿垂直于阵列基板的方向在阵列基板上的投影无 重叠区域。
2、根据权利要求 1所述的阵列基板， 其中， 所述相邻两行亚像素单元之 间的两条栅线中， 上一行的栅线与下一行亚像素单元连接， 下一行栅线与上 一行亚像素单元连接， 两条栅线分别驱动与之相连的亚像素单元。
3、 根据权利要求 2所述的阵列基板， 其中， 所述各亚像素单元的 TFT 设置在驱动该亚像素单元的栅线上，所述 TFT的漏电极与所述亚像素单元中 的像素电极连接。
4、 根据权利要求 1-3中任一项所述的阵列基板， 其中， 所述像素电极包 括位于两条栅线之间的部分以及位于两条栅线两侧的部分， 所述漏电极与所 述像素电极中所述位于两条栅线之间的部分连接。
5、 根据权利要求 1-4中任一项所述的阵列基板， 还包括公共电极， 所述 公共电极与所述栅线和像素电极位于不同层且相绝缘， 所述公共电极位于所 述像素电极和所述栅线之间； 所述栅线位于所述公共电极沿垂直与阵列基板 的方向在阵列基板上的投影区域内。
6、 根据权利要求 1-5中任一项所述的阵列基板， 其中， 所述漏电极与所 述像素电极位于不同层， 且通过第一过孔电性连接。
7、根据权利要求 6所述的阵列基板，还包括与公共电极位于不同层且与 公共电极相绝缘的多条公共电极线， 所述各公共电极线通过第二过孔与所述 公共电极连接。
8、根据权利要求 7所述的阵列基板， 其中， 所述阵列基板包括显示区域 以及位于显示区域周围的外围区域， 所述多条公共电极线分布在显示区域和 外围区域， 分布在外围区域的公共电极线与公共电极连接的所述第二过孔的 数量至少为两个。
9、根据权利要求 1所述的阵列基板， 其中，位于相邻两行亚像素单元之 间的两条栅线之间的区域为不透光区域， 该两条栅线两侧的亚像素单元的像 素电极延伸到该不透光区域， 并且在该不透光区域内与相应的漏极连接。
10、 根据权利要求 9所述的阵列基板， 其中， 所述相邻两行亚像素单元 中的各亚像素单元的像素电极跨过与之相邻的栅线， 并与所述两条栅线中的 另一个栅线相连， 各亚像素单元包括公共电极且该公共电极延伸到与该亚像 素单元相邻的栅线与该像素单元的像素电极之间。
11、 一种液晶显示面板， 包括对盒设置的彩膜基板和阵列基板， 其中， 所述阵列基板为如权利要求 1~10任一权利要求所述的阵列基板。
12、根据权利要求 11所述的液晶显示面板， 其中， 所述彩膜基板包括黑 矩阵， 所述栅线在所述阵列基板上的投影落在所述彩膜基板上黑矩阵在所述 阵列基板上的投影内。
13、根据权利要求 11所述的液晶显示面板， 其中， 在彩膜基板侧， 当一 个像素单元由三种颜色的亚像素单元组成时， 所述栅线位置对应的黑矩阵与 所述公共电极线位置对应的黑矩阵宽度相同；
当一个像素单元由至少四种颜色的亚像素单元组成时， 所述栅线位置对 应的黑矩阵与所述公共电极线位置对应的黑矩阵宽度不相同。
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Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103116238B (zh) * 2013-02-05 2015-09-09 北京京东方光电科技有限公司 一种阵列基板及液晶显示面板
JP6245957B2 (ja) * 2013-11-20 2017-12-13 株式会社ジャパンディスプレイ 表示素子
TWI523205B (zh) * 2014-03-28 2016-02-21 友達光電股份有限公司 畫素結構及顯示面板
CN104181740B (zh) 2014-07-25 2017-01-18 京东方科技集团股份有限公司 一种阵列基板和显示装置
CN104483788B (zh) * 2014-10-10 2018-04-10 上海中航光电子有限公司 像素结构及其制造方法、阵列基板、显示面板和显示装置
CN104317123B (zh) * 2014-10-10 2017-05-03 上海中航光电子有限公司 像素结构及其制造方法、阵列基板、显示面板和显示装置
KR102222189B1 (ko) * 2014-12-24 2021-03-05 엘지디스플레이 주식회사 표시패널 및 표시장치
TWI551931B (zh) * 2015-03-23 2016-10-01 群創光電股份有限公司 顯示器面板
CN104880871B (zh) * 2015-06-23 2018-05-11 合肥鑫晟光电科技有限公司 显示面板和显示装置
CN104900207B (zh) * 2015-06-24 2017-06-06 京东方科技集团股份有限公司 阵列基板及其驱动方法及显示装置
EP3534208A4 (en) * 2016-11-17 2020-02-12 Huawei Technologies Co., Ltd. ARRAY SUBSTRATE AND MANUFACTURING METHOD AND LIQUID CRYSTAL DISPLAY PANEL
KR102705901B1 (ko) * 2017-02-07 2024-09-11 삼성디스플레이 주식회사 표시 장치
CN106876409B (zh) * 2017-02-22 2018-08-17 武汉华星光电技术有限公司 一种ltps制程中的tft器件的分布结构
CN108628045B (zh) * 2017-03-21 2022-01-25 京东方科技集团股份有限公司 阵列基板、显示面板和显示装置
CN107844008B (zh) * 2017-11-06 2020-03-17 深圳市华星光电技术有限公司 阵列基板、阵列基板的检测方法及显示面板
CN108267900B (zh) * 2018-02-08 2021-03-02 京东方科技集团股份有限公司 光阀结构及其制造方法、操作方法、阵列基板、电子装置
KR102562943B1 (ko) * 2018-09-12 2023-08-02 엘지디스플레이 주식회사 표시 장치
CN109471562B (zh) * 2018-12-27 2021-11-19 上海中航光电子有限公司 显示面板、显示装置和显示面板的驱动方法
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CN110109305B (zh) * 2019-04-12 2020-12-04 深圳市华星光电半导体显示技术有限公司 显示面板
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CN113009739B (zh) * 2021-03-22 2023-02-17 厦门天马微电子有限公司 一种显示面板及显示装置

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10268349A (ja) * 1997-03-26 1998-10-09 Advanced Display:Kk 液晶表示素子及びこれを用いた液晶表示装置
CN1495476A (zh) * 2002-06-28 2004-05-12 三星电子株式会社 液晶显示器及其薄膜晶体管阵列面板
US20070132902A1 (en) * 2005-12-14 2007-06-14 Quanta Display Inc. Lcd and method of manufacturing the same
CN101398581A (zh) * 2007-09-28 2009-04-01 群康科技(深圳)有限公司 液晶显示面板及其所采用的基板的制造方法
CN101405648A (zh) * 2006-03-17 2009-04-08 夏普株式会社 液晶显示装置
CN101540329A (zh) * 2008-03-19 2009-09-23 群康科技(深圳)有限公司 薄膜晶体管基板及其制造工艺
CN103048838A (zh) * 2012-12-13 2013-04-17 北京京东方光电科技有限公司 一种阵列基板、液晶显示面板及驱动方法
CN103116238A (zh) * 2013-02-05 2013-05-22 北京京东方光电科技有限公司 一种阵列基板及液晶显示面板
CN203084393U (zh) * 2013-02-05 2013-07-24 北京京东方光电科技有限公司 一种阵列基板及液晶显示面板

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100494694B1 (ko) * 2001-10-05 2005-06-13 비오이 하이디스 테크놀로지 주식회사 박막트랜지스터 액정표시장치
CN101706637B (zh) * 2009-04-03 2011-07-13 深超光电（深圳）有限公司 高显示质量的画素电极结构
WO2010127515A1 (zh) * 2009-05-06 2010-11-11 深超光电（深圳）有限公司 显示面板
US8451407B2 (en) 2009-06-30 2013-05-28 Samsung Display Co., Ltd. Liquid crystal display and method of manufacturing the same
JP5448875B2 (ja) * 2010-01-22 2014-03-19 株式会社ジャパンディスプレイ 液晶表示装置
JP2011227225A (ja) * 2010-04-19 2011-11-10 Hitachi Displays Ltd 表示装置
TWI457674B (zh) * 2011-04-13 2014-10-21 Au Optronics Corp 畫素陣列、畫素結構及畫素結構的驅動方法
CN102629053A (zh) * 2011-08-29 2012-08-08 京东方科技集团股份有限公司 阵列基板及显示装置
JP6053278B2 (ja) * 2011-12-14 2016-12-27 三菱電機株式会社 ２画面表示装置
CN103975270B (zh) * 2011-12-26 2015-10-21 夏普株式会社 有源矩阵基板和具备它的液晶显示面板
CN103226412A (zh) * 2013-04-10 2013-07-31 北京京东方光电科技有限公司 一种内嵌式触摸屏及显示装置

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10268349A (ja) * 1997-03-26 1998-10-09 Advanced Display:Kk 液晶表示素子及びこれを用いた液晶表示装置
CN1495476A (zh) * 2002-06-28 2004-05-12 三星电子株式会社 液晶显示器及其薄膜晶体管阵列面板
US20070132902A1 (en) * 2005-12-14 2007-06-14 Quanta Display Inc. Lcd and method of manufacturing the same
CN101405648A (zh) * 2006-03-17 2009-04-08 夏普株式会社 液晶显示装置
CN101398581A (zh) * 2007-09-28 2009-04-01 群康科技(深圳)有限公司 液晶显示面板及其所采用的基板的制造方法
CN101540329A (zh) * 2008-03-19 2009-09-23 群康科技(深圳)有限公司 薄膜晶体管基板及其制造工艺
CN103048838A (zh) * 2012-12-13 2013-04-17 北京京东方光电科技有限公司 一种阵列基板、液晶显示面板及驱动方法
CN103116238A (zh) * 2013-02-05 2013-05-22 北京京东方光电科技有限公司 一种阵列基板及液晶显示面板
CN203084393U (zh) * 2013-02-05 2013-07-24 北京京东方光电科技有限公司 一种阵列基板及液晶显示面板

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