WO2014090049A1 - 一种低关断态电流晶体管电路 - Google Patents

一种低关断态电流晶体管电路 Download PDF

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Publication number
WO2014090049A1
WO2014090049A1 PCT/CN2013/086160 CN2013086160W WO2014090049A1 WO 2014090049 A1 WO2014090049 A1 WO 2014090049A1 CN 2013086160 W CN2013086160 W CN 2013086160W WO 2014090049 A1 WO2014090049 A1 WO 2014090049A1
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Prior art keywords
transistor
string
switch
state current
circuit
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PCT/CN2013/086160
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English (en)
French (fr)
Inventor
苏强
奕江涛
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广州慧智微电子有限公司
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Priority to EP13862306.1A priority Critical patent/EP2933922A4/en
Publication of WO2014090049A1 publication Critical patent/WO2014090049A1/zh
Priority to US14/735,820 priority patent/US9660529B2/en

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/10—Modifications for increasing the maximum permissible switched voltage
    • H03K17/102—Modifications for increasing the maximum permissible switched voltage in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/06—Modifications for ensuring a fully conducting state
    • H03K17/063—Modifications for ensuring a fully conducting state in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/06—Modifications for ensuring a fully conducting state
    • H03K2017/066—Maximizing the OFF-resistance instead of minimizing the ON-resistance
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0018—Special modifications or use of the back gate voltage of a FET

Definitions

  • the present invention relates to a semiconductor integrated circuit, and more particularly to a low off-state current transistor circuit. Background technique
  • a more common problem is: When the feature size of the integrated circuit is reduced, the threshold voltage of the transistor is reduced, so that when the gate-source voltage difference of the transistor is 0 and the transistor is in the off state, the transistor is turned off. The state current increases.
  • Low-power integrated circuits are rapidly developing integrated circuits in recent years. Especially in industrial control, medical and other applications, low-power integrated circuits have broad prospects for development. Low-power integrated circuits require the transistor's off-state current to be very small, so that it does not affect its standby time of months or even years. When the feature size of the integrated circuit is reduced, the increase in the off-state current of the transistor is in conflict with the demand of the low-power integrated circuit.
  • the off-state current of the transistor can be reduced by increasing the channel length L of the transistor.
  • the transistor is turned off, when the switch S1 is turned on, the gate and source of the N-type metal oxide semiconductor (NMOS) transistor N1 are short-circuited, and the gate and source of the NMOS transistor N1 are The voltage difference is 0.
  • the NMOS transistor N1 is in an off state; increasing the channel length L of the NMOS transistor N1 can increase the drift length of the carrier in the channel region, thereby reducing the off of the NMOS transistor N1.
  • Off-state current However, increasing the channel length L of the NMOS transistor N1 tends to cause an increase in the size of the transistor, which in turn causes an increase in the overall size of the integrated circuit and increases the cost per chip of the integrated circuit. Summary of the invention
  • embodiments of the present invention provide a low off-state current transistor circuit.
  • An embodiment of the present invention provides a low off-state current transistor circuit, including: a first transistor, a transistor string, and a switch; wherein, the first transistor is connected in series with the transistor string;
  • a switch configured to turn off the circuit
  • a first transistor configured to reduce a turn-off current flowing through itself by a negative feedback of the transistor string when the circuit is in an off state
  • the transistor string is configured to use its own negative gate-to-source voltage difference and the body effect of the transistor to reduce the off-state current flowing through itself.
  • the gate of the first transistor is connected to the gate of the transistor string, the source of the first transistor, the body region of the first transistor and the body region of the transistor string are connected to the common terminal, and the drain of the first transistor is connected to the transistor string.
  • a source, one end of the switch is connected to the gate of the first transistor, the other end of the switch is connected to the common end, and the switch is controlled by the switch control end; wherein the gate of the first transistor, the drain of the transistor string, and the switch control end are the circuit
  • the interconnect node with the external circuit, the common terminal is the power supply, or the ground line.
  • the first transistor is implemented by an NMOS transistor, or the first transistor is implemented by a PMOS transistor.
  • the common terminal is a ground line; when the first transistor is implemented by a PMOS transistor, the common terminal is a power source.
  • the transistor string is composed of an NMOS transistor, or the transistor string is composed of a PMOS transistor.
  • the transistor string when the first transistor is implemented by an NMOS transistor, the transistor string is composed of an NMOS transistor; when the first transistor is implemented by a PMOS transistor, the transistor string is composed of a PMOS transistor Body tube composition.
  • the number of transistors in the transistor string is one or more.
  • the gates of all the transistors in the transistor string are connected together, and the body regions of all the transistors in the transistor string are connected together, and the drain of the transistor connected to the drain of the first transistor in the transistor string is connected to the source of the adjacent transistor.
  • a drain of a neighboring transistor of a transistor connected to a source of the first transistor is connected to a source of an adjacent transistor thereof, and so on, until a drain of one transistor in the transistor string is connected to the transistor string The source of the transistor connected to the node.
  • the switch is implemented by an NMOS transistor, or the switch is implemented by a PMOS transistor.
  • the switch when the first transistor is implemented by an NMOS transistor, the switch is implemented by an NMOS transistor; when the first transistor is implemented by a PMOS transistor, the switch is implemented by a PMOS transistor.
  • the switch when the switch is implemented by an NMOS transistor, the switch is turned on when the switch control terminal is at a high level, and the switch is turned off when the switch control terminal is at a low level; when the switch is implemented by a PMOS transistor, when the switch control terminal is at a high level, the switch is turned on. Disconnected, the switch is turned on when the switch control terminal is low.
  • the negative feedback action of the transistor string reduces the off-state current flowing through the first transistor, the transistor string
  • the negative gate-to-source voltage difference and the body effect of the transistor of the transistor string reduce the off-state current flowing through the transistor string, thus effectively reducing the off-state current flowing through the first transistor and reducing the flow through
  • the off-state current of the transistor string effectively reduces the off-state current IOFF of the entire circuit.
  • Figure 1 is a conventional transistor off state circuit
  • FIG. 2 is a circuit diagram of a low off-state current transistor of an embodiment of the present invention
  • 3A is a schematic structural diagram of an implementation manner of a first transistor in an embodiment of the present invention
  • FIG. 3B is a schematic structural diagram of another implementation manner of a first transistor in an embodiment of the present invention
  • FIG. 4A is a transistor string in an embodiment of the present invention
  • FIG. 4B is a schematic structural diagram of another implementation manner of a transistor string according to an embodiment of the present invention
  • FIG. 5A is a schematic structural diagram of an implementation manner of a switch according to an embodiment of the present invention
  • FIG. 5B is a schematic structural diagram of another implementation of a switch according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a circuit of a low-off state current transistor according to Embodiment 1 of the present invention.
  • FIG. 7 is a schematic structural diagram of a circuit of a low off-state current transistor according to Embodiment 2 of the present invention. detailed description
  • the low-off state current transistor circuit provided by the embodiment of the present invention, as shown in FIG. 2, includes: a first transistor 100, a transistor string 102, and a switch 104; wherein the first transistor is connected in series with the transistor string;
  • the negative feedback action of the transistor string 102 reduces the off-state current flowing through the first transistor 100.
  • the negative gate-to-source voltage difference of transistor string 102 and the bulk effect of the transistor of transistor string 102 reduce the off-state current flowing through transistor string 102, thereby achieving the goal of low off-state current.
  • the connection relationship of the components of the low off-state current transistor circuit shown in FIG. 2 is as follows: the gate of the first transistor 100 is connected to the first node A, and the source and the body region of the first transistor 100 are connected to the second node: The drain of the first transistor 100 is connected to the fourth node D; the transistor string 102 The gate is connected to the first node A, the source of the transistor string 102 is connected to the fourth node D, the drain of the transistor string 102 is connected to the fifth node E; one end of the switch 104 is connected to the first node A, and the other end of the switch 104 is connected.
  • the second node B, the switch control end of the switch 104 is the third node C; here, the first node A, the third node C, and the fifth node E are the interconnection nodes of the circuit and other circuits of the embodiment; the fourth node D The interconnecting node inside the circuit of the embodiment of the present invention; the second node B is connected to the common end, and the common end may be the power source VDD or the ground line.
  • the low-off state current transistor circuit shown in Figure 2 works as follows:
  • the off-state current IOFF flows through the first transistor 100, causing the voltage difference between the drain and source of the first transistor 100 to rise, but due to the drain of the first transistor 100 and the transistor string 102.
  • the source is connected, so due to the negative feedback, the amplitude of the drain voltage of the first transistor 100 is limited, that is, the amplitude of the voltage difference between the drain and the source is limited, thereby reducing the flow.
  • the off state current of the first transistor 100 is passed.
  • the rise of the drain voltage of the first transistor 100 causes the gate-to-source voltage difference of the transistor string 102 to become a negative value, thereby reducing the off-state current flowing through the transistor string 102; meanwhile, the transistor string 102 The body region and source voltage difference also become negative, and the body effect of the transistor will increase the threshold voltage of each transistor in the transistor string 102, thereby reducing the off-state current flowing through the transistor string 102, thereby reducing 'J' The off-state current IOFF of the entire circuit.
  • the first transistor 100 can be implemented by a ninth NMOS transistor 200.
  • the second node B is connected to the ground.
  • the first transistor 100 can also be implemented by a ninth p-type metal oxide semiconductor (PMOS) transistor 202.
  • the second node B is connected to the power supply VDD.
  • the transistor string may be composed of a plurality of NMOS transistors. As shown in FIG. 4A, the transistor string may include: a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, and a fourth NMOS transistor NM4.
  • a source of the fifth NMOS transistor NM5 a drain of the fifth NMOS transistor NM5 is connected to a source of the sixth NMOS transistor NM6, and a drain of the sixth NMOS transistor NM6 is connected to a drain
  • the source of the NMOS transistor NM7, the drain of the seventh NMOS transistor NM7 is connected to the source of the eighth NMOS transistor NM8;
  • the source of the first NMOS transistor NM1 is the source of the transistor string, and the gate of the first NMOS transistor NM1 is the transistor string.
  • the gate, the drain of the eighth NMOS transistor NM8 is the drain of the transistor string.
  • the transistor string may also be composed of a plurality of PMOS transistors. As shown in FIG. 4B, the transistor string may include: a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, and a fourth PMOS transistor.
  • the drain of the fourth PMOS transistor PM4 is connected to the source of the fifth PMOS transistor PM5, the drain of the fifth PMOS transistor PM5 is connected to the source of the sixth PMOS transistor PM6, and the drain of the sixth PMOS transistor PM6 is connected to the seventh PMOS.
  • the source of the transistor PM7, the drain of the seventh PMOS transistor PM7 is connected to the source of the eighth PMOS transistor PM8; the source of the first PMOS transistor PM1 is the source of the transistor string, and the gate of the first PMOS transistor PM1 is the gate of the transistor string.
  • the drain of the eighth PMOS transistor PM8 is the drain of the transistor string.
  • the type of transistor in the transistor string is determined by the implementation of the first transistor. Specifically, when the first transistor is implemented by an NMOS transistor, the transistor string is composed of an NMOS transistor; when the first transistor is implemented by a PMOS transistor, The transistor string is composed of PMOS transistors.
  • the number of transistors in the transistor string may be one or more. Preferably, the number of transistors in the transistor string may be 1 to 8.
  • the gate of the transistor connected to the fourth node D in the transistor string is the gate of the transistor string, and the source of the transistor connected to the fourth node D in the transistor string is the source of the transistor string, and the transistor string is connected to the fifth node E.
  • the drain of the transistor is the drain of the transistor string, the gates of all the transistors in the transistor string are connected together, the body regions of all the transistors in the transistor string are connected together, and the drain connection of the transistor connected to the fourth node D in the transistor string
  • the source of the adjacent transistor, the drain of the adjacent transistor of the transistor connected to the fourth node D is connected to the source of its adjacent transistor, and so on, until the drain of the transistor in the transistor string is connected to the transistor string
  • the switch 104 can be the tenth NMOS transistor 300. to realise. In this case, the switch is turned on when the switch control terminal is at a high level, and the switch is turned off when the switch control terminal is at a low level.
  • the switch 104 can also be implemented by the tenth PMOS transistor 302. In this case, the switch is turned on when the switch control terminal is low, and the switch is turned off when the switch control terminal is high.
  • the implementation of the switch is determined by the implementation of the first transistor. Specifically, when the first transistor is implemented by an NMOS transistor, the switch is implemented by the tenth NMOS transistor 300; when the first transistor is implemented by a PMOS transistor The switch is implemented by the tenth PMOS transistor 302.
  • the gate-source voltage difference of the first transistor is 0, and the off-state current IOFF flows through the first transistor and the transistor string. Therefore, the off-state current flowing through the first transistor is reduced and the off-state current flowing through the transistor string is reduced, thereby reducing the off-state current IOFF of the entire circuit.
  • the sum of the channel lengths of all the transistors in the first transistor and the transistor string in the low off-state current transistor circuit provided by the embodiment of the present invention is Ltot, and the NMOS transistor N1 in the conventional transistor off-state circuit shown in FIG.
  • the channel length is L, even if Ltot and L are equal, that is, the area is equal, compared with the conventional transistor turn-off circuit shown in FIG. 1, the low off-state current transistor circuit provided by the embodiment of the present invention is used, since the flow is reduced. After the first transistor and the transistor string are turned off, the current is off, so that the off-state current IOFF can still be reduced. From another point of view, under the same off-state current IOFF condition, compared with the conventional transistor turn-off circuit shown in FIG. 1, the low-off current transistor circuit provided by the embodiment of the present invention is Ltot. Will be less than L.
  • the low off-state current transistor circuit provided by the embodiment of the present invention is manufactured without depending on the type of process used, and may be, for example, a standard CMOS process, a BiCMOS process, or a silicon-on-insulator (SOI) process.
  • FIG. 6 is a schematic structural diagram of a circuit of a low off-state current transistor according to a first embodiment of the present invention.
  • the first transistor is implemented by the ninth NMOS transistor 200
  • the transistor string is implemented by the eleventh NMOS transistor 400
  • the switch is implemented by the tenth NMOS transistor 300
  • the source of the ninth transistor 200 The body region and the body region of the eleventh NMOS transistor 400 are grounded.
  • the sum of the channel lengths of the first transistor 100 and the eleventh NMOS transistor 400 is Ltot.
  • the channel length of the NMOS transistor N1 is L, even if Ltot and L are equal, that is, the area Equally, compared with the conventional transistor turn-off circuit shown in FIG. 1, the off-state current IOFF provided by the present embodiment can still reduce the off-state current IOFF. From another point of view, under the same off-state current IOFF condition, compared with the conventional transistor turn-off circuit shown in FIG. 1, with the low off-state current transistor circuit provided in this embodiment, Ltot is smaller than L.
  • FIG. 7 is a schematic structural diagram of a circuit of a low off-state current transistor according to Embodiment 2 of the present invention.
  • the first transistor is implemented by the ninth PMOS transistor 202
  • the transistor string 102 is implemented by the eleventh PMOS transistor 500 and the twelfth PMOS transistor 502
  • the switch 104 is the tenth PMOS transistor.
  • 302 is implemented; the source and body regions of the ninth PMOS transistor 202, the body region of the eleventh PMOS transistor 500, and the body region of the twelfth PMOS transistor 502 are connected to the power supply VDD; and the drain connection of the eleventh PMOS transistor 500 is The source of the twelve PMOS transistor 502.
  • the sum of the channel lengths of the twelfth PMOS transistor 202, the eleventh PMOS transistor 500, and the twelfth PMOS transistor 502 is Ltot.
  • the channel length of the NMOS transistor N1 in the conventional transistor off state circuit shown in FIG. Even if Ltot and L are equal, that is, the area is equal, the off-state current IOFF can be reduced by using the low off-state current transistor circuit provided in this embodiment as compared with the conventional transistor turn-off circuit shown in FIG. From another point of view, under the same off-state current IOFF condition, compared with the conventional transistor turn-off circuit shown in FIG. 1, with the low off-state current transistor circuit provided by the embodiment, Ltot is smaller than L.

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  • Engineering & Computer Science (AREA)
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  • Electronic Switches (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本发明公开了一种低关断态电流晶体管电路，该电路包括：第一晶体管、晶体管串和开关；第一晶体管与晶体管串串联；开关，配置为关断所述电路；第一晶体管，配置为当所述电路处于关断态时，利用晶体管串的负反馈作用减小流过自身的关断态电流；晶体管串，配置为利用自身负的栅极源极电压差及晶体管的体效应，减小流过自身的关断态电流，采用本发明的技术方案，能实现低关断态电流。

Description

一种低关断态电流晶体管电路 技术领域
本发明涉及一种半导体集成电路， 特别涉及一种低关断态电流晶体管 电路。 背景技术
随着集成电路技术的飞速发展， 集成电路的特征尺寸迅速减小， 这带 来了诸多优点， 如增大集成电路的集成度、 减小电路的时延、 降低集成电 路的成本等， 但是这同时也带来了一些问题。 一个较为普遍的问题是： 当 集成电路的特征尺寸减小后， 其中晶体管的阈值电压减小， 这样， 当晶体 管的栅极源极电压差为 0、晶体管处于关断态时，晶体管的关断态电流增大。
低功耗集成电路是近年快速发展的集成电路领域， 特别是在工业控制、 医疗等应用领域， 低功耗集成电路有着广阔的发展前景。 低功耗集成电路 要求晶体管的关断态电流非常小， 这样才不会影响其长达数月、 甚至数年 的待机时间。 而集成电路的特征尺寸减小后， 晶体管的关断态电流增大就 和低功耗集成电路的需求产生了矛盾。
一般情况下， 可以通过增大晶体管的沟道长度 L来减小晶体管的关断 态电流。 如图 1中常见的晶体管关断态电路， 开关 S1闭合导通时， N型金 属氧化物半导体（NMOS ) 晶体管 N1 的栅极和源极短路， NMOS 晶体管 N1的栅极和源极之间的电压差为 0， 此时， NMOS晶体管 Nl处于关断态； 增大 NMOS晶体管 N1的沟道长度 L, 可以增大载流子在沟道区的漂移长 度， 从而减小了 NMOS晶体管 Nl的关断态电流。 但是， 增大 NMOS晶体 管 N1的沟道长度 L势必造成晶体管尺寸的增大，进而造成集成电路总尺寸 的增大， 并增加集成电路的单片成本。 发明内容
为解决现有技术中的问题， 本发明实施例提供一种低关断态电流晶体 管电路。
为实现以上功能， 本发明实施例采取如下技术方案：
本发明实施例提供一种低关断态电流晶体管电路， 包括： 第一晶体管、 晶体管串和开关； 其中， 第一晶体管与晶体管串串联；
开关， 配置为关断所述电路；
第一晶体管， 配置为当所述电路处于关断态时， 利用晶体管串的负反 馈作用减小流过自身的关断态电流；
晶体管串， 配置为利用自身负的栅极源极电压差及晶体管的体效应， 减小流过自身的关断态电流。
上述方案中， 第一晶体管的栅极连接晶体管串的栅极， 第一晶体管的 源极、 第一晶体管的体区和晶体管串的体区连接公共端， 第一晶体管的漏 极连接晶体管串的源极， 开关的一端连接第一晶体管的栅极， 开关的另一 端连接公共端， 开关由开关控制端控制； 其中， 第一晶体管的栅极、 晶体 管串的漏极、 开关控制端为本电路和外部电路的互连节点， 公共端为电源、 或为地线。
上述方案中， 第一晶体管由 NMOS晶体管实现， 或者， 第一晶体管由 PMOS晶体管实现。
上述方案中， 当第一晶体管由 NMOS晶体管实现时， 公共端为地线； 当第一晶体管由 PMOS晶体管实现时， 公共端为电源。
上述方案中，晶体管串由 NMOS晶体管构成，或者，晶体管串由 PMOS 晶体管构成。
上述方案中，当第一晶体管由 NMOS晶体管实现时，晶体管串由 NMOS 晶体管构成； 当第一晶体管由 PMOS晶体管实现时， 晶体管串由 PMOS晶 体管构成。
上述方案中， 晶体管串中晶体管的数目为一个或者一个以上。
上述方案中， 晶体管串中所有晶体管的栅极连接在一起， 晶体管串中 所有晶体管的体区连接在一起， 晶体管串中与第一晶体管的漏极连接的晶 体管的漏极连接相邻晶体管的源极， 与第一晶体管的源极连接的晶体管的 相邻晶体管的漏极连接其相邻晶体管的源极， 以此类推， 直至晶体管串中 的一个晶体管的漏极连接晶体管串中与所述互连节点连接的晶体管的源 极。
上述方案中， 开关由 NMOS晶体管实现， 或者， 开关由 PMOS晶体管 实现。
上述方案中， 当第一晶体管由 NMOS晶体管实现时， 开关由 NMOS晶 体管来实现； 当第一晶体管由 PMOS晶体管实现时， 开关由 PMOS晶体管 来实现。
上述方案中， 当开关由 NMOS晶体管实现时， 开关控制端为高电平时 开关导通， 开关控制端为低电平时开关断开； 当开关由 PMOS晶体管实现 时， 开关控制端为高电平时开关断开， 开关控制端为低电平时开关导通。
本发明实施例提供的低关断态电流晶体管电路， 当低关断态电流晶体 管电路处于关断态时， 晶体管串的负反馈作用减小流过第一晶体管的关断 态电流 , 晶体管串的负的栅极源极电压差及晶体管串的晶体管的体效应减 小流过晶体管串的关断态电流， 如此， 能有效地减小流过第一晶体管的关 断态电流和减小流过晶体管串的关断态电流， 从而有效地减小了整个电路 的关断态电流 IOFF。 附图说明
图 1是常用的晶体管关断态电路；
图 2是本发明实施例的一种低关断态电流晶体管电路； 图 3 A是本发明实施例中第一晶体管的一种实现方式结构示意图； 图 3B是本发明实施例中第一晶体管的另一种实现方式结构示意图； 图 4A是本发明实施例中晶体管串的一种实现方式结构示意图； 图 4B是本发明实施例中晶体管串的另一种实现方式结构示意图； 图 5 A是本发明实施例中开关的一种实现方式结构示意图；
图 5B是是本发明实施例中开关的另一种实现方式结构示意图； 图 6是本发明实施一的低关断态电流晶体管电路结构示意图；
图 7是本发明实施二的低关断态电流晶体管电路结构示意图。 具体实施方式
下面通过特定的具体实例说明本发明的实施方式。 本领域的技术人员 可以由本说明书所揭示的内容轻易的了解本发明的其他优点与功效。 本发 明还可以通过另外不同的具体实施方式加以实施或应用。 本说明书中的各 项细节也可以基于不同观点与应用， 在没有背离本发明的精神下进行各种 爹饰或改变。
本发明实施例提供的低关断态电流晶体管电路， 如图 2 所示， 包括： 第一晶体管 100、 晶体管串 102及开关 104; 其中， 第一晶体管与晶体管串 串联；
当开关 104 关断低关断态电流晶体管电路时， 即： 当低关断态电流晶 体管电路处于关断态时， 晶体管串 102 的负反馈作用减小流过第一晶体管 100的关断态电流，晶体管串 102的负的栅极源极电压差及晶体管串 102的 晶体管的体效应减小流过晶体管串 102 的关断态电流， 从而实现低关断态 电流的目的。
图 2所示的低关断态电流晶体管电路的各部件的连接关系为： 第一晶体管 100的栅极连接第一节点 A， 第一晶体管 100的源极和体 区连接第二节点：6， 第一晶体管 100的漏极连接第四节点 D; 晶体管串 102 的栅极连接第一节点 A， 晶体管串 102的源极连接第四节点 D， 晶体管串 102的漏极连接第五节点 E; 开关 104的一端连接第一节点 A， 开关 104的 另一端连接第二节点 B， 开关 104的开关控制端为第三节点 C; 这里， 第一 节点 A、 第三节点 C、 第五节点 E为本实施例的电路和其它电路的互连节 点； 第四节点 D为本发明实施例的电路内部的互联节点； 第二节点 B连接 公共端， 公共端可以是电源 VDD， 也可以是地线。
图 2所示的低关断态电流晶体管电路的工作原理为：
当电路处于关断态时， 关断态电流 IOFF流过第一晶体管 100， 致使第 一晶体管 100漏极源极之间的电压差抬高， 但由于第一晶体管 100的漏极 和晶体管串 102 的源极相连接， 所以由于负反馈的作用， 第一晶体管 100 的漏极电压抬高的幅度受到限制， 即漏极源极之间的电压差抬高的幅度受 到限制， 从而可以减小流过第一晶体管 100 的关断态电流。 另一方面， 第 一晶体管 100漏极电压的升高， 致使晶体管串 102的栅极源极电压差变为 负值， 从而减小流过晶体管串 102的关断态电流； 同时， 晶体管串 102的 体区、 源极电压差也变为负值， 而晶体管的体效应将增大晶体管串 102 中 各晶体管的阈值电压， 从而减小流过晶体管串 102 的关断态电流， 进而减 'J、了整个电路的关断态电流 IOFF。
在一实施例中， 如图 3A所示， 第一晶体管 100可以由第九 NMOS晶 体管 200来实现。 在这种情况下， 第二节点 B连接地线。
在一实施例中， 如图 3B所示， 第一晶体管 100也可以由第九 P型金属 氧化物半导体（PMOS ) 晶体管 202 来实现。 在这种情况下， 第二节点 B 连接电源 VDD。
在一实施例中， 晶体管串可以由多个 NMOS晶体管构成， 如图 4A所 示，晶体管串可以包括：第一 NMOS晶体管 NM1、第二 NMOS晶体管 NM2、 第三 NMOS晶体管 NM3、 第四 NMOS晶体管 NM4、 第五 NMOS晶体管 NM5、第六 NMOS晶体管 NM6、第七 NMOS晶体管 NM7以及第八 NMOS 晶体管 NM8; 其中， 第一 NMOS晶体管 NM1、 第二 NMOS晶体管 NM2、 第三 NMOS晶体管 NM3、 第四 NMOS晶体管 NM4、 第五 NMOS晶体管 NM5、第六 NMOS晶体管 NM6、第七 NMOS晶体管 NM7以及第八 NMOS 晶体管 NM8中所有晶体管的栅极连接在一起， 第一 NMOS晶体管 NM 1、 第二 NMOS晶体管 NM2、 第三 NMOS晶体管 NM3、 第四 NMOS晶体管 NM4、 第五 NMOS晶体管 NM5、 第六 NMOS晶体管 NM6、 第七 NMOS 晶体管 NM7以及第八 NMOS晶体管 NM8中所有晶体管的体区连接在一起， 第一 NMOS晶体管 NM1的漏极连接第二 NMOS晶体管 NM2的源极， 第 二 NMOS晶体管 NM2的漏极连接第三 NMOS晶体管 NM3的源极， 第三 NMOS晶体管 NM3的漏极连接第四 NMOS晶体管 NM4的源极，第四 NMOS 晶体管 NM4的漏极连接第五 NMOS晶体管 NM5的源极， 第五 NMOS晶 体管 NM5的漏极连接第六 NMOS晶体管 NM6的源极， 第六 NMOS晶体 管 NM6的漏极连接第七 NMOS晶体管 NM7的源极， 第七 NMOS晶体管 NM7的漏极连接第八 NMOS晶体管 NM8的源极；第一 NMOS晶体管 NM1 的源极为晶体管串的源极， 第一 NMOS晶体管 NM1的栅极为晶体管串的 栅极， 第八 NMOS晶体管 NM8的漏极为晶体管串的漏极。
在一实施例中， 晶体管串也可以由多个 PMOS 晶体管构成， 如图 4B 所示， 晶体管串可以包括： 第一 PMOS 晶体管 PM1、 第二 PMOS 晶体管 PM2、 第三 PMOS晶体管 PM3、 第四 PMOS晶体管 PM4、 第五 PMOS晶 体管 PM5、第六 PMOS晶体管 PM6、第七 PMOS晶体管 PM7以及第八 PMOS 晶体管 PM8; 其中， 第一 PMOS晶体管 PM1、 第二 PMOS晶体管 PM2、 第三 PMOS晶体管 PM3、第四 PMOS晶体管 PM4、第五 PMOS晶体管 PM5、 第六 PMOS晶体管 PM6、 第七 PMOS晶体管 PM7以及第八 PMOS晶体管 PM8中所有晶体管的栅极连接在一起，第一 PMOS晶体管 PM1、第二 PMOS 晶体管 PM2、第三 PMOS晶体管 PM3、第四 PMOS晶体管 PM4、第五 PMOS 晶体管 PM5、 第六 PMOS晶体管 PM6、 第七 PMOS晶体管 PM7以及第八 PMOS 晶体管 PM8 中所有晶体管的体区连接在一起， 第一 PMOS晶体管 PM1的漏极连接第二 PMOS晶体管 PM2的源极， 第二 PMOS晶体管 PM2 的漏极连接第三 PMOS晶体管 PM3的源极， 第三 PMOS晶体管 PM3的漏 极连接第四 PMOS晶体管 PM4的源极， 第四 PMOS晶体管 PM4的漏极连 接第五 PMOS晶体管 PM5的源极， 第五 PMOS晶体管 PM5的漏极连接第 六 PMOS晶体管 PM6的源极， 第六 PMOS晶体管 PM6的漏极连接第七 PMOS晶体管 PM7的源极，第七 PMOS晶体管 PM7的漏极连接第八 PMOS 晶体管 PM8的源极； 第一 PMOS晶体管 PM1的源极为晶体管串的源极， 第一 PMOS晶体管 PM1的栅极为晶体管串的栅极，第八 PMOS晶体管 PM8 的漏极为晶体管串的漏极。
在实际应用时， 晶体管串中晶体管的类型由第一晶体管的实现方式决 定， 具体地， 当第一晶体管由 NMOS晶体管实现时， 晶体管串由 NMOS晶 体管构成； 当第一晶体管由 PMOS晶体管实现时， 晶体管串由 PMOS晶体 管构成。 其中， 晶体管串中晶体管的个数可以为一个或者一个以上， 优选 地， 晶体管串中晶体管的个数可以为 1至 8个。 晶体管串中与第四节点 D 连接的晶体管的栅极为晶体管串的栅极， 晶体管串中与第四节点 D连接的 晶体管的源极为晶体管串的源极， 晶体管串中与第五节点 E连接的晶体管 的漏极为晶体管串的漏极， 晶体管串中所有晶体管的栅极连接在一起， 晶 体管串中所有晶体管的体区连接在一起， 晶体管串中与第四节点 D连接的 晶体管的漏极连接相邻晶体管的源极， 与第四节点 D连接的晶体管的相邻 晶体管的漏极连接其相邻晶体管的源极， 以此类推， 直至晶体管串中的一 个晶体管的漏极连接体管串中与第五节点 E连接的晶体管的源极。
在一实施例中，如图 5A所示，开关 104可以由第十 NMOS晶体管 300 来实现。 在这种情况下， 开关控制端为高电平时开关导通， 开关控制端为 低电平时开关断开。
在一实施例中， 如图 5B所示， 开关 104也可以由第十 PMOS晶体管 302来实现。 在这种情况下， 开关控制端为低电平时开关导通， 开关控制端 为高电平时开关断开。
在实际应用时， 开关的实现方式由第一晶体管的实现方式决定， 具体 地， 当第一晶体管由 NMOS晶体管实现时， 开关由第十 NMOS晶体管 300 来实现； 当第一晶体管由 PMOS晶体管实现时， 开关由第十 PMOS晶体管 302来实现。
本发明实施例提供的低关断态电流晶体管电路， 当电路处于关断态时， 第一晶体管的栅极源极电压差为 0， 关断态电流 IOFF流过了第一晶体管和 晶体管串， 所以减小了流过第一晶体管的关断态电流和减小流过晶体管串 的关断态电流， 从而减小了整个电路的关断态电流 IOFF。
假设本发明实施例提供的低关断态电流晶体管电路中的第一晶体管和 晶体管串中所有晶体管的沟道长度总和为 Ltot， 图 1 所示的常用的晶体管 关断态电路中 NMOS晶体管 N1的沟道长度为 L， 即使 Ltot和 L相等， 即 面积相等， 与图 1 所示的常用晶体管关断电路相比， 采用本发明实施例提 供的低关断态电流晶体管电路， 由于减小了流过经第一晶体管和晶体管串 的关断太电流， 所以依然能减小关断态电流 IOFF。 从另一角度来说， 在相 同的关断态电流 IOFF条件下， 与图 1所示的常用的晶体管关断电路相比， 采用本发明实施例提供的低关断态电流晶体管电路， 则 Ltot会小于 L。
本发明实施例提供的低关断态电流晶体管电路在制造时， 并不依赖于 所采用的工艺类型， 例如可以是标准 CMOS工艺， 可以是 BiCMOS工艺， 也可以是绝缘硅 ( SOI )工艺等。
实施例一 图 6是本发明实施一的低关断态电流晶体管电路结构示意图。 如图 6 所示， 在本实施例中， 第一晶体管由第九 NMOS晶体管 200实现， 晶体管 串由第十一 NMOS晶体管 400实现， 开关由第十 NMOS晶体管 300实现； 第九晶体管 200的源极和体区、以及第十一 NMOS晶体管 400的体区接地。 第一晶体管 100和第十一 NMOS晶体管 400的沟道长度总和为 Ltot， 图 1 所示的常用的晶体管关断态电路中 NMOS晶体管 N1的沟道长度为 L， 即 使 Ltot和 L相等， 即面积相等， 与图 1所示的常用晶体管关断电路相比， 采用本实施例提供的低关断态电流晶体管电路， 依然能减小关断态电流 IOFF。 从另一角度来说， 在相同的关断态电流 IOFF条件下， 与图 1所示的 常用的晶体管关断电路相比， 采用本实施例提供的低关断态电流晶体管电 路， 则 Ltot小于 L。
图 7是本发明实施二的低关断态电流晶体管电路结构示意图。 如图 7 所示， 在本实施例中， 第一晶体管由第九 PMOS晶体管 202实现， 晶体管 串 102由第十一 PMOS晶体管 500和第十二 PMOS晶体管 502来实现， 开 关 104由第十 PMOS晶体管 302实现； 第九 PMOS晶体管 202的源极和体 区、 第十一 PMOS晶体管 500的体区、 以及第十二 PMOS晶体管 502的体 区连接电源 VDD;第十一 PMOS晶体管 500的漏极连接第十二 PMOS晶体 管 502的源极。 第十二 PMOS晶体管 202、 第十一 PMOS晶体管 500和第 十二 PMOS晶体管 502的沟道长度总和为 Ltot， 图 1所示的常用的晶体管 关断态电路中 NMOS晶体管 N1的沟道长度为 L， 即使 Ltot和 L相等， 即 面积相等， 与图 1 所示的常用晶体管关断电路相比， 采用本实施例提供的 低关断态电流晶体管电路，依然能减小关断态电流 IOFF。从另一角度来说， 在相同的关断态电流 IOFF条件下，与图 1所示的常用的晶体管关断电路相 比， 采用本实施例提供的低关断态电流晶体管电路， 则 Ltot小于 L。
上述实施例仅示例性说明本发明的原理及其功效， 而非用于限制本发 明。 熟悉此领域的技术人员皆可在不违背本发明的精神及范畴下， 对上述 实施例进行修饰或改变。 因此， 举凡所属技术领域中具有通常知识者在未 脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变， 仍 然由本发明的权利要求所涵盖。

Claims

权利要求书
1、 一种低关断态电流晶体管电路， 包括： 第一晶体管、 晶体管串和开 关； 其中， 第一晶体管与晶体管串串联；
开关， 配置为关断所述电路；
第一晶体管， 配置为当所述电路处于关断态时， 利用晶体管串的负反 馈作用减小流过自身的关断态电流；
晶体管串， 配置为利用自身负的栅极源极电压差及晶体管的体效应， 减小流过自身的关断态电流。
2、 如权利要求 1所述的低关断态电流晶体管电路， 其中， 第一晶体管 的栅极连接晶体管串的栅极， 第一晶体管的源极、 第一晶体管的体区和晶 体管串的体区连接公共端， 第一晶体管的漏极连接晶体管串的源极， 开关 的一端连接第一晶体管的栅极， 开关的另一端连接公共端， 开关由开关控 制端控制； 其中， 第一晶体管的栅极、 晶体管串的漏极、 开关控制端为本 电路和外部电路的互连节点， 公共端为电源、 或为地线。
3、 如权利要求 1或 2所述的低关断态电流晶体管电路， 其中， 第一晶 体管由 NMOS晶体管实现， 或者， 第一晶体管由 PMOS晶体管实现。
4、 如权利要求 3所述的低关断态电流晶体管电路， 其中， 当第一晶体 管由 NMOS晶体管实现时， 公共端为地线； 当第一晶体管由 PMOS晶体管 实现时， 公共端为电源。
5、 如权利要求 1或 2所述的低关断态电流晶体管电路， 其中， 晶体管 串由 NMOS晶体管构成， 或者， 晶体管串由 PMOS晶体管构成。
6、 如权利要求 5所述的低关断态电流晶体管电路， 其中， 当第一晶体 管由 NMOS晶体管实现时， 晶体管串由 NMOS晶体管构成； 当第一晶体管 由 PMOS晶体管实现时， 晶体管串由 PMOS晶体管构成。
7、 如权利要求 5所述的低关断态电流晶体管电路， 其中， 晶体管串中 晶体管的数目为一个或者一个以上。
8、 如权利要求 7所述的低关断态电流晶体管电路， 其中， 晶体管串中 所有晶体管的栅极连接在一起， 晶体管串中所有晶体管的体区连接在一起， 晶体管串中与第一晶体管的漏极连接的晶体管的漏极连接相邻晶体管的源 极， 与第一晶体管的源极连接的晶体管的相邻晶体管的漏极连接其相邻晶 体管的源极， 以此类推， 直至晶体管串中的一个晶体管的漏极连接晶体管 串中与所述互连节点连接的晶体管的源极。
9、 如权利要求 1或 2所述的低关断态电流晶体管电路， 其中， 开关由 NMOS晶体管实现， 或者， 开关由 PMOS晶体管实现。
10、 如权利要求 9所述的低关断态电流晶体管电路， 其中， 当第一晶 体管由 NMOS晶体管实现时， 开关由 NMOS晶体管来实现； 当第一晶体管 由 PMOS晶体管实现时， 开关由 PMOS晶体管来实现。
11、 如权利要求 9 所述的低关断态电流晶体管电路， 其中， 当开关由 NMOS 晶体管实现时， 开关控制端为高电平时开关导通， 开关控制端为低 电平时开关断开； 当开关由 PMOS晶体管实现时， 开关控制端为高电平时 开关断开， 开关控制端为低电平时开关导通。
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EP2933922A1 (en) 2015-10-21
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