WO2006103624A1

WO2006103624A1 - Electronic device

Info

Publication number: WO2006103624A1
Application number: PCT/IB2006/050934
Authority: WO
Inventors: Chau B. Pham; Johannes P. M. Verdaasdonk; Michel C. Korenhof
Original assignee: Nxp B.V.
Priority date: 2005-03-31
Filing date: 2006-03-28
Publication date: 2006-10-05
Also published as: EP1867048A1

Abstract

An electronic device is provided which comprises at least one first power domain (PDl) having a first supply voltage (VDDl) and at least one second power domain (PD2) having a second supply voltage (VDD2). The second power domain (PD2) comprises an input circuitry (IM) for coupling the output (CS) of the first power domain (PDl) to the second power domain (PD2). The input circuitry (IM) comprises a leakage current reduction means (N3) for reducing the leakage current through the input circuitry (IM). The leakage current reduction means (N3) is controlled by the output (O) of the second power domain (PD2).

Description

Electronic device

The invention is related to an electronic device with a first power domain having a first supply voltage and a second power domain having a second supply voltage. Within modern low power electronic devices for low power applications a plurality of CMOS elements may be combined which may be operating while others will be in a steady off-state. These elements in the steady off-state also consume a certain amount of power leading to a static power consumption. Furthermore, it is desirable to be able to cater for different power domains in the electronic device such that these separate domains can be switched off into a power saving mode if required.

Fig. 4 shows a block diagram of an electronic device based on CMOS technology. Here, three different power domains A, B and C are shown which are supplied by three different supply voltages VDDl, VDD2 and VDD3, respectively. Within a normal application, a full supply level voltage VDD2 will be applied to the power domain block B. Therefore, the input signal for the power domain block C will also have a full CMOS-level, leading to minimum leakage current. However, if a power saving mode is activated, the supply voltage VDD2 is switched off by the switch S such that the power domain block B will not consume power. Accordingly, all outputs of the power domain blocks will be floating which can cause a significant amount of leakage current in the power domain block C.

JP 2002-319630 describes an efficient way to implement the switching off a second supply voltage VDD2 to a second power domain block within an electronic device having multiple power domains. In particular, a static memory device is described here. The current for a memory matrix is reduced to VCL2/R by an additional transistor Tl, which is controlled by a signal LM. A voltage supply VCLl is switched off by a transistor T2, which is controlled by a PD signal, in order to reduce the power consumption of a circuit block 5D. However, a supply voltage VCL2 will still be present because of the data-retention requirement. Although the power consumption may be reduced for the memory matrix, all output signals thereof, namely the output signals of the sense amplifier as well as the output of the others are floating, leading to a significant amount of leakage for any subsequent power domain block in the chain. One way to deal with the floating output of power domains and the leakage current is the usage of the circuitry of Fig. 5 within one of the several power domains. The circuit has two inputs, namely A and B. Two PMOS transistors PlO, Pl 1 are connected in parallel. The gate of the PMOS transistor PlO is coupled to input A and the gate of the PMOS transistor Pl 1 is coupled to input B. In series to the parallel PMOS transistors PlO, Pl 1, two NMOS transistors Nl 2, Nl 3 are arranged, wherein the NMOS transistor Nl 3 is coupled to ground gnd and the NMOS transistor Nl 2 is coupled between the NMOS transistor Nl 3 and the output terminal Z. The circuitry of Fig. 5 is used to implement an AND function, i.e. the input A as well as the input B must be high such that the output is high. Accordingly, by applying a low state to one of the input signals A or B a defined 'low' state can be achieved the output and accordingly at the input of a power domain. In other words a floating signal is overruled. However, as the output of a previous power domain is only one of the two input signal a further control signal is required. To effectively provide this control signal the information whether the power domain is switched- off or not must be known. Therefore, the provision of such a control signal is very difficult.

It is an object of the invention to provide an electronic device with several different power domain blocks, wherein the leakage currents within these power domain blocks are reduced.

This object is solved by an electronic device according to claim 1. Therefore, an electronic device is provided which comprises at least one first power domain having a first supply voltage and at least one second power domain having a second supply voltage. The second power domain comprises an input circuitry for coupling the output of the first power domain to the second power domain. The input circuitry comprises a leakage current reduction means for reducing the leakage current through the input circuitry. The leakage current reduction means is controlled by the output of the second power domain.

Accordingly, as the leakage current reduction circuit is controlled by the output of the input circuitry, a feedback loop is established. Even if the circuitry is switched on, the input will correspond to a defined potential, i.e. will not be floating. Furthermore, the solution is easy to implement and is directly arranged within the respective power domain. No additional control signal will be needed.

According to an aspect of the invention the leakage current reduction means comprises an NMOS transistor which couples the input circuitry to ground. Therefore, the reduction of the leakage current can be performed by the introduction of a NMOS transistor which is controlled by the output of the second power domain.

According to a further aspect of the invention the second power domain comprises a first stage and a second stage. The first stage corresponds to the input circuitry. The output of the first stage is coupled to the input of the second stage. The first and second stage are each coupled between the second supply voltage and ground. The reduction of the leakage current can be realized by the introduction of the input circuitry in addition to the second stage.

These and other aspects of the invention are apparent from and will be elucidated with reference to the embodiments described hereinafter and with respect to the following figures.

Fig. Ia shows a circuit diagram of an electronic device with two power domains,

Fig. Ib shows a cross section of a PMOS transistor Pl from Fig. Ia, Fig. 2 shows a circuit diagram of an electronic device according to a first embodiment,

Fig. 3 shows a simulation of a buffer according to the state of the art as well as a buffer according to the first embodiment;

Fig. 4 shows a block diagram of an electronic device according to the prior art; and

Fig. 5 shows a circuit diagram of an input circuitry according to the prior art.

Fig. Ia shows a circuit diagram of an electronic device with two power domains, supplied by the supply voltages VDDl and VDD2, respectively. A first PMOS transistor Pl and second NMOS transistor Nl are coupled between the first supply voltage VDDl and ground, wherein the inputs thereof are coupled together, forming a first stage. A third PMOS transistor P2 and fourth NMOS transistor N2 are coupled between the second supply voltage VDD2 and ground forming a second stage, wherein the inputs thereof are also coupled together and are furthermore connected to a signal path CS which in turn corresponds to the output of the first power domain block. Fig. Ib shows a cross section of the first PMOS transistor Pl in Fig. Ia. The first PMOS transistor Pl is implemented by an N- well, a p+ region for connecting the output CS and a further p+ neighboring a n+ region, which are connected to a terminal for the first supply voltage VDDl. Within an application mode, the first supply voltage VDDl as well as the second supply voltage VDD2 are set to a high level. If this circuitry is implemented by CMOS technology then the first and second supply voltage VDDl, VDD2 will correspond to 1,8 volt. However, if a power saving mode is activated, the first supply voltage VDDl is set to a VSS level, i.e. 0 volt. The output signal CS of the first power domain block will be discharged via the junction diode Dl-level if the N-well is shorted to ground, i.e. approximately 0,6 - 0,7 volt.

In the circuitry according to Fig. Ia, the leakage current of the fourth NMOS transistor N2 in the second power domain block PD2 can impose a significant problem in accordance of the actual threshold value Vtn of the fourth NMOS transistor N2. For example, in a CMOS process, the threshold value Vtn can be 0,6 volt such that the fourth NMOS transistor N2 is in danger of conducting, when the output of the first power domain block is discharged to the level of the diode Dl, i.e. 0,6 - 0,7 volt.

Fig. 2 shows a circuit diagram of an electronic device according to a first embodiment. The electronic device comprises a first and second power domain block PDl, PD2. The first power domain block PDl corresponds to the power domain block of Fig. Ia and is supplied with a first supply voltage VDDl. The second power domain block PD2 is supplied by the second power supply voltage VDD2. A third PMOS transistor P2, fourth and fifth NMOS transistor N2 and N3 are coupled in series between the second supply voltage VDD2 and ground gnd. The inputs of the third and fourth transistor P2, N2 are coupled together and are connected to the output CS of the first power domain block PDl . Accordingly, the arrangement of the third and fourth transistor P2, N2 substantially corresponds to the arrangement of third and fourth transistor according to Fig. Ia. However, a fifth NMOS transistor N3 is now coupled between ground gnd and the fourth NMOS transistor N2. A sixth transistor PMOS P3 and a seventh NMOS transistor N4 are also coupled between the second supply voltage VDD2 and ground gnd, wherein their inputs are coupled together and are connected to the output P of the first stage, i.e. here the first power domain PDl, comprising the third PMOS, fourth NMOS and fifth NMOS transistor P2, N2, N3, respectively. The node between the sixth and seventh transistor P3, N4 constitutes the output O of the second power domain block PD2. This output signal O is coupled to the input of the fifth transistor N3.

Accordingly, the output CS of the first power domain block PDl is in a floating level, i.e. ± 0,6 volt and VDDl is set to VSS in a power saving mode. The third transistor P2 will therefore be in a conducting mode and the output P of the first stage IM will become high, then the output node O will become low. As the output O is coupled to the input of the fifth NMOS transistor N3, the NMOS transistor N3 will be switched off such that current path through the fourth NMOS transistor N2 is prevented.

Fig. 3 shows a simulation of a buffer Bl according to the prior art as well as a buffer B2 according to the first embodiment. On the x-axis the voltage and on the y-axis the current is shown. In particular, the leakage currents of the two buffers are shown. For typical conditions, i.e. 1,8 volt and a typical CMOS process, if the output of the first power domain block CS is at approximately 0,7 volt (ca 70OmV), a leakage current of 4,3 μA will be present for a buffer Bl according to the prior art. However, under the same conditions, the leakage current of a buffer B2 according to the first embodiment will only be 18 pA.

Accordingly, a significant reduction in the leakage current is achieved according to the first embodiment.

The principles of the first embodiment are applicable to all integrated circuits with different or separated power domains, in particular for low power applications. It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. In the device claim in numerating several means, several of these means can be embodied by one and the same item of hardware. The mere fact that certain measures are resided in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Furthermore, any reference signs in the claims shall not be constitute as limiting the scope of the claims.

Claims

CLAIMS:

1. An electronic device, comprising: at least one first power domain (PDl) having a first supply voltage (VDDl) and at least one second power domain (PD2) having a second supply voltage (VDD2), the second power domain (PD2) comprising an input circuitry (IM) for coupling an output of the first power domain (PDl) to the second power domain (PD2), the input circuitry (IM) comprising a leakage current reduction means (N3) for reducing a leakage current through the input circuitry (IM), the leakage current reduction means (N3) being controlled by an output of the second power domain (PD2).

2. An electronic device according to claim 1, wherein the leakage current reduction means (N3) comprises an NMOS transistor (N3), which couples the input circuitry (IM) to ground (gnd).

3. An electronic device according to claim 2, wherein the second power domain

(PD2) comprises a first stage (IM) and a second stage (S2), wherein the first stage (IM) corresponds to the input circuitry (IM), wherein the output (P) of the first stage (IM) is coupled to the input of the second stage (S2), wherein the first and second stage (IM, S2) are each coupled between the second supply voltage (VDD2) and ground (gnd).

4. An electronic device according to claim 3, wherein the first and second stage (IM, S2) each comprise a PMOS transistor and a NMOS transistor coupled in series, respectively.

5. An electronic device according to claim 4, wherein the transistors (P2, N2, N3, N4) are CMOS transistors.