WO2014059791A1 - 视频图像处理方法及装置 - Google Patents

视频图像处理方法及装置 Download PDF

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Publication number
WO2014059791A1
WO2014059791A1 PCT/CN2013/076051 CN2013076051W WO2014059791A1 WO 2014059791 A1 WO2014059791 A1 WO 2014059791A1 CN 2013076051 W CN2013076051 W CN 2013076051W WO 2014059791 A1 WO2014059791 A1 WO 2014059791A1
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WIPO (PCT)
Prior art keywords
signal
video image
original
blanking
display window
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Application number
PCT/CN2013/076051
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English (en)
French (fr)
Inventor
雷伟林
卢长军
Original Assignee
利亚德光电股份有限公司
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Application filed by 利亚德光电股份有限公司 filed Critical 利亚德光电股份有限公司
Priority to CA2888926A priority Critical patent/CA2888926C/en
Priority to DK13847903.5T priority patent/DK2911381T3/en
Priority to EP13847903.5A priority patent/EP2911381B1/en
Priority to KR1020157012983A priority patent/KR101659346B1/ko
Priority to ES13847903.5T priority patent/ES2686728T3/es
Priority to US14/436,759 priority patent/US9570036B2/en
Priority to JP2015537112A priority patent/JP2016502126A/ja
Publication of WO2014059791A1 publication Critical patent/WO2014059791A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/005—Adapting incoming signals to the display format of the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G09G5/008—Clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/14—Display of multiple viewports
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
    • H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
    • H04N21/234—Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs
    • H04N21/2343—Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs involving reformatting operations of video signals for distribution or compliance with end-user requests or end-user device requirements
    • H04N21/234309—Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs involving reformatting operations of video signals for distribution or compliance with end-user requests or end-user device requirements by transcoding between formats or standards, e.g. from MPEG-2 to MPEG-4 or from Quicktime to Realvideo
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/4302—Content synchronisation processes, e.g. decoder synchronisation
    • H04N21/4305—Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
    • H04N21/4402—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display
    • H04N21/440263—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display by altering the spatial resolution, e.g. for displaying on a connected PDA
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H04N7/0117—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving conversion of the spatial resolution of the incoming video signal
    • H04N7/0122—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving conversion of the spatial resolution of the incoming video signal the input and the output signals having different aspect ratios
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G09G2340/0435—Change or adaptation of the frame rate of the video stream
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0442—Handling or displaying different aspect ratios, or changing the aspect ratio

Definitions

  • TECHNICAL FIELD The present invention relates to the field of image processing, and in particular to a video image processing method and apparatus.
  • full-color LED displays are widely used in spliced video display, that is, a full-color full-color LED screen is formed by splicing a series of display screens with fixed physical resolution, such as a single-block display module screen with a resolution of n. *m (that is, the effective area has n columns of pixels, m rows of pixels), then the whole block of full-color LED display screen is composed of horizontal K and vertical P display module screens, and the whole block of full-color LED display The display resolution of the screen is K*n column pixels, P*m line pixels, and the screen area of different customer requirements is different.
  • the number of display modules of the full-color LED screen is also uncertain, so it can be composed of any not less than n. *m resolution display area.
  • the effective resolution of the standard video signal is specified, such as 800*600, 1024*768, 1280*1024, 1920*1080, etc. If the 1080P signal is decoded and decrypted by the HDMI signal, the effective pixel point is 1920 points horizontally.
  • the video image needs the physical display resolution of the terminal display device 1920*1080 points as the best display, but for a display device whose physical pixel does not reach 1920*1080, the effective area of the display is part of the image, and LED full-color display has no fixed physical pixel points in the field application, especially for less than 1080P physical point display requirements, the image display area is different, so when displaying video images through full-color LED display, it can not be followed
  • the pixel points are displayed point by point, which easily causes the difference between the video image and the full color LED display image.
  • the image pixel clock frequency is too high, it will bring hidden danger to the LED display driver circuit for LVDS (low-voltage differential signal) transmission interface, for example: the pixel clock frequency is too high, so that The transmission bit rate of LVDS is too high. Under the temperature rise and noise interference, the LVDS receiving end is unstable, that is, the anti-interference ability is deteriorated. Even at a large resolution, such as 1600*1200 resolution, the clock frequency reaches 162.0Mhz. Transmission of video data using the LVDS protocol is not possible.
  • LVDS low-voltage differential signal
  • the image is generally reduced or enlarged according to the size of the screen to suit the display of the LED screen, for example, the physical pixel number of the screen is P. *K, and the resolution of the image is ⁇ * ⁇ , the image with the resolution of ⁇ * ⁇ is scaled to ⁇ * ⁇ , so that although the complete video picture can be displayed, the processing method increases the front-end processing system.
  • the complexity increases the cost and the image itself is lost after processing, which reduces the quality of the image.
  • the current LED technology uses network transmission technology to limit the data transmission rate of the screen.
  • the Gbit Ethernet transmission single-port transmission rate is much smaller than the low-voltage differential transmission mode, which is not conducive to the transmission of high-definition images, so in order to transmit high-definition images. It is necessary to add multiple Ethernet transmission ports for simultaneous transmission, which increases the cost.
  • the scaling of the video images reduces the quality of the displayed images, and the processing process is complicated.
  • the display image is distorted. Currently, no effective solution has been proposed.
  • the present invention is directed to a video image processing method and apparatus, in order to display a video image of a different resolution on a splicing screen and to perform a scaling process on the video image, thereby causing distortion of the display image.
  • a video image processing method includes: receiving an original video image; adjusting a signal clock frequency of the original video image to obtain a processed video image; After receiving the command signal input by the user, intercepting the processed video image according to a predetermined size, and acquiring a video image corresponding to the display window of a predetermined size; encoding the video image corresponding to the display window of the predetermined size, and Get the encoded video image.
  • the command signal includes predetermined lateral coordinates and predetermined longitudinal coordinates, wherein after receiving the command signal input by the user, the processed video image is subjected to a clipping process according to a predetermined size to acquire a video image corresponding to the display window of a predetermined size.
  • the step of: performing pixel point calculation according to the first formula to obtain a horizontal maximum pixel point Ho of the display window of a predetermined size, wherein the first formula is: Ho ⁇ xHit -H OS ,
  • /3 ⁇ 4 is the fixed pixel clock frequency
  • ' is the pixel clock frequency of the original video image
  • the total number of line period clocks of the original video image is the interval of the effective pixels between the two lines of the output video
  • the predetermined size according to the predetermined lateral coordinate
  • the horizontal maximum pixel of the display window is intercepted to obtain a horizontal pixel of the display window of a predetermined size
  • the vertical vertical point of the original video image resolution is taken as the vertical vertical pixel of the display window of the predetermined size
  • the processed video image is captured by the horizontal pixel and the vertical vertical pixel of the display window to obtain a video image corresponding to the display window of a predetermined size.
  • the step of adjusting the signal clock frequency of the original video image to obtain the processed video image comprises: extracting the original line signal, the original field signal, the original blanking signal, and the original cancellation in the control signal of the original video image. Implicit mask signal; taking the original row signal as the clock, resetting the original field signal at the jump point of the original field signal to obtain the field sync signal; using the fixed pixel clock frequency as the clock, at the jump point of the original line signal The original line signal is reset and counted to obtain a line synchronization signal; the line synchronization signal is used as a clock, and the original blanking signal is reset and counted at a time greater than a synchronization head of the line synchronization signal as a jump point to obtain a cancellation Implicit synchronization signal; resetting the original blanking mask signal at the hopping point of the blanking synchronization signal with the blanking synchronization signal as a clock to obtain the blanking mask signal; according to the field synchronization signal, the line synchronization signal, and the
  • the method further comprises: receiving a command signal input by the user, and parsing the command signal to obtain predetermined lateral coordinates and predetermined longitudinal coordinates. Further, before the signal clock frequency of the original video image is adjusted to obtain the processed video image, the method further includes: detecting whether the data signal of the original video image is a DDR signal; and the data signal of the original video image is DDR In the case of a signal, the bit width adjustment of the data signal of the original video image is performed to obtain the original video image of the clock single edge transmission mode.
  • the method further includes: using the clock frequency of the original video image as a storage clock, and blanking the processed video image A ping-pong access operation is performed on the processed video image for storage enablement.
  • a video image processing apparatus comprising: a receiving module, configured to receive an original video image; and a first processing module, configured to: convert a signal clock frequency of the original video image Performing an adjustment process to obtain a processed video image; a second processing module, configured to: after receiving the command signal input by the user, perform a clipping process on the processed video image according to a predetermined size to obtain a display window corresponding to the predetermined size a video image; an encoding module, configured to encode a video image corresponding to a display window of a predetermined size to obtain an encoded video image.
  • the command signal includes predetermined lateral coordinates and predetermined longitudinal coordinates
  • the second processing module includes: a first calculating module, configured to perform pixels according to the first formula to obtain a horizontal maximum pixel point Ho of the display window of a predetermined size, wherein , the first formula is: Ho -H OS , where, is a fixed image
  • the clock frequency is the pixel clock frequency of the original video image
  • ⁇ is the total number of line period clocks of the original video image, and is the interval of the effective pixels between the two lines of the output video
  • the first sub-processing module is configured according to the predetermined horizontal coordinate Performing a clipping process on a horizontal maximum pixel point of a display window of a predetermined size to obtain a horizontal pixel point of a display window of a predetermined size, and using a vertical vertical point number of the original video image resolution as a vertical vertical pixel point of the display window of a predetermined size
  • the second sub-processing module is configured to intercept the processed video image according to the horizontal pixel point and the vertical vertical pixel point of the display window of the predetermined size to obtain a video image corresponding to the display window of the predetermined size.
  • the first processing module includes: an extraction module, configured to extract an original row signal, an original field signal, an original blanking signal, and an original blanking mask signal in the control signal of the original video image; For counting the original line signal, resetting the original field signal at the jump point of the original field signal to obtain the field sync signal; and second counting module for using the fixed pixel clock frequency as the clock, in the original line signal The trip point resets the original line signal to obtain the line sync signal; the third counting module is configured to use the line sync signal as the clock, and the time of the sync head larger than the line sync signal is the trip point to the original blanking signal Performing a reset count to obtain a blanking synchronization signal; a fourth counting module, configured to reset the original blanking mask signal at a trip point of the blanking synchronization signal by using a blanking synchronization signal as a clock to obtain a blanking mask The fourth sub-processing module is configured to generate a control signal of the processed video image according to the field sync signal, the line
  • the device further includes: a third processing module, configured to receive a command signal input by the user, and parse the command signal to obtain predetermined lateral coordinates and predetermined longitudinal coordinates. Further, before executing the first processing module, the device further includes: a detecting module, configured to detect whether the data signal of the original video image is a DDR signal; and a fourth processing module, configured to: the data signal of the original video image is a DDR signal In the case, the bit width adjustment of the data signal of the original video image is performed to obtain the original video image signal of the clock single edge transmission mode.
  • the device further includes: a reading module, configured to use the clock frequency of the original video image as a storage clock, and the blanking signal of the processed video image is stored and enabled
  • the video image is subjected to a ping-pong access operation.
  • the method and device for processing a video image of the present invention acquires a new line, field, and blanking synchronization signal by adjusting the clock frequency of the input image, and acquires a new video image, and then performs corresponding according to the user's demand for displaying the image.
  • FIG. 1 is a block diagram showing a structure of a video image processing apparatus according to an embodiment of the present invention
  • FIG. 2 is a detailed structural diagram of a video image processing apparatus according to an embodiment of the present invention
  • the first horizontal picture of the video output image of the display window 4 is a second horizontal screen view of a display window output video image according to an embodiment of the present invention
  • FIG. 5 is a third horizontal screen view of a display window output video image according to an embodiment of the present invention
  • FIG. 6 is an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a stitching screen of a video output window of a display window according to an embodiment of the present invention
  • FIG. 1 is a block diagram showing a structure of a video image processing apparatus according to an embodiment of the present invention
  • FIG. 2 is a detailed structural diagram of a video image processing apparatus according to an embodiment of the present invention
  • the first horizontal picture of the video output image of the display window 4 is a second horizontal screen view of a display window output video image
  • FIG. 8 is a waveform diagram of a counting process of a third counting module of a user according to an embodiment of the present invention
  • 9 is a flowchart of a video image processing method according to an embodiment of the present invention
  • FIG. 10 is a flowchart of a video image processing method according to the embodiment shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • the apparatus includes: a receiving module 10, configured to receive an original video image; and a first processing module 30, configured to adjust a signal clock frequency of the original video image to obtain a processed video.
  • the second processing module 50 is configured to: after receiving the command signal input by the user, perform a clipping process on the processed video image according to a predetermined size to obtain a video image corresponding to the display window of a predetermined size; the encoding module 70, The video image corresponding to the display window of the predetermined size is encoded to obtain the encoded video image.
  • the input original video image is received by the receiving module, and then the first processing module adjusts the signal clock frequency of the original video image to obtain the processed video image, and the second processing module receives After the command signal input by the user, the processed video image is intercepted according to a predetermined size to obtain a video image corresponding to the display window of a predetermined size, and finally the video image corresponding to the predetermined size of the display window is encoded using the encoding module. , to get the encoded video image.
  • the processing device for the video image of the present application obtains a new video image by adjusting the clock frequency of the input image, and then performs corresponding intercept output according to the requirement of the user to display the image, thereby solving the difference in the prior art in order to display on the splicing screen.
  • Resolution of the video image, and the scaling of the video image results in distortion of the displayed image
  • the problem is to achieve reliable and stable display of video images of arbitrary resolution within the optimal display area.
  • the second processing module 50 opens the display window, and then defines and outputs the video image by setting the pixel coordinates of the upper left corner of the display image region (for example, the abscissa is X and the ordinate is Y).
  • the encoding module 70 can be implemented by an LVDS encoder, that is, the encoder outputs the corresponding display window output video to the display window in a serial bit rate, for example, at 10:1.
  • the method performs parallel and serial processing, so that the bit rate of the LVDS will be 10 times the output clock frequency of the display window.
  • the command signal includes predetermined lateral coordinates and predetermined longitudinal coordinates
  • the second processing module includes: a first calculating module, configured to perform an image according to the first formula to obtain a horizontal direction of the display window of a predetermined size
  • the maximum pixel point H 0 where the first formula is Ho _H OS , Po is
  • the fixed pixel clock frequency is the pixel clock frequency of the original video image
  • HzY is the total number of line period clocks of the original video image
  • Hos is the interval of the effective pixels between the two lines of the output video
  • the first sub-processing module is used according to the predetermined horizontal direction
  • the coordinate performs a clipping process on the horizontal maximum pixel point of the display window of the predetermined size to obtain a horizontal pixel point of the display window of a predetermined size
  • the vertical vertical point number of the original video image resolution is taken as the vertical vertical pixel point of the display window of the predetermined size
  • a second sub-processing module configured to intercept the processed video image according to the horizontal pixel point and the vertical vertical pixel point of the display window of the predetermined size to obtain a video image corresponding to the display window of the predetermined size.
  • the function of the second processing module may be implemented according to the video control signal processor shown in FIG. 2, and the video control is generated according to the field synchronization signal, the line synchronization signal, the blanking synchronization signal, and the blanking mask signal. And correcting the digital signal of the original video image according to the processed video control signal to obtain the processed video image.
  • the first calculating module performs pixel point calculation according to the first formula to obtain a horizontal maximum pixel point of the display window of a predetermined size, and then the first sub-processing module compares the horizontal maximum pixel of the display window of the predetermined size according to the predetermined lateral coordinate.
  • the point is subjected to an intercepting process to obtain a horizontal pixel point of the display window of a predetermined size, and the vertical vertical point number of the original video image resolution is taken as a vertical vertical pixel point of the display window of the predetermined size, and then the third sub-processing module according to the second sub- The processing module processes the obtained horizontal pixels of the display window of a predetermined size And processing the processed video image with the vertical vertical pixel to obtain a video image corresponding to the display window of a predetermined size.
  • H 0 ⁇ xH t - H
  • 73 ⁇ 4 is a constant, which is a fixed pixel clock frequency.
  • H t is the total number of line period clocks of the original video image
  • Has is the interval of the effective pixels between the two lines of the output video
  • Ho is also the largest pixel point that the memory can read.
  • 3 is a first horizontal screen view of a display window output video image according to an embodiment of the present invention
  • FIG. 4 is a second horizontal screen view of a display window output video image according to an embodiment of the present invention
  • FIG. 6 is a schematic diagram of a vertical screen of a video output window according to an embodiment of the present invention
  • FIG. 7 is a schematic diagram of a stitching screen of a video output window of a display window according to an embodiment of the invention.
  • the input video may be a video image processed by the first processing module 30.
  • the video data output of the set image display window is always fixed at 73 ⁇ 4, and the horizontal effective pixel point Ho of the display window is enabled. The achieved is:
  • Ho is the maximum pixel output of the display window of a predetermined size, which is a fixed pixel clock frequency, which is the pixel clock frequency of the input video (ie, the original video image in the above embodiment), and Hit is the input video resolution.
  • the total number of line period clocks, Hos is the interval of the effective pixels between the two lines of the output video, that is, the time interval between the last effective pixel of the previous line and the first effective pixel of the next line in the adjacent two lines (in pixel clock cycles) Number calculation).
  • the fixed clock frequency in this embodiment may be 75 Mhz.
  • the horizontal pixel of the video input resolution can be completely output in the opening window of the predetermined size, that is, the horizontal width of the display window of the predetermined size is larger than the original video image.
  • the lateral width Specifically, the user sets the abscissa X of the initial position of the upper left corner of the display window to be 0, and the first pixel displayed in the open window is the first pixel of the input video image (ie, the original video image), such as opening the window.
  • the horizontal picture of the input image can be completely displayed. As shown in FIG. 4 and FIG.
  • the image of the open window displays one of the areas of the input image, and the area is moved by the set X coordinate, if the user inputs
  • the predetermined coordinate is ( ⁇ , ⁇ )
  • the processed video image is shifted to the right by n1 coordinates
  • the predetermined coordinate input by the user is (n2, 0)
  • the processed video image is shifted to the right by n2 coordinates.
  • the maximum displayable number of vertical vertical dots of the display window of a predetermined size is the same as the effective pixel vertical dots of the actual input image, such as the vertical resolution of the display window for an image resolution of 1280*1024@60hz
  • the maximum number of points is 1024.
  • the number of vertical dots of the display window is exactly the same as the number of vertical dots of the input image.
  • the actual application points of the LED full color screen may be uncertain. Therefore, the user can also adjust the Y coordinate to select the display of the image according to the embodiment shown in FIG. 6, that is, according to the predetermined coordinates (n, m) input by the user.
  • the user can arbitrarily adjust the display area of the LED full color screen, and intercept the image on the processed video image to obtain the best display image.
  • the user can also splicing the high-resolution image by increasing the output of the display window. If the horizontal pixel of the processed video image is twice the horizontal maximum pixel of the display window of a predetermined size, then two display frequencies can be used.
  • the set Y coordinate it is necessary to adjust the field, line and blanking signals newly generated in the above steps. If the set coordinate Y is 15, it is necessary to count the clock with the new blanking synchronization signal as The new field synchronous jump is reset, and a corresponding blanking mask signal is generated.
  • the mask signal is invalid, that is, the remaining mask signals are valid, and the mask is 0-14.
  • the data is masked by the line, and the time value of the blanking period of the field blanking signal is shifted backwards to maintain the phase with the first blanking line data.
  • the new video control signal generation and operation, as well as the memory read clock can be performed by the clock generator shown in Figure 2 at a set fixed pixel clock frequency.
  • the first processing module 30 may include: an extraction module, configured to extract an original row signal, an original field signal, an original blanking signal, and an original blanking mask signal in the control signal of the original video image.
  • a first counting module configured to clock the original row signal, reset the original field signal at a trip point of the original field signal to obtain a field sync signal; and a second counting module configured to use a fixed pixel clock frequency a clock, resetting the original line signal at a trip point of the original line signal to obtain a line sync signal;
  • a module configured to use a line synchronization signal as a clock, to reset the original blanking signal by using a time point greater than a synchronization head of the horizontal synchronization signal to obtain a blanking synchronization signal;
  • the hidden synchronization signal is that the clock resets the original blanking mask signal at the jump point of the blanking synchronization signal to obtain the blanking mask signal; the fourth sub processing module is configured to use
  • the extraction module extracts the original line signal, the original field signal, the original blanking signal, and the original blanking mask signal in the control signal of the original video image, and applies the above signal to the count of the following module.
  • the first counting module takes the original row signal as a clock, and resets the original field signal at the hopping point of the original field signal to obtain the field synchronization signal;
  • the second counting module uses the fixed pixel clock frequency as the clock, in the original line.
  • the trip point of the signal is reset and counted to obtain the line sync signal;
  • the third counting module takes the line sync signal as the clock, and performs the original blanking signal with the jump point larger than the sync head of the line sync signal as the jump point.
  • FIG. 8 is a waveform diagram of a user third counting module counting process according to an embodiment of the present invention.
  • the first counting module performs clock frequency processing on the control signal of the original video to generate a field synchronization signal: the field signal outputted by the video is jumped into the boundary with the original field signal (ie, the field signal in the control signal of the original video image).
  • the original field signal is reset and counted by using the line signal as a clock.
  • the count setting 0-nl (0 to nl) is the field signal synchronization head, the field signal level is low, and the remaining count values are high, generating a new field.
  • the sync signal i.e., the field sync signal in the above embodiment).
  • the second counting module performs clock frequency processing on the control signal of the original video to generate a field synchronization signal: for the new line synchronization signal, the original line signal (ie, the line signal in the control signal of the original video image) jumps into a boundary
  • the output clock that is, the fixed clock frequency is used as the clock for reset counting, 0-ml is set for the line signal synchronization (ie, the line signal level is low), and the remaining count values are high for the line signal to generate a new line sync signal (ie, the above)
  • the third counting module performs clock frequency processing on the control signal of the original video to generate a field synchronization signal: as shown in FIG.
  • the new blanking synchronization signal is generated by using a new line synchronization signal.
  • the clock, and the sync header of the new blanking sync signal is larger than the new line sync signal sync header.
  • the new blanking sync signal is closely connected to the memory read.
  • the memory will read.
  • the blanking signal is high, the memory will read.
  • the first data of the corresponding line of the display window of the predetermined size such as setting 0-m2 (m2>ml) to blank the blanking signal, reading the memory from m2+l
  • the blanking signal is high, that is, the pixel data output time, and in addition, the blanking signal becomes low.
  • the apparatus may further include: a third processing module, configured to receive a command signal input by the user, and parse the command signal to obtain predetermined lateral coordinates and a predetermined longitudinal direction. coordinate.
  • the device may further set a third processing module, that is, the display window coordinate resolution processor shown in FIG. 2 parses the command signal input by the user, and generally transmits the command in an SPI protocol manner. Words, including command keywords, command addresses, command data, parsing through the SPI protocol, and parsing the commands into parallel addresses, data, and control signals to the corresponding processing module.
  • the apparatus may further include: a detecting module, configured to detect whether the data signal of the original video image is a DDR signal; and a fourth processing module, configured to: in the original video In the case where the data signal of the image is a DDR signal, the bit width adjustment of the data signal of the original video image is performed to obtain the original video image of the clock single edge transmission mode.
  • the input video image ie, the original video image in the above embodiment
  • the receiving module 10 the function of the receiving module can be implemented by the data receiver shown in FIG.
  • the user may extract the video data signal in the original video image through the data receiver, and perform data synchronization processing on the video data signal, that is, perform bit width adjustment, if the video data signal is DDR.
  • the signal adjusts the DDR dual edge input mode to the clock single edge output.
  • the video data signal acquired in the foregoing module may be adjusted to obtain the processed video data.
  • the device may further include: a reading module, configured to use a clock frequency of the original video image as a storage clock, and a blanking signal of the processed video image as a storage enable pair The video image is pinged for ping-pong operations.
  • the reading module performs a ping-pong access operation on the processed video image, wherein the reading module can be implemented by using two sizes of 2048 bit (or 4096 bits) memory.
  • the reading module can be implemented by using two sizes of 2048 bit (or 4096 bits) memory.
  • one of the memories 1 is stored in one line period
  • the other memory 2 performs reading of the video image
  • the memory 2 is stored in the next line period
  • the other memory 2 performs reading, and sequentially alternates the access operation.
  • the original input clock is used as the storage clock
  • the blanking signal is stored
  • the address is incremented by 0, and the line data is incremented from the leftmost to the right. Take one pixel point of data.
  • the apparatus may further include a selector that can switch the ping-pong-operated read memory, that is, always switch to the data output of the read memory, before executing the encoding module 70.
  • a selector that can switch the ping-pong-operated read memory, that is, always switch to the data output of the read memory, before executing the encoding module 70.
  • Step S102 Receive an original video image.
  • Step S104 the signal clock frequency of the original video image is adjusted to obtain the processed video image.
  • Step S106 after receiving the command signal input by the user, performing a clipping process on the processed video image according to a predetermined size to acquire a video image corresponding to the display window of a predetermined size.
  • Step S108 Perform a coding process on the video image corresponding to the display window of a predetermined size to obtain the encoded video image.
  • the video image processing method of the present application by receiving the input original video image, and then adjusting the signal clock frequency of the original video image to obtain the processed video image, and after receiving the command signal input by the user, according to
  • the processed image is subjected to a clipping process to acquire a video image corresponding to a display window of a predetermined size, and finally a video image corresponding to a display window of a predetermined size is encoded to obtain the encoded video image.
  • the processing method of the video image of the present application obtains a new video image by adjusting the clock frequency of the input image, and then performs corresponding intercept output according to the requirement of the user to display the image, thereby solving the input video resolution or field in the prior art.
  • Step S202 as shown in FIG. 10, the video image is received, and the step S102 in the above embodiment may be implemented.
  • Step S204 the original video image is processed and the processed video image is cached. Steps S104 to 106 in the above embodiment may be performed. Step S204 in FIG. 10 is implemented; step S108 in FIG. 9 can be implemented by step S208 in FIG. 10, step S208: encoding the video image.
  • step S106 can be implemented by: opening a display window, and then defining and outputting the video image by setting pixel coordinates of the upper left corner of the display image area (eg, the abscissa is X and the ordinate is Y) to achieve
  • the intercepted output of the processed video image, and the size of the window area in which the effective image display is turned on differs depending on the resolution of the different input images (i.e., the original video image in the above embodiment).
  • the display window of the predetermined size may be the display screen size of the spliced full color LED display.
  • step S204 also receives and parses the user command signal in step S206.
  • step S108 can be implemented by an LVDS encoder, that is, the encoder outputs the corresponding display window output video to the display window in a serial bit rate, for example, serially and serially processed in a 10:1 manner.
  • the bit rate of LVDS will be 10 times of the output window output clock frequency.
  • the display window pixel clock of 75Mhz the bit rate of LVDS reaches 750Mbps. Because LVDS is differential low-voltage transmission, it can achieve high transmission bit rate and low power consumption. , high reliability, and less transmission pin characteristics.
  • the command signal includes predetermined lateral coordinates and predetermined longitudinal coordinates, wherein after receiving the command signal input by the user, the processed video image is subjected to intercept processing according to a predetermined size to obtain a corresponding predetermined size.
  • the step of displaying the video image of the window includes: performing pixel point calculation according to the first formula to obtain a horizontal maximum pixel point Ho of the display window of a predetermined size, wherein the first formula is p n
  • Ho —xHit - Hos , 73 ⁇ 4 is the fixed pixel clock frequency
  • P is the pixel clock frequency of the original video image
  • H t is the total number of line period clocks of the original video image, H is the interval of the effective pixels between the two lines of the output video; and the horizontal maximum pixel points of the display window of the predetermined size are intercepted according to the predetermined lateral coordinates to obtain a predetermined size Displaying a horizontal pixel point of the window; taking the vertical vertical point number of the original video image resolution as a vertical vertical pixel point of the display window of the predetermined size; and intercepting the processed video image according to the horizontal pixel point and the vertical vertical pixel point of the display window of the predetermined size , to obtain a video image corresponding to a display window of a predetermined size.
  • the generated video control signal is generated according to the field sync signal, the line sync signal, the blanking sync signal, and the blanking mask signal, and the digital signal of the original video image is corrected according to the processed video control signal to obtain Processed video image.
  • the command signal includes predetermined lateral coordinates and predetermined longitudinal coordinates, wherein after receiving the command signal input by the user, the processed video image is subjected to a clipping process according to a predetermined size to acquire a video image corresponding to the display window of a predetermined size.
  • the step may be implemented by: performing pixel point calculation according to the first formula to obtain a horizontal maximum pixel point of the display window of a predetermined size, and then performing interception processing on the horizontal maximum pixel point of the display window of the predetermined size according to the predetermined horizontal coordinate , to obtain a horizontal pixel point of the display window of a predetermined size, and the vertical vertical point number of the original video image resolution is taken as the vertical vertical pixel point of the display window of the predetermined size, and then the horizontal pixel point and the vertical vertical direction of the display window according to the predetermined size
  • the pixel is intercepted by the processed video image to obtain a video image corresponding to a display window of a predetermined size.
  • HzY is the total number of line period clocks of the original video image
  • Hos is the interval of the effective pixels between the two lines of the output video.
  • 3 is a first horizontal screen view of a display window output video image according to an embodiment of the present invention
  • FIG. 4 is a second horizontal screen view of a display window output video image according to an embodiment of the present invention
  • FIG. a third horizontal picture of the video output image of the display window
  • FIG. 6 is an implementation according to the present invention
  • the display window of the example outputs a schematic view of the vertical picture of the video image
  • FIG. 7 is a schematic diagram of the spliced picture of the output video image of the display window according to an embodiment of the invention.
  • the input video may be a video image processed by the first processing module 30.
  • the video data output of the set image display window is always fixed to 71 ⁇ 2, and the horizontal effective pixel point Ho of the display window is enabled. The achieved is:
  • Ho is the maximum pixel output of the display window of a predetermined size, which is a fixed pixel clock frequency, which is the pixel clock frequency of the input video (ie, the original video image in the above embodiment), and Hit is the input video resolution.
  • the total number of line period clocks, Hos is the interval of the effective pixels between the two lines of the output video, that is, the time interval between the last effective pixel of the previous line and the first effective pixel of the next line in the adjacent two lines (in pixel clock cycles) Number calculation).
  • the larger the fixed frequency is, the larger the size of the open window is, but the stability of the system may be affected.
  • the fixed pixel clock frequency in this embodiment may be 75 Mhz. In the above embodiment, as shown in FIG.
  • the horizontal pixel of the video input resolution can be completely output in the opening window of the predetermined size, that is, the horizontal width of the display window of the predetermined size is larger than the original video image.
  • the lateral width Specifically, the user sets the abscissa X of the initial position of the upper left corner of the display window to be 0, and the first pixel displayed in the open window is the first pixel of the input video image (ie, the original video image), such as opening the window.
  • the horizontal picture of the input image can be completely displayed. As shown in FIG. 4 and FIG.
  • the image of the open window displays one of the areas of the input image, and the area is moved by the set X coordinate
  • the predetermined coordinates input by the user are ( ⁇ , ⁇ )
  • the processed video image is shifted to the right by n1 coordinates
  • the predetermined coordinates input by the user is (n2, 0)
  • the processed video image is shifted to the right by n2 coordinates.
  • the maximum displayable number of vertical vertical dots of the display window of a predetermined size is the same as the effective pixel vertical dots of the actual input image, such as the vertical resolution of the display window for an image resolution of 1280*1024@60hz
  • the maximum number of points is 1024.
  • the number of vertical dots of the display window is exactly the same as the number of vertical dots of the input image.
  • the actual application points of the LED full color screen may be uncertain. Therefore, the user can also adjust the Y coordinate to select the display of the image according to the embodiment shown in FIG. 6, that is, according to the predetermined coordinates (n, m) input by the user.
  • the user can arbitrarily adjust the display area of the LED full color screen, and intercept the image on the processed video image to obtain the best display image.
  • the user can also splicing the high-resolution image by increasing the output of the display window. If the horizontal pixel of the processed video image is twice the horizontal maximum pixel of the display window of a predetermined size, two display screens can be used.
  • the user's preset coordinates for the two display screens are (0, 0) and (n, 0), respectively, and the coordinate points (xl, yl) of the first pixel of the first line of the two display screens.
  • For the set Y coordinate it is necessary to adjust the field, line and blanking signals newly generated in the above steps. If the set coordinate Y is 15, it is necessary to count the clock with the new blanking synchronization signal as The new field synchronous jump is reset, and a corresponding blanking mask signal is generated.
  • the mask signal is invalid, that is, the remaining mask signals are valid, and the mask is 0-14.
  • the data is masked by the line, and the time value of the blanking period of the field blanking signal is shifted backwards to maintain the phase with the first blanking line data.
  • the new video control signal generation and operation, as well as the memory read clock, are all performed at a set fixed pixel clock frequency.
  • the step of adjusting the signal clock frequency of the original video image to obtain the processed video image may include: extracting the original line signal, the original field signal, and the original field signal in the control signal of the original video image.
  • the trip point of the row signal resets and counts the original row signal to obtain a line sync signal; the line sync signal is used as a clock, and the original blanking signal is reset and counted by using the time of the sync head of the line sync signal as a jump point.
  • the original line signal, the original field signal, the original blanking signal, and the original blanking mask signal in the control signal of the original video image are extracted, and then the signal in the original video signal is subjected to clock frequency calculation to generate a new one.
  • the control signal is obtained, and the processed video image is acquired according to the generated new control signal.
  • the clock frequency calculation of the signal in the original video signal may be implemented by the following steps: For the clock, the original field signal is reset and counted at the jump point of the original field signal to obtain the field sync signal; the fixed pixel clock frequency is used as the clock, and the original line signal is reset and counted at the jump point of the original line signal to obtain The line sync signal is clocked by the line sync signal, and the original blanking signal is reset and counted by the time of the sync head of the line sync signal as a jump point to obtain the blanking synchronization signal; The jump point of the hidden sync signal resets the original blanking mask signal to obtain a blanking mask signal.
  • the field signal outputted by the video is jumped to the boundary with the original field signal (ie, the field signal in the control signal of the original video image), and the original field signal is reset and counted by using the line signal as a clock, and the count setting is 0.
  • -nl (0 to nl) is the field signal sync header, the field signal level is low, and the remaining count values are high, generating a new field sync signal (i.e., the field sync signal in the above embodiment).
  • the original line signal ie, the line signal in the control signal of the original video image
  • the output clock ie, the fixed clock frequency p 0
  • 0-ml is the line signal synchronization (i.e., the line signal level is low), and the remaining count values are high in the line signal to generate a new line sync signal (i.e., the line sync signal in the above embodiment).
  • the new blanking synchronization signal is generated by the new line synchronization signal, and the synchronization header of the new blanking synchronization signal is larger than the new line synchronization signal synchronization.
  • the new blanking synchronization signal is closely connected to the reading of the memory. When the blanking signal is high, the memory will read the first data of the corresponding row of the display window of the predetermined size, such as setting 0.
  • the method may further include: receiving a command signal input by the user, and parsing the command signal to obtain predetermined lateral coordinates and predetermined longitudinal coordinates.
  • the step may be implemented by step S206 in FIG. 10: receiving and parsing a user command signal, generally transmitting a command word in an SPI protocol manner, including a command keyword, a command address, and a command data.
  • the method may further include: detecting whether the data signal of the original video image is a DDR signal; In the case where the data signal of the video image is a DDR signal, the bit width adjustment of the data signal of the original video image is performed to obtain the original video image signal of the clock single edge transmission mode. Specifically, the steps are all completed in the data buffering and processing steps shown in FIG.
  • the video data signal in the original video image may be extracted, and Data synchronization is performed on the video data signal, that is, bit width adjustment is performed.
  • the video data signal is a DDR signal
  • the DDR dual edge input mode is adjusted to a clock single edge output.
  • the method may further include: using the clock frequency of the original video image as a storage clock to process the processed image
  • the blanking signal of the video image is a storage enable ping-pong access operation on the processed video image. Specifically, after receiving the original video image, the processed video image is subjected to a ping-pong access operation.
  • two sizes of 2048 bit (or 4096 bit) memories can be used by the following methods: one of the memories 1 is stored in one line period, the other memory 2 is for reading a video image, and the memory 2 is performed in the next line period. For storage, another memory 2 reads, and alternately accesses the operation.
  • the original input clock is used as the storage clock, the blanking signal is stored, the address is incremented by 0, and the line data is incremented. From the leftmost to the rightmost, incremental accesses are sequentially accessed from address 0, and each address accesses one pixel of data.
  • the method can also switch the read memory of the ping-pong operation through the selector, that is, always switch to the data output of the memory that is read.
  • the invention is not limited to any specific combination of hardware and software.
  • the above is only the preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes can be made to the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and scope of the present invention are intended to be included within the scope of the present invention.

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Abstract

本发明公开了一种视频图像处理方法及装置。其中，该方法包括：接收原始视频图像；将原始视频图像的信号时钟频率进行调整处理，以获取处理后的视频图像；在接收到用户输入的命令信号之后，根据预定尺寸对处理后的视频图像进行截取处理，并获取对应预定尺寸的显示窗口的视频图像；将对应预定尺寸的显示窗口的视频图像进行编码处理，并获取编码后的视频图像。通过本发明的视频图像的处理方法及装置，通过调整输入的图像的时钟频率，获取新的行、场、消隐同步信号，然后根据用户显示图像的需求进行相应的截取输出，实现了可靠、稳定的将任意分辨率的视频图像在最佳显示区域范围内显示的效果。

Description

视频图像处理方法及装置 技术领域 本发明涉及图像处理领域， 具体而言， 涉及一种视频图像处理方法及装置。 背景技术 目前， 全彩 LED显示器广泛应用于拼接型的视频显示， 即整块全彩 LED屏幕由 一系列固定物理分辨率的显示模块屏拼接而成， 如若单块显示模块屏的分辨率为 n*m (即显示有效区域有 n列像素， m行像素），那么整块全彩 LED显示屏在由横向 K个， 纵向 P个显示模块屏拼接而成的情况下， 整块全彩 LED显示屏的显示分辨率为 K*n 列像素， P*m行像素， 并且， 不同客户需求屏体面积的大小不同， 全彩 LED屏的显示 模块拼接数目也不确定， 因此可以组成任意不小于 n*m分辨率的显示区域。 然而， 标 准视频信号的有效分辨率是有规格的，比如 800*600， 1024*768， 1280*1024, 1920*1080 等，如 1080P信号经 HDMI信号解码及解密后，其有效像素点横向 1920点，纵向 1080 点， 则该视频图像需要终端显示设备物理分辨率 1920*1080点作为最佳显示， 可是对 于物理像素达不到 1920*1080的显示设备，其显示的有效区域为图像的一部分，而 LED 全彩显示屏其现场应用物理像素点的不固定， 特别是对于小于 1080P物理点显示的需 求， 对图像显示的区域要求不同， 因此在通过全彩 LED显示器显示视频图像时， 由于 不能够按照像素点逐点显示， 容易造成视频图像与全彩 LED显示图像的差异。 此外， 对于高分辨率的视频流信号， 由于图像像素时钟频率过高， 会给适用于 LVDS (低压差 分信号)传输接口的 LED显示驱动电路带来接收隐患， 例如： 像素时钟频率过高， 使 得 LVDS的传输比特率过高， 电路在温升和噪声干扰下， LVDS接收端的不稳定， 即 抗干扰能力变差，甚至在大分辨率下，如 1600*1200分辨率， 时钟频率达到 162.0Mhz， 运用 LVDS协议传输视频数据是无法实现的。 为了解决上述问题， 在使用全彩 LED显示器显示任意分辨率的情况下，一般对图 像按照屏体的大小进行图像的缩小或者放大处理以适合 LED屏的显示，比如屏体的物 理像素点数为 P*K， 而图像的分辨率为 Μ*Ν， 会采用把分辨率为 Μ*Ν的图像进行缩 放为 Ρ*Κ， 这样虽然能显示完整的视频画面， 但是该处理方法增加了前端处理系统的 复杂度， 提高了成本， 并且图像本身进行处理后有所损失， 降低了图像的品质。 此外， 目前 LED采用网络传输的技术方法使得屏体的数据传输速率受限， 比如 Gbit以太网 传输单口传输速率要远小于低压差分传输的方式， 不利于对于高清图像的传输， 因此 为了传输高清图像就要增加多个以太网传输口进行同时传输， 这样又增加了成本。 由上可知， 现有技术中为了在拼接屏体上显示不同分辨率的视频图像， 而对视频 图像进行缩放处理后降低了显示图像的品质， 并且处理过程复杂。 针对现有技术中为了在拼接屏上显示不同分辨率的视频图像， 而对视频图像进行 缩放处理后， 导致显示图像失真的问题， 目前尚未提出有效的解决方案。 发明内容 针对相关技术为了在拼接屏上显示不同分辨率的视频图像， 而对视频图像进行缩 放处理后， 导致显示图像失真的问题， 本发明的主要目的在于提供一种视频图像处理 方法及装置， 以解决上述问题。 为了实现上述目的， 根据本发明的一个方面， 提供了一种视频图像处理方法， 该 方法包括： 接收原始视频图像； 将原始视频图像的信号时钟频率进行调整处理， 以获 取处理后的视频图像； 在接收到用户输入的命令信号之后， 根据预定尺寸对处理后的 视频图像进行截取处理， 并获取对应预定尺寸的显示窗口的视频图像； 将对应预定尺 寸的显示窗口的视频图像进行编码处理， 并获取编码后的视频图像。 进一步地， 命令信号包括预定横向坐标和预定纵向坐标， 其中， 在接收到用户输 入的命令信号之后， 根据预定尺寸对处理后的视频图像进行截取处理， 以获取对应预 定尺寸的显示窗口的视频图像的步骤包括： 根据第一公式进行像素点计算， 以获取预 定尺寸的显示窗口的横向最大像素点 Ho， 其中， 第一公式为： Ho = ^xHit -HOS，
Pi
其中， /¾为固定像素时钟频率， '为原始视频图像的像素时钟频率， 为原始视频 图像的行周期时钟总数， 为输出视频的两行之间有效像素的间隔； 根据预定横向 坐标对预定尺寸的显示窗口的横向最大像素点进行截取处理， 以获取预定尺寸的显示 窗口的横向像素点； 将原始视频图像分辨率的垂直纵向点数作为预定尺寸的显示窗口 的垂直纵向像素点； 根据预定尺寸的显示窗口的横向像素点和垂直纵向像素点截取处 理后的视频图像， 以获取对应预定尺寸的显示窗口的视频图像。 进一步地， 将原始视频图像的信号时钟频率进行调整处理， 以获取处理后的视频 图像的步骤包括： 提取原始视频图像的控制信号中的原始行信号、 原始场信号、 原始 消隐信号以及原始消隐掩模信号； 以原始行信号为时钟， 在原始场信号的跳变点对原 始场信号进行复位计数， 以获取场同步信号； 以固定像素时钟频率为时钟， 在原行信 号的跳变点对原始行信号进行复位计数， 以获取行同步信号； 以行同步信号为时钟， 以大于行同步信号的同步头的时刻为跳变点对原始消隐信号进行复位计数， 以获取消 隐同步信号； 以消隐同步信号为时钟在消隐同步信号的跳变点对原始消隐掩模信号进 行复位计数， 以获取消隐掩模信号； 根据场同步信号、 行同步信号、 消隐同步信号以 及消隐掩模信号生成处理后的视频控制信号， 并获取处理后的视频图像。 进一步地， 在接收原始视频图像之后， 方法还包括： 接收用户输入的命令信号， 并将命令信号进行解析处理， 以获取预定横向坐标和预定纵向坐标。 进一步地， 在将原始视频图像的信号时钟频率进行调整处理， 以获取处理后的视 频图像之前， 方法还包括： 检测原始视频图像的数据信号是否为 DDR信号； 在原始 视频图像的数据信号为 DDR信号的情况下， 对原始视频图像的数据信号进行比特位 宽调整， 以获取时钟单沿传输模式的原始视频图像。 进一步地， 在将原始视频图像的信号时钟频率进行调整处理， 以获取处理后的视 频图像之后， 方法还包括： 以原始视频图像的时钟频率为存储时钟， 以处理后的视频 图像的消隐信号为存储使能对处理后的视频图像进行乒乓存取操作。 为了实现上述目的， 根据本发明的一个方面， 提供了一种视频图像处理装置， 该 装置包括： 接收模块， 用于接收原始视频图像； 第一处理模块， 用于将原始视频图像 的信号时钟频率进行调整处理， 以获取处理后的视频图像； 第二处理模块， 用于在接 收到用户输入的命令信号之后， 根据预定尺寸对处理后的视频图像进行截取处理， 以 获取对应预定尺寸的显示窗口的视频图像； 编码模块， 用于将对应预定尺寸的显示窗 口的视频图像进行编码处理， 以获取编码后的视频图像。 进一步地， 命令信号包括预定横向坐标和预定纵向坐标， 其中， 第二处理模块包 括： 第一计算模块， 用于根据第一公式进行像素 以获取预定尺寸的显示窗口 的横向最大像素点 Ho， 其中， 第一公式为： Ho -HOS， 其中， 为固定像
Figure imgf000005_0001
素时钟频率， 为原始视频图像的像素时钟频率， ^^为原始视频图像的行周期时钟 总数， 为输出视频的两行之间有效像素的间隔； 第一子处理模块， 用于根据预定 横向坐标对预定尺寸的显示窗口的横向最大像素点进行截取处理， 以获取预定尺寸的 显示窗口的横向像素点， 并将原始视频图像分辨率的垂直纵向点数作为预定尺寸的显 示窗口的垂直纵向像素点； 第二子处理模块， 用于根据预定尺寸的显示窗口的横向像 素点和垂直纵向像素点截取处理后的视频图像， 以获取对应预定尺寸的显示窗口的视 频图像。 进一步地， 第一处理模块包括： 提取模块， 用于提取原始视频图像的控制信号中 的原始行信号、 原始场信号、 原始消隐信号以及原始消隐掩模信号； 第一计数模块， 用于以原始行信号为时钟， 在原始场信号的跳变点对原始场信号进行复位计数， 以获 取场同步信号； 第二计数模块， 用于以固定像素时钟频率为时钟， 在原行信号的跳变 点对原始行信号进行复位计数， 以获取行同步信号； 第三计数模块， 用于以行同步信 号为时钟，以大于行同步信号的同步头的时刻为跳变点对原始消隐信号进行复位计数， 以获取消隐同步信号； 第四计数模块， 用于以消隐同步信号为时钟在消隐同步信号的 跳变点对原始消隐掩模信号进行复位计数， 以获取消隐掩模信号； 第四子处理模块， 用于根据场同步信号、 行同步信号、 消隐同步信号以及消隐掩模信号生成处理后的视 频图像的控制信号， 并获取处理后的视频图像。 进一步地， 在执行接收模块之后， 装置还包括： 第三处理模块， 用于接收用户输 入的命令信号， 并将命令信号进行解析处理， 以获取预定横向坐标和预定纵向坐标。 进一步地， 在执行第一处理模块之前， 装置还包括： 检测模块， 用于检测原始视 频图像的数据信号是否为 DDR信号； 第四处理模块， 用于在原始视频图像的数据信 号为 DDR信号的情况下， 对原始视频图像的数据信号进行比特位宽调整， 以获取时 钟单沿传输模式的原始视频图像信号。 进一步地， 在执行第一处理模块之后， 装置还包括： 读取模块， 用于以原始视频 图像的时钟频率为存储时钟， 以处理后的视频图像的消隐信号为存储使能对处理后的 视频图像进行乒乓存取操作。 通过本发明的视频图像的处理方法及装置， 通过调整输入的图像的时钟频率， 获 取新的行、 场、 消隐同步信号， 并获取新的视频图像， 然后根据用户显示图像的需求 进行相应的截取输出，解决了现有技术中为了在拼接屏上显示不同分辨率的视频图像， 而对视频图像进行缩放处理后， 导致显示图像失真的问题， 实现了可靠、 稳定的将任 意分辨率的视频图像在最佳显示区域范围内显示的效果。 附图说明 此处所说明的附图用来提供对本发明的进一步理解， 构成本申请的一部分， 本发 明的示意性实施例及其说明用于解释本发明， 并不构成对本发明的不当限定。 在附图 中： 图 1是根据本发明实施例的视频图像处理装置方法的结构示意图； 图 2是根据本发明实施例的视频图像处理装置方法的详细结构示意图； 图 3是根据本发明实施例的显示窗口输出视频图像的第一横向画面示意图； 图 4是根据本发明实施例的显示窗口输出视频图像的第二横向画面示意图； 图 5是根据本发明实施例的显示窗口输出视频图像的第三横向画面示意图； 图 6是根据本发明实施例的显示窗口输出视频图像的纵向画面示意图； 图 7是根据本发明实施例的显示窗口输出视频图像的拼接画面示意图； 图 8是根据本发明实施例的用户第三计数模块计数处理的波形示意图； 图 9是根据本发明实施例的视频图像处理方法的流程图； 以及 图 10是根据图 9所示实施例的视频图像处理方法的流程图。 具体实施方式 需要说明的是， 在不冲突的情况下， 本申请中的实施例及实施例中的特征可以相 互组合。 下面将参考附图并结合实施例来详细说明本发明。 图 1是根据本发明实施例的视频图像处理装置的结构示意图。 图 2是根据本发明 实施例的视频图像处理装置的详细结构示意图。 如图 1和图 2所示， 该装置包括： 接收模块 10， 用于接收原始视频图像； 第一处 理模块 30， 用于将原始视频图像的信号时钟频率进行调整处理， 以获取处理后的视频 图像； 第二处理模块 50， 用于在接收到用户输入的命令信号之后， 根据预定尺寸对处 理后的视频图像进行截取处理， 以获取对应预定尺寸的显示窗口的视频图像； 编码模 块 70， 用于将对应预定尺寸的显示窗口的视频图像进行编码处理， 以获取编码后的视 频图像。 采用本申请的视频图像处理装置， 通过接收模块接收输入的原始视频图像， 然后 第一处理模块将原始视频图像的信号时钟频率进行调整处理， 以获取处理后的视频图 像， 第二处理模块在接收到用户输入的命令信号之后， 根据预定尺寸对处理后的视频 图像进行截取处理， 以获取对应预定尺寸的显示窗口的视频图像， 最后使用编码模块 将对应预定尺寸的显示窗口的视频图像进行编码处理， 以获取编码后的视频图像。 本 申请的视频图像的处理装置， 通过调整输入的图像的时钟频率， 获取新的视频图像， 然后根据用户显示图像的需求进行相应的截取输出， 解决了现有技术中为了在拼接屏 上显示不同分辨率的视频图像， 而对视频图像进行缩放处理后， 导致显示图像失真的 问题， 实现了可靠、 稳定的将任意分辨率的视频图像在最佳显示区域范围内显示的效 果。 在上述实施例中，第二处理模块 50开启显示窗口，然后通过设置显示图像区域的 左上角的像素坐标 （如： 横坐标为 X， 纵坐标为 Y) 对视频图像进行定义输出， 以实 现对处理后的视频图像的截取输出， 并且， 开启有效图像显示的窗口面积大小随不同 输入图像 （即为上述实施例中的原始视频图像） 的分辨率而有所不同。 其中， 预定尺 寸的显示窗口可以是拼接型全彩 LED显示器的显示屏幕大小。 在上述实施例中， 如图 2所示， 编码模块 70可以通过 LVDS编码器实现， 即编码 器把相应的显示窗口输出视频以串行比特率的方式输出到显示窗口， 比如以 10: 1的 方式进行并串处理，这样 LVDS的比特率将为显示窗口输出时钟频率的 10倍，如 Po为 75Mhz的显示窗口像素时钟， 则 LVDS的比特率达到 750Mbps， 由于 LVDS为差分低 压传输， 因此可实现传输比特率高， 功耗小， 可靠性高， 并且较少传输引脚的特点。 根据本申请的上述实施例， 命令信号包括预定横向坐标和预定纵向坐标， 其中， 第二处理模块包括： 第一计算模块， 用于根据第一公式进行像 ， 以获取预定 尺寸的显示窗口的横向最大像素点 H0， 其中， 第一公式为 Ho _HOS， Po为
Figure imgf000008_0001
固定像素时钟频率， 为原始视频图像的像素时钟频率， HzY为原始视频图像的行周 期时钟总数， Hos为输出视频的两行之间有效像素的间隔； 第一子处理模块， 用于根 据预定横向坐标对预定尺寸的显示窗口的横向最大像素点进行截取处理， 以获取预定 尺寸的显示窗口的横向像素点， 并将原始视频图像分辨率的垂直纵向点数作为预定尺 寸的显示窗口的垂直纵向像素点； 第二子处理模块， 用于根据预定尺寸的显示窗口的 横向像素点和垂直纵向像素点截取处理后的视频图像， 以获取对应预定尺寸的显示窗 口的视频图像。 其中， 可以根据图 2中所示的视频控制信号处理器实现上述第二处理 模块的功能， 具体根据场同步信号、 行同步信号、 消隐同步信号以及消隐掩模信号生 成处理后的视频控制信号， 并根据处理后的视频控制信号对原始视频图像的数字信号 进行修正处理， 以获取处理后的视频图像。 具体地， 第一计算模块根据第一公式进行像素点计算， 以获取预定尺寸的显示窗 口的横向最大像素点^，然后第一子处理模块根据预定横向坐标对预定尺寸的显示窗 口的横向最大像素点进行截取处理， 以获取预定尺寸的显示窗口的横向像素点， 并将 原始视频图像分辨率的垂直纵向点数作为预定尺寸的显示窗口的垂直纵向像素点， 之 后第三子处理模块根据第二子处理模块处理得到的预定尺寸的显示窗口的横向像素点 和垂直纵向像素点截取处理后的视频图像， 以获取对应预定尺寸的显示窗口的视频图 像。 其中， 第一公式为 H0 = ^xH t - H ， 7¾是一个常量， 为固定像素时钟频率，
Pi
为原始视频图像的像素时钟频率， H t为原始视频图像的行周期时钟总数， Has为 输出视频的两行之间有效像素的间隔， Ho也为存储器能读取的最大的像素点。 图 3是根据本发明实施例的显示窗口输出视频图像的第一横向画面示意图； 图 4 是根据本发明实施例的显示窗口输出视频图像的第二横向画面示意图； 图 5是根据本 发明实施例的显示窗口输出视频图像的第三横向画面示意图； 图 6是根据本发明实施 例的显示窗口输出视频图像的纵向画面示意图； 图 7是根据本发明实施例的显示窗口 输出视频图像的拼接画面示意图。 其中， 上述图 3至图 7中的显示窗口均可以是预定 尺寸的显示窗口， 输入视频均可以是对经过第一处理模块 30处理后的视频图像。 例如， 以输入的视频图像 （即原始视频图像） 的分辨率 M*N为例， 设定开启的 图像显示窗口的视频数据输出始终固定为 7¾， 则开启显示窗口的横向有效像素点 Ho 最大能达到的为：
Po
Ho =— xHit - Hos ,
Pi 上述公式中， Ho为预定尺寸的显示窗口输出的最大像素点， 为固定像素时钟 频率， 为输入视频 （即上述实施例中的原始视频图像） 的像素时钟频率， Hit为输 入视频分辨率的行周期时钟总数， Hos为输出视频的两行之间有效像素的间隔， 即相 邻两行中前一行最后一个有效像素与后一行第一个有效像素之间的时间间隔 （以像素 时钟周期个数计算）。 其中， 固定频率 越大， 则开启窗口的尺寸越大， 但系统的稳 定性会受影响， 在本实施例中的固定时钟频率 可以是 75Mhz。 在上述实施例中， 如图 3所示， 若 Po > P ,则在预定尺寸的开启窗口能够完全输 出视频输入分辨率的横向像素点， 即开启预定尺寸的显示窗口的横向宽度大于原始视 频图像的横向宽度。 具体地， 用户设定显示窗口的左上角初始位置的横坐标 X为 0， 则开启窗口显示的第一个像素为输入视频图像 （即原始视频图像） 的第一个像素点， 如开启窗口的横向像素点数大于输入图像的横向像素点数， 则能够完整显示输入图像 的横向画面。 如图 4和图 5所示， 如果输入图像横向点数大于开启窗口点数， 则开启窗口的图 像显示输入图像的其中一个区域， 该区域由设定的 X坐标进行移动， 如果用户输入的 预定坐标为（ηΐ,θ) ,则将处理后的视频图像向右平移 nl个坐标， 如果用户输入的预定 坐标为 （n2,0) ，则将处理后的视频图像向右平移 n2个坐标。 在本申请的上述实施例中， 预定尺寸的显示窗口的垂直纵向点数的最大可显示数 目与实际输入图像的有效像素垂直点数相同， 如对于 1280*1024@60hz的图像分辨率 其显示窗口的垂直点数最大为 1024。 如图 6所示， 对于用户设定的 Y坐标为 0时， 其 显示窗口的垂直点数与输入图像的垂直点数刚好相同。然而， 对于 LED全彩屏的实际 应用点数可能不确定， 因此， 用户也可以按照图 6所示的实施例调整 Y坐标进行图像 的显示的选取， 即， 根据用户输入的预定坐标 （n， m) 设定显示窗口的输出视频图像 的第一行第一列的第一个像素点的坐标。 由上描述可知， 在本申请的上述实施例中， 用户可以任意调整 LED全彩屏的显示 区域， 在处理后的视频图像上截取图像以得到最佳的显示影像， 另外， 如图 7所示， 用户还可以对于高分辨率的图像可以通过增加显示窗口的输出进行拼接， 如果处理后 的视频图像的横向像素点预定尺寸的显示窗口的横向最大像素点的两倍， 则可以用两 个显示频拼接显示， 则用户对于两个显示屏的预设坐标分别为 （0， 0)和 （n， 0)， 则 两个显示屏的的第一行第一个像素点的坐标点 （xl， yl )和 （x2， y2)分别为 （0， 0) 和 （n， 0)， 其中， n=xl+l， 图 7中的 m可以为 0。 而对于设定的 Y坐标则需要对完成上述步骤新产生的场、行、消隐信号进行调整， 如设定坐标 Y为 15， 则需要对以新的消隐同步信号为时钟进行计数， 以新场同步跳变 进行复位， 并产生相应的消隐掩模信号， 例如， 对于计数值为 0-14， 掩模信号无效即 为 0， 其余掩模信号有效， 掩模后则把 0-14行的数据屏蔽， 同时向后移位场同步信号 15个消隐周期的时间值， 以保持与第一个消隐行数据的相位。 另外， 对于新的视频控制信号产生及操作， 以及存储器读取的时钟均可以通过图 2所示的时钟发生器在设定的固定像素时钟频率下进行。 通过本申请的上述实施例， 既可以实现图像的任意区域显示及拼接， 而且能够灵 活的适应 LED实际应用的需求， 以固定较低的传输码率实现与 LED屏体的信号传输， 保证系统的可靠性。 在本发明的上述实施例中， 第一处理模块 30可以包括： 提取模块， 用于提取原始 视频图像的控制信号中的原始行信号、 原始场信号、 原始消隐信号以及原始消隐掩模 信号； 第一计数模块， 用于以原始行信号为时钟， 在原始场信号的跳变点对原始场信 号进行复位计数， 以获取场同步信号； 第二计数模块， 用于以固定像素时钟频率为时 钟， 在原行信号的跳变点对原始行信号进行复位计数， 以获取行同步信号； 第三计数 模块， 用于以行同步信号为时钟， 以大于行同步信号的同步头的时刻为跳变点对原始 消隐信号进行复位计数， 以获取消隐同步信号； 第四计数模块， 用于以消隐同步信号 为时钟在消隐同步信号的跳变点对原始消隐掩模信号进行复位计数， 以获取消隐掩模 信号； 第四子处理模块， 用于根据场同步信号、 行同步信号、 消隐同步信号以及消隐 掩模信号生成处理后的视频图像的控制信号， 并获取处理后的视频图像。 具体地， 提取模块提取原始视频图像的控制信号中的原始行信号、 原始场信号、 原始消隐信号以及原始消隐掩模信号， 将上述信号运用到下述模块的计数中。 其中， 第一计数模块， 以原始行信号为时钟， 在原始场信号的跳变点对原始场信号进行复位 计数， 以获取场同步信号； 第二计数模块以固定像素时钟频率为时钟， 在原行信号的 跳变点对原始行信号进行复位计数， 以获取行同步信号； 第三计数模块以行同步信号 为时钟， 以大于行同步信号的同步头的时刻为跳变点对原始消隐信号进行复位计数， 以获取消隐同步信号； 第四计数模块以消隐同步信号为时钟在消隐同步信号的跳变点 对原始消隐掩模信号进行复位计数， 以获取消隐掩模信号。 在执行完上述模块之后， 第四子处理模块根据执行上述模块获取的场同步信号、 行同步信号、 消隐同步信号以 及消隐掩模信号生成处理后的视频图像的控制信号， 并获取处理后的视频图像。 图 8是根据本发明实施例的用户第三计数模块计数处理的波形示意图。 例如，第一计数模块对原始视频的控制信号进行时钟频率处理， 生成场同步信号： 视频输出的场信号以原有的场信号 （即原始视频图像的控制信号中的场信号） 跳变为 界， 以行信号为时钟对原有的场信号进行复位计数， 计数设定 0-nl(0至 nl)为场信号 同步头， 场信号电平为低， 其余计数值为高， 生成新的场同步信号 （即上述实施例中 的场同步信号）。第二计数模块对原始视频的控制信号进行时钟频率处理， 生成场同步 信号： 对于新的行同步信号， 以原有的行信号 （即原始视频图像的控制信号中的行信 号） 跳变为界， 以输出时钟 （即固定时钟频率 为时钟进行复位计数， 设定 0-ml 为行信号同步（即行信号电平为低），其余计数值为行信号高，生成新的行同步信号（即 上述实施例中的行同步信号）。 第三计数模块对原始视频的控制信号进行时钟频率处 理， 生成场同步信号： 如图 8所示， 新的消隐同步信号的生成以新的行同步信号为时 钟， 且新的消隐同步信号的同步头要大于新的行同步信号同步头， 另外， 新的消隐同 步信号与存储器的读取紧密相连， 在消隐信号一旦为高时， 存储器将读取输出预定尺 寸的显示窗口的相应行的第一个数据， 如设定 0-m2 ( m2>ml ) 为消隐信号为低， 从 m2+l 读取存储器像素数据， 在 （m2+l ) -m3 期间， 消隐信号为高， 即像素数据输出 时间， 此外， 消隐信号变为低。 根据本申请的上述实施例， 在执行接收模块 10之后， 装置还可以包括： 第三处理 模块， 用于接收用户输入的命令信号， 并将命令信号进行解析处理， 以获取预定横向 坐标和预定纵向坐标。 具体地， 在执行接收模块之后， 该装置还可以设置第三处理模块， 也即图 2中所 示的显示窗口坐标解析处理器对用户输入的命令信号进行解析， 一般以 SPI的协议方 式传输命令字， 包括命令关键字， 命令地址， 命令数据， 通过 SPI协议的解析， 并把 命令解析为并行的地址， 数据， 控制信号给相应的处理模块。 在本申请的上述实施例中， 在执行第一处理模块 30之前， 装置还可以包括： 检测 模块， 用于检测原始视频图像的数据信号是否为 DDR信号； 第四处理模块， 用于在 原始视频图像的数据信号为 DDR信号的情况下， 对原始视频图像的数据信号进行比 特位宽调整， 以获取时钟单沿传输模式的原始视频图像。 具体地， 输入的视频图像 （即上述实施例中原始视频图像）通过接收模块 10 (可 通过图 2所示的数据接收器实现接收模块的功能） 对其进行接收， 上述实施例中的接 收模块 10用户接收原始视频图像之后，可以通过数据接收器将原始视频图像中的视频 数据信号进行提取， 并对该视频数据信号进行数据同步处理， 也即进行比特位宽调整， 如果视频数据信号为 DDR信号，则将 DDR双沿输入模式调整为时钟单沿输出。并且， 在执行第一处理模块 30之后，可以对上述模块中获取到的视频数据信号进行调整， 以 获取处理后的视频数据。 另外， 在执行第一处理模块 30之后， 装置还可以包括： 读取模块， 用于以原始视 频图像的时钟频率为存储时钟， 以处理后的视频图像的消隐信号为存储使能对处理后 的视频图像进行乒乓存取操作。 具体地，在执行第一处理模块 30之后， 读取模块对处理后的视频图像进行乒乓存 取操作， 其中， 读取模块可以使用两个大小为 2048bit (或者 4096bit) 存储器来实现。 具体地， 在一行周期下其中一个存储器 1进行存储， 另外一个存储器 2进行读取视频 图像， 而在下一行周期下进行存储器 2进行存储， 另外一个存储器 2进行读取， 依次 交替存取操作， 在存储数据时， 以原输入时钟为存储时钟， 消隐信号为存储使能， 地 址从 0依次时钟节拍递增， 把行数据从最左边至最右边， 从地址 0依次递增存取， 每 个地址存取一个像素点数据。 另外， 该装置在执行编码模块 70之前， 还可以包括选择器， 该选择器可以对乒乓 操作的读取存储器进行切换， 即总是切换到读取的那个存储器的数据输出中去。 图 9是根据本发明实施例的视频图像处理方法的流程图。图 10是根据图 9所示实 施例的视频图像处理方法的流程图。 如图 9和图 10所示， 该方法包括如下步骤： 步骤 S102, 接收原始视频图像。 步骤 S104, 将原始视频图像的信号时钟频率进行调整处理， 以获取处理后的视频 图像。 步骤 S106, 在接收到用户输入的命令信号之后， 根据预定尺寸对处理后的视频图 像进行截取处理， 以获取对应预定尺寸的显示窗口的视频图像。 步骤 S108, 将对应预定尺寸的显示窗口的视频图像进行编码处理， 以获取编码后 的视频图像。 采用本申请的视频图像处理方法， 通过接收输入的原始视频图像， 然后将原始视 频图像的信号时钟频率进行调整处理， 以获取处理后的视频图像， 并在接收到用户输 入的命令信号之后， 根据预定尺寸对处理后的视频图像进行截取处理， 以获取对应预 定尺寸的显示窗口的视频图像， 最后将对应预定尺寸的显示窗口的视频图像进行编码 处理， 以获取编码后的视频图像。 本申请的视频图像的处理方法， 通过调整输入的图 像的时钟频率， 获取新的视频图像， 然后根据用户显示图像的需求进行相应的截取输 出， 解决了现有技术中在输入视频分辨率或场频不同的情况下， 为了适应拼接屏的图 像显示而对图像进行缩放处理会导致图像失真的问题， 实现了可靠、 稳定的将任意分 辨率的视频图像在最佳显示区域范围内显示的效果。 如图 10所示的步骤 S202, 接收视频图像， 可以实现上述实施例中的步骤 S102; 步骤 S204, 处理原始视频图像并缓存处理后的视频图像， 上述实施例中的步骤 S104 至步骤 106均可以在图 10中的步骤 S204实现； 图 9中的步骤 S108可以通过图 10中 的步骤 S208实现， 步骤 S208: 对视频图像进行编码。 具体地， 步骤 S106可以通过如 下方法实现： 开启显示窗口， 然后通过设置显示图像区域的左上角的像素坐标 （如： 横坐标为 X， 纵坐标为 Y) 对视频图像进行定义输出， 以实现对处理后的视频图像的 截取输出， 并且， 开启有效图像显示的窗口面积大小随不同输入图像 （即为上述实施 例中的原始视频图像） 的分辨率而有所不同。 其中， 预定尺寸的显示窗口可以是拼接 型全彩 LED显示器的显示屏幕大小。 另外， 步骤 S204也会将步骤 S206: 接收并解析 用户命令信号。 在上述实施例中，步骤 S108可以通过 LVDS编码器实现， 即编码器把相应的显示 窗口输出视频以串行比特率的方式输出到显示窗口， 比如以 10: 1的方式进行并串处 理， 这样 LVDS的比特率将为显示窗口输出时钟频率的 10倍， 如 为 75Mhz的显示 窗口像素时钟， 则 LVDS的比特率达到 750Mbps， 由于 LVDS为差分低压传输， 因此 可实现传输比特率高， 功耗小， 可靠性高， 并且较少传输引脚的特点。 在本申请的上述实施例中， 命令信号包括预定横向坐标和预定纵向坐标， 其中， 在接收到用户输入的命令信号之后，根据预定尺寸对处理后的视频图像进行截取处理， 以获取对应预定尺寸的显示窗口的视频图像的步骤包括： 根据第一公式进行像素点计 算， 以获取预定尺寸的显示窗口的横向最大像素点 Ho， 其中， 第一公式为 pn
Ho =—xHit - Hos , 7¾为固定像素时钟频率， P为原始视频图像的像素时钟频率， Pi
H t为原始视频图像的行周期时钟总数， H 为输出视频的两行之间有效像素的间隔； 根据预定横向坐标对预定尺寸的显示窗口的横向最大像素点进行截取处理， 以获取预 定尺寸的显示窗口的横向像素点； 将原始视频图像分辨率的垂直纵向点数作为预定尺 寸的显示窗口的垂直纵向像素点； 根据预定尺寸的显示窗口的横向像素点和垂直纵向 像素点截取处理后的视频图像， 以获取对应预定尺寸的显示窗口的视频图像。 其中， 根据场同步信号、 行同步信号、 消隐同步信号以及消隐掩模信号生成处理后的视频控 制信号， 并根据处理后的视频控制信号对原始视频图像的数字信号进行修正处理， 以 获取处理后的视频图像。 具体地， 命令信号包括预定横向坐标和预定纵向坐标， 其中， 在接收到用户输入 的命令信号之后， 根据预定尺寸对处理后的视频图像进行截取处理， 以获取对应预定 尺寸的显示窗口的视频图像的步骤可以通过如下方法实现： 根据第一公式进行像素点 计算， 以获取预定尺寸的显示窗口的横向最大像素点 ^，然后根据预定横向坐标对预 定尺寸的显示窗口的横向最大像素点进行截取处理， 以获取预定尺寸的显示窗口的横 向像素点， 并将原始视频图像分辨率的垂直纵向点数作为预定尺寸的显示窗口的垂直 纵向像素点， 之后根据预定尺寸的显示窗口的横向像素点和垂直纵向像素点截取处理 后的视频图像， 以获取对应预定尺寸的显示窗口的视频图像。 其中， 第一公式为
Ho =—xHit -Hos , 为固定像素时钟频率， 为原始视频图像的像素时钟频率， Pi
HzY为原始视频图像的行周期时钟总数， Hos为输出视频的两行之间有效像素的间隔。 图 3是根据本发明实施例的显示窗口输出视频图像的第一横向画面示意图； 图 4 是根据本发明实施例的显示窗口输出视频图像的第二横向画面示意图； 图 5是根据本 发明实施例的显示窗口输出视频图像的第三横向画面示意图； 图 6是根据本发明实施 例的显示窗口输出视频图像的纵向画面示意图； 图 7是根据本发明实施例的显示窗口 输出视频图像的拼接画面示意图。 其中， 上述图 3至图 7中的显示窗口均可以是预定 尺寸的显示窗口， 输入视频均可以是对经过第一处理模块 30处理后的视频图像。 例如， 以输入的视频图像 （即原始视频图像） 的分辨率 M*N为例， 设定开启的 图像显示窗口的视频数据输出始终固定为 7½， 则开启显示窗口的横向有效像素点 Ho 最大能达到的为：
Po
Ho =—— xHit - Hos，
Pi 上述公式中， Ho为预定尺寸的显示窗口输出的最大像素点， 为固定像素时钟 频率， 为输入视频 （即上述实施例中的原始视频图像） 的像素时钟频率， Hit为输 入视频分辨率的行周期时钟总数， Hos为输出视频的两行之间有效像素的间隔， 即相 邻两行中前一行最后一个有效像素与后一行第一个有效像素之间的时间间隔 （以像素 时钟周期个数计算）。 其中， 固定频率 越大， 则开启窗口的尺寸越大， 但系统的稳 定性会受影响， 在本实施例中的固定像素时钟频率 可以是 75Mhz。 在上述实施例中， 如图 3所示， 若 Po > P ,则在预定尺寸的开启窗口能够完全输 出视频输入分辨率的横向像素点， 即开启预定尺寸的显示窗口的横向宽度大于原始视 频图像的横向宽度。 具体地， 用户设定显示窗口的左上角初始位置的横坐标 X为 0， 则开启窗口显示的第一个像素为输入视频图像 （即原始视频图像） 的第一个像素点， 如开启窗口的横向像素点数大于输入图像的横向像素点数， 则能够完整显示输入图像 的横向画面。 如图 4和图 5所示， 如果输入图像横向点数大于开启窗口点数， 则开启窗口的图 像显示输入图像的其中一个区域， 该区域由设定的 X坐标进行移动， 如果用户输入的 预定坐标为（ηΐ,θ) ,则将处理后的视频图像向右平移 nl个坐标， 如果用户输入的预定 坐标为 （n2,0) ，则将处理后的视频图像向右平移 n2个坐标。 在本申请的上述实施例中， 预定尺寸的显示窗口的垂直纵向点数的最大可显示数 目与实际输入图像的有效像素垂直点数相同， 如对于 1280* 1024@60hz的图像分辨率 其显示窗口的垂直点数最大为 1024。 如图 6所示， 对于用户设定的 Y坐标为 0时， 其 显示窗口的垂直点数与输入图像的垂直点数刚好相同。然而， 对于 LED全彩屏的实际 应用点数可能不确定， 因此， 用户也可以按照图 6所示的实施例调整 Y坐标进行图像 的显示的选取， 即， 根据用户输入的预定坐标 （n， m) 设定显示窗口的输出视频图像 的第一行第一列的第一个像素点的坐标。 由上描述可知， 在本申请的上述实施例中， 用户可以任意调整 LED全彩屏的显示 区域， 在处理后的视频图像上截取图像以得到最佳的显示影像， 另外， 如图 7所示， 用户还可以对于高分辨率的图像可以通过增加显示窗口的输出进行拼接， 如果处理后 的视频图像的横向像素点预定尺寸的显示窗口的横向最大像素点的两倍， 则可以用两 个显示屏拼接显示， 则用户对于两个显示屏的预设坐标分别为 （0， 0)和 （n， 0)， 则 两个显示屏的第一行第一个像素点的坐标点 （xl， yl ) 和 （x2， y2) 分别为 （0， 0) 和 （n， 0)， 其中， n=xl+l， 图 7中的 m可以为 0。 而对于设定的 Y坐标则需要对完成上述步骤新产生的场、行、消隐信号进行调整， 如设定坐标 Y为 15， 则需要对以新的消隐同步信号为时钟进行计数， 以新场同步跳变 进行复位， 并产生相应的消隐掩模信号， 例如， 对于计数值为 0-14， 掩模信号无效即 为 0， 其余掩模信号有效， 掩模后则把 0-14行的数据屏蔽， 同时向后移位场同步信号 15个消隐周期的时间值， 以保持与第一个消隐行数据的相位。 另外， 对于新的视频控制信号产生及操作， 以及存储器读取的时钟均在设定的固 定像素时钟频率下进行。 通过本申请的上述实施例， 既可以实现图像的任意区域显示及拼接， 而且能够灵 活的适应 LED实际应用的需求， 以固定较低的传输码率实现与 LED屏体的信号传输， 保证系统的可靠性。 在本申请的上述实施例中， 将原始视频图像的信号时钟频率进行调整处理， 以获 取处理后的视频图像的步骤可以包括：提取原始视频图像的控制信号中的原始行信号、 原始场信号、 原始消隐信号以及原始消隐掩模信号； 以原始行信号为时钟， 在原始场 信号的跳变点对原始场信号进行复位计数， 以获取场同步信号； 以固定像素时钟频率 为时钟， 在原行信号的跳变点对原始行信号进行复位计数， 以获取行同步信号； 以行 同步信号为时钟， 以大于行同步信号的同步头的时刻为跳变点对原始消隐信号进行复 位计数， 以获取消隐同步信号； 以消隐同步信号为时钟在消隐同步信号的跳变点对原 始消隐掩模信号进行复位计数， 以获取消隐掩模信号； 根据场同步信号、行同步信号、 消隐同步信号以及消隐掩模信号生成处理后的视频控制信号， 并获取处理后的视频图 像。 具体地， 提取原始视频图像的控制信号中的原始行信号、 原始场信号、 原始消隐 信号以及原始消隐掩模信号， 然后对上述原始视频信号中的信号进行时钟频率计算， 以生成新的控制信号， 并根据生成的新的控制信号获取处理后的视频图像。 其中， 对 上述原始视频信号中的信号进行时钟频率计算可以通过如下步骤实现： 以原始行信号 为时钟， 在原始场信号的跳变点对原始场信号进行复位计数， 以获取场同步信号； 以 固定像素时钟频率为时钟， 在原行信号的跳变点对原始行信号进行复位计数， 以获取 行同步信号； 以行同步信号为时钟， 以大于行同步信号的同步头的时刻为跳变点对原 始消隐信号进行复位计数， 以获取消隐同步信号； 以消隐同步信号为时钟在消隐同步 信号的跳变点对原始消隐掩模信号进行复位计数， 以获取消隐掩模信号。 例如， 视频输出的场信号以原有的场信号 （即原始视频图像的控制信号中的场信 号）跳变为界， 以行信号为时钟对原有的场信号进行复位计数，计数设定 0-nl(0至 nl) 为场信号同步头， 场信号电平为低， 其余计数值为高， 生成新的场同步信号 （即上述 实施例中的场同步信号）。对于新的行同步信号， 以原有的行信号（即原始视频图像的 控制信号中的行信号）跳变为界， 以输出时钟（即固定时钟频率 p0 )为时钟进行复位 计数， 设定 0-ml为行信号同步 （即行信号电平为低）， 其余计数值为行信号高， 生成 新的行同步信号 （即上述实施例中的行同步信号）。 而对于新的消隐同步信号， 如图 8 所示， 新的消隐同步信号的生成以新的行同步信号为时钟， 且新的消隐同步信号的同 步头要大于新的行同步信号同步头， 另外， 新的消隐同步信号与存储器的读取紧密相 连， 在消隐信号一旦为高时， 存储器将读取输出预定尺寸的显示窗口的相应行的第一 个数据， 如设定 0-m2 (m2>ml ) 为消隐信号为低， 从 m2+l读取存储器像素数据， 在 (m2+l ) -m3期间， 消隐信号为高， 即像素数据输出时间， 此外， 消隐信号变为低。 根据本申请的上述实施例， 在接收原始视频图像之后， 方法还可以包括： 接收用 户输入的命令信号， 并将命令信号进行解析处理， 以获取预定横向坐标和预定纵向坐 标。 具体地， 如图 10所示， 该步骤可以通过图 10中的步骤 S206实现： 接收并解析用 户命令信号， 一般以 SPI的协议方式传输命令字， 包括命令关键字， 命令地址， 命令 数据， 通过 SPI协议的解析， 并把命令解析为并行的地址， 数据， 控制信号给相应的 处理模块。 在本申请的上述实施例中， 在将原始视频图像的信号时钟频率进行调整处理， 以 获取处理后的视频图像之前， 方法还可以包括： 检测原始视频图像的数据信号是否为 DDR信号； 在原始视频图像的数据信号为 DDR信号的情况下， 对原始视频图像的数 据信号进行比特位宽调整， 以获取时钟单沿传输模式的原始视频图像信号。 具体地， 该步骤均在如图 10所示的数据缓存及处理步骤中完成，接收输入的视频 图像 （即原始视频图像） 之后， 可以将原始视频图像中的视频数据信号进行提取， 并 对该视频数据信号进行数据同步， 也即进行比特位宽调整， 如果视频数据信号为 DDR 信号， 则将 DDR双沿输入模式调整为时钟单沿输出。 根据本申请的上述实施例， 在将原始视频图像的信号时钟频率进行调整处理， 以 获取处理后的视频图像之后， 方法还可以包括： 以原始视频图像的时钟频率为存储时 钟， 以处理后的视频图像的消隐信号为存储使能对处理后的视频图像进行乒乓存取操 作。 具体地， 在接收原始视频图像之后， 对处理后的视频图像进行乒乓存取操作。 具 体地， 可以使用两个大小为 2048bit (或者 4096bit) 存储器通过下述方法实现： 在一 行周期下其中一个存储器 1进行存储， 另外一个存储器 2进行读取视频图像， 而在下 一行周期下进行存储器 2进行存储， 另外一个存储器 2进行读取， 依次交替存取操作， 在存储数据时， 以原输入时钟为存储时钟， 消隐信号为存储使能， 地址从 0依次时钟 节拍递增， 把行数据从最左边至最右边， 从地址 0依次递增存取， 每个地址存取一个 像素点数据。 另外， 该方法还可以通过选择器可以对乒乓操作的读取存储器进行切换， 即总是 切换到读取的那个存储器的数据输出中去。 需要说明的是， 在附图的流程图示出的步骤可以在诸如一组计算机可执行指令的 计算机系统中执行， 并且， 虽然在流程图中示出了逻辑顺序， 但是在某些情况下， 可 以以不同于此处的顺序执行所示出或描述的步骤。 从以上的描述中， 可以看出， 本发明实现了如下技术效果： 通过本发明的视频图 像的处理方法及装置， 通过调整输入的图像的时钟频率， 获取新的行、 场、 消隐同步 信号， 并获取新的视频图像， 然后根据用户显示图像的需求进行相应的截取输出， 解 决了现有技术中为了在拼接屏上显示不同分辨率的视频图像， 而对视频图像进行缩放 处理后， 导致显示图像失真的问题， 实现了可靠、 稳定的将任意分辨率的视频图像在 最佳显示区域范围内显示的效果。 显然， 本领域的技术人员应该明白， 上述的本发明的各模块或各步骤可以用通用 的计算装置来实现， 它们可以集中在单个的计算装置上， 或者分布在多个计算装置所 组成的网络上， 可选地， 它们可以用计算装置可执行的程序代码来实现， 从而， 可以 将它们存储在存储装置中由计算装置来执行， 或者将它们分别制作成各个集成电路模 块， 或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。 这样， 本发明 不限制于任何特定的硬件和软件结合。 以上所述仅为本发明的优选实施例而已， 并不用于限制本发明， 对于本领域的技 术人员来说， 本发明可以有各种更改和变化。 凡在本发明的精神和原则之内， 所作的 任何修改、 等同替换、 改进等， 均应包含在本发明的保护范围之内。

Claims

权 利 要 求 书
1. 一种视频图像处理方法， 其特征在于， 包括：
接收原始视频图像；
将所述原始视频图像的信号时钟频率进行调整处理， 以获取处理后的视频 图像；
在接收到用户输入的命令信号之后， 根据预定尺寸对所述处理后的视频图 像进行截取处理， 以获取对应预定尺寸的显示窗口的视频图像；
将所述对应预定尺寸的显示窗口的视频图像进行编码处理， 并获取编码后 的视频图像。
2. 根据权利要求 1所述的方法， 其特征在于， 所述命令信号包括预定横向坐标和 预定纵向坐标， 其中， 在接收到用户输入的命令信号之后， 根据预定尺寸对所 述处理后的视频图像进行截取处理， 以获取对应所述预定尺寸的显示窗口的视 频图像的步骤包括：
根据第一公式进行像素点计算， 以获取所述预定尺寸的显示窗口的横向最 大像素点 Ho， 其中， 所述第一公式为：
Ho =— Hit -Hos，
Pi
其中， 所述 为固定像素时钟频率， 所述 为所述原始视频图像的像素 时钟频率， 所述 HzY为所述原始视频图像的行周期时钟总数， 所述 Hos为输出 视频的两行之间有效像素的间隔；
根据所述预定横向坐标对所述预定尺寸的显示窗口的横向最大像素点进行 截取处理， 以获取所述预定尺寸的显示窗口的横向像素点；
将所述原始视频图像分辨率的垂直纵向点数作为所述预定尺寸的显示窗口 的垂直纵向像素点；
根据所述预定尺寸的显示窗口的横向像素点和所述垂直纵向像素点截取所 述处理后的视频图像， 以获取所述对应所述预定尺寸的显示窗口的视频图像。
3. 根据权利要求 1所述的方法， 其特征在于， 将所述原始视频图像的信号时钟频 率进行调整处理， 以获取处理后的视频图像的步骤包括： 提取所述原始视频图像的控制信号中的原始行信号、 原始场信号、 原始消 隐信号以及原始消隐掩模信号；
以所述原始行信号为时钟， 在所述原始场信号的跳变点对所述原始场信号 进行复位计数， 以获取场同步信号；
以固定像素时钟频率为时钟， 在所述原行信号的跳变点对所述原始行信号 进行复位计数， 以获取行同步信号；
以所述行同步信号为时钟， 以大于所述行同步信号的同步头的时刻为跳变 点对所述原始消隐信号进行复位计数， 以获取消隐同步信号；
以所述消隐同步信号为时钟在所述消隐同步信号的跳变点对所述原始消隐 掩模信号进行复位计数， 以获取消隐掩模信号；
根据所述场同步信号、 所述行同步信号、 所述消隐同步信号以及所述消隐 掩模信号生成处理后的视频控制信号， 并获取所述处理后的视频图像。
4. 根据权利要求 2所述的方法， 其特征在于， 在接收原始视频图像之后， 所述方 法还包括：
接收所述用户输入的所述命令信号， 并将所述命令信号进行解析处理， 以 获取所述预定横向坐标和所述预定纵向坐标。
5. 根据权利要求 1所述的方法， 其特征在于， 在将所述原始视频图像的信号时钟 频率进行调整处理， 以获取处理后的视频图像之前， 所述方法还包括：
检测所述原始视频图像的数据信号是否为 DDR信号；
在所述原始视频图像的数据信号为所述 DDR信号的情况下， 对所述原始 视频图像的数据信号进行比特位宽调整， 以获取时钟单沿传输模式的原始视频 图像。
6. 根据权利要求 1所述的方法， 其特征在于， 在将所述原始视频图像的信号时钟 频率进行调整处理， 以获取处理后的视频图像之后， 所述方法还包括：
以所述原始视频图像的时钟频率为存储时钟， 以所述处理后的视频图像的 消隐信号为存储使能对所述处理后的视频图像进行乒乓存取操作。
7. 一种视频图像处理装置， 其特征在于， 包括：
接收模块， 用于接收原始视频图像； 第一处理模块， 用于将所述原始视频图像的信号时钟频率进行调整处理， 以获取处理后的视频图像；
第二处理模块， 用于在接收到用户输入的命令信号之后， 根据预定尺寸对 所述处理后的视频图像进行截取处理， 以获取对应所述预定尺寸的显示窗口的 视频图像；
编码模块， 用于将所述对应所述预定尺寸的显示窗口的视频图像进行编码 处理， 以获取编码后的视频图像。
8. 根据权利要求 7所述的装置， 其特征在于， 所述命令信号包括预定横向坐标和 预定纵向坐标， 其中， 所述第二处理模块包括：
第一计算模块， 用于根据第一公式进行像素点计算， 以获取所述预定尺寸 的显示窗口的横向最大像素点 H0， 其中， 所述第一公式为：
Ho =— Hit -Hos，
Pi
其中， 所述 为固定像素时钟频率， 所述 为所述原始视频图像的像素 时钟频率， 所述 HzY为所述原始视频图像的行周期时钟总数， 所述 Hos为输出 视频的两行之间有效像素的间隔；
第一子处理模块， 用于根据所述预定横向坐标对所述预定尺寸的显示窗口 的横向最大像素点进行截取处理， 以获取所述预定尺寸的显示窗口的横向像素 点， 并将所述原始视频图像分辨率的垂直纵向点数作为所述预定尺寸的显示窗 口的垂直纵向像素点；
第二子处理模块， 用于根据所述预定尺寸的显示窗口的横向像素点和所述 垂直纵向像素点截取所述处理后的视频图像， 以获取所述对应所述预定尺寸的 显示窗口的视频图像。
9. 根据权利要求 7所述的装置， 其特征在于， 所述第一处理模块包括： 提取模块， 用于提取所述原始视频图像的控制信号中的原始行信号、 原始 场信号、 原始消隐信号以及原始消隐掩模信号；
第一计数模块， 用于以所述原始行信号为时钟， 在所述原始场信号的跳变 点对所述原始场信号进行复位计数， 以获取场同步信号；
第二计数模块， 用于以固定像素时钟频率为时钟， 在所述原行信号的跳变 点对所述原始行信号进行复位计数， 以获取行同步信号； 第三计数模块， 用于以所述行同步信号为时钟， 以大于所述行同步信号的 同步头的时刻为跳变点对所述原始消隐信号进行复位计数， 以获取消隐同步信 号；
第四计数模块， 用于以所述消隐同步信号为时钟在所述消隐同步信号的跳 变点对所述原始消隐掩模信号进行复位计数， 以获取消隐掩模信号；
第四子处理模块， 用于根据所述场同步信号、 所述行同步信号、 所述消隐 同步信号以及所述消隐掩模信号生成处理后的视频图像的控制信号， 并获取所 述处理后的视频图像。
10. 根据权利要求 8所述的装置， 其特征在于， 在执行所述接收模块之后， 所述装 置还包括：
第三处理模块， 用于接收所述用户输入的所述命令信号， 并将所述命令信 号进行解析处理， 以获取所述预定横向坐标和所述预定纵向坐标。
11. 根据权利要求 7所述的装置， 其特征在于， 在执行所述第一处理模块之前， 所 述装置还包括：
检测模块， 用于检测所述原始视频图像的数据信号是否为 DDR信号； 第四处理模块， 用于在所述原始视频图像的数据信号为所述 DDR信号的 情况下， 对所述原始视频图像的数据信号进行比特位宽调整， 以获取时钟单沿 传输模式的原始视频图像信号。
12. 根据权利要求 7所述的装置， 其特征在于， 在执行所述第一处理模块之后， 所 述装置还包括：
读取模块， 用于以所述原始视频图像的时钟频率为存储时钟， 以所述处理 后的视频图像的消隐信号为存储使能对所述处理后的视频图像进行乒乓存取操 作。
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CN114245029A (zh) * 2021-12-20 2022-03-25 北京镁伽科技有限公司 基于fpga的数据流处理方法、装置及pg设备
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