WO2014050389A1 - Module à semi-conducteurs de puissance - Google Patents

Module à semi-conducteurs de puissance Download PDF

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Publication number
WO2014050389A1
WO2014050389A1 PCT/JP2013/072596 JP2013072596W WO2014050389A1 WO 2014050389 A1 WO2014050389 A1 WO 2014050389A1 JP 2013072596 W JP2013072596 W JP 2013072596W WO 2014050389 A1 WO2014050389 A1 WO 2014050389A1
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Prior art keywords
terminal
semiconductor element
power semiconductor
semiconductor module
heat
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PCT/JP2013/072596
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English (en)
Japanese (ja)
Inventor
康平 松井
智 谷本
村上　善則
祐輔 図子
佐藤　伸二
秀和 谷澤
Original Assignee
富士電機株式会社
日産自動車株式会社
サンケン電気株式会社
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Priority to JP2014538290A priority Critical patent/JP5925328B2/ja
Publication of WO2014050389A1 publication Critical patent/WO2014050389A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48111—Disposition the wire connector extending above another semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Definitions

  • the present invention relates to a power semiconductor module used for a power converter or the like.
  • wide band gap semiconductor elements such as silicon carbide (SiC) and gallium nitride (GaN) (hereinafter referred to as wide band gap semiconductor elements) are attracting attention as semiconductor elements for power semiconductor modules.
  • the wide band gap semiconductor element can operate in a high temperature environment as compared with a conventional semiconductor element using silicon, and has excellent characteristics such as low loss and high speed operation.
  • the power semiconductor module can be miniaturized and improved in performance.
  • the power semiconductor module generally includes a heat radiating member such as a heat sink (see, for example, Patent Document 1).
  • a heat radiating member such as a heat sink
  • the power semiconductor module of Patent Document 1 includes two heat dissipating members so as to sandwich the upper and lower sides of the semiconductor element, thereby realizing high cooling efficiency.
  • heat generated in the semiconductor element may be conducted to an external configuration connected to the power semiconductor module.
  • the operation of the power semiconductor module becomes unstable even if there is no malfunction in the semiconductor element.
  • Wide band gap semiconductor elements having high resistance to temperature tend to operate at higher temperatures than conventional semiconductor elements. Therefore, in power semiconductor modules using wide band gap semiconductor elements, heat conduction to external components is difficult. The problem is more serious.
  • the present invention has been made in view of such a point, and an object thereof is to provide a power semiconductor module capable of suppressing conduction of heat generated in a semiconductor element to the outside.
  • the power semiconductor module of the present invention includes a ceramic substrate, a semiconductor element disposed on one main surface side of the ceramic substrate, a terminal connected to the semiconductor element, and the other main surface side of the ceramic substrate.
  • a first heat dissipating member and a second heat dissipating member disposed at a distance from the semiconductor element on the one main surface side of the ceramic substrate, and the terminal includes the second heat dissipating member. It is connected to a heat radiating member.
  • the terminal connected to the semiconductor element is connected to the second heat radiating member, the heat transmitted from the semiconductor element to the terminal is mainly conducted to the second heat radiating member, and the power semiconductor module is transmitted from the terminal. Heat conduction to the outside is suppressed. That is, conduction of heat generated in the semiconductor element to the outside can be suppressed.
  • the terminal is a control terminal for controlling the semiconductor element.
  • the control terminal that is at a higher temperature than the terminal through which the input / output current flows can be efficiently cooled by the second heat radiating member. Further, heat conduction to an external control circuit connected to the semiconductor element through the control terminal and the wiring can be suppressed.
  • the semiconductor element and the terminal are connected via a metal plate, and the terminal is formed of a material having a lower thermal conductivity than the metal plate. According to this configuration, the conduction of heat generated in the semiconductor element to the outside can be further suppressed by keeping the thermal conductivity of the terminal low.
  • the semiconductor element may be a semiconductor element using a wide band gap semiconductor material. According to this configuration, heat conduction to the outside can be appropriately suppressed in a power semiconductor module using a wide band gap semiconductor element that tends to be high temperature.
  • the second heat radiating member has insulating properties, and the semiconductor element is connected to a plurality of external wirings via a plurality of terminals connected to the second heat radiating member. Also good. According to this configuration, since the plurality of terminals are connected to the insulating second heat radiating member, the plurality of terminals can be cooled while maintaining insulation.
  • the present invention it is possible to provide a power semiconductor module that can suppress conduction of heat generated in the semiconductor element to the outside.
  • FIG. 1 is a schematic diagram illustrating a configuration example of a power semiconductor module according to the present embodiment.
  • 1A is a schematic plan view seen from the element arrangement surface side
  • FIG. 1B is a schematic cross-sectional view showing a cross section perpendicular to the element arrangement surface.
  • FIG. 1A for convenience of explanation, a part of the configuration is indicated by a broken line.
  • the power semiconductor module 1 includes a ceramic substrate 11 that supports each component.
  • the ceramic substrate 11 is made of an insulating material such as silicon nitride, aluminum nitride, or aluminum oxide, and has a substantially rectangular planar shape.
  • a plurality of metal plates 12 a, 12 b, 12 c, 12 d, 12 e, 12 f, and 12 g are provided on one main surface (upper main surface) 11 a serving as an element arrangement surface of the ceramic substrate 11.
  • a metal plate 12h is provided on the other main surface (lower main surface) 11b.
  • the metal plates 12a to 12h are all copper plates, and are soldered to the ceramic substrate 11.
  • the metal plates 12a to 12h may be made of a metal other than copper.
  • a transistor 13a and a diode 14a which are semiconductor elements, are disposed on the metal plate 12a. Electrodes (not shown) are formed on the lower surfaces of the transistor 13a and the diode 14a, respectively, and the electrodes and the metal plate 12a are electrically connected by solder. Further, electrodes are formed on the upper surfaces of the transistor 13a and the diode 14a, respectively, and conductive wires 21a, 21b, 21c, and 21d are connected to the electrodes so as to form a connection relationship described later. Yes.
  • a transistor 13b and a diode 14b which are semiconductor elements, are arranged on the metal plate 12b. Electrodes (not shown) are formed on the lower surfaces of the transistor 13b and the diode 14b, respectively, and this electrode and the metal plate 12b are electrically connected by solder. Further, electrodes are formed on the upper surfaces of the transistor 13b and the diode 14b, respectively, and conductive wires 21e, 21f, 21g, and 21h are connected to the electrodes so as to form a connection relationship described later. Yes.
  • the transistors 13a and 13b and the diodes 14a and 14b are formed using a semiconductor (wide band gap semiconductor) material having a wider band gap than silicon.
  • a semiconductor element using such a semiconductor material can reduce loss as compared with a conventional semiconductor element using silicon. Further, such a semiconductor element can operate at a relatively high temperature of 200 ° C. or higher.
  • the wide band gap semiconductor material for example, silicon carbide (SiC), gallium nitride (GaN), or the like can be used.
  • the transistors 13a and 13b and the diodes 14a and 14b are used for the transistors 13a and 13b and the diodes 14a and 14b, so that they can operate at high temperatures. Therefore, high melting point Au—Ge solder (melting point is about 350 ° C.), Au—Sn solder (melting point is about 285 ° C.), or the like is used around these semiconductor elements. If such a solder is used, an appropriate electrical connection can be realized even in a high temperature environment of 200 ° C. or higher. In order to improve the wetness of the solder, the electrodes of the semiconductor elements, the surfaces of the metal plates 12a to 12h, etc. may be plated with gold.
  • Transistors 13a and 13b are FETs (Field Effect Transistors). By using FETs as the transistors 13a and 13b, a high switching speed can be realized and the conversion efficiency of the power converter using the power semiconductor module 1 can be increased.
  • the transistors 13a and 13b are not limited to FETs, but may be IGBTs (InsulatedulGate Bipolar Transistors) or the like.
  • the metal plates 12a, 12b, and 12c are connected to input / output terminals 22a, 22b, and 22c through which input / output currents flow, respectively.
  • a control terminal (gate terminal) 22d for controlling the gate potential of the transistor 13a is connected to the metal plate 12d, and a control terminal (source terminal) for controlling the source potential of the transistor 13a is connected to the metal plate 12e.
  • a control terminal (gate terminal) 22f for controlling the gate potential of the transistor 13b is connected to the metal plate 12f, and a control terminal (for controlling the source potential of the transistor 13a) is connected to the metal plate 12g.
  • Source terminal) 22g is connected.
  • terminals 22a to 22c and control terminals 22e to 22g are made of a material having a lower thermal conductivity than the metal plates 12a to 12c.
  • each terminal has aluminum (about 236 W / m ⁇ K), iron (about 84 W / m ⁇ K), platinum (about 70 W / m ⁇ K) whose thermal conductivity is lower than that of copper (about 398 W / m ⁇ K).
  • stainless steel (10 to 25 W / m ⁇ K).
  • the cross-sectional area perpendicular to the current direction is larger at the input / output terminals 22a-22c than at the control terminals 22d-22g, and the electrical resistance of the input / output terminals 22a-22c is smaller than at the control terminals 22e-22g.
  • the control terminals 22d to 22g are formed so as to have a minimum cross-sectional area (for example, a thickness of about 0.1 mm to 0.5 mm, or a diameter of about 1 mm) that can maintain structural strength. It is difficult to conduct.
  • the copper base 41a of the heat radiating member (first heat radiating member) 41 is fixed to the lower surface of the metal plate 12h with solder.
  • solder having a lower melting point than that used for connecting a semiconductor element or the like is used.
  • Au—Ge solder is used around the semiconductor element described above
  • Au—Sn solder can be used to fix the copper base 41a.
  • a heat sink 41b having heat radiating fins 41c is fixed to the copper base 41a.
  • the heat sink 41b is fixed to the copper base 41a via, for example, a bolt (not shown). In this way, the temperature of the semiconductor element is kept in an operable range by the heat radiation member 41 fixed to the lower surface of the metal plate 12h.
  • a resin case 51 covering the periphery of the ceramic substrate 11 is attached above the copper base 41 a, and silicone gel is sealed inside the case 51.
  • silicone gel for example, a gel in which the terminal siloxane does not change even at a temperature of 200 ° C. or higher is selected.
  • the case 51 is made of a highly heat-resistant resin such as PPS resin or polyimide resin.
  • a heat radiating member (second heat radiating member) 61 is attached to the upper surface of the case 51 at a position spaced from the semiconductor element.
  • the heat radiating member 61 includes a heat radiating substrate 61a having heat conductivity and insulating properties, and heat radiating fins 61b.
  • the heat dissipation substrate 61a is a ceramic substrate made of an insulating material having a high thermal conductivity such as silicon nitride, aluminum nitride, or aluminum oxide, and has a substantially rectangular planar shape.
  • the heat radiating fins 61b are made of metal such as copper or aluminum, and are fixed to the heat radiating substrate 61a by soldering or soldering.
  • the structure of the heat radiating member 61 is not limited to what is shown in FIG.
  • FIG. 2 is a schematic cross-sectional view showing a configuration example of the heat dissipation member 61.
  • the heat dissipating member 61 may have a plurality of plate-like objects serving as heat dissipating fins 61b attached to the heat dissipating substrate 61a, or a bent metal plate as shown in FIG. 2B.
  • the heat radiating fins 61b may be attached to the heat radiating substrate 61a.
  • a heat sink to which the heat radiating fins 61b are fixed may be attached to the heat radiating substrate 61a.
  • a plurality of terminals are connected to the heat dissipation member 61.
  • conductor patterns 71a to 71g corresponding to the input / output terminals 22a to 22c and the control terminals 22d to 22g are formed on the surface of the heat dissipation board 61a, and the input / output terminals 22a to 22c and the control terminals 22d to 22g are formed.
  • 22g is soldered to the conductor patterns 71a to 71g.
  • Wide conductor patterns 71a, 71b, 71c are connected to the input / output terminals 22a, 22b, 22c through which the input / output current flows.
  • Conductor patterns 71d, 71e, 71f, and 71g are connected to the control terminals 22d, 22e, 22f, and 22g, respectively.
  • the heat dissipation board 61a since the heat dissipation board 61a has insulation, insulation between terminals is maintained.
  • the plurality of terminals are respectively connected to external wiring (not shown) via conductor patterns 71a to 71g. Accordingly, the plurality of terminals are connected to the external configuration of the power semiconductor module 1 through the conductor patterns 71a to 71g and the external wiring.
  • the input / output terminals 22a to 22c through which the input / output current flows are connected to a power source or a current supply destination through the conductor patterns 71a to 71c and the external wiring.
  • the control terminals 22d to 22g are connected to the control circuit through conductor patterns 71d to 71g and external wiring, respectively.
  • a plurality of terminals connected to the semiconductor element are connected to a heat dissipation member 61 (for example, 10 W / m ⁇ K or more) having high thermal conductivity.
  • the heat transmitted to each terminal is diffused by the heat radiating member 61. That is, each terminal is forcibly cooled by the heat radiating member 61.
  • each terminal of the power semiconductor module 1 is made of a material having a lower thermal conductivity than the metal plates 12a to 12c, the semiconductor is compared with the case where each terminal is made of the same material as the metal plates 12a to 12c. Heat conduction from the element to the terminal is suppressed.
  • the heat difference generated between the semiconductor elements is suppressed by generating a temperature difference between the semiconductor elements and the terminals.
  • FIG. 3 is a circuit diagram of the power semiconductor module 1 according to the present embodiment.
  • a transistor 13a that is an n-channel FET and a transistor 13b that is an n-channel FET are provided.
  • a metal plate 12a is connected to the drain electrode exposed on the lower surface of the transistor 13a so that a current flows between the drain electrode and the power source through the input / output terminal 22a.
  • the source electrode exposed on the upper surface of the transistor 13b is connected to the metal plate 12c by the conductive wire 21e. As a result, a current flows between the source electrode of the transistor 13b and the power supply through the input / output terminal 22c.
  • the source electrode exposed on the upper surface of the transistor 13a is connected to the metal plate 12b by the conductive wire 21a.
  • the drain electrode exposed on the lower surface of the transistor 13b is connected to the metal plate 12b. Thereby, the source electrode of the transistor 13a and the drain electrode of the transistor 13b are connected to a common input / output terminal 22b connected to the metal plate 12b.
  • the gate electrode exposed on the upper surface of the transistor 13a is connected to the metal plate 12d by the conductive wire 21b, and a control potential for controlling the switching of the transistor 13a is applied through the control terminal 22d connected to the metal plate 12d.
  • the gate electrode exposed on the upper surface of the transistor 13b is connected to the metal plate 12f by the conductive wire 21f, and a control potential for controlling the switching of the transistor 13b is applied through the control terminal 22f connected to the metal plate 12f.
  • the source electrode exposed on the upper surface of the transistor 13a is connected to the metal plate 12e by the conductive wire 21c, and the source potential of the transistor 13a is controlled by the control terminal 22e connected to the metal plate 12e.
  • the source electrode exposed on the upper surface of the transistor 13b is connected to the metal plate 12g by the conductive wire 21g, and the source potential of the transistor 13b is controlled by the control terminal 22g connected to the metal plate 12g. Since the transistors 13a and 13b are both n-channel FETs, they are turned on when the potential difference between the gate electrode and the source electrode becomes larger than the threshold voltage, and the potential difference between the gate electrode and the source electrode is smaller than the threshold voltage. Turn off.
  • a diode 14a is connected in parallel to the transistor 13a. Specifically, the cathode exposed on the lower surface of the diode 14a is connected to the input / output terminal 22a via the metal plate 12a, and the anode exposed on the upper surface of the diode 14a connects the conductive wire 21d and the metal plate 12b. Via the input / output terminal 22b. As a result, a reverse bias is applied to the diode 14a from the power supply.
  • a diode 14b is connected in parallel to the transistor 13b. Specifically, the cathode exposed on the lower surface of the diode 14b is connected to the input / output terminal 22b via the metal plate 12b. The anode exposed on the upper surface of the diode 14b is connected to the input / output terminal 22c through the conductive wire 21h and the metal plate 12c. Thereby, a reverse bias is applied to the diode 14b from the power source.
  • this power semiconductor module 1 for example, the potential difference between the gate electrode and the source electrode of the transistor 13a is increased and the transistor 13a is turned on, or the potential difference between the gate electrode and the source electrode of the transistor 13b is increased and the transistor 13b is turned on. Then, there is no substantial potential difference between the source electrode and the drain electrode of the transistor 13a or between the source electrode and the drain electrode of the transistor 13b. For this reason, the current flowing through the input / output terminal 22b can be controlled according to whether the transistors 13a and 13b are on or off. For example, by using a plurality of such power semiconductor modules 1, an inverter that converts direct current into alternating current (single-phase alternating current when there are two power semiconductor modules 1 and three-phase alternating current when there are three) can be configured. .
  • the control terminals 22d to 22g for controlling the semiconductor elements are connected to the heat radiating member 61 having a high thermal conductivity. Therefore, heat conduction to the control terminal 22d and the control circuit connected via the wiring can be prevented. That is, since the control circuit does not become unstable due to heat from the semiconductor element, the operation of the power semiconductor module 1 can be stabilized. In particular, in the power semiconductor module 1 according to the present embodiment, since a semiconductor element using a wide gap semiconductor material is used, even when operating at a high temperature so that the performance of the semiconductor element is maximized, the power semiconductor module 1 is exposed to the outside. Can be suppressed appropriately.
  • FIG. 4 is a diagram showing the verification results of the terminal temperature.
  • FIG. 4A shows a verification result of a power semiconductor module using a heat dissipation substrate having a high thermal conductivity
  • FIG. 4B shows a verification result of a power semiconductor module using an insulating substrate having a low thermal conductivity. That is, the verification result of FIG. 4A corresponds to the power semiconductor module 1 of the present embodiment.
  • the conditions other than the use / non-use of the heat dissipation substrate are the same.
  • FIG. 4 shows a temperature distribution when the power semiconductor module is viewed from the substrate B side corresponding to the heat dissipation substrate or the insulating substrate.
  • the substrate B is provided with a plurality of heat radiation fins F.
  • the region of 80 ° C. to 100 ° C. is a
  • the region of 100 ° C. to 120 ° C. is b
  • the region of 120 ° C. to 140 ° C. is c
  • the region of 140 ° C. to 160 ° C. is d
  • the above regions are indicated by e, respectively.
  • the terminals T1, T2, T3, and T4 corresponding to the control terminals were all 160 ° C. or less. More specifically, the temperature of the terminals T1, T2, T3, T4 was 150 ° C. or less. The temperatures of the terminals T5, T6, T7 corresponding to the input / output terminals were 120 ° C. to 160 ° C. As described above, the reason why the terminals T1, T2, T3, and T4 corresponding to the control terminals become low temperature is that the heat of the terminals T1, T2, T3, and T4 can be sufficiently diffused by the substrate B having high thermal conductivity. .
  • the terminals T1, T2, T3, and T4 corresponding to the control terminals were all 160 ° C. or higher. More specifically, the temperature of the terminals T1, T2, T3, and T4 was 200 ° C. or higher.
  • the terminals T5, T6, and T7 corresponding to the input / output terminals were 120 ° C. to 160 ° C. This is because the input / output terminals are connected to wide conductive patterns (corresponding to the conductive patterns 71a to 71c in FIG. 1A), which is advantageous for heat dissipation.
  • the control terminal becomes hot due to heat from the semiconductor element. This tendency is even more pronounced in semiconductor devices that use wide gap semiconductor materials that enable high temperature operation.
  • the terminals are cooled by the heat dissipation board. For this reason, heat conduction from the terminal to the outside can be suppressed.
  • the terminals (input / output terminals 22a to 22c, control terminals 22d to 22g) connected to the semiconductor elements (transistors 13a and 13b, diodes 14a and 14b) are heat radiating members (second terminals). Since the heat transmitted from the semiconductor element to the terminal is mainly conducted to the heat radiating member 61, heat conduction from the terminal to the outside of the power semiconductor module 1 is suppressed. Therefore, conduction of heat generated in the semiconductor element to the outside can be suppressed.
  • the semiconductor element and the terminal are connected via the metal plates 12a to 12g, and the terminal is formed of a material having a lower thermal conductivity than the metal plates 12a to 12g, so that the thermal conductivity of the terminal is increased. It is possible to further suppress the conduction of heat generated in the semiconductor element to the outside by keeping it low.
  • the heat radiating member 61 provides control terminals that have a higher temperature than the input / output terminals 22a to 22c through which input / output current flows. It can be cooled efficiently. Further, heat conduction to an external control circuit or the like connected to the semiconductor element via the control terminals 22d to 22g and wiring can be suppressed. In addition, a wide band gap semiconductor material is used for the semiconductor element, and the temperature tends to be high. However, the heat conduction to the outside can be appropriately suppressed by the configuration of the present invention.
  • the heat dissipation member 61 has an insulating property and the semiconductor element is connected to a plurality of external wirings via a plurality of terminals connected to the heat dissipation member 61, the plurality of terminals can be cooled while maintaining insulation. .
  • the present invention is not limited to the above embodiment, and can be implemented with various modifications.
  • a semiconductor material such as silicon may be used for the transistor or the diode.
  • the input / output terminal or the control terminal may be formed of the same material as the metal plate.
  • size, a shape, etc. can be changed and implemented in the range with which the effect of this invention is exhibited.
  • the present invention can be modified and implemented without departing from the object.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

L'invention concerne un module à semi-conducteurs de puissance, capable de supprimer le transfert de la chaleur générée dans un élément à semi-conducteurs, vers l'extérieur. Ce module à semi-conducteurs de puissance est caractérisé en ce qu'il comprend un substrat en céramique (11), des éléments à semi-conducteurs (13a, 13b, 14a, 14b) agencés sur une surface principale (11a) du substrat en céramique, des bornes (22a-22g) connectées aux éléments à semi-conducteurs, un premier élément de dissipation thermique (41) agencé sur l'autre surface principale (11b) du substrat en céramique et un second élément de dissipation thermique (61), agencé sur le côté de surface principale du substrat en céramique, à une certaine distance des éléments à semi-conducteurs. Ce module à semi-conducteurs de puissance est également caractérisé en ce que les bornes sont connectées au second élément de dissipation thermique.
PCT/JP2013/072596 2012-09-27 2013-08-23 Module à semi-conducteurs de puissance WO2014050389A1 (fr)

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JP2014538290A JP5925328B2 (ja) 2012-09-27 2013-08-23 パワー半導体モジュール

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Cited By (1)

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JP2021174795A (ja) * 2020-04-20 2021-11-01 三菱電機株式会社 半導体装置

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Publication number Priority date Publication date Assignee Title
JP7095632B2 (ja) * 2019-03-11 2022-07-05 株式会社デンソー 半導体装置

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JP2004363295A (ja) * 2003-06-04 2004-12-24 Mitsubishi Electric Corp 半導体装置
JP2009105389A (ja) * 2007-10-02 2009-05-14 Rohm Co Ltd パワーモジュール
JP2009231685A (ja) * 2008-03-25 2009-10-08 Mitsubishi Electric Corp パワー半導体装置
JP2011086768A (ja) * 2009-10-15 2011-04-28 Mitsubishi Electric Corp 電力半導体装置とその製造方法

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JP2021174795A (ja) * 2020-04-20 2021-11-01 三菱電機株式会社 半導体装置
JP7270576B2 (ja) 2020-04-20 2023-05-10 三菱電機株式会社 半導体装置

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JP5925328B2 (ja) 2016-05-25

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