WO2014050389A1 - Power semiconductor module - Google Patents

Power semiconductor module Download PDF

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Publication number
WO2014050389A1
WO2014050389A1 PCT/JP2013/072596 JP2013072596W WO2014050389A1 WO 2014050389 A1 WO2014050389 A1 WO 2014050389A1 JP 2013072596 W JP2013072596 W JP 2013072596W WO 2014050389 A1 WO2014050389 A1 WO 2014050389A1
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Prior art keywords
terminal
semiconductor element
power semiconductor
semiconductor module
heat
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PCT/JP2013/072596
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French (fr)
Japanese (ja)
Inventor
康平 松井
智 谷本
村上　善則
祐輔 図子
佐藤　伸二
秀和 谷澤
Original Assignee
富士電機株式会社
日産自動車株式会社
サンケン電気株式会社
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Application filed by 富士電機株式会社, 日産自動車株式会社, サンケン電気株式会社 filed Critical 富士電機株式会社
Priority to JP2014538290A priority Critical patent/JP5925328B2/en
Publication of WO2014050389A1 publication Critical patent/WO2014050389A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48111—Disposition the wire connector extending above another semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Definitions

  • the present invention relates to a power semiconductor module used for a power converter or the like.
  • wide band gap semiconductor elements such as silicon carbide (SiC) and gallium nitride (GaN) (hereinafter referred to as wide band gap semiconductor elements) are attracting attention as semiconductor elements for power semiconductor modules.
  • the wide band gap semiconductor element can operate in a high temperature environment as compared with a conventional semiconductor element using silicon, and has excellent characteristics such as low loss and high speed operation.
  • the power semiconductor module can be miniaturized and improved in performance.
  • the power semiconductor module generally includes a heat radiating member such as a heat sink (see, for example, Patent Document 1).
  • a heat radiating member such as a heat sink
  • the power semiconductor module of Patent Document 1 includes two heat dissipating members so as to sandwich the upper and lower sides of the semiconductor element, thereby realizing high cooling efficiency.
  • heat generated in the semiconductor element may be conducted to an external configuration connected to the power semiconductor module.
  • the operation of the power semiconductor module becomes unstable even if there is no malfunction in the semiconductor element.
  • Wide band gap semiconductor elements having high resistance to temperature tend to operate at higher temperatures than conventional semiconductor elements. Therefore, in power semiconductor modules using wide band gap semiconductor elements, heat conduction to external components is difficult. The problem is more serious.
  • the present invention has been made in view of such a point, and an object thereof is to provide a power semiconductor module capable of suppressing conduction of heat generated in a semiconductor element to the outside.
  • the power semiconductor module of the present invention includes a ceramic substrate, a semiconductor element disposed on one main surface side of the ceramic substrate, a terminal connected to the semiconductor element, and the other main surface side of the ceramic substrate.
  • a first heat dissipating member and a second heat dissipating member disposed at a distance from the semiconductor element on the one main surface side of the ceramic substrate, and the terminal includes the second heat dissipating member. It is connected to a heat radiating member.
  • the terminal connected to the semiconductor element is connected to the second heat radiating member, the heat transmitted from the semiconductor element to the terminal is mainly conducted to the second heat radiating member, and the power semiconductor module is transmitted from the terminal. Heat conduction to the outside is suppressed. That is, conduction of heat generated in the semiconductor element to the outside can be suppressed.
  • the terminal is a control terminal for controlling the semiconductor element.
  • the control terminal that is at a higher temperature than the terminal through which the input / output current flows can be efficiently cooled by the second heat radiating member. Further, heat conduction to an external control circuit connected to the semiconductor element through the control terminal and the wiring can be suppressed.
  • the semiconductor element and the terminal are connected via a metal plate, and the terminal is formed of a material having a lower thermal conductivity than the metal plate. According to this configuration, the conduction of heat generated in the semiconductor element to the outside can be further suppressed by keeping the thermal conductivity of the terminal low.
  • the semiconductor element may be a semiconductor element using a wide band gap semiconductor material. According to this configuration, heat conduction to the outside can be appropriately suppressed in a power semiconductor module using a wide band gap semiconductor element that tends to be high temperature.
  • the second heat radiating member has insulating properties, and the semiconductor element is connected to a plurality of external wirings via a plurality of terminals connected to the second heat radiating member. Also good. According to this configuration, since the plurality of terminals are connected to the insulating second heat radiating member, the plurality of terminals can be cooled while maintaining insulation.
  • the present invention it is possible to provide a power semiconductor module that can suppress conduction of heat generated in the semiconductor element to the outside.
  • FIG. 1 is a schematic diagram illustrating a configuration example of a power semiconductor module according to the present embodiment.
  • 1A is a schematic plan view seen from the element arrangement surface side
  • FIG. 1B is a schematic cross-sectional view showing a cross section perpendicular to the element arrangement surface.
  • FIG. 1A for convenience of explanation, a part of the configuration is indicated by a broken line.
  • the power semiconductor module 1 includes a ceramic substrate 11 that supports each component.
  • the ceramic substrate 11 is made of an insulating material such as silicon nitride, aluminum nitride, or aluminum oxide, and has a substantially rectangular planar shape.
  • a plurality of metal plates 12 a, 12 b, 12 c, 12 d, 12 e, 12 f, and 12 g are provided on one main surface (upper main surface) 11 a serving as an element arrangement surface of the ceramic substrate 11.
  • a metal plate 12h is provided on the other main surface (lower main surface) 11b.
  • the metal plates 12a to 12h are all copper plates, and are soldered to the ceramic substrate 11.
  • the metal plates 12a to 12h may be made of a metal other than copper.
  • a transistor 13a and a diode 14a which are semiconductor elements, are disposed on the metal plate 12a. Electrodes (not shown) are formed on the lower surfaces of the transistor 13a and the diode 14a, respectively, and the electrodes and the metal plate 12a are electrically connected by solder. Further, electrodes are formed on the upper surfaces of the transistor 13a and the diode 14a, respectively, and conductive wires 21a, 21b, 21c, and 21d are connected to the electrodes so as to form a connection relationship described later. Yes.
  • a transistor 13b and a diode 14b which are semiconductor elements, are arranged on the metal plate 12b. Electrodes (not shown) are formed on the lower surfaces of the transistor 13b and the diode 14b, respectively, and this electrode and the metal plate 12b are electrically connected by solder. Further, electrodes are formed on the upper surfaces of the transistor 13b and the diode 14b, respectively, and conductive wires 21e, 21f, 21g, and 21h are connected to the electrodes so as to form a connection relationship described later. Yes.
  • the transistors 13a and 13b and the diodes 14a and 14b are formed using a semiconductor (wide band gap semiconductor) material having a wider band gap than silicon.
  • a semiconductor element using such a semiconductor material can reduce loss as compared with a conventional semiconductor element using silicon. Further, such a semiconductor element can operate at a relatively high temperature of 200 ° C. or higher.
  • the wide band gap semiconductor material for example, silicon carbide (SiC), gallium nitride (GaN), or the like can be used.
  • the transistors 13a and 13b and the diodes 14a and 14b are used for the transistors 13a and 13b and the diodes 14a and 14b, so that they can operate at high temperatures. Therefore, high melting point Au—Ge solder (melting point is about 350 ° C.), Au—Sn solder (melting point is about 285 ° C.), or the like is used around these semiconductor elements. If such a solder is used, an appropriate electrical connection can be realized even in a high temperature environment of 200 ° C. or higher. In order to improve the wetness of the solder, the electrodes of the semiconductor elements, the surfaces of the metal plates 12a to 12h, etc. may be plated with gold.
  • Transistors 13a and 13b are FETs (Field Effect Transistors). By using FETs as the transistors 13a and 13b, a high switching speed can be realized and the conversion efficiency of the power converter using the power semiconductor module 1 can be increased.
  • the transistors 13a and 13b are not limited to FETs, but may be IGBTs (InsulatedulGate Bipolar Transistors) or the like.
  • the metal plates 12a, 12b, and 12c are connected to input / output terminals 22a, 22b, and 22c through which input / output currents flow, respectively.
  • a control terminal (gate terminal) 22d for controlling the gate potential of the transistor 13a is connected to the metal plate 12d, and a control terminal (source terminal) for controlling the source potential of the transistor 13a is connected to the metal plate 12e.
  • a control terminal (gate terminal) 22f for controlling the gate potential of the transistor 13b is connected to the metal plate 12f, and a control terminal (for controlling the source potential of the transistor 13a) is connected to the metal plate 12g.
  • Source terminal) 22g is connected.
  • terminals 22a to 22c and control terminals 22e to 22g are made of a material having a lower thermal conductivity than the metal plates 12a to 12c.
  • each terminal has aluminum (about 236 W / m ⁇ K), iron (about 84 W / m ⁇ K), platinum (about 70 W / m ⁇ K) whose thermal conductivity is lower than that of copper (about 398 W / m ⁇ K).
  • stainless steel (10 to 25 W / m ⁇ K).
  • the cross-sectional area perpendicular to the current direction is larger at the input / output terminals 22a-22c than at the control terminals 22d-22g, and the electrical resistance of the input / output terminals 22a-22c is smaller than at the control terminals 22e-22g.
  • the control terminals 22d to 22g are formed so as to have a minimum cross-sectional area (for example, a thickness of about 0.1 mm to 0.5 mm, or a diameter of about 1 mm) that can maintain structural strength. It is difficult to conduct.
  • the copper base 41a of the heat radiating member (first heat radiating member) 41 is fixed to the lower surface of the metal plate 12h with solder.
  • solder having a lower melting point than that used for connecting a semiconductor element or the like is used.
  • Au—Ge solder is used around the semiconductor element described above
  • Au—Sn solder can be used to fix the copper base 41a.
  • a heat sink 41b having heat radiating fins 41c is fixed to the copper base 41a.
  • the heat sink 41b is fixed to the copper base 41a via, for example, a bolt (not shown). In this way, the temperature of the semiconductor element is kept in an operable range by the heat radiation member 41 fixed to the lower surface of the metal plate 12h.
  • a resin case 51 covering the periphery of the ceramic substrate 11 is attached above the copper base 41 a, and silicone gel is sealed inside the case 51.
  • silicone gel for example, a gel in which the terminal siloxane does not change even at a temperature of 200 ° C. or higher is selected.
  • the case 51 is made of a highly heat-resistant resin such as PPS resin or polyimide resin.
  • a heat radiating member (second heat radiating member) 61 is attached to the upper surface of the case 51 at a position spaced from the semiconductor element.
  • the heat radiating member 61 includes a heat radiating substrate 61a having heat conductivity and insulating properties, and heat radiating fins 61b.
  • the heat dissipation substrate 61a is a ceramic substrate made of an insulating material having a high thermal conductivity such as silicon nitride, aluminum nitride, or aluminum oxide, and has a substantially rectangular planar shape.
  • the heat radiating fins 61b are made of metal such as copper or aluminum, and are fixed to the heat radiating substrate 61a by soldering or soldering.
  • the structure of the heat radiating member 61 is not limited to what is shown in FIG.
  • FIG. 2 is a schematic cross-sectional view showing a configuration example of the heat dissipation member 61.
  • the heat dissipating member 61 may have a plurality of plate-like objects serving as heat dissipating fins 61b attached to the heat dissipating substrate 61a, or a bent metal plate as shown in FIG. 2B.
  • the heat radiating fins 61b may be attached to the heat radiating substrate 61a.
  • a heat sink to which the heat radiating fins 61b are fixed may be attached to the heat radiating substrate 61a.
  • a plurality of terminals are connected to the heat dissipation member 61.
  • conductor patterns 71a to 71g corresponding to the input / output terminals 22a to 22c and the control terminals 22d to 22g are formed on the surface of the heat dissipation board 61a, and the input / output terminals 22a to 22c and the control terminals 22d to 22g are formed.
  • 22g is soldered to the conductor patterns 71a to 71g.
  • Wide conductor patterns 71a, 71b, 71c are connected to the input / output terminals 22a, 22b, 22c through which the input / output current flows.
  • Conductor patterns 71d, 71e, 71f, and 71g are connected to the control terminals 22d, 22e, 22f, and 22g, respectively.
  • the heat dissipation board 61a since the heat dissipation board 61a has insulation, insulation between terminals is maintained.
  • the plurality of terminals are respectively connected to external wiring (not shown) via conductor patterns 71a to 71g. Accordingly, the plurality of terminals are connected to the external configuration of the power semiconductor module 1 through the conductor patterns 71a to 71g and the external wiring.
  • the input / output terminals 22a to 22c through which the input / output current flows are connected to a power source or a current supply destination through the conductor patterns 71a to 71c and the external wiring.
  • the control terminals 22d to 22g are connected to the control circuit through conductor patterns 71d to 71g and external wiring, respectively.
  • a plurality of terminals connected to the semiconductor element are connected to a heat dissipation member 61 (for example, 10 W / m ⁇ K or more) having high thermal conductivity.
  • the heat transmitted to each terminal is diffused by the heat radiating member 61. That is, each terminal is forcibly cooled by the heat radiating member 61.
  • each terminal of the power semiconductor module 1 is made of a material having a lower thermal conductivity than the metal plates 12a to 12c, the semiconductor is compared with the case where each terminal is made of the same material as the metal plates 12a to 12c. Heat conduction from the element to the terminal is suppressed.
  • the heat difference generated between the semiconductor elements is suppressed by generating a temperature difference between the semiconductor elements and the terminals.
  • FIG. 3 is a circuit diagram of the power semiconductor module 1 according to the present embodiment.
  • a transistor 13a that is an n-channel FET and a transistor 13b that is an n-channel FET are provided.
  • a metal plate 12a is connected to the drain electrode exposed on the lower surface of the transistor 13a so that a current flows between the drain electrode and the power source through the input / output terminal 22a.
  • the source electrode exposed on the upper surface of the transistor 13b is connected to the metal plate 12c by the conductive wire 21e. As a result, a current flows between the source electrode of the transistor 13b and the power supply through the input / output terminal 22c.
  • the source electrode exposed on the upper surface of the transistor 13a is connected to the metal plate 12b by the conductive wire 21a.
  • the drain electrode exposed on the lower surface of the transistor 13b is connected to the metal plate 12b. Thereby, the source electrode of the transistor 13a and the drain electrode of the transistor 13b are connected to a common input / output terminal 22b connected to the metal plate 12b.
  • the gate electrode exposed on the upper surface of the transistor 13a is connected to the metal plate 12d by the conductive wire 21b, and a control potential for controlling the switching of the transistor 13a is applied through the control terminal 22d connected to the metal plate 12d.
  • the gate electrode exposed on the upper surface of the transistor 13b is connected to the metal plate 12f by the conductive wire 21f, and a control potential for controlling the switching of the transistor 13b is applied through the control terminal 22f connected to the metal plate 12f.
  • the source electrode exposed on the upper surface of the transistor 13a is connected to the metal plate 12e by the conductive wire 21c, and the source potential of the transistor 13a is controlled by the control terminal 22e connected to the metal plate 12e.
  • the source electrode exposed on the upper surface of the transistor 13b is connected to the metal plate 12g by the conductive wire 21g, and the source potential of the transistor 13b is controlled by the control terminal 22g connected to the metal plate 12g. Since the transistors 13a and 13b are both n-channel FETs, they are turned on when the potential difference between the gate electrode and the source electrode becomes larger than the threshold voltage, and the potential difference between the gate electrode and the source electrode is smaller than the threshold voltage. Turn off.
  • a diode 14a is connected in parallel to the transistor 13a. Specifically, the cathode exposed on the lower surface of the diode 14a is connected to the input / output terminal 22a via the metal plate 12a, and the anode exposed on the upper surface of the diode 14a connects the conductive wire 21d and the metal plate 12b. Via the input / output terminal 22b. As a result, a reverse bias is applied to the diode 14a from the power supply.
  • a diode 14b is connected in parallel to the transistor 13b. Specifically, the cathode exposed on the lower surface of the diode 14b is connected to the input / output terminal 22b via the metal plate 12b. The anode exposed on the upper surface of the diode 14b is connected to the input / output terminal 22c through the conductive wire 21h and the metal plate 12c. Thereby, a reverse bias is applied to the diode 14b from the power source.
  • this power semiconductor module 1 for example, the potential difference between the gate electrode and the source electrode of the transistor 13a is increased and the transistor 13a is turned on, or the potential difference between the gate electrode and the source electrode of the transistor 13b is increased and the transistor 13b is turned on. Then, there is no substantial potential difference between the source electrode and the drain electrode of the transistor 13a or between the source electrode and the drain electrode of the transistor 13b. For this reason, the current flowing through the input / output terminal 22b can be controlled according to whether the transistors 13a and 13b are on or off. For example, by using a plurality of such power semiconductor modules 1, an inverter that converts direct current into alternating current (single-phase alternating current when there are two power semiconductor modules 1 and three-phase alternating current when there are three) can be configured. .
  • the control terminals 22d to 22g for controlling the semiconductor elements are connected to the heat radiating member 61 having a high thermal conductivity. Therefore, heat conduction to the control terminal 22d and the control circuit connected via the wiring can be prevented. That is, since the control circuit does not become unstable due to heat from the semiconductor element, the operation of the power semiconductor module 1 can be stabilized. In particular, in the power semiconductor module 1 according to the present embodiment, since a semiconductor element using a wide gap semiconductor material is used, even when operating at a high temperature so that the performance of the semiconductor element is maximized, the power semiconductor module 1 is exposed to the outside. Can be suppressed appropriately.
  • FIG. 4 is a diagram showing the verification results of the terminal temperature.
  • FIG. 4A shows a verification result of a power semiconductor module using a heat dissipation substrate having a high thermal conductivity
  • FIG. 4B shows a verification result of a power semiconductor module using an insulating substrate having a low thermal conductivity. That is, the verification result of FIG. 4A corresponds to the power semiconductor module 1 of the present embodiment.
  • the conditions other than the use / non-use of the heat dissipation substrate are the same.
  • FIG. 4 shows a temperature distribution when the power semiconductor module is viewed from the substrate B side corresponding to the heat dissipation substrate or the insulating substrate.
  • the substrate B is provided with a plurality of heat radiation fins F.
  • the region of 80 ° C. to 100 ° C. is a
  • the region of 100 ° C. to 120 ° C. is b
  • the region of 120 ° C. to 140 ° C. is c
  • the region of 140 ° C. to 160 ° C. is d
  • the above regions are indicated by e, respectively.
  • the terminals T1, T2, T3, and T4 corresponding to the control terminals were all 160 ° C. or less. More specifically, the temperature of the terminals T1, T2, T3, T4 was 150 ° C. or less. The temperatures of the terminals T5, T6, T7 corresponding to the input / output terminals were 120 ° C. to 160 ° C. As described above, the reason why the terminals T1, T2, T3, and T4 corresponding to the control terminals become low temperature is that the heat of the terminals T1, T2, T3, and T4 can be sufficiently diffused by the substrate B having high thermal conductivity. .
  • the terminals T1, T2, T3, and T4 corresponding to the control terminals were all 160 ° C. or higher. More specifically, the temperature of the terminals T1, T2, T3, and T4 was 200 ° C. or higher.
  • the terminals T5, T6, and T7 corresponding to the input / output terminals were 120 ° C. to 160 ° C. This is because the input / output terminals are connected to wide conductive patterns (corresponding to the conductive patterns 71a to 71c in FIG. 1A), which is advantageous for heat dissipation.
  • the control terminal becomes hot due to heat from the semiconductor element. This tendency is even more pronounced in semiconductor devices that use wide gap semiconductor materials that enable high temperature operation.
  • the terminals are cooled by the heat dissipation board. For this reason, heat conduction from the terminal to the outside can be suppressed.
  • the terminals (input / output terminals 22a to 22c, control terminals 22d to 22g) connected to the semiconductor elements (transistors 13a and 13b, diodes 14a and 14b) are heat radiating members (second terminals). Since the heat transmitted from the semiconductor element to the terminal is mainly conducted to the heat radiating member 61, heat conduction from the terminal to the outside of the power semiconductor module 1 is suppressed. Therefore, conduction of heat generated in the semiconductor element to the outside can be suppressed.
  • the semiconductor element and the terminal are connected via the metal plates 12a to 12g, and the terminal is formed of a material having a lower thermal conductivity than the metal plates 12a to 12g, so that the thermal conductivity of the terminal is increased. It is possible to further suppress the conduction of heat generated in the semiconductor element to the outside by keeping it low.
  • the heat radiating member 61 provides control terminals that have a higher temperature than the input / output terminals 22a to 22c through which input / output current flows. It can be cooled efficiently. Further, heat conduction to an external control circuit or the like connected to the semiconductor element via the control terminals 22d to 22g and wiring can be suppressed. In addition, a wide band gap semiconductor material is used for the semiconductor element, and the temperature tends to be high. However, the heat conduction to the outside can be appropriately suppressed by the configuration of the present invention.
  • the heat dissipation member 61 has an insulating property and the semiconductor element is connected to a plurality of external wirings via a plurality of terminals connected to the heat dissipation member 61, the plurality of terminals can be cooled while maintaining insulation. .
  • the present invention is not limited to the above embodiment, and can be implemented with various modifications.
  • a semiconductor material such as silicon may be used for the transistor or the diode.
  • the input / output terminal or the control terminal may be formed of the same material as the metal plate.
  • size, a shape, etc. can be changed and implemented in the range with which the effect of this invention is exhibited.
  • the present invention can be modified and implemented without departing from the object.

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Abstract

To provide a power semiconductor module which is capable of suppressing the transfer of the heat generated in a semiconductor element to the outside. This power semiconductor module is characterized by comprising a ceramic substrate (11), semiconductor elements (13a, 13b, 14a, 14b) arranged on one main surface (11a) of the ceramic substrate, terminals (22a-22g) connected to the semiconductor elements, a first heat dissipation member (41) that is arranged on the other main surface (11b) of the ceramic substrate, and a second heat dissipation member (61) that is arranged on the one main surface side of the ceramic substrate at a distance from the semiconductor elements. This power semiconductor module is also characterized in that the terminals are connected to the second heat dissipation member.

Description

パワー半導体モジュールPower semiconductor module
　本発明は、電力変換器などに用いられるパワー半導体モジュールに関する。 The present invention relates to a power semiconductor module used for a power converter or the like.
　近年、パワー半導体モジュール向けの半導体素子として、炭化ケイ素（ＳｉＣ）や窒化ガリウム（ＧａＮ）のようなワイドバンドギャップ半導体を使用する半導体素子（以下、ワイドバンドギャップ半導体素子）が注目されている。ワイドバンドギャップ半導体素子は、シリコンを使用する従来の半導体素子と比較して高温環境での動作が可能であり、低損失、高速動作などの優れた特性を併せ備えている。このワイドバンドギャップ半導体素子を用いることで、パワー半導体モジュールを小型高性能化できる。 In recent years, semiconductor elements using wide band gap semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) (hereinafter referred to as wide band gap semiconductor elements) are attracting attention as semiconductor elements for power semiconductor modules. The wide band gap semiconductor element can operate in a high temperature environment as compared with a conventional semiconductor element using silicon, and has excellent characteristics such as low loss and high speed operation. By using this wide band gap semiconductor element, the power semiconductor module can be miniaturized and improved in performance.
　ところで、パワー半導体モジュールは、一般に、ヒートシンクなどの放熱部材を備えている（例えば、特許文献１参照）。この放熱部材により、半導体素子で生じる熱は外部に発散されてパワー半導体モジュールの動作は安定化される。なお、特許文献１のパワー半導体モジュールは、半導体素子の上下を挟みこむように２個の放熱部材を備えており、高い冷却効率を実現している。 Incidentally, the power semiconductor module generally includes a heat radiating member such as a heat sink (see, for example, Patent Document 1). By this heat radiating member, heat generated in the semiconductor element is dissipated to the outside, and the operation of the power semiconductor module is stabilized. Note that the power semiconductor module of Patent Document 1 includes two heat dissipating members so as to sandwich the upper and lower sides of the semiconductor element, thereby realizing high cooling efficiency.
国際公開第２００９／１２５７７９号International Publication No. 2009/12579
　しかしながら、上述のようなパワー半導体モジュールにおいて、半導体素子で生じる熱は、パワー半導体モジュールと接続される外部の構成にまで伝導してしまうことがある。例えば、配線などを介して制御用の外部回路などに熱が伝わると、半導体素子に不具合はなくともパワー半導体モジュールの動作は不安定になる。温度への耐性が高いワイドバンドギャップ半導体素子は、従来の半導体素子と比較して高温で動作される傾向にあるので、ワイドバンドギャップ半導体素子を用いるパワー半導体モジュールでは、外部構成への熱伝導の問題はより深刻である。 However, in the power semiconductor module as described above, heat generated in the semiconductor element may be conducted to an external configuration connected to the power semiconductor module. For example, if heat is transmitted to an external circuit for control through wiring or the like, the operation of the power semiconductor module becomes unstable even if there is no malfunction in the semiconductor element. Wide band gap semiconductor elements having high resistance to temperature tend to operate at higher temperatures than conventional semiconductor elements. Therefore, in power semiconductor modules using wide band gap semiconductor elements, heat conduction to external components is difficult. The problem is more serious.
　本発明は、かかる点に鑑みてなされたものであり、半導体素子で生じる熱の外部への伝導を抑制可能なパワー半導体モジュールを提供することを目的とする。 The present invention has been made in view of such a point, and an object thereof is to provide a power semiconductor module capable of suppressing conduction of heat generated in a semiconductor element to the outside.
　本発明のパワー半導体モジュールは、セラミック基板と、前記セラミック基板の一方の主面側に配置される半導体素子と、前記半導体素子に接続される端子と、前記セラミック基板の他方の主面側に配置される第１の放熱部材と、前記セラミック基板の前記一方の主面側において、前記半導体素子から間隔をあけて配置される第２の放熱部材と、を備え、前記端子は、前記第２の放熱部材と接続されることを特徴とする。 The power semiconductor module of the present invention includes a ceramic substrate, a semiconductor element disposed on one main surface side of the ceramic substrate, a terminal connected to the semiconductor element, and the other main surface side of the ceramic substrate. A first heat dissipating member and a second heat dissipating member disposed at a distance from the semiconductor element on the one main surface side of the ceramic substrate, and the terminal includes the second heat dissipating member. It is connected to a heat radiating member.
　この構成によれば、半導体素子に接続される端子が第２の放熱部材と接続されるので、半導体素子から端子に伝わる熱は主に第２の放熱部材へと伝導され、端子からパワー半導体モジュール外への熱伝導は抑制される。すなわち、半導体素子で生じる熱の外部への伝導を抑制できる。 According to this configuration, since the terminal connected to the semiconductor element is connected to the second heat radiating member, the heat transmitted from the semiconductor element to the terminal is mainly conducted to the second heat radiating member, and the power semiconductor module is transmitted from the terminal. Heat conduction to the outside is suppressed. That is, conduction of heat generated in the semiconductor element to the outside can be suppressed.
　本発明のパワー半導体モジュールにおいて、前記端子は、前記半導体素子を制御する制御端子であることが好ましい。この構成によれば、入出力電流の流れる端子などと比較して高温になる制御端子を、第２の放熱部材で効率良く冷却できる。また、制御端子及び配線を介して半導体素子と接続される外部の制御回路などへの熱伝導を抑制できる。 In the power semiconductor module of the present invention, it is preferable that the terminal is a control terminal for controlling the semiconductor element. According to this configuration, the control terminal that is at a higher temperature than the terminal through which the input / output current flows can be efficiently cooled by the second heat radiating member. Further, heat conduction to an external control circuit connected to the semiconductor element through the control terminal and the wiring can be suppressed.
　本発明のパワー半導体モジュールにおいて、前記半導体素子と前記端子とは、金属板を介して接続されており、前記端子は、前記金属板より熱伝導率の低い材料で形成されることが好ましい。この構成によれば、端子の熱伝導率を低く抑えることで、半導体素子で生じる熱の外部への伝導をさらに抑制できる。 In the power semiconductor module of the present invention, it is preferable that the semiconductor element and the terminal are connected via a metal plate, and the terminal is formed of a material having a lower thermal conductivity than the metal plate. According to this configuration, the conduction of heat generated in the semiconductor element to the outside can be further suppressed by keeping the thermal conductivity of the terminal low.
　本発明のパワー半導体モジュールにおいて、前記半導体素子は、ワイドバンドギャップ半導体材料を使用した半導体素子であっても良い。この構成によれば、高温になりがちなワイドバンドギャップ半導体素子を用いるパワー半導体モジュールにおいて、外部への熱伝導を適切に抑制できる。 In the power semiconductor module of the present invention, the semiconductor element may be a semiconductor element using a wide band gap semiconductor material. According to this configuration, heat conduction to the outside can be appropriately suppressed in a power semiconductor module using a wide band gap semiconductor element that tends to be high temperature.
　本発明のパワー半導体モジュールにおいて、前記第２の放熱部材は、絶縁性を有し、前記半導体素子は、前記第２の放熱部材と接続する複数の端子を介して複数の外部配線と接続されても良い。この構成によれば、絶縁性を有する第２の放熱部材に複数の端子を接続するので、絶縁を保ちながら複数の端子を冷却できる。 In the power semiconductor module of the present invention, the second heat radiating member has insulating properties, and the semiconductor element is connected to a plurality of external wirings via a plurality of terminals connected to the second heat radiating member. Also good. According to this configuration, since the plurality of terminals are connected to the insulating second heat radiating member, the plurality of terminals can be cooled while maintaining insulation.
　本発明によれば、半導体素子で生じる熱の外部への伝導を抑制可能なパワー半導体モジュールを提供できる。 According to the present invention, it is possible to provide a power semiconductor module that can suppress conduction of heat generated in the semiconductor element to the outside.
本実施の形態に係るパワー半導体モジュールの構成例を示す模式図である。It is a schematic diagram which shows the structural example of the power semiconductor module which concerns on this Embodiment. 本実施の形態に係る放熱部材の構成例を示す断面模式図である。It is a cross-sectional schematic diagram which shows the structural example of the thermal radiation member which concerns on this Embodiment. 本実施の形態に係るパワー半導体モジュールの回路図である。It is a circuit diagram of the power semiconductor module which concerns on this Embodiment. 端子温度の検証結果を示す図である。It is a figure which shows the verification result of terminal temperature.
　以下、本発明の実施の形態について添付図面を参照して詳細に説明する。図１は、本実施の形態に係るパワー半導体モジュールの構成例を示す模式図である。図１Ａは、素子配置面側から見た平面模式図であり、図１Ｂは、素子配置面に垂直な断面を示す断面模式図である。なお、図１Ａでは、説明の便宜上、一部の構成を破線で示している。 Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a schematic diagram illustrating a configuration example of a power semiconductor module according to the present embodiment. 1A is a schematic plan view seen from the element arrangement surface side, and FIG. 1B is a schematic cross-sectional view showing a cross section perpendicular to the element arrangement surface. In FIG. 1A, for convenience of explanation, a part of the configuration is indicated by a broken line.
　図１に示すように、パワー半導体モジュール１は、各構成を支持するセラミック基板１１を備えている。セラミック基板１１は、窒化ケイ素、窒化アルミニウム、酸化アルミニウムなどの絶縁性の材料で構成されており、略長方形状の平面形状を有している。 As shown in FIG. 1, the power semiconductor module 1 includes a ceramic substrate 11 that supports each component. The ceramic substrate 11 is made of an insulating material such as silicon nitride, aluminum nitride, or aluminum oxide, and has a substantially rectangular planar shape.
　セラミック基板１１の素子配置面となる一方の主面（上側の主面）１１ａには、複数の金属板１２ａ，１２ｂ，１２ｃ，１２ｄ，１２ｅ，１２ｆ，１２ｇが設けられており、セラミック基板１１の他方の主面（下側の主面）１１ｂには、金属板１２ｈが設けられている。金属板１２ａ～１２ｈは、いずれも銅板であり、セラミック基板１１にろう接されている。なお、金属板１２ａ～１２ｈは、銅以外の金属で構成されても良い。 A plurality of metal plates 12 a, 12 b, 12 c, 12 d, 12 e, 12 f, and 12 g are provided on one main surface (upper main surface) 11 a serving as an element arrangement surface of the ceramic substrate 11. A metal plate 12h is provided on the other main surface (lower main surface) 11b. The metal plates 12a to 12h are all copper plates, and are soldered to the ceramic substrate 11. The metal plates 12a to 12h may be made of a metal other than copper.
　金属板１２ａ上には、半導体素子であるトランジスタ１３ａ及びダイオード１４ａが配置されている。トランジスタ１３ａ及びダイオード１４ａの下面には、それぞれ電極（不図示）が露出するように形成されており、半田によって、この電極と金属板１２ａとは電気的に接続されている。また、トランジスタ１３ａ及びダイオード１４ａの上面にはそれぞれ電極が露出するように形成されており、当該電極には後述する接続関係を形成するように導電性ワイヤ２１ａ，２１ｂ，２１ｃ，２１ｄが接続されている。 A transistor 13a and a diode 14a, which are semiconductor elements, are disposed on the metal plate 12a. Electrodes (not shown) are formed on the lower surfaces of the transistor 13a and the diode 14a, respectively, and the electrodes and the metal plate 12a are electrically connected by solder. Further, electrodes are formed on the upper surfaces of the transistor 13a and the diode 14a, respectively, and conductive wires 21a, 21b, 21c, and 21d are connected to the electrodes so as to form a connection relationship described later. Yes.
　同様に、金属板１２ｂ上には、半導体素子であるトランジスタ１３ｂ及びダイオード１４ｂが配置されている。トランジスタ１３ｂ及びダイオード１４ｂの下面には、それぞれ電極（不図示）が露出するように形成されており、半田によって、この電極と金属板１２ｂとが電気的に接続されている。また、トランジスタ１３ｂ及びダイオード１４ｂの上面にはそれぞれ電極が露出するように形成されており、当該電極には後述する接続関係を構成するように導電性ワイヤ２１ｅ，２１ｆ，２１ｇ，２１ｈが接続されている。 Similarly, a transistor 13b and a diode 14b, which are semiconductor elements, are arranged on the metal plate 12b. Electrodes (not shown) are formed on the lower surfaces of the transistor 13b and the diode 14b, respectively, and this electrode and the metal plate 12b are electrically connected by solder. Further, electrodes are formed on the upper surfaces of the transistor 13b and the diode 14b, respectively, and conductive wires 21e, 21f, 21g, and 21h are connected to the electrodes so as to form a connection relationship described later. Yes.
　トランジスタ１３ａ，１３ｂ、ダイオード１４ａ，１４ｂは、シリコンよりバンドギャップの広い半導体（ワイドバンドギャップ半導体）材料を用いて形成されている。このような半導体材料を用いた半導体素子は、シリコンを用いる従来の半導体素子と比較して損失を低減できる。また、このような半導体素子は、２００℃以上の比較的高い温度でも動作可能である。ワイドバンドギャップ半導体材料としては、例えば、炭化ケイ素（ＳｉＣ）や窒化ガリウム（ＧａＮ）などを用いることができる。 The transistors 13a and 13b and the diodes 14a and 14b are formed using a semiconductor (wide band gap semiconductor) material having a wider band gap than silicon. A semiconductor element using such a semiconductor material can reduce loss as compared with a conventional semiconductor element using silicon. Further, such a semiconductor element can operate at a relatively high temperature of 200 ° C. or higher. As the wide band gap semiconductor material, for example, silicon carbide (SiC), gallium nitride (GaN), or the like can be used.
　上述のように、トランジスタ１３ａ，１３ｂ、ダイオード１４ａ，１４ｂには、ワイドバンドギャップ半導体材料が用いられており、高温での動作が可能になっている。このため、これら半導体素子の周辺には、高融点のＡｕ－Ｇｅ半田（融点は約３５０℃）やＡｕ－Ｓｎ半田（融点は約２８５℃）などが用いられる。このような半田を用いれば、２００℃以上の高温環境でも、適切な電気的接続を実現できる。なお、半田の濡れを良くするために、半導体素子の電極や金属板１２ａ～１２ｈの表面などを金メッキしても良い。 As described above, wide bandgap semiconductor materials are used for the transistors 13a and 13b and the diodes 14a and 14b, so that they can operate at high temperatures. Therefore, high melting point Au—Ge solder (melting point is about 350 ° C.), Au—Sn solder (melting point is about 285 ° C.), or the like is used around these semiconductor elements. If such a solder is used, an appropriate electrical connection can be realized even in a high temperature environment of 200 ° C. or higher. In order to improve the wetness of the solder, the electrodes of the semiconductor elements, the surfaces of the metal plates 12a to 12h, etc. may be plated with gold.
　トランジスタ１３ａ，１３ｂは、ＦＥＴ（Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｅｒ）である。トランジスタ１３ａ，１３ｂとしてＦＥＴを用いることで、高いスイッチング速度を実現し、パワー半導体モジュール１を用いた電力変換器の変換効率を高めることができる。なお、トランジスタ１３ａ，１３ｂは、ＦＥＴであることに限られず、ＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ）などであっても良い。 Transistors 13a and 13b are FETs (Field Effect Transistors). By using FETs as the transistors 13a and 13b, a high switching speed can be realized and the conversion efficiency of the power converter using the power semiconductor module 1 can be increased. The transistors 13a and 13b are not limited to FETs, but may be IGBTs (InsulatedｕｌGate Bipolar Transistors) or the like.
　金属板１２ａ，１２ｂ，１２ｃには、それぞれ、入出力電流の流れる入出力端子２２ａ，２２ｂ，２２ｃが接続されている。金属板１２ｄには、トランジスタ１３ａのゲート電位を制御するための制御端子（ゲート端子）２２ｄが接続されており、金属板１２ｅには、トランジスタ１３ａのソース電位を制御するための制御端子（ソース端子）２２ｅが接続されている。また、金属板１２ｆには、トランジスタ１３ｂのゲート電位を制御するための制御端子（ゲート端子）２２ｆが接続されており、金属板１２ｇには、トランジスタ１３ａのソース電位を制御するための制御端子（ソース端子）２２ｇが接続されている。 The metal plates 12a, 12b, and 12c are connected to input / output terminals 22a, 22b, and 22c through which input / output currents flow, respectively. A control terminal (gate terminal) 22d for controlling the gate potential of the transistor 13a is connected to the metal plate 12d, and a control terminal (source terminal) for controlling the source potential of the transistor 13a is connected to the metal plate 12e. ) 22e is connected. Further, a control terminal (gate terminal) 22f for controlling the gate potential of the transistor 13b is connected to the metal plate 12f, and a control terminal (for controlling the source potential of the transistor 13a) is connected to the metal plate 12g. Source terminal) 22g is connected.
　これらの端子（入出力端子２２ａ～２２ｃ、及び制御端子２２ｅ～２２ｇ）は、金属板１２ａ～１２ｃと比較して熱伝導率の低い材料で形成されている。つまり、各端子は、銅（約３９８Ｗ／ｍ・Ｋ）より熱伝導率の低いアルミニウム（約２３６Ｗ／ｍ・Ｋ）、鉄（約８４Ｗ／ｍ・Ｋ）、白金（約７０Ｗ／ｍ・Ｋ）、ステンレス（１０～２５Ｗ／ｍ・Ｋ）などの材料で形成されている。 These terminals (input / output terminals 22a to 22c and control terminals 22e to 22g) are made of a material having a lower thermal conductivity than the metal plates 12a to 12c. In other words, each terminal has aluminum (about 236 W / m · K), iron (about 84 W / m · K), platinum (about 70 W / m · K) whose thermal conductivity is lower than that of copper (about 398 W / m · K). And stainless steel (10 to 25 W / m · K).
　電流方向に垂直な断面積は、制御端子２２ｄ～２２ｇより入出力端子２２ａ～２２ｃで大きくなっており、入出力端子２２ａ～２２ｃの電気抵抗は、制御端子２２ｅ～２２ｇより小さくなっている。また、制御端子２２ｄ～２２ｇは、構造的な強度を保てる最小限の断面積（例えば、厚みが０．１ｍｍ～０．５ｍｍ程度、又は直径が１ｍｍ程度）となるように形成されており、熱を伝導し難くなっている。 The cross-sectional area perpendicular to the current direction is larger at the input / output terminals 22a-22c than at the control terminals 22d-22g, and the electrical resistance of the input / output terminals 22a-22c is smaller than at the control terminals 22e-22g. The control terminals 22d to 22g are formed so as to have a minimum cross-sectional area (for example, a thickness of about 0.1 mm to 0.5 mm, or a diameter of about 1 mm) that can maintain structural strength. It is difficult to conduct.
　金属板１２ｈの下面には、放熱部材（第１の放熱部材）４１の銅ベース４１ａが半田で固定されている。銅ベース４１ａの固定には、半導体素子の接続などに用いられる半田より低融点の半田が使用される。例えば、上述した半導体素子の周辺においてＡｕ－Ｇｅ半田を用いる場合、銅ベース４１ａの固定には、Ａｕ－Ｓｎ半田を用いることができる。銅ベース４１ａには、放熱フィン４１ｃを有するヒートシンク４１ｂが固定されている。ヒートシンク４１ｂは、例えば、ボルト（不図示）を介して銅ベース４１ａに固定される。このように、金属板１２ｈの下面に固定された放熱部材４１で、半導体素子の温度は動作可能な範囲に保たれる。 The copper base 41a of the heat radiating member (first heat radiating member) 41 is fixed to the lower surface of the metal plate 12h with solder. For fixing the copper base 41a, solder having a lower melting point than that used for connecting a semiconductor element or the like is used. For example, when Au—Ge solder is used around the semiconductor element described above, Au—Sn solder can be used to fix the copper base 41a. A heat sink 41b having heat radiating fins 41c is fixed to the copper base 41a. The heat sink 41b is fixed to the copper base 41a via, for example, a bolt (not shown). In this way, the temperature of the semiconductor element is kept in an operable range by the heat radiation member 41 fixed to the lower surface of the metal plate 12h.
　銅ベース４１ａの上方には、セラミック基板１１の周囲を覆う樹脂製のケース５１が取り付けられており、ケース５１の内部にはシリコーンゲルが封入されている。シリコーンゲルとしては、例えば、２００℃以上の温度でも末端のシロキサンが変質しないものを選ぶ。また、ケース５１にはＰＰＳ樹脂やポリイミド樹脂など高耐熱の樹脂が用いられる。 A resin case 51 covering the periphery of the ceramic substrate 11 is attached above the copper base 41 a, and silicone gel is sealed inside the case 51. As the silicone gel, for example, a gel in which the terminal siloxane does not change even at a temperature of 200 ° C. or higher is selected. The case 51 is made of a highly heat-resistant resin such as PPS resin or polyimide resin.
　ケース５１の上面には、半導体素子から間隔をあけた位置に放熱部材（第２の放熱部材）６１が取り付けられている。この放熱部材６１は、熱伝導性及び絶縁性を有する放熱基板６１ａと、放熱フィン６１ｂとを備えている。放熱基板６１ａは、例えば、窒化ケイ素、窒化アルミニウム、酸化アルミニウムなどの熱伝導率の高い絶縁性材料で構成されたセラミック基板であり、略長方形状の平面形状を有している。放熱フィン６１ｂは、銅やアルミニウムなどの金属で構成されており、ろう接又は半田付けで放熱基板６１ａに固定されている。なお、放熱部材６１の構成は、図１に示すものに限定されない。 A heat radiating member (second heat radiating member) 61 is attached to the upper surface of the case 51 at a position spaced from the semiconductor element. The heat radiating member 61 includes a heat radiating substrate 61a having heat conductivity and insulating properties, and heat radiating fins 61b. The heat dissipation substrate 61a is a ceramic substrate made of an insulating material having a high thermal conductivity such as silicon nitride, aluminum nitride, or aluminum oxide, and has a substantially rectangular planar shape. The heat radiating fins 61b are made of metal such as copper or aluminum, and are fixed to the heat radiating substrate 61a by soldering or soldering. In addition, the structure of the heat radiating member 61 is not limited to what is shown in FIG.
　図２は、放熱部材６１の構成例を示す断面模式図である。放熱部材６１は、例えば、図２Ａに示すように、放熱フィン６１ｂとなる複数の板状物が放熱基板６１ａに取り付けられていても良いし、図２Ｂに示すように、折り曲げられた金属板が放熱フィン６１ｂとして放熱基板６１ａに取り付けられていても良い。さらに、図２Ｃに示すように、放熱フィン６１ｂの固定されたヒートシンクが放熱基板６１ａに取り付けられていても良い。 FIG. 2 is a schematic cross-sectional view showing a configuration example of the heat dissipation member 61. For example, as shown in FIG. 2A, the heat dissipating member 61 may have a plurality of plate-like objects serving as heat dissipating fins 61b attached to the heat dissipating substrate 61a, or a bent metal plate as shown in FIG. 2B. The heat radiating fins 61b may be attached to the heat radiating substrate 61a. Furthermore, as shown in FIG. 2C, a heat sink to which the heat radiating fins 61b are fixed may be attached to the heat radiating substrate 61a.
　図１に示すように、放熱部材６１には複数の端子が接続されている。具体的には、放熱基板６１ａの表面には、入出力端子２２ａ～２２ｃ及び制御端子２２ｄ～２２ｇに対応する導体パターン７１ａ～７１ｇが形成されており、入出力端子２２ａ～２２ｃ及び制御端子２２ｄ～２２ｇは、この導体パターン７１ａ～７１ｇに半田付けされている。入出力電流の流れる入出力端子２２ａ，２２ｂ，２２ｃには、それぞれ幅広の導体パターン７１ａ，７１ｂ，７１ｃが接続されている。制御端子２２ｄ，２２ｅ，２２ｆ，２２ｇには、それぞれ導体パターン７１ｄ，７１ｅ，７１ｆ，７１ｇが接続されている。なお、放熱基板６１ａは絶縁性を有しているので、端子間の絶縁は保たれている。 As shown in FIG. 1, a plurality of terminals are connected to the heat dissipation member 61. Specifically, conductor patterns 71a to 71g corresponding to the input / output terminals 22a to 22c and the control terminals 22d to 22g are formed on the surface of the heat dissipation board 61a, and the input / output terminals 22a to 22c and the control terminals 22d to 22g are formed. 22g is soldered to the conductor patterns 71a to 71g. Wide conductor patterns 71a, 71b, 71c are connected to the input / output terminals 22a, 22b, 22c through which the input / output current flows. Conductor patterns 71d, 71e, 71f, and 71g are connected to the control terminals 22d, 22e, 22f, and 22g, respectively. In addition, since the heat dissipation board 61a has insulation, insulation between terminals is maintained.
　複数の端子は、それぞれ、導体パターン７１ａ～７１ｇを介して外部配線（不図示）と接続されている。これにより、複数の端子は、各導体パターン７１ａ～７１ｇ及び外部配線を通じて、パワー半導体モジュール１の外部の構成に接続される。例えば、入出力電流の流れる入出力端子２２ａ～２２ｃは、導体パターン７１ａ～７１ｃ及び外部配線を通じて電源又は電流の供給先に接続されている。また、制御端子２２ｄ～２２ｇは、それぞれ導体パターン７１ｄ～７１ｇ及び外部配線を通じて制御回路に接続されている。 The plurality of terminals are respectively connected to external wiring (not shown) via conductor patterns 71a to 71g. Accordingly, the plurality of terminals are connected to the external configuration of the power semiconductor module 1 through the conductor patterns 71a to 71g and the external wiring. For example, the input / output terminals 22a to 22c through which the input / output current flows are connected to a power source or a current supply destination through the conductor patterns 71a to 71c and the external wiring. The control terminals 22d to 22g are connected to the control circuit through conductor patterns 71d to 71g and external wiring, respectively.
　このように構成されたパワー半導体モジュール１において、半導体素子と接続される複数の端子は、熱伝導率の高い放熱部材６１（例えば、１０Ｗ／ｍ・Ｋ以上）に接続されており、半導体素子から各端子に伝わる熱は、放熱部材６１で拡散される。つまり、各端子は放熱部材６１で強制的に冷却される。また、パワー半導体モジュール１の各端子は、金属板１２ａ～１２ｃより熱伝導率の低い材料で形成されているので、金属板１２ａ～１２ｃと同じ材料で各端子を形成する場合と比べて、半導体素子から端子への熱伝導は抑制される。このように、本実施の形態のパワー半導体モジュール１では、半導体素子と端子との間に温度差を生じさせることで、半導体素子で生じる熱の外部への伝導を抑制している。 In the power semiconductor module 1 configured as described above, a plurality of terminals connected to the semiconductor element are connected to a heat dissipation member 61 (for example, 10 W / m · K or more) having high thermal conductivity. The heat transmitted to each terminal is diffused by the heat radiating member 61. That is, each terminal is forcibly cooled by the heat radiating member 61. Further, since each terminal of the power semiconductor module 1 is made of a material having a lower thermal conductivity than the metal plates 12a to 12c, the semiconductor is compared with the case where each terminal is made of the same material as the metal plates 12a to 12c. Heat conduction from the element to the terminal is suppressed. As described above, in the power semiconductor module 1 of the present embodiment, the heat difference generated between the semiconductor elements is suppressed by generating a temperature difference between the semiconductor elements and the terminals.
　図３は、本実施の形態に係るパワー半導体モジュール１の回路図である。以下、図１及び図３を参照して説明する。図３に示すように、パワー半導体モジュール１において、電力供給用の入出力端子２２ａと入出力端子２２ｃとの間には、ｎチャネル型ＦＥＴであるトランジスタ１３ａと、ｎチャネル型ＦＥＴであるトランジスタ１３ｂとが直列に接続されている。具体的には、トランジスタ１３ａの下面において露出するドレイン電極には、金属板１２ａが接続されており、入出力端子２２ａを通じて電源との間で電流が流れるようになっている。また、トランジスタ１３ｂの上面において露出するソース電極は、導電性ワイヤ２１ｅによって金属板１２ｃと接続されている。これにより、トランジスタ１３ｂのソース電極には、入出力端子２２ｃを通じて電源との間で電流が流れるようになっている。 FIG. 3 is a circuit diagram of the power semiconductor module 1 according to the present embodiment. Hereinafter, a description will be given with reference to FIGS. 1 and 3. As shown in FIG. 3, in the power semiconductor module 1, between the input / output terminal 22a for power supply and the input / output terminal 22c, a transistor 13a that is an n-channel FET and a transistor 13b that is an n-channel FET are provided. Are connected in series. Specifically, a metal plate 12a is connected to the drain electrode exposed on the lower surface of the transistor 13a so that a current flows between the drain electrode and the power source through the input / output terminal 22a. The source electrode exposed on the upper surface of the transistor 13b is connected to the metal plate 12c by the conductive wire 21e. As a result, a current flows between the source electrode of the transistor 13b and the power supply through the input / output terminal 22c.
　トランジスタ１３ａの上面において露出するソース電極は、導電性ワイヤ２１ａによって金属板１２ｂと接続されている。また、トランジスタ１３ｂの下面において露出するドレイン電極は、金属板１２ｂと接続されている。これにより、トランジスタ１３ａのソース電極及びトランジスタ１３ｂのドレイン電極は、金属板１２ｂと接続される共通の入出力端子２２ｂに接続されている。 The source electrode exposed on the upper surface of the transistor 13a is connected to the metal plate 12b by the conductive wire 21a. The drain electrode exposed on the lower surface of the transistor 13b is connected to the metal plate 12b. Thereby, the source electrode of the transistor 13a and the drain electrode of the transistor 13b are connected to a common input / output terminal 22b connected to the metal plate 12b.
　トランジスタ１３ａの上面において露出するゲート電極は、導電性ワイヤ２１ｂによって金属板１２ｄと接続されており、金属板１２ｄに接続される制御端子２２ｄを通じてトランジスタ１３ａのスイッチングを制御する制御電位が印加される。また、トランジスタ１３ｂの上面において露出するゲート電極は、導電性ワイヤ２１ｆによって金属板１２ｆと接続されており、金属板１２ｆに接続される制御端子２２ｆを通じてトランジスタ１３ｂのスイッチングを制御する制御電位が印加される。 The gate electrode exposed on the upper surface of the transistor 13a is connected to the metal plate 12d by the conductive wire 21b, and a control potential for controlling the switching of the transistor 13a is applied through the control terminal 22d connected to the metal plate 12d. The gate electrode exposed on the upper surface of the transistor 13b is connected to the metal plate 12f by the conductive wire 21f, and a control potential for controlling the switching of the transistor 13b is applied through the control terminal 22f connected to the metal plate 12f. The
　また、トランジスタ１３ａの上面において露出するソース電極は、導電性ワイヤ２１ｃによって金属板１２ｅと接続されており、金属板１２ｅに接続される制御端子２２ｅでトランジスタ１３ａのソース電位は制御される。また、トランジスタ１３ｂの上面において露出するソース電極は、導電性ワイヤ２１ｇによって金属板１２ｇと接続されており、金属板１２ｇに接続される制御端子２２ｇでトランジスタ１３ｂのソース電位は制御される。トランジスタ１３ａ、１３ｂは、共にｎチャネル型のＦＥＴであるから、ゲート電極とソース電極との電位差がしきい値電圧より大きくなるとオンし、ゲート電極とソース電極との電位差がしきい値電圧より小さくなるとオフする。 Further, the source electrode exposed on the upper surface of the transistor 13a is connected to the metal plate 12e by the conductive wire 21c, and the source potential of the transistor 13a is controlled by the control terminal 22e connected to the metal plate 12e. The source electrode exposed on the upper surface of the transistor 13b is connected to the metal plate 12g by the conductive wire 21g, and the source potential of the transistor 13b is controlled by the control terminal 22g connected to the metal plate 12g. Since the transistors 13a and 13b are both n-channel FETs, they are turned on when the potential difference between the gate electrode and the source electrode becomes larger than the threshold voltage, and the potential difference between the gate electrode and the source electrode is smaller than the threshold voltage. Turn off.
　また、図３に示すように、トランジスタ１３ａに対して並列にダイオード１４ａが接続されている。具体的には、ダイオード１４ａの下面において露出するカソードは、金属板１２ａを介して入出力端子２２ａと接続されており、ダイオード１４ａの上面において露出するアノードは、導電性ワイヤ２１ｄ及び金属板１２ｂを介して入出力端子２２ｂと接続されている。これにより、ダイオード１４ａは、電源から逆方向バイアスが印加される。 As shown in FIG. 3, a diode 14a is connected in parallel to the transistor 13a. Specifically, the cathode exposed on the lower surface of the diode 14a is connected to the input / output terminal 22a via the metal plate 12a, and the anode exposed on the upper surface of the diode 14a connects the conductive wire 21d and the metal plate 12b. Via the input / output terminal 22b. As a result, a reverse bias is applied to the diode 14a from the power supply.
　同様に、トランジスタ１３ｂに対して並列にダイオード１４ｂが接続されている。具体的には、ダイオード１４ｂの下面において露出するカソードは、金属板１２ｂを介して入出力端子２２ｂと接続されている。また、ダイオード１４ｂの上面において露出するアノードは、導電性ワイヤ２１ｈ及び金属板１２ｃを介して入出力端子２２ｃと接続されている。これにより、ダイオード１４ｂは、電源から逆方向バイアスが印加される。 Similarly, a diode 14b is connected in parallel to the transistor 13b. Specifically, the cathode exposed on the lower surface of the diode 14b is connected to the input / output terminal 22b via the metal plate 12b. The anode exposed on the upper surface of the diode 14b is connected to the input / output terminal 22c through the conductive wire 21h and the metal plate 12c. Thereby, a reverse bias is applied to the diode 14b from the power source.
　このパワー半導体モジュール１において、例えば、トランジスタ１３ａのゲート電極とソース電極との電位差が大きくなってトランジスタ１３ａがオンされ、又はトランジスタ１３ｂのゲート電極とソース電極との電位差が大きくなってトランジスタ１３ｂがオンされると、トランジスタ１３ａのソース電極とドレイン電極との間、又はトランジスタ１３ｂのソース電極とドレイン電極との間には、実質的な電位差が無くなる。このため、トランジスタ１３ａ、１３ｂのオン、オフに応じて入出力端子２２ｂに流れる電流を制御できる。例えば、このようなパワー半導体モジュール１を複数使用することで、直流を交流に変換するインバータ(パワー半導体モジュール１が２個の場合は単相交流、３個の場合は三相交流)を構成できる。 In this power semiconductor module 1, for example, the potential difference between the gate electrode and the source electrode of the transistor 13a is increased and the transistor 13a is turned on, or the potential difference between the gate electrode and the source electrode of the transistor 13b is increased and the transistor 13b is turned on. Then, there is no substantial potential difference between the source electrode and the drain electrode of the transistor 13a or between the source electrode and the drain electrode of the transistor 13b. For this reason, the current flowing through the input / output terminal 22b can be controlled according to whether the transistors 13a and 13b are on or off. For example, by using a plurality of such power semiconductor modules 1, an inverter that converts direct current into alternating current (single-phase alternating current when there are two power semiconductor modules 1 and three-phase alternating current when there are three) can be configured. .
　本実施の形態のパワー半導体モジュール１では、半導体素子を制御する制御端子２２ｄ～２２ｇが熱伝導率の高い放熱部材６１に接続されている。このため制御端子２２ｄ及び配線を介して接続される制御回路などへの熱伝導を防止できる。つまり、半導体素子からの熱で制御回路が不安定になることはないので、パワー半導体モジュール１の動作を安定化できる。特に、本実施の形態のパワー半導体モジュール１では、ワイドギャップ半導体材料を使用した半導体素子が用いられているので、半導体素子の性能が最大限に発揮されるように高温動作させる場合でも、外部への熱伝導を適切に抑制できる。 In the power semiconductor module 1 of the present embodiment, the control terminals 22d to 22g for controlling the semiconductor elements are connected to the heat radiating member 61 having a high thermal conductivity. Therefore, heat conduction to the control terminal 22d and the control circuit connected via the wiring can be prevented. That is, since the control circuit does not become unstable due to heat from the semiconductor element, the operation of the power semiconductor module 1 can be stabilized. In particular, in the power semiconductor module 1 according to the present embodiment, since a semiconductor element using a wide gap semiconductor material is used, even when operating at a high temperature so that the performance of the semiconductor element is maximized, the power semiconductor module 1 is exposed to the outside. Can be suppressed appropriately.
　図４は、端子温度の検証結果を示す図である。図４Ａは、熱伝導率の高い放熱基板を使用したパワー半導体モジュールの検証結果を示し、図４Ｂは、熱伝導率の低い絶縁基板を使用したパワー半導体モジュールの検証結果を示している。すなわち、図４Ａの検証結果が、本実施の形態のパワー半導体モジュール１に対応する。なお、図４Ａと図４Ｂとで、放熱基板の使用の有無以外の条件は同じにした。 FIG. 4 is a diagram showing the verification results of the terminal temperature. FIG. 4A shows a verification result of a power semiconductor module using a heat dissipation substrate having a high thermal conductivity, and FIG. 4B shows a verification result of a power semiconductor module using an insulating substrate having a low thermal conductivity. That is, the verification result of FIG. 4A corresponds to the power semiconductor module 1 of the present embodiment. In FIG. 4A and FIG. 4B, the conditions other than the use / non-use of the heat dissipation substrate are the same.
　図４は、パワー半導体モジュールを、放熱基板又は絶縁基板に相当する基板Ｂ側から見た温度分布を示している。なお、基板Ｂには、複数の放熱フィンＦが設けられている。図４では、８０℃～１００℃の領域をａで、１００℃～１２０℃の領域をｂで、１２０℃～１４０℃の領域をｃで、１４０℃～１６０℃の領域をｄで、１６０℃以上の領域をｅで、それぞれ示す。 FIG. 4 shows a temperature distribution when the power semiconductor module is viewed from the substrate B side corresponding to the heat dissipation substrate or the insulating substrate. The substrate B is provided with a plurality of heat radiation fins F. In FIG. 4, the region of 80 ° C. to 100 ° C. is a, the region of 100 ° C. to 120 ° C. is b, the region of 120 ° C. to 140 ° C. is c, the region of 140 ° C. to 160 ° C. is d, and 160 ° C. The above regions are indicated by e, respectively.
　図４Ａに示すように、熱伝導率の高い放熱基板を使用したパワー半導体モジュールでは、制御端子に相当する端子Ｔ１，Ｔ２，Ｔ３，Ｔ４はいずれも１６０℃以下であった。より詳細には、端子Ｔ１，Ｔ２，Ｔ３，Ｔ４の温度は、１５０℃以下となっていた。また、入出力端子に相当する端子Ｔ５，Ｔ６，Ｔ７の温度は１２０℃～１６０℃であった。このように、制御端子に相当する端子Ｔ１，Ｔ２，Ｔ３，Ｔ４が低温になるのは、熱伝導率の高い基板Ｂで端子Ｔ１，Ｔ２，Ｔ３，Ｔ４の熱を十分に拡散できるからである。 As shown in FIG. 4A, in the power semiconductor module using the heat dissipation substrate with high thermal conductivity, the terminals T1, T2, T3, and T4 corresponding to the control terminals were all 160 ° C. or less. More specifically, the temperature of the terminals T1, T2, T3, T4 was 150 ° C. or less. The temperatures of the terminals T5, T6, T7 corresponding to the input / output terminals were 120 ° C. to 160 ° C. As described above, the reason why the terminals T1, T2, T3, and T4 corresponding to the control terminals become low temperature is that the heat of the terminals T1, T2, T3, and T4 can be sufficiently diffused by the substrate B having high thermal conductivity. .
　これに対して、図４Ｂに示すように、熱伝導率の低い絶縁基板を使用したパワー半導体モジュールでは、制御端子に相当する端子Ｔ１，Ｔ２，Ｔ３，Ｔ４はいずれも１６０℃以上であった。より詳細には、端子Ｔ１，Ｔ２，Ｔ３，Ｔ４の温度は、２００℃以上になっていた。入出力端子に相当する端子Ｔ５，Ｔ６，Ｔ７については、１２０℃～１６０℃であった。入出力端子は、幅広の導電パターン（図１Ａの導電パターン７１ａ～７１ｃに相当）に接続されており、放熱に有利なためである。 On the other hand, as shown in FIG. 4B, in the power semiconductor module using the insulating substrate having low thermal conductivity, the terminals T1, T2, T3, and T4 corresponding to the control terminals were all 160 ° C. or higher. More specifically, the temperature of the terminals T1, T2, T3, and T4 was 200 ° C. or higher. The terminals T5, T6, and T7 corresponding to the input / output terminals were 120 ° C. to 160 ° C. This is because the input / output terminals are connected to wide conductive patterns (corresponding to the conductive patterns 71a to 71c in FIG. 1A), which is advantageous for heat dissipation.
　このように、熱伝導率の高い放熱基板を使用しないパワー半導体モジュールでは、半導体素子からの熱で制御端子は高温になる。高温動作を可能にするワイドギャップ半導体材料を用いる半導体素子では、その傾向はさらに顕著である。これに対し、熱伝導率の高い放熱基板を使用したパワー半導体モジュールでは、放熱基板で端子が冷却される。このため、端子から外部への熱伝導を抑制できる。 Thus, in a power semiconductor module that does not use a heat dissipation substrate with high thermal conductivity, the control terminal becomes hot due to heat from the semiconductor element. This tendency is even more pronounced in semiconductor devices that use wide gap semiconductor materials that enable high temperature operation. On the other hand, in a power semiconductor module using a heat dissipation board with high thermal conductivity, the terminals are cooled by the heat dissipation board. For this reason, heat conduction from the terminal to the outside can be suppressed.
　以上、本発明の構成によれば、半導体素子（トランジスタ１３ａ，１３ｂ、ダイオード１４ａ，１４ｂ）に接続される端子（入出力端子２２ａ～２２ｃ、制御端子２２ｄ～２２ｇ）が、放熱部材（第２の放熱部材）６１と接続されるので、半導体素子から端子に伝わる熱は主に放熱部材６１へと伝導され、端子からパワー半導体モジュール１外への熱伝導は抑制される。よって、半導体素子で生じる熱の外部への伝導を抑制できる。また、半導体素子と端子とは、金属板１２ａ～１２ｇを介して接続されており、端子は、金属板１２ａ～１２ｇより熱伝導率の低い材料で形成されているので、端子の熱伝導率を低く抑えて、半導体素子で生じる熱の外部への伝導をさらに抑制できる。 As described above, according to the configuration of the present invention, the terminals (input / output terminals 22a to 22c, control terminals 22d to 22g) connected to the semiconductor elements ( transistors 13a and 13b, diodes 14a and 14b) are heat radiating members (second terminals). Since the heat transmitted from the semiconductor element to the terminal is mainly conducted to the heat radiating member 61, heat conduction from the terminal to the outside of the power semiconductor module 1 is suppressed. Therefore, conduction of heat generated in the semiconductor element to the outside can be suppressed. Further, the semiconductor element and the terminal are connected via the metal plates 12a to 12g, and the terminal is formed of a material having a lower thermal conductivity than the metal plates 12a to 12g, so that the thermal conductivity of the terminal is increased. It is possible to further suppress the conduction of heat generated in the semiconductor element to the outside by keeping it low.
　また、半導体素子を制御する制御端子２２ｄ～２２ｇが放熱部材６１に接続されているので、入出力電流の流れる入出力端子２２ａ～２２ｃなどと比較して高温になる制御端子を、放熱部材６１で効率良く冷却できる。また、制御端子２２ｄ～２２ｇ及び配線を介して半導体素子と接続される外部の制御回路などへの熱伝導を抑制できる。また、半導体素子には、ワイドバンドギャップ半導体材料が使用されており、高温になりがちであるが、本発明の構成により、外部への熱伝導を適切に抑制できる。 Further, since the control terminals 22d to 22g for controlling the semiconductor elements are connected to the heat radiating member 61, the heat radiating member 61 provides control terminals that have a higher temperature than the input / output terminals 22a to 22c through which input / output current flows. It can be cooled efficiently. Further, heat conduction to an external control circuit or the like connected to the semiconductor element via the control terminals 22d to 22g and wiring can be suppressed. In addition, a wide band gap semiconductor material is used for the semiconductor element, and the temperature tends to be high. However, the heat conduction to the outside can be appropriately suppressed by the configuration of the present invention.
　また、放熱部材６１は、絶縁性を有し、半導体素子は、放熱部材６１と接続する複数の端子を介して複数の外部配線と接続されているので、絶縁を保ちながら複数の端子を冷却できる。 Moreover, since the heat dissipation member 61 has an insulating property and the semiconductor element is connected to a plurality of external wirings via a plurality of terminals connected to the heat dissipation member 61, the plurality of terminals can be cooled while maintaining insulation. .
　なお、本発明は上記実施の形態に限定されず、さまざまに変更して実施可能である。例えば、トランジスタ又はダイオードには、シリコンなどの半導体材料が用いられていても良い。また、入出力端子又は制御端子は、金属板と同じ材料で形成されていても良い。また、上記実施の形態において、図面に示される各構成の位置、大きさ、形状などは、本発明の効果が発揮される範囲において変更して実施可能である。その他、本発明は、その目的を逸脱しない限りにおいて変更して実施可能である。 It should be noted that the present invention is not limited to the above embodiment, and can be implemented with various modifications. For example, a semiconductor material such as silicon may be used for the transistor or the diode. Further, the input / output terminal or the control terminal may be formed of the same material as the metal plate. Moreover, in the said embodiment, the position of each structure shown by drawing, a magnitude | size, a shape, etc. can be changed and implemented in the range with which the effect of this invention is exhibited. In addition, the present invention can be modified and implemented without departing from the object.
　本出願は、２０１２年９月２７日出願の特願２０１２－２１３６２０に基づく。この内容は、全てここに含めておく。 This application is based on Japanese Patent Application No. 2012-213620 filed on September 27, 2012. All this content is included here.

Claims (5)

  1. 　セラミック基板と、
    　前記セラミック基板の一方の主面側に配置される半導体素子と、
    　前記半導体素子に接続される端子と、
    　前記セラミック基板の他方の主面側に配置される第１の放熱部材と、
    　前記セラミック基板の前記一方の主面側において、前記半導体素子から間隔をあけて配置される第２の放熱部材と、を備え、
    　前記端子は、前記第２の放熱部材と接続されることを特徴とするパワー半導体モジュール。     A ceramic substrate;
    A semiconductor element disposed on one main surface side of the ceramic substrate;
    A terminal connected to the semiconductor element;
    A first heat dissipating member disposed on the other main surface side of the ceramic substrate;
    A second heat dissipating member disposed at a distance from the semiconductor element on the one main surface side of the ceramic substrate;
    The power semiconductor module, wherein the terminal is connected to the second heat dissipation member.
  2. 　前記端子は、前記半導体素子を制御する制御端子であることを特徴とする請求項１に記載のパワー半導体モジュール。 The power semiconductor module according to claim 1, wherein the terminal is a control terminal for controlling the semiconductor element.
  3. 　前記半導体素子と前記端子とは、金属板を介して接続されており、
    　前記端子は、前記金属板より熱伝導率の低い材料で形成されることを特徴とする請求項１に記載のパワー半導体モジュール。     The semiconductor element and the terminal are connected via a metal plate,
    The power semiconductor module according to claim 1, wherein the terminal is made of a material having a lower thermal conductivity than the metal plate.
  4. 　前記半導体素子は、ワイドバンドギャップ半導体材料を使用した半導体素子であることを特徴とする請求項１に記載のパワー半導体モジュール。 2. The power semiconductor module according to claim 1, wherein the semiconductor element is a semiconductor element using a wide band gap semiconductor material.
  5. 　前記第２の放熱部材は、絶縁性を有し、
    　前記半導体素子は、前記第２の放熱部材と接続する複数の端子を介して複数の外部配線と接続されることを特徴とする請求項１から請求項４のいずれかに記載のパワー半導体モジュール。     The second heat radiating member has an insulating property,
    5. The power semiconductor module according to claim 1, wherein the semiconductor element is connected to a plurality of external wirings via a plurality of terminals connected to the second heat dissipation member.
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