JP2017199830A - Power module - Google Patents

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JP2017199830A
JP2017199830A JP2016090263A JP2016090263A JP2017199830A JP 2017199830 A JP2017199830 A JP 2017199830A JP 2016090263 A JP2016090263 A JP 2016090263A JP 2016090263 A JP2016090263 A JP 2016090263A JP 2017199830 A JP2017199830 A JP 2017199830A
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semiconductor element
circuit pattern
semiconductor elements
insulating substrate
power module
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JP6540587B2 (en
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聡 川畑
Satoshi Kawabata
聡 川畑
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements

Abstract

PROBLEM TO BE SOLVED: To provide a power module capable of suppressing heat generation imbalance of a plurality of semiconductor elements and stably operating even at a high temperature.SOLUTION: In an insulating substrate 3 having a circuit pattern on one main surface thereof and at least three semiconductor elements bonded in a row to the circuit pattern, a thickness in a direction perpendicular to the main surface of a circuit pattern 2b immediately below a semiconductor element 1b at a position sandwiched between semiconductor elements 1a, 1c located at both ends is larger than a thickness in a direction perpendicular to the main surface of the circuit patterns 2a, 2c immediately below the semiconductor elements 1a, 1c located at both ends.SELECTED DRAWING: Figure 2

Description

本発明は、パワーモジュールの構造に関する。   The present invention relates to a structure of a power module.

近年、車両分野や産業機械分野または民生用機器分野において、高電圧、大電流動作が可能なパワーモジュールが用いられている。このようなパワーモジュールでは、搭載されている半導体素子が自己の発熱により高温になるため、高放熱性が要求される。そのため、熱伝導性に優れる銅を材料とした回路板及び放熱板を基板両面に接合するパワーモジュールが提案されている。例えば、特許文献１のパワーモジュールでは、回路板及び放熱板に異なる銅合金材料を使用して、異なる塑性変形能を与えて基板との密着性を良くし、放熱性を向上させている。   In recent years, power modules capable of high-voltage and large-current operation have been used in the vehicle field, industrial machine field, and consumer device field. In such a power module, since the mounted semiconductor element becomes high temperature due to its own heat generation, high heat dissipation is required. Therefore, a power module has been proposed in which a circuit board and a heat radiating board made of copper having excellent thermal conductivity are joined to both surfaces of a substrate. For example, in the power module of Patent Document 1, different copper alloy materials are used for the circuit board and the heat radiating plate to give different plastic deformability to improve the adhesion with the substrate and to improve the heat radiating property.

特開２０１２−２３４０３公報JP2012-23403

しかしながら、特許文献１のパワーモジュールでは、同一基板上において、複数の半導体素子を回路板表面に配置した場合、同じパワーを半導体素子に与えたとしても、同一基板上の中心部に熱が集中するため、素子間の発熱アンバランスを生み、放熱効率が悪化するという問題点があった。   However, in the power module of Patent Document 1, when a plurality of semiconductor elements are arranged on the surface of the circuit board on the same substrate, even if the same power is given to the semiconductor elements, heat is concentrated at the central portion on the same substrate. For this reason, there is a problem that heat generation imbalance occurs between elements, and heat dissipation efficiency deteriorates.

本発明は上記した問題点を解決するためになされたものであり、少なくとも３つ以上の半導体素子の発熱アンバランスを抑制するので、高温でも安定に動作させることができるパワーモジュールを得ることを目的とするものである。   The present invention has been made in order to solve the above-described problems, and suppresses heat generation imbalance of at least three or more semiconductor elements. Therefore, an object of the present invention is to obtain a power module that can be stably operated even at high temperatures. It is what.

一方主面に回路パターンが接合された絶縁基板に一列状に載置された半導体素子を有するパワーモジュールにおいて、半導体素子は回路パターンと接合して絶縁基板に載置され、少なくとも３つ以上の半導体素子のうち、両端に位置する第１半導体素子と第２半導体素子とに挟まれて位置する第３半導体素子の直下の回路パターンの主面に対する垂直方向の厚みは、第１半導体素子又は第２半導体素子の直下の回路パターンの主面に対する垂直方向の厚みより大きいことを特徴とする。   On the other hand, in a power module having semiconductor elements mounted in a row on an insulating substrate having a circuit pattern bonded to the main surface, the semiconductor elements are mounted on the insulating substrate bonded to the circuit pattern, and at least three or more semiconductors are mounted. Among the elements, the thickness in the direction perpendicular to the main surface of the circuit pattern immediately below the third semiconductor element located between the first semiconductor element and the second semiconductor element located at both ends is the first semiconductor element or the second semiconductor element. The thickness is greater than the thickness in the direction perpendicular to the main surface of the circuit pattern directly under the semiconductor element.

本発明に係るパワーモジュールによれば、パワーモジュール中で同一絶縁基板上に一列に載置された少なくとも３つ以上の半導体素子のうち、両端に位置する半導体素子に挟まれる半導体素子の素子温度が高くなる傾向にあるため、両端に位置する半導体素子に挟まれる半導体素子の直下の回路パターンを厚くすることで、両端に位置する半導体素子よりも両端に位置する半導体素子に挟まれる半導体素子の放熱効率を向上させて発熱アンバランスを抑制するので、パワーモジュールを高温でも安定に動作させることができる。   According to the power module of the present invention, the element temperature of the semiconductor element sandwiched between the semiconductor elements located at both ends among at least three or more semiconductor elements placed in a line on the same insulating substrate in the power module. Since the circuit pattern immediately below the semiconductor element sandwiched between the semiconductor elements located at both ends is made thicker, the heat dissipation of the semiconductor element sandwiched between the semiconductor elements located at both ends than the semiconductor element located at both ends is increased. Since efficiency is improved and heat generation imbalance is suppressed, the power module can be stably operated even at high temperatures.

実施の形態１のパワーモジュールを示す平面図である。FIG. 3 is a plan view showing the power module according to the first embodiment. 実施の形態１のパワーモジュールにおいて図１のＡ−Ａ’線における断面図である。FIG. 2 is a cross-sectional view taken along line A-A ′ of FIG. 1 in the power module according to the first embodiment. 実施の形態１のパワーモジュールにおいて図２の点線１０で囲われた部分を示す拡大図である。FIG. 3 is an enlarged view showing a portion surrounded by a dotted line 10 in FIG. 2 in the power module according to the first embodiment. 実施の形態２のパワーモジュールを示す断面図である。FIG. 4 is a cross-sectional view showing a power module according to a second embodiment.

実施の形態１
実施の形態１におけるパワーモジュールについて説明する。図１は、実施の形態１のパワーモジュールを示す平面図である。図２は、図１のＡ−Ａ’線における断面図である。なお、図１、図２において、同一符号は同一又は相当部分を示し、以下も同様である。パワーモジュール１００は、半導体素子１ａ、１ｂ、１ｃ（以下、１で代表する場合もある）がはんだを介して絶縁基板３の一方主面（上面）に接合されている回路パターン２ａ、２ｂ，２ｃ（以下、２で代表する場合もある）に接合し、絶縁基板３の主面に対向する絶縁基板３の他面（下面）に銅ベース４がはんだを介して接合される構成である。なお、銅ベース４はモジュール基板の一例である。 Embodiment 1
The power module in Embodiment 1 is demonstrated. 1 is a plan view showing a power module according to Embodiment 1. FIG. 2 is a cross-sectional view taken along line AA ′ of FIG. 1 and 2, the same reference numerals indicate the same or corresponding parts, and the same applies to the following. The power module 100 includes circuit patterns 2a, 2b, and 2c in which semiconductor elements 1a, 1b, and 1c (hereinafter, sometimes represented by 1) are joined to one main surface (upper surface) of the insulating substrate 3 via solder. The copper base 4 is bonded to the other surface (lower surface) of the insulating substrate 3 facing the main surface of the insulating substrate 3 through solder. The copper base 4 is an example of a module substrate.

図１に示すパワーモジュールでは、半導体素子１ａ、１ｂ、１ｃが並列回路を構成している。半導体素子１は、スイッチング素子であるＩＧＢＴであり、はんだを介して回路パターン２の上面に一列に接合される。なお、半導体素子は、ＩＧＢＴ以外のＭＯＳＦＥＴあるいはダイオード等であってもよい。また、半導体素子の個数は３個に限定されるものではなく、例えば、６個の半導体素子を組み合わせてインバータ回路を形成してもよい。回路パターン２は、銅または銅合金により回路パターンを構成しており絶縁基板３の上面にはんだあるいはろう材を介して接合される。回路パターン２は、半導体素子１の裏面電極、すなわち、ＩＧＢＴの場合はコレクタ電極と接続しており、半導体素子１の動作時に発生した熱を広げた上で、絶縁基板３側に放熱する役割を果たす。さらに、回路パターン２ａ、２ｂ，２ｃは、各回路パターン間において、金属ワイヤー６により電気的に接続されており、また、外部との電気信号を授受するための端子（図示せず）を有する。   In the power module shown in FIG. 1, the semiconductor elements 1a, 1b, and 1c constitute a parallel circuit. The semiconductor element 1 is an IGBT that is a switching element, and is joined in a row to the upper surface of the circuit pattern 2 via solder. The semiconductor element may be a MOSFET or a diode other than the IGBT. Further, the number of semiconductor elements is not limited to three. For example, an inverter circuit may be formed by combining six semiconductor elements. The circuit pattern 2 is a circuit pattern made of copper or copper alloy, and is joined to the upper surface of the insulating substrate 3 via solder or brazing material. The circuit pattern 2 is connected to the back electrode of the semiconductor element 1, that is, the collector electrode in the case of IGBT, and spreads the heat generated during the operation of the semiconductor element 1 and then radiates heat to the insulating substrate 3 side. Fulfill. Furthermore, the circuit patterns 2a, 2b, and 2c are electrically connected by a metal wire 6 between the circuit patterns, and have terminals (not shown) for exchanging electrical signals with the outside.

絶縁基板３は、セラミックス基板、窒化珪素基板、窒化アルミニウム基板、その他の窒化物、ホウ化物、酸化物、炭化物あるいはこれらの複合化合物の絶縁基板を用いることができる。絶縁基板３は銅ベース４の上面にはんだで接合されており、絶縁基板３の同一平面上に回路パターン２を介して半導体素子１が接続されて、銅ベース４と半導体素子１とが電気的に絶縁される。   As the insulating substrate 3, a ceramic substrate, a silicon nitride substrate, an aluminum nitride substrate, other nitrides, borides, oxides, carbides, or a composite compound thereof can be used. The insulating substrate 3 is joined to the upper surface of the copper base 4 with solder, and the semiconductor element 1 is connected to the same plane of the insulating substrate 3 via the circuit pattern 2 so that the copper base 4 and the semiconductor element 1 are electrically connected. Insulated.

出力パターン５は銅または銅合金で形成されており、絶縁基板３の上面にはんだを介して接合される。出力パターン５は、半導体素子１の表面電極、すなわちＩＧＢＴの場合はエミッタ電極と金属ワイヤー６を介して電気的に接続され、電気信号を外部へ出力するための端子（図示せず）を有する。銅ベース４は銅または銅合金で形成されており、半導体素子１の動作時に発生した熱を放熱するヒートシンクとしての役割を果たす。半導体素子１の動作時に発生した熱は、半導体素子１から回路パターン２を介して、絶縁基板３に伝達し、さらに、銅ベース４を介して放熱する。   The output pattern 5 is formed of copper or a copper alloy, and is joined to the upper surface of the insulating substrate 3 via solder. The output pattern 5 is electrically connected to the surface electrode of the semiconductor element 1, that is, in the case of an IGBT, via an emitter electrode and a metal wire 6, and has a terminal (not shown) for outputting an electric signal to the outside. The copper base 4 is made of copper or a copper alloy, and serves as a heat sink that dissipates heat generated during the operation of the semiconductor element 1. Heat generated during the operation of the semiconductor element 1 is transferred from the semiconductor element 1 to the insulating substrate 3 via the circuit pattern 2 and further dissipated through the copper base 4.

図３は、図２の点線１０で囲われた部分を示す拡大図である。ここで、半導体素子１ａ、１ｂに同じパワーを印加した場合における半導体素子１ａ、１ｂの各々で発生する熱の放熱経路を矢印１１ａ、１１ｂで示している。半導体素子１ａで発生した熱は、回路パターン２ａが薄いため、回路パターンの端部１２ａ、１２ｄまで熱が広がらず、熱の広がりが回路パターンのある位置１２ｂ、１２ｃに制限されている。一方、半導体素子１ｂで発生した熱は、回路パターン２ｂが厚く、回路パターンの端部１３ａ、１３ｂまで熱が広がるため、回路パターンが薄い場合よりも放熱効率を向上させることができる。   FIG. 3 is an enlarged view showing a portion surrounded by a dotted line 10 in FIG. Here, heat radiation paths of heat generated in each of the semiconductor elements 1a and 1b when the same power is applied to the semiconductor elements 1a and 1b are indicated by arrows 11a and 11b. Since the heat generated in the semiconductor element 1a is thin in the circuit pattern 2a, the heat does not spread to the ends 12a and 12d of the circuit pattern, and the spread of the heat is limited to the positions 12b and 12c where the circuit pattern is present. On the other hand, since the heat generated in the semiconductor element 1b is thick in the circuit pattern 2b and spreads to the end portions 13a and 13b of the circuit pattern, the heat radiation efficiency can be improved as compared with the case where the circuit pattern is thin.

図２のようなパワーモジュールを想定した場合、半導体素子１ｂは半導体素子１ａ、１ｃに挟まれて位置しており、半導体素子１ｂは、半導体素子１ａ、１ｃに対して素子温度が高くなる。かかる現象が生じるのは、半導体素子１ａ、１ｃから発生した熱が、半導体素子１ａ、１ｃに挟まれて位置する半導体素子１ｂの方向に熱伝導して、素子温度を相対的に上昇させるからである。
また、図２に示すような同一の絶縁基板上に回路パターンを介して一列に載置された半導体素子が３つの場合は、両端に位置する２つの半導体素子により１つの半導体素子が挟まれる。さらに、同一の絶縁基板上に回路パターンを介して載置された半導体素子が一列に並べられた５個である場合は、両端に位置する２つの半導体素子により３つの半導体素子が挟まれる。なお、実施例に限らず、半導体素子の個数は少なくとも３つ以上で一列に並んでいればよく、例えば、Ｌ字型に半導体素子を配置するパワーモジュールに対して、半導体素子を一列に配置することでパワーモジュールを小型化することができる。 When the power module as shown in FIG. 2 is assumed, the semiconductor element 1b is located between the semiconductor elements 1a and 1c, and the element temperature of the semiconductor element 1b is higher than that of the semiconductor elements 1a and 1c. This phenomenon occurs because the heat generated from the semiconductor elements 1a and 1c is conducted in the direction of the semiconductor element 1b located between the semiconductor elements 1a and 1c, and the element temperature is relatively increased. is there.
In the case where there are three semiconductor elements placed in a line on the same insulating substrate as shown in FIG. 2 via a circuit pattern, one semiconductor element is sandwiched between two semiconductor elements located at both ends. Further, when there are five semiconductor elements placed in a line on the same insulating substrate via a circuit pattern, the three semiconductor elements are sandwiched between the two semiconductor elements located at both ends. Note that the number of semiconductor elements is not limited to the embodiment, and it is sufficient that the number of semiconductor elements is at least three and arranged in a line. Thus, the power module can be reduced in size.

両端に位置する２つの半導体素子１ａ、１ｃに対して、半導体素子１ａ、１ｃに挟まれて位置し半導体素子１ａ、１ｃからの熱拡散の影響を受けて相対的に素子温度が高くなる半導体素子１ｂの直下にある回路パターン２ｂの絶縁基板３の上面に対して垂直方向の厚みを、半導体素子１ａ、１ｃの直下にある回路パターン２ａ、２ｂの絶縁基板の上面に対して垂直方向の厚みよりも大きくすることで、半導体素子１ａ、１ｃに対して半導体素子１ｂの放熱効率を高めることができる。なお、実施例に限らず回路パターン２は絶縁基板３の上面に一様に広がるように形成され、部分的に回路パターン２を厚くしても半導体素子１ａ、１ｃに対して半導体素子１ｂの放熱効率を高めることができる。さらに、両端に位置する２つの半導体素子に挟まれる位置にある半導体素子の直下にある回路パターンの厚さは、両端に位置する半導体素子の直下にある回路パターンの厚みに対して例えば１．５倍程度大きくすることが好ましい。   A semiconductor element having a relatively high element temperature due to the influence of thermal diffusion from the semiconductor elements 1a and 1c, which is located between the semiconductor elements 1a and 1c, relative to the two semiconductor elements 1a and 1c located at both ends The thickness in the direction perpendicular to the upper surface of the insulating substrate 3 of the circuit pattern 2b immediately below 1b is greater than the thickness in the direction perpendicular to the upper surface of the insulating substrate of circuit patterns 2a and 2b immediately below the semiconductor elements 1a and 1c Also, the heat dissipation efficiency of the semiconductor element 1b can be increased with respect to the semiconductor elements 1a and 1c. The circuit pattern 2 is not limited to the embodiment, and is formed so as to spread uniformly on the upper surface of the insulating substrate 3. Even if the circuit pattern 2 is partially thickened, the heat dissipation of the semiconductor element 1b with respect to the semiconductor elements 1a and 1c. Efficiency can be increased. Further, the thickness of the circuit pattern immediately below the semiconductor element located between the two semiconductor elements located at both ends is, for example, 1.5% of the thickness of the circuit pattern immediately below the semiconductor element located at both ends. It is preferable to make it about twice as large.

この実施の形態１のパワーモジュールによれば、一列に並ぶ少なくとも３つ以上の半導体素子のうち、両端に位置する半導体素子に挟まれる半導体素子の素子温度が相対的に高くなる傾向にあることから、両端に位置する半導体素子に挟まれる半導体素子の直下の回路パターンを厚くすることで、両端に位置する半導体素子よりも両端に位置する半導体素子に挟まれる半導体素子の放熱効率を向上させて、全体として発熱アンバランスを抑制できるという効果を奏する。   According to the power module of the first embodiment, among the at least three or more semiconductor elements arranged in a row, the element temperature of the semiconductor element sandwiched between the semiconductor elements located at both ends tends to be relatively high. By increasing the circuit pattern immediately below the semiconductor element sandwiched between the semiconductor elements located at both ends, the heat dissipation efficiency of the semiconductor element sandwiched between the semiconductor elements located at both ends is improved compared to the semiconductor element located at both ends, As a whole, there is an effect that heat imbalance can be suppressed.

実施の形態２
実施の形態２のパワーモジュールについて説明する。図４は、実施の形態２のパワーモジュールを示す断面図である。実施の形態２のパワーモジュールは、実施の形態１のパワーモジュールにおいて、半導体素子が搭載される絶縁基板の厚みが同一であるのに対して、絶縁基板の厚みが同一でない点が異なる。 Embodiment 2
A power module according to the second embodiment will be described. FIG. 4 is a cross-sectional view showing the power module of the second embodiment. The power module according to the second embodiment is different from the power module according to the first embodiment in that the thickness of the insulating substrate on which the semiconductor element is mounted is the same, whereas the thickness of the insulating substrate is not the same.

図４より、絶縁基板３は半導体素子１ａと１ｂ、および、１ｂと１ｃの各半導体素子間において段差を有し、半導体素子１ｂの下方に位置する絶縁基板３が凹部を有するように形成されている。絶縁基板３の凹部の底面は、回路パターン２ｂと絶縁基板３とが接合する接合部を有しており、絶縁基板３の凹部の底面から絶縁基板３の上面に対向する絶縁基板３の下面までの部位を絶縁基板部位３ｂとしている。両端に位置する半導体素子１ａ、１ｃの下方には回路パターン２ａ、２ｃと絶縁基板３とが接合する接合部を絶縁基板３が有しており、絶縁基板３の凹部底面より半導体素子側に高く位置する絶縁基板３の上面から絶縁基板３の下面までの部位を絶縁基板部位３ａ、３ｃとしている。半導体素子１ｂは半導体素子１ａ、１ｃに挟まれて位置しており、半導体素子１ｂは、両端に位置する半導体素子１ａ、１ｃに対して素子温度が高くなるため、絶縁基板部位３ａ、３ｃと回路パターン２ａ、２ｃとの接合部から絶縁基板３の下面までの絶縁基板の上面に対する垂直方向の厚みは、絶縁基板部位３ｂと回路パターン２ｂとの接合部から絶縁基板３の下面までの絶縁基板３の上面に対する垂直方向の厚みよりも大きく、さらに半導体素子１ｂの直下の回路パターン２ｂを半導体素子１ａ、１ｃの直下の回路パターン２ａ、２ｃに対して相対的に厚くすることで、両端に位置する半導体素子１ａ、１ｃよりも半導体素子１ｂの放熱効率をさらに高めることができる。なお、半導体素子１ａ、１ｃに対して素子温度が高い半導体素子１ｂの直下に位置する回路パターン２ｂを、両端に位置する半導体素子１ａ、１ｃの直下に位置する回路パターン２ａ、２ｃよりも熱伝導率の良い材料である銀などに変更することで、半導体素子１ａ、１ｃよりも半導体素子１ｂの放熱効率をさらに向上させることができる。   As shown in FIG. 4, the insulating substrate 3 has a step between the semiconductor elements 1a and 1b and the semiconductor elements 1b and 1c, and the insulating substrate 3 located below the semiconductor element 1b has a recess. Yes. The bottom surface of the concave portion of the insulating substrate 3 has a joint where the circuit pattern 2b and the insulating substrate 3 are bonded. From the bottom surface of the concave portion of the insulating substrate 3 to the lower surface of the insulating substrate 3 facing the upper surface of the insulating substrate 3. This part is an insulating substrate part 3b. Below the semiconductor elements 1a and 1c located at both ends, the insulating substrate 3 has a joint where the circuit patterns 2a and 2c and the insulating substrate 3 are joined. The portions from the upper surface of the insulating substrate 3 positioned to the lower surface of the insulating substrate 3 are defined as insulating substrate portions 3a and 3c. The semiconductor element 1b is positioned between the semiconductor elements 1a and 1c. Since the semiconductor element 1b has a higher element temperature than the semiconductor elements 1a and 1c located at both ends, the semiconductor element 1b is connected to the insulating substrate portions 3a and 3c. The thickness in the direction perpendicular to the upper surface of the insulating substrate from the junction between the patterns 2a and 2c to the lower surface of the insulating substrate 3 is the insulating substrate 3 from the junction between the insulating substrate portion 3b and the circuit pattern 2b to the lower surface of the insulating substrate 3. The circuit pattern 2b directly below the semiconductor element 1b is thicker than the circuit pattern 2a and 2c immediately below the semiconductor elements 1a and 1c, thereby being positioned at both ends. The heat dissipation efficiency of the semiconductor element 1b can be further increased as compared with the semiconductor elements 1a and 1c. Note that the circuit pattern 2b located immediately below the semiconductor element 1b having a higher element temperature than the semiconductor elements 1a and 1c is more thermally conductive than the circuit patterns 2a and 2c located immediately below the semiconductor elements 1a and 1c located at both ends. By changing to silver or the like, which is a good material, the heat dissipation efficiency of the semiconductor element 1b can be further improved than the semiconductor elements 1a and 1c.

この実施の形態２のパワーモジュールによれば、一列に並ぶ少なくとも３つ以上の半導体素子のうち、両端に位置する半導体素子に挟まれる半導体素子の素子温度が高くなる傾向にあることから、両端に位置する半導体素子に挟まれる半導体素子の直下の回路パターンと絶縁基板との接合部から絶縁基板の下面までの厚みを両端に位置する半導体素子の直下の回路パターンと絶縁基板との接合部から絶縁基板の下面までの厚みより相対的に薄く、かつ、回路パターンを厚くすることで両端に位置する半導体素子よりも両端に位置する半導体素子に挟まれる半導体素子の放熱効率を向上させて発熱アンバランスを抑制できるという効果を奏する。   According to the power module of the second embodiment, among the at least three or more semiconductor elements arranged in a row, the element temperature of the semiconductor element sandwiched between the semiconductor elements located at both ends tends to increase. Insulating from the junction between the circuit pattern directly under the semiconductor element sandwiched between the semiconductor element located and the insulating substrate to the bottom surface of the insulating substrate from the junction between the circuit pattern directly under the semiconductor element located at both ends and the insulation substrate Unbalanced heat generation by improving the heat dissipation efficiency of the semiconductor elements sandwiched between the semiconductor elements located at both ends than the semiconductor elements located at both ends by making the circuit pattern relatively thicker than the thickness to the bottom surface of the substrate. There is an effect that can be suppressed.

また、両端に位置する半導体素子に挟まれる半導体素子の直下の回路パターンの部位を、両端に位置する半導体素子の直下の回路パターンの部位よりも熱伝導率の良い材料である銀などに変更することで、両端に位置する半導体素子よりも両端に位置する半導体素子に挟まれる半導体素子の放熱効率をさらに向上させることができる。   Further, the part of the circuit pattern immediately below the semiconductor element sandwiched between the semiconductor elements located at both ends is changed to silver, which is a material having a higher thermal conductivity than the part of the circuit pattern immediately below the semiconductor element located at both ends. Thus, the heat dissipation efficiency of the semiconductor element sandwiched between the semiconductor elements located at both ends can be further improved than the semiconductor elements located at both ends.

なお、本発明は、その発明の範囲内において、各実施の形態及び変形例を自由に組み合わせ、各実施の形態を適宜、変形、省略することが可能である。   Note that the present invention can be freely combined with each embodiment and modification within the scope of the invention, and each embodiment can be appropriately modified and omitted.

１ａ，１ｂ，１ｃ 半導体素子、２ａ，２ｂ，２ｃ 回路パターン、３ 絶縁基板、４ 銅ベース、５ 出力パターン、６ 金属ワイヤー、１１ａ，１１ｂ 放熱経路、１００ パワーモジュール。   1a, 1b, 1c Semiconductor element, 2a, 2b, 2c Circuit pattern, 3 Insulating substrate, 4 Copper base, 5 Output pattern, 6 Metal wire, 11a, 11b Heat dissipation path, 100 Power module.

Claims (3)

一方主面に回路パターンが接合された絶縁基板と、前記回路パターンと接合して前記絶縁基板に一列状に載置された少なくとも３つ以上の半導体素子を有するパワーモジュールであって、
前記半導体素子のうち、両端に位置する第１半導体素子と第２半導体素子とに挟まれて位置する第３半導体素子の直下の前記回路パターンの前記主面に対する垂直方向の厚みは、前記第１半導体素子又は前記第２半導体素子の直下の前記回路パターンの前記主面に対する垂直方向の厚みより大きいことを特徴とするパワーモジュール。 On the other hand, an insulating substrate having a circuit pattern bonded to the main surface, and a power module having at least three or more semiconductor elements bonded to the circuit pattern and placed in a row on the insulating substrate,
Among the semiconductor elements, the thickness in the direction perpendicular to the main surface of the circuit pattern directly below the third semiconductor element located between the first semiconductor element and the second semiconductor element located at both ends is the first thickness. A power module having a thickness greater than a thickness in a direction perpendicular to the main surface of the circuit pattern immediately below the semiconductor element or the second semiconductor element. 前記第１半導体素子又は前記第２半導体素子の直下の前記回路パターンと前記主面との接合部から前記主面に対向する前記絶縁基板の他面までの前記主面に対する垂直方向の前記絶縁基板厚みは、前記第３半導体素子の直下の前記回路パターンと前記主面との接合部から前記他面までの前記主面に対する垂直方向の前記絶縁基板の厚みより大きいことを特徴とする請求項１に記載のパワーモジュール。   The insulating substrate in a direction perpendicular to the main surface from a junction between the circuit pattern directly below the first semiconductor element or the second semiconductor element and the main surface to the other surface of the insulating substrate facing the main surface 2. The thickness is greater than the thickness of the insulating substrate in a direction perpendicular to the main surface from a junction between the circuit pattern directly below the third semiconductor element and the main surface to the other surface. Power module as described in 前記第３半導体素子の直下に位置する前記回路パターンは、銀で構成されていることを特徴とする請求項１又は２に記載のパワーモジュール。   3. The power module according to claim 1, wherein the circuit pattern located immediately below the third semiconductor element is made of silver. 4.
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