WO2014038243A1 - Structure graphène-cnt et son procédé de fabrication - Google Patents

Structure graphène-cnt et son procédé de fabrication Download PDF

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WO2014038243A1
WO2014038243A1 PCT/JP2013/062501 JP2013062501W WO2014038243A1 WO 2014038243 A1 WO2014038243 A1 WO 2014038243A1 JP 2013062501 W JP2013062501 W JP 2013062501W WO 2014038243 A1 WO2014038243 A1 WO 2014038243A1
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graphene
layer
vertical
base
cnt structure
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PCT/JP2013/062501
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Japanese (ja)
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川端　章夫
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独立行政法人産業技術総合研究所
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/26—Deposition of carbon only
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53276—Conductive materials containing carbon, e.g. fullerenes
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0676—Nanowires or nanotubes oriented perpendicular or at an angle to a substrate
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1606—Graphene
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors
    • H01L2221/1094—Conducting structures comprising nanotubes or nanowires
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
    • H10K85/221—Carbon nanotubes

Definitions

  • the present invention relates to a graphene-CNT structure and a manufacturing method thereof.
  • CNT Carbon-NanoTube
  • Graphene graphene
  • the present invention has been made in view of the above problems, and a highly reliable graphene-CNT structure in which a composite structure of graphene and CNT grows in a desired fine region at a sufficiently high density, and its manufacture It aims to provide a method.
  • the graphene-CNT structure of the present invention includes a base, a base formed above the base, vertical graphene grown from the base, and vertically densely standing upright in a direction perpendicular to the base surface; And carbon nanotubes grown from the base and integrally formed with the lower end of the vertical graphene at the upper end.
  • the method for producing a graphene-CNT structure according to the present invention includes a step of forming a base above a base, and using the base, grows vertical graphene that is densely stacked upright in a vertical direction with respect to the surface of the base And subsequently growing a carbon nanotube connected at the lower end and the upper end of the vertical graphene.
  • FIG. 1A is a schematic cross-sectional view illustrating the method of manufacturing the graphene structure according to the first embodiment in the order of steps.
  • FIG. 1B is a schematic cross-sectional view illustrating the manufacturing method of the graphene structure according to the first embodiment in the order of steps, following FIG. 1A.
  • FIG. 1C is a schematic cross-sectional view subsequent to FIG. 1B, illustrating the graphene structure manufacturing method according to the first embodiment in the order of steps.
  • FIG. 1D is a schematic cross-sectional view subsequent to FIG. 1C, illustrating the graphene structure manufacturing method according to the first embodiment in the order of steps.
  • FIG. 2 is a schematic diagram showing a vacuum process system for performing a consistent vacuum process in the first embodiment.
  • FIG. 1A is a schematic cross-sectional view illustrating the method of manufacturing the graphene structure according to the first embodiment in the order of steps.
  • FIG. 1B is a schematic cross-sectional view illustrating the manufacturing method of the graphene structure according
  • FIG. 3 is a characteristic diagram showing the relationship between the growth time and the growth temperature when forming an integral structure of horizontal graphene, vertical graphene, and CNT.
  • FIG. 4A is a schematic cross-sectional view illustrating the method of manufacturing the MOS transistor according to the second embodiment in the order of steps.
  • FIG. 4B is a schematic cross-sectional view illustrating the method of manufacturing the MOS transistor according to the second embodiment in the order of steps, following FIG. 4A.
  • FIG. 4C is a schematic cross-sectional view subsequent to FIG. 4B, showing the MOS transistor manufacturing method according to the second embodiment in the order of steps.
  • FIG. 5 is an enlarged schematic cross-sectional view showing a state in the contact hole in the MOS transistor according to the second embodiment.
  • FIG. 6 is an enlarged schematic plan view showing the state of vertical graphene in the contact hole in the MOS transistor according to the second embodiment.
  • FIGS. 1A to 1D are schematic cross-sectional views showing a method of manufacturing a graphene-CNT structure according to the first embodiment in the order of steps.
  • FIG. 2 is a schematic diagram showing a vacuum process system for performing a consistent vacuum process.
  • This vacuum process system includes a transfer chamber 101 provided in the center, a load lock chamber 102 for loading and unloading a growth substrate, a deposition chamber 103 for forming a base, and a CVD chamber 104 for growing graphene-CNT. I have.
  • the growth substrate is vacuum-transferred to each desired chamber by a robot arm provided in the transfer chamber 101.
  • each process can be performed in-situ consistently without exposing the growth substrate to the outside air.
  • a base 2 is formed on a silicon substrate 1.
  • a silicon substrate 1 is prepared as a growth substrate.
  • the silicon substrate 1 is transferred to the deposition chamber 103 of the vacuum process system.
  • the first layer 2a and the second layer 2b are sequentially stacked on the silicon substrate 1 by a vacuum evaporation method, a sputtering method, an atomic layer deposition method (ALD method), or the like.
  • the first layer 2a is at least one selected from titanium (Ti), titanium nitride (TiN), titanium oxide (TiO 2 ), niobium (Nb), and vanadium (V), and has a film shape. It is formed. For example, Ti is deposited to a thickness of about 0.5 nm to 1.5 nm to form the first layer 2a.
  • the first layer 2a has an adhesion function with the silicon substrate 1 of the second layer 2b.
  • the second layer 2b is at least one selected from cobalt (Co), nickel (Ni), and iron (Fe), and becomes a film immediately after formation.
  • Co is deposited to a thickness of about 2 nm to 5 nm to form the second layer 2b.
  • the second layer 2b has a direct catalytic function for graphene growth.
  • FIG. 3 is a characteristic diagram showing the relationship between the growth time and the growth temperature when forming an integral structure of horizontal graphene, vertical graphene, and CNT.
  • the silicon substrate 1 is transferred to the CVD chamber 104.
  • a source gas is introduced into the CVD chamber 104.
  • acetylene (C 2 H 2 ) gas is used as the source gas.
  • the flow rate of C 2 H 2 gas is set to about 50 sccm.
  • the growth temperature (environment temperature in the CVD method 104) is set to a value within a low temperature range of 400 ° C. to 450 ° C., here about 450 ° C., and the temperature is raised to 450 ° C.
  • Graphene grows in the horizontal direction (lateral direction) with respect to the surface of the silicon substrate 1 using the Co film of the second layer 2b as a catalyst.
  • This graphene is referred to as lateral graphene 3.
  • the lateral graphene 3 is stacked in one or more layers. The situation at this time is shown in FIG. 1B.
  • the Co film of the second layer 2b aggregates to become particulate or island-shaped Co.
  • the Co of the third layer 2c is in the form of particles or islands
  • graphene grows in a direction perpendicular to the surface of the silicon substrate 1 (longitudinal direction). This graphene is called longitudinal graphene 4.
  • the vertical graphene 4 is connected to the horizontal graphene 3 at the upper end, is integrally formed, and is stacked in a plurality of layers that stand upright in the vertical direction and are densely superimposed. The state at this time is shown in FIG. 1C.
  • the growth temperature (environment temperature in the CVD method 104) is set to a value within a high temperature range of 250 ° C. to 1000 ° C., here about 800 ° C., from 450 ° C. to 800 ° C.
  • the temperature rises gradually.
  • the aggregation of particulate or island-like Co in the second layer 2b further proceeds, the Co in the second layer 2b starts to become fine particles, and the CNT 5 grows in a direction perpendicular to the surface of the silicon substrate 1 (longitudinal direction). To do.
  • the CNTs 5 are integrally formed with the upper ends thereof connected to the lower ends of the vertical graphenes 4, and a plurality of the CNTs 5 stand densely in the vertical direction.
  • the situation at this time is shown in FIG. 1D.
  • the thickness of the CNT 5 can be changed by changing the temperature increase rate (temperature gradient) when the temperature is increased from 450 ° C. to 800 ° C. If the temperature gradient is set gently as shown in FIG. 3a, the CNT 5 has a large diameter. On the other hand, if the temperature gradient is set steep as shown in FIG. 3b, the CNT5 has a smaller diameter than the CNT5 of FIG.
  • the integrated structure of the lateral graphene 3, the longitudinal graphene 4, and the CNT 5 can be formed in one continuous process, and the longitudinal direction is stacked at an extremely high density. Graphene 4 and CNT5 can be obtained.
  • FIG. 4A to FIG. 4C and FIG. 5 are schematic cross-sectional views showing the MOS transistor manufacturing method according to the second embodiment in the order of steps.
  • a transistor element 20 is formed as a functional element on a silicon substrate 10.
  • the element isolation structure 11 is formed on the surface layer of the silicon substrate 10 by, for example, the STI (Shallow Trench Isolation) method to determine the element active region.
  • an impurity of a predetermined conductivity type is ion-implanted into the element active region to form the well 12.
  • a gate insulating film 13 is formed in the element active region by thermal oxidation or the like, a polycrystalline silicon film and a film thickness such as a silicon nitride film are deposited on the gate insulating film 13 by a CVD method, and a silicon nitride film or a polycrystalline silicon film is deposited.
  • the gate electrode 14 is patterned on the gate insulating film 13 by processing the film and the gate insulating film 13 into an electrode shape by lithography and subsequent dry etching.
  • a cap film 15 made of a silicon nitride film is patterned on the gate electrode 14.
  • an impurity having a conductivity type opposite to that of the well 12 is ion-implanted into the element active region to form a so-called extension region 16.
  • a silicon oxide film is deposited on the entire surface by the CVD method, and this silicon oxide film is so-called etched back, thereby leaving the silicon oxide film only on the side surfaces of the gate electrode 14 and the cap film 15 to form the sidewall insulating film 17. Form.
  • the transistor element 20 is formed.
  • an interlayer insulating film 19 is formed. Specifically, for example, silicon oxide is deposited so as to cover the transistor element 20, and the interlayer insulating film 21 is formed. The surface of the interlayer insulating film 19 is polished by CMP.
  • a contact hole 19 a is formed in the interlayer insulating film 19.
  • a resist is applied on the interlayer insulating film 19, and the resist is processed by lithography.
  • a resist mask having an opening in a portion aligned with the source / drain region 18 is formed.
  • the interlayer insulating film 19 is dry-etched using the source / drain region 18 as an etching stopper until a part of the surface of the source / drain region 18 is exposed.
  • a contact hole 19 a is formed in the interlayer insulating film 21.
  • the contact hole 19a is formed with an opening diameter of about 10 nm to 30 nm, here about 10 nm.
  • the contact hole 19a is embedded with an integrated structure of horizontal graphene, vertical graphene, and CNT.
  • the formation process of the catalyst, the longitudinal graphene, the lateral graphene, and the CNT formation process are performed as an integrated vacuum process. -Situ.
  • the base 2 described in the first embodiment is formed at the bottom of the contact hole 19a.
  • the silicon substrate 1 is transferred to the deposition chamber 103 of the vacuum process system.
  • the first layer 2a and the second layer 2b are sequentially stacked on the bottom of the contact hole 19a by vacuum deposition, sputtering, ALD, or the like.
  • the first layer 2a deposits Ti, for example, in a film thickness of about 0.5 nm to 1.5 nm.
  • Co is deposited in a film shape with a thickness of about 2 nm to 5 nm.
  • an integrated structure of the lateral graphene 3, the longitudinal graphene 4, and the CNT 5 is continuously formed in the contact hole 19a under the growth conditions described in the first embodiment.
  • the contact hole 19a is embedded by an integral structure of the lateral graphene 3, the longitudinal graphene 4 grown at a high density, and the CNT 5 grown at a high density.
  • the vertical graphene 4 stands up in the vertical direction and is densely superimposed.
  • the lateral graphene 3 formed on the interlayer insulating film 19 may be processed into a wiring shape by lithography and dry etching and used as a wiring.
  • the lateral graphene 3 formed on the interlayer insulating film 19 can be removed by etching, and a wiring can be formed using a desired conductive material.
  • a MOS transistor having a highly reliable wiring structure in which a composite structure of graphene and CNT grows in a contact hole that is a fine region with a sufficiently high density is provided. Realize.
  • the integrated structure of the lateral graphene, the longitudinal graphene, and the CNT disclosed in the first embodiment can be applied not only to the LSI wiring structure but also to a heat dissipation mechanism.

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Abstract

L'invention concerne une structure graphène-CNT qui est constituée : d'un substrat (1) ; d'une base (2) qui est formée sur l'extrémité supérieure du substrat (1) ; de graphène vertical (4) qui croît à partir de la base (2), s'étend dans une direction verticale par rapport à la surface du substrat (1) et présente une structure densément imbriquée ; de graphène horizontal (3) qui est joint à l'extrémité supérieure du graphène vertical (4) et formé intégralement par le graphène vertical (4), et croît dans une direction horizontale par rapport à la surface du substrat (1) ; et de nanotubes de carbone qui croissent à partir de la base (2) et sont intégralement formés par l'extrémité inférieure du graphène vertical (4) à l'extrémité supérieure de celui-ci. En conséquence, une structure graphène-CNT hautement fiable est obtenue dans laquelle la structure composite du graphène et du CNT croît dans une région fine souhaitée présentant une densité suffisamment élevée.
PCT/JP2013/062501 2012-09-07 2013-04-26 Structure graphène-cnt et son procédé de fabrication WO2014038243A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2012197324A JP2014051413A (ja) 2012-09-07 2012-09-07 グラフェン−ｃｎｔ構造及びその製造方法
JP2012-197324 2012-09-07

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CN108933082A (zh) * 2017-05-25 2018-12-04 中芯国际集成电路制造(上海)有限公司 晶体管及其制作方法
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CN109722641A (zh) * 2017-10-30 2019-05-07 深圳先进技术研究院 金刚石/石墨烯复合导热膜及其制备方法和散热系统
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CN113213454A (zh) * 2021-04-21 2021-08-06 温州大学 以石墨烯为催化剂制备单壁碳纳米管的方法

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