WO2014038244A1 - Structure de graphène et son procédé de fabrication - Google Patents

Structure de graphène et son procédé de fabrication Download PDF

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WO2014038244A1
WO2014038244A1 PCT/JP2013/062507 JP2013062507W WO2014038244A1 WO 2014038244 A1 WO2014038244 A1 WO 2014038244A1 JP 2013062507 W JP2013062507 W JP 2013062507W WO 2014038244 A1 WO2014038244 A1 WO 2014038244A1
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layer
graphene
substrate
structure according
vertical
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PCT/JP2013/062507
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Japanese (ja)
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川端　章夫
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独立行政法人産業技術総合研究所
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • C—CHEMISTRY; METALLURGY
    • C01—INORGANIC CHEMISTRY
    • C01B—NON-METALLIC ELEMENTS; COMPOUNDS THEREOF; METALLOIDS OR COMPOUNDS THEREOF NOT COVERED BY SUBCLASS C01C
    • C01B32/00—Carbon; Compounds thereof
    • C01B32/15—Nano-sized carbon materials
    • C01B32/182—Graphene
    • C01B32/184—Preparation
    • C01B32/186—Preparation by chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53276—Conductive materials containing carbon, e.g. fullerenes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0676—Nanowires or nanotubes oriented perpendicular or at an angle to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1606—Graphene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a graphene structure and a manufacturing method thereof.
  • CNT Carbon-NanoTube
  • Graphene graphene
  • the present invention has been made in view of the above problems, and an object of the present invention is to provide a highly reliable graphene structure in which graphene grows in a desired fine region with a sufficiently high density and a method for manufacturing the same. To do.
  • the graphene structure of the present invention includes a base, a base formed above the base, and vertical graphene that grows from the base and stands upright in a direction perpendicular to the base surface and is densely superimposed.
  • the method for producing a graphene structure of the present invention includes a step of forming a base above a base, and a step of growing vertical graphene that stands upright in the vertical direction with respect to the surface of the base and is densely superimposed using the base Including.
  • FIG. 1A is a schematic cross-sectional view illustrating the method of manufacturing the graphene structure according to the first embodiment in the order of steps.
  • FIG. 1B is a schematic cross-sectional view illustrating the manufacturing method of the graphene structure according to the first embodiment in the order of steps, following FIG. 1A.
  • FIG. 1C is a schematic cross-sectional view subsequent to FIG. 1B, illustrating the graphene structure manufacturing method according to the first embodiment in the order of steps.
  • FIG. 2 is a schematic diagram showing a vacuum process system for performing a consistent vacuum process in the first embodiment.
  • FIG. 3A is a schematic cross-sectional view illustrating the method of manufacturing the MOS transistor according to the second embodiment in the order of steps.
  • FIG. 3B is a schematic cross-sectional view subsequent to FIG. 3A, illustrating the MOS transistor manufacturing method according to the second embodiment in the order of steps.
  • FIG. 3C is a schematic cross-sectional view subsequent to FIG. 3B, illustrating the method of manufacturing the MOS transistor according to the second embodiment in the order of steps.
  • FIG. 4 is an enlarged schematic cross-sectional view showing a state in the contact hole in the MOS transistor according to the second embodiment.
  • FIG. 5 is a schematic plan view showing an enlarged view of the vertical graphene in the contact hole in the MOS transistor according to the second embodiment.
  • FIGS. 1A to 1C are schematic cross-sectional views illustrating a method of manufacturing a graphene structure according to the first embodiment in the order of steps.
  • FIG. 2 is a schematic diagram showing a vacuum process system for performing a consistent vacuum process.
  • This vacuum process system includes a transfer chamber 101 provided in the center, a load lock chamber 102 for taking in and out a growth substrate, a deposition chamber 103 for forming a base, and a CVD chamber 104 for growing graphene. Yes.
  • the growth substrate is vacuum-transferred to each desired chamber by a robot arm provided in the transfer chamber 101.
  • each process can be performed in-situ consistently without exposing the growth substrate to the outside air.
  • a base 2 is formed on a silicon substrate 1.
  • a silicon substrate 1 is prepared as a growth substrate.
  • the silicon substrate 1 is transferred to the deposition chamber 103 of the vacuum process system.
  • the first layer 2a, the second layer 2b, and the third layer 2c are sequentially stacked on the silicon substrate 1 by vacuum deposition, sputtering, atomic layer deposition (ALD), or the like. To do.
  • the first layer 2a is at least one selected from titanium nitride (TiN), titanium oxide (TiO 2 ), tantalum nitride (TaN), and tantalum oxide (TaO 2 ). It is formed. For example, TaN is deposited to a thickness of about 15 nm to form the first layer 2a.
  • the first layer 2a has a function of preventing the constituent elements of the second layer 2b and the third layer 2c from diffusing to the silicon substrate 1 side.
  • the second layer 2b is at least one selected from titanium (Ti), titanium nitride (TiN), titanium oxide (TiO 2 ), niobium (Nb), and vanadium (V), and has a film shape. It is formed. For example, Ti is deposited to a thickness of about 0.5 nm to 1.5 nm to form the second layer 2b.
  • the second layer 2b has a close contact function with the first layer 2a of the third layer 2c.
  • the third layer 2c is at least one selected from cobalt (Co), nickel (Ni), and iron (Fe), and has a film shape immediately after formation.
  • Co is deposited to a thickness of about 2 nm to 5 nm to form the third layer 2c.
  • the third layer 2c has a direct catalytic function for graphene growth.
  • an integrated structure of horizontal graphene and vertical graphene is continuously formed.
  • the silicon substrate 1 is transferred to the CVD chamber 104.
  • a source gas is introduced into the CVD chamber 104.
  • acetylene (C 2 H 2 ) gas is used as the source gas.
  • the flow rate of C 2 H 2 gas is set to about 50 sccm.
  • the growth temperature (environment temperature in the CVD method 104) is set to a value within a low temperature range of 400 ° C. to 450 ° C., here about 450 ° C.
  • Graphene grows in the horizontal direction (lateral direction) with respect to the surface of the silicon substrate 1 using the Co film of the third layer 2c as a catalyst.
  • This graphene is referred to as lateral graphene 3.
  • the lateral graphene 3 is stacked in one or more layers. The situation at this time is shown in FIG. 1B.
  • the Co film of the third layer 2c aggregates to become particulate or island-shaped Co.
  • the Co of the third layer 2c is in the form of particles or islands
  • graphene grows in a direction perpendicular to the surface of the silicon substrate 1 (longitudinal direction). This graphene is called longitudinal graphene 4.
  • the vertical graphene 4 is integrally formed with the horizontal graphene 3 connected at the top end, and is stacked in a plurality of layers standing upright in the vertical direction and densely superimposed. The state at this time is shown in FIG. 1C.
  • the integrated structure of the lateral graphene 3 and the longitudinal graphene 4 can be formed in one continuous process, and the longitudinal graphene 4 stacked at an extremely high density. Can be obtained.
  • FIG. 3A to FIG. 3C and FIG. 4 are schematic cross-sectional views showing the MOS transistor manufacturing method according to the second embodiment in the order of steps.
  • a transistor element 20 is formed as a functional element on a silicon substrate 10.
  • the element isolation structure 11 is formed on the surface layer of the silicon substrate 10 by, for example, the STI (Shallow Trench Isolation) method to determine the element active region.
  • an impurity of a predetermined conductivity type is ion-implanted into the element active region to form the well 12.
  • a gate insulating film 13 is formed in the element active region by thermal oxidation or the like, a polycrystalline silicon film and a film thickness such as a silicon nitride film are deposited on the gate insulating film 13 by a CVD method, and a silicon nitride film or a polycrystalline silicon film is deposited.
  • the gate electrode 14 is patterned on the gate insulating film 13 by processing the film and the gate insulating film 13 into an electrode shape by lithography and subsequent dry etching.
  • a cap film 15 made of a silicon nitride film is patterned on the gate electrode 14.
  • an impurity having a conductivity type opposite to that of the well 12 is ion-implanted into the element active region to form a so-called extension region 16.
  • a silicon oxide film is deposited on the entire surface by the CVD method, and this silicon oxide film is so-called etched back, thereby leaving the silicon oxide film only on the side surfaces of the gate electrode 14 and the cap film 15 to form the sidewall insulating film 17. Form.
  • the transistor element 20 is formed.
  • an interlayer insulating film 19 is formed. Specifically, for example, silicon oxide is deposited so as to cover the transistor element 20, and the interlayer insulating film 21 is formed. The surface of the interlayer insulating film 19 is polished by CMP.
  • a contact hole 19 a is formed in the interlayer insulating film 19.
  • a resist is applied on the interlayer insulating film 19, and the resist is processed by lithography.
  • a resist mask having an opening in a portion aligned with the source / drain region 18 is formed.
  • the interlayer insulating film 19 is dry-etched using the source / drain region 18 as an etching stopper until a part of the surface of the source / drain region 18 is exposed.
  • a contact hole 19 a is formed in the interlayer insulating film 21.
  • the contact hole 19a is formed with an opening diameter of about 10 nm to 30 nm, here about 10 nm.
  • the contact hole 19a is embedded with an integrated structure of horizontal graphene and vertical graphene.
  • the catalyst formation process, the vertical graphene formation process, and the horizontal graphene formation process are performed in-situ as an integrated vacuum process. To do.
  • the base 2 described in the first embodiment is formed at the bottom of the contact hole 19a.
  • the silicon substrate 1 is transferred to the deposition chamber 103 of the vacuum process system.
  • the first layer 2a, the second layer 2b, and the third layer 2c are sequentially stacked on the bottom of the contact hole 19a by vacuum deposition, sputtering, ALD, or the like.
  • the first layer 2a is formed by depositing, for example, TaN in a film shape with a thickness of about 15 nm.
  • the second layer 2b deposits Ti, for example, in a film shape with a thickness of about 0.5 nm to 1.5 nm.
  • the third layer 2c deposits, for example, Co in a film shape with a thickness of about 2 nm to 5 nm.
  • an integrated structure of the lateral graphene 3 and the longitudinal graphene 4 is continuously formed in the contact hole 19a under the growth conditions described in the first embodiment.
  • the contact hole 19 a is embedded by an integral structure of the lateral graphene 3 and the longitudinal graphene 4 grown at a high density.
  • the vertical graphene 4 stands up in the vertical direction and is densely superimposed.
  • the lateral graphene 3 formed on the interlayer insulating film 19 may be processed into a wiring shape by lithography and dry etching and used as a wiring.
  • the lateral graphene 3 formed on the interlayer insulating film 19 can be removed by etching, and a wiring can be formed using a desired conductive material.
  • a MOS transistor having a highly reliable wiring structure in which graphene is grown in a contact hole that is a fine region with a sufficiently high density is realized.
  • the integrated structure of the lateral graphene and the longitudinal graphene disclosed in the first embodiment can be applied not only to the LSI wiring structure but also to a heat dissipation mechanism.

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

L'invention concerne une structure de graphène qui est constituée : d'un substrat (1) ; d'une base (2) qui est formée sur l'extrémité supérieure du substrat (1) ; de graphène vertical (4) qui croît à partir de la base (2), s'étend dans une direction verticale par rapport à la surface du substrat (1) et présente une structure densément imbriquée ; et de graphène horizontal (3) qui est joint à l'extrémité supérieure du graphène vertical (4) et formé intégralement par le graphène vertical (4), et croît dans une direction horizontale par rapport à la surface du substrat (1). En conséquence, une structure graphène hautement fiable est atteinte dans laquelle du graphène croît dans une région fine désirée présentant une densité suffisamment élevée.
PCT/JP2013/062507 2012-09-07 2013-04-26 Structure de graphène et son procédé de fabrication WO2014038244A1 (fr)

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JP2012197270A JP2014051412A (ja) 2012-09-07 2012-09-07 グラフェン構造及びその製造方法
JP2012-197270 2012-09-07

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007049103A (ja) * 2005-08-05 2007-02-22 Zycube:Kk 半導体チップおよびその製造方法、ならびに半導体装置
JP2009253052A (ja) * 2008-04-07 2009-10-29 Toshiba Corp 半導体装置及びその製造方法
JP2010062333A (ja) * 2008-09-03 2010-03-18 Fujitsu Ltd 集積回路装置及びその製造方法
JP2012064784A (ja) * 2010-09-16 2012-03-29 Toshiba Corp 半導体装置及び半導体装置の製造方法
JP2012166989A (ja) * 2011-02-15 2012-09-06 Vision Development Co Ltd グラフェン積層ナノカーボン、その製造方法及びグラフェン積層ナノカーボン製造用触媒

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007049103A (ja) * 2005-08-05 2007-02-22 Zycube:Kk 半導体チップおよびその製造方法、ならびに半導体装置
JP2009253052A (ja) * 2008-04-07 2009-10-29 Toshiba Corp 半導体装置及びその製造方法
JP2010062333A (ja) * 2008-09-03 2010-03-18 Fujitsu Ltd 集積回路装置及びその製造方法
JP2012064784A (ja) * 2010-09-16 2012-03-29 Toshiba Corp 半導体装置及び半導体装置の製造方法
JP2012166989A (ja) * 2011-02-15 2012-09-06 Vision Development Co Ltd グラフェン積層ナノカーボン、その製造方法及びグラフェン積層ナノカーボン製造用触媒

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