WO2014038244A1 - Graphene structure and method for producing same - Google Patents

Graphene structure and method for producing same Download PDF

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WO2014038244A1
WO2014038244A1 PCT/JP2013/062507 JP2013062507W WO2014038244A1 WO 2014038244 A1 WO2014038244 A1 WO 2014038244A1 JP 2013062507 W JP2013062507 W JP 2013062507W WO 2014038244 A1 WO2014038244 A1 WO 2014038244A1
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layer
graphene
substrate
structure according
vertical
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川端　章夫
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独立行政法人産業技術総合研究所
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
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    • C01B32/00—Carbon; Compounds thereof
    • C01B32/15—Nano-sized carbon materials
    • C01B32/182—Graphene
    • C01B32/184—Preparation
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    • H01L29/0669—Nanowires or nanotubes
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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Definitions

  • the present invention relates to a graphene structure and a manufacturing method thereof.
  • CNT Carbon-NanoTube
  • Graphene graphene
  • the present invention has been made in view of the above problems, and an object of the present invention is to provide a highly reliable graphene structure in which graphene grows in a desired fine region with a sufficiently high density and a method for manufacturing the same. To do.
  • the graphene structure of the present invention includes a base, a base formed above the base, and vertical graphene that grows from the base and stands upright in a direction perpendicular to the base surface and is densely superimposed.
  • the method for producing a graphene structure of the present invention includes a step of forming a base above a base, and a step of growing vertical graphene that stands upright in the vertical direction with respect to the surface of the base and is densely superimposed using the base Including.
  • FIG. 1A is a schematic cross-sectional view illustrating the method of manufacturing the graphene structure according to the first embodiment in the order of steps.
  • FIG. 1B is a schematic cross-sectional view illustrating the manufacturing method of the graphene structure according to the first embodiment in the order of steps, following FIG. 1A.
  • FIG. 1C is a schematic cross-sectional view subsequent to FIG. 1B, illustrating the graphene structure manufacturing method according to the first embodiment in the order of steps.
  • FIG. 2 is a schematic diagram showing a vacuum process system for performing a consistent vacuum process in the first embodiment.
  • FIG. 3A is a schematic cross-sectional view illustrating the method of manufacturing the MOS transistor according to the second embodiment in the order of steps.
  • FIG. 3B is a schematic cross-sectional view subsequent to FIG. 3A, illustrating the MOS transistor manufacturing method according to the second embodiment in the order of steps.
  • FIG. 3C is a schematic cross-sectional view subsequent to FIG. 3B, illustrating the method of manufacturing the MOS transistor according to the second embodiment in the order of steps.
  • FIG. 4 is an enlarged schematic cross-sectional view showing a state in the contact hole in the MOS transistor according to the second embodiment.
  • FIG. 5 is a schematic plan view showing an enlarged view of the vertical graphene in the contact hole in the MOS transistor according to the second embodiment.
  • FIGS. 1A to 1C are schematic cross-sectional views illustrating a method of manufacturing a graphene structure according to the first embodiment in the order of steps.
  • FIG. 2 is a schematic diagram showing a vacuum process system for performing a consistent vacuum process.
  • This vacuum process system includes a transfer chamber 101 provided in the center, a load lock chamber 102 for taking in and out a growth substrate, a deposition chamber 103 for forming a base, and a CVD chamber 104 for growing graphene. Yes.
  • the growth substrate is vacuum-transferred to each desired chamber by a robot arm provided in the transfer chamber 101.
  • each process can be performed in-situ consistently without exposing the growth substrate to the outside air.
  • a base 2 is formed on a silicon substrate 1.
  • a silicon substrate 1 is prepared as a growth substrate.
  • the silicon substrate 1 is transferred to the deposition chamber 103 of the vacuum process system.
  • the first layer 2a, the second layer 2b, and the third layer 2c are sequentially stacked on the silicon substrate 1 by vacuum deposition, sputtering, atomic layer deposition (ALD), or the like. To do.
  • the first layer 2a is at least one selected from titanium nitride (TiN), titanium oxide (TiO 2 ), tantalum nitride (TaN), and tantalum oxide (TaO 2 ). It is formed. For example, TaN is deposited to a thickness of about 15 nm to form the first layer 2a.
  • the first layer 2a has a function of preventing the constituent elements of the second layer 2b and the third layer 2c from diffusing to the silicon substrate 1 side.
  • the second layer 2b is at least one selected from titanium (Ti), titanium nitride (TiN), titanium oxide (TiO 2 ), niobium (Nb), and vanadium (V), and has a film shape. It is formed. For example, Ti is deposited to a thickness of about 0.5 nm to 1.5 nm to form the second layer 2b.
  • the second layer 2b has a close contact function with the first layer 2a of the third layer 2c.
  • the third layer 2c is at least one selected from cobalt (Co), nickel (Ni), and iron (Fe), and has a film shape immediately after formation.
  • Co is deposited to a thickness of about 2 nm to 5 nm to form the third layer 2c.
  • the third layer 2c has a direct catalytic function for graphene growth.
  • an integrated structure of horizontal graphene and vertical graphene is continuously formed.
  • the silicon substrate 1 is transferred to the CVD chamber 104.
  • a source gas is introduced into the CVD chamber 104.
  • acetylene (C 2 H 2 ) gas is used as the source gas.
  • the flow rate of C 2 H 2 gas is set to about 50 sccm.
  • the growth temperature (environment temperature in the CVD method 104) is set to a value within a low temperature range of 400 ° C. to 450 ° C., here about 450 ° C.
  • Graphene grows in the horizontal direction (lateral direction) with respect to the surface of the silicon substrate 1 using the Co film of the third layer 2c as a catalyst.
  • This graphene is referred to as lateral graphene 3.
  • the lateral graphene 3 is stacked in one or more layers. The situation at this time is shown in FIG. 1B.
  • the Co film of the third layer 2c aggregates to become particulate or island-shaped Co.
  • the Co of the third layer 2c is in the form of particles or islands
  • graphene grows in a direction perpendicular to the surface of the silicon substrate 1 (longitudinal direction). This graphene is called longitudinal graphene 4.
  • the vertical graphene 4 is integrally formed with the horizontal graphene 3 connected at the top end, and is stacked in a plurality of layers standing upright in the vertical direction and densely superimposed. The state at this time is shown in FIG. 1C.
  • the integrated structure of the lateral graphene 3 and the longitudinal graphene 4 can be formed in one continuous process, and the longitudinal graphene 4 stacked at an extremely high density. Can be obtained.
  • FIG. 3A to FIG. 3C and FIG. 4 are schematic cross-sectional views showing the MOS transistor manufacturing method according to the second embodiment in the order of steps.
  • a transistor element 20 is formed as a functional element on a silicon substrate 10.
  • the element isolation structure 11 is formed on the surface layer of the silicon substrate 10 by, for example, the STI (Shallow Trench Isolation) method to determine the element active region.
  • an impurity of a predetermined conductivity type is ion-implanted into the element active region to form the well 12.
  • a gate insulating film 13 is formed in the element active region by thermal oxidation or the like, a polycrystalline silicon film and a film thickness such as a silicon nitride film are deposited on the gate insulating film 13 by a CVD method, and a silicon nitride film or a polycrystalline silicon film is deposited.
  • the gate electrode 14 is patterned on the gate insulating film 13 by processing the film and the gate insulating film 13 into an electrode shape by lithography and subsequent dry etching.
  • a cap film 15 made of a silicon nitride film is patterned on the gate electrode 14.
  • an impurity having a conductivity type opposite to that of the well 12 is ion-implanted into the element active region to form a so-called extension region 16.
  • a silicon oxide film is deposited on the entire surface by the CVD method, and this silicon oxide film is so-called etched back, thereby leaving the silicon oxide film only on the side surfaces of the gate electrode 14 and the cap film 15 to form the sidewall insulating film 17. Form.
  • the transistor element 20 is formed.
  • an interlayer insulating film 19 is formed. Specifically, for example, silicon oxide is deposited so as to cover the transistor element 20, and the interlayer insulating film 21 is formed. The surface of the interlayer insulating film 19 is polished by CMP.
  • a contact hole 19 a is formed in the interlayer insulating film 19.
  • a resist is applied on the interlayer insulating film 19, and the resist is processed by lithography.
  • a resist mask having an opening in a portion aligned with the source / drain region 18 is formed.
  • the interlayer insulating film 19 is dry-etched using the source / drain region 18 as an etching stopper until a part of the surface of the source / drain region 18 is exposed.
  • a contact hole 19 a is formed in the interlayer insulating film 21.
  • the contact hole 19a is formed with an opening diameter of about 10 nm to 30 nm, here about 10 nm.
  • the contact hole 19a is embedded with an integrated structure of horizontal graphene and vertical graphene.
  • the catalyst formation process, the vertical graphene formation process, and the horizontal graphene formation process are performed in-situ as an integrated vacuum process. To do.
  • the base 2 described in the first embodiment is formed at the bottom of the contact hole 19a.
  • the silicon substrate 1 is transferred to the deposition chamber 103 of the vacuum process system.
  • the first layer 2a, the second layer 2b, and the third layer 2c are sequentially stacked on the bottom of the contact hole 19a by vacuum deposition, sputtering, ALD, or the like.
  • the first layer 2a is formed by depositing, for example, TaN in a film shape with a thickness of about 15 nm.
  • the second layer 2b deposits Ti, for example, in a film shape with a thickness of about 0.5 nm to 1.5 nm.
  • the third layer 2c deposits, for example, Co in a film shape with a thickness of about 2 nm to 5 nm.
  • an integrated structure of the lateral graphene 3 and the longitudinal graphene 4 is continuously formed in the contact hole 19a under the growth conditions described in the first embodiment.
  • the contact hole 19 a is embedded by an integral structure of the lateral graphene 3 and the longitudinal graphene 4 grown at a high density.
  • the vertical graphene 4 stands up in the vertical direction and is densely superimposed.
  • the lateral graphene 3 formed on the interlayer insulating film 19 may be processed into a wiring shape by lithography and dry etching and used as a wiring.
  • the lateral graphene 3 formed on the interlayer insulating film 19 can be removed by etching, and a wiring can be formed using a desired conductive material.
  • a MOS transistor having a highly reliable wiring structure in which graphene is grown in a contact hole that is a fine region with a sufficiently high density is realized.
  • the integrated structure of the lateral graphene and the longitudinal graphene disclosed in the first embodiment can be applied not only to the LSI wiring structure but also to a heat dissipation mechanism.

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Abstract

A graphene structure is constituted comprising: a substrate (1); a base (2) which is formed on top of the substrate (1); vertical graphene (4) which grows from the base (2), stands in a vertical direction relative to the surface of the substrate (1) and has a densely layered structure; and horizontal graphene (3) which is joined to the upper end of the vertical graphene (4) and integrally formed with the vertical graphene (4), and grows in a horizontal direction relative to the surface of the substrate (1). Accordingly, a highly reliable graphene structure is achieved in which graphene grows in a desired fine region with a sufficiently high density.

Description

グラフェン構造及びその製造方法Graphene structure and manufacturing method thereof
　本発明は、グラフェン構造及びその製造方法に関するものである。 The present invention relates to a graphene structure and a manufacturing method thereof.
　近年、半導体デバイスにおける配線の微細化に伴い、従来の銅配線において信頼性の低下が懸案となっている。そこで、銅に置き換わる材料として、炭素原子からなる材料であるカーボンナノチューブ（ＣＮＴ：Carbon NanoTube）やグラフェン（Graphene）の利用が提案されている。グラフェンは、層状の結晶であるグラファイト（Graphite）の１層であって、炭素（Ｃ）原子が六角形に結合した理想的な２次元結晶であり、移動度が観測されており、バリスティック伝導が発現する。これらの材料は、ナノカーボン材料として注目されている。配線の微細化が１０ｎｍ程度まで進行すると、銅からナノカーボン材料に置き換えることが予測される。ＣＮＴは、配線と接続されるビアと呼ばれる基板表面に垂直な方向の配線（縦配線）で研究が進んでいる。グラフェンは、透明電極等へ適用する研究が盛んである。 In recent years, with the miniaturization of wiring in semiconductor devices, there has been a concern about a decrease in reliability in conventional copper wiring. Therefore, the use of carbon nanotubes (CNT: Carbon-NanoTube) and graphene (Graphene), which are materials made of carbon atoms, has been proposed as a material to replace copper. Graphene is a layer of graphite, a layered crystal, and is an ideal two-dimensional crystal with carbon (C) atoms bonded to a hexagon. Mobility has been observed and ballistic conduction has been observed. Is expressed. These materials are attracting attention as nanocarbon materials. When the miniaturization of wiring proceeds to about 10 nm, it is predicted that copper will be replaced with a nanocarbon material. Research on CNT is progressing with wiring (vertical wiring) in a direction perpendicular to the substrate surface called a via connected to the wiring. Graphene is actively researched to apply to transparent electrodes.
　従来の技術では、ＣＮＴを用いて縦配線を形成することは可能である。ところがこの場合、ビア孔内におけるＣＮＴの密度が不十分であり、抵抗値が高く電流密度が低いという問題がある。 In the conventional technology, it is possible to form vertical wiring using CNT. However, in this case, there is a problem that the density of CNTs in the via hole is insufficient, the resistance value is high, and the current density is low.
　本発明は、上記の課題に鑑みてなされるものであり、グラフェンが十分に高い密度で所期の微細領域に成長してなる信頼性の高いグラフェン構造及びその製造方法を提供することを目的とする。 The present invention has been made in view of the above problems, and an object of the present invention is to provide a highly reliable graphene structure in which graphene grows in a desired fine region with a sufficiently high density and a method for manufacturing the same. To do.
　本発明のグラフェン構造は、基体と、前記基体の上方に形成された下地と、前記下地から成長した、前記基体表面に対して垂直方向に起立して稠密に重畳された垂直グラフェンとを含む。 The graphene structure of the present invention includes a base, a base formed above the base, and vertical graphene that grows from the base and stands upright in a direction perpendicular to the base surface and is densely superimposed.
　本発明のグラフェン構造の製造方法は、基体の上方に下地を形成する工程と、前記下地を用いて、前記基体表面に対して垂直方向に起立して稠密に重畳された垂直グラフェンを成長する工程とを含む。 The method for producing a graphene structure of the present invention includes a step of forming a base above a base, and a step of growing vertical graphene that stands upright in the vertical direction with respect to the surface of the base and is densely superimposed using the base Including.
　本発明によれば、グラフェンが十分に高い密度で所期の微細領域に成長してなる信頼性の高いグラフェン構造が実現する。 According to the present invention, it is possible to realize a highly reliable graphene structure in which graphene is grown in a desired fine region with a sufficiently high density.
図１Ａは、第１の実施形態によるグラフェン構造の製造方法を工程順に示す概略断面図である。FIG. 1A is a schematic cross-sectional view illustrating the method of manufacturing the graphene structure according to the first embodiment in the order of steps. 図１Ｂは、図１Ａに引き続き、第１の実施形態によるグラフェン構造の製造方法を工程順に示す概略断面図である。FIG. 1B is a schematic cross-sectional view illustrating the manufacturing method of the graphene structure according to the first embodiment in the order of steps, following FIG. 1A. 図１Ｃは、図１Ｂに引き続き、第１の実施形態によるグラフェン構造の製造方法を工程順に示す概略断面図である。FIG. 1C is a schematic cross-sectional view subsequent to FIG. 1B, illustrating the graphene structure manufacturing method according to the first embodiment in the order of steps. 図２は、第１の実施形態において、真空一貫プロセスを行うための真空プロセスシステムを示す模式図である。FIG. 2 is a schematic diagram showing a vacuum process system for performing a consistent vacuum process in the first embodiment. 図３Ａは、第２の実施形態によるＭＯＳトランジスタの製造方法を工程順に示す概略断面図である。FIG. 3A is a schematic cross-sectional view illustrating the method of manufacturing the MOS transistor according to the second embodiment in the order of steps. 図３Ｂは、図３Ａに引き続き、第２の実施形態によるＭＯＳトランジスタの製造方法を工程順に示す概略断面図である。FIG. 3B is a schematic cross-sectional view subsequent to FIG. 3A, illustrating the MOS transistor manufacturing method according to the second embodiment in the order of steps. 図３Ｃは、図３Ｂに引き続き、第２の実施形態によるＭＯＳトランジスタの製造方法を工程順に示す概略断面図である。FIG. 3C is a schematic cross-sectional view subsequent to FIG. 3B, illustrating the method of manufacturing the MOS transistor according to the second embodiment in the order of steps. 図４は、第２の実施形態によるＭＯＳトランジスタのうち、コンタクト孔内の様子を拡大して示す概略断面図である。FIG. 4 is an enlarged schematic cross-sectional view showing a state in the contact hole in the MOS transistor according to the second embodiment. 図５は、第２の実施形態によるＭＯＳトランジスタのうち、コンタクト孔内の縦方向グラフェンの様子を拡大して示す概略平面図である。FIG. 5 is a schematic plan view showing an enlarged view of the vertical graphene in the contact hole in the MOS transistor according to the second embodiment.
　　以下、本発明を適用した具体的な諸実施形態について、図面を参照しながら詳細に説明する。 Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings.
　（第１の実施形態）
　本実施形態では、グラフェン構造について、その製造方法と共に開示する。図１Ａ～図１Ｃは、第１の実施形態によるグラフェン構造の製造方法を工程順に示す概略断面図である。 (First embodiment)
In this embodiment, a graphene structure is disclosed together with its manufacturing method. 1A to 1C are schematic cross-sectional views illustrating a method of manufacturing a graphene structure according to the first embodiment in the order of steps.
　本実施形態では、後述する触媒の形成工程、縦方向グラフェン及び横方向グラフェンの形成工程（図１Ａ～図１Ｃの全工程）を、真空一貫プロセスとして、in-situで行う。図２は、真空一貫プロセスを行うための真空プロセスシステムを示す模式図である。この真空プロセスシステムは、中央部に設けられた搬送室１０１と、成長用基板の出し入れを行うロードロック室１０２と、下地形成を行う堆積室１０３と、グラフェン成長を行うＣＶＤ室１０４とを備えている。成長用基板は、搬送室１０１に設けられたロボットアームにより、所期の各室に真空搬送される。真空プロセスシステムでは、成長用基板を外気に晒すことなく、各工程を一貫してin-situで行うことができる。 In this embodiment, the catalyst formation step, the vertical graphene formation step, and the horizontal graphene formation step (all steps in FIGS. 1A to 1C), which will be described later, are performed in-situ as an integrated vacuum process. FIG. 2 is a schematic diagram showing a vacuum process system for performing a consistent vacuum process. This vacuum process system includes a transfer chamber 101 provided in the center, a load lock chamber 102 for taking in and out a growth substrate, a deposition chamber 103 for forming a base, and a CVD chamber 104 for growing graphene. Yes. The growth substrate is vacuum-transferred to each desired chamber by a robot arm provided in the transfer chamber 101. In the vacuum process system, each process can be performed in-situ consistently without exposing the growth substrate to the outside air.
　先ず、図１Ａに示すように、シリコン基板１上に下地２を形成する。
　詳細には、成長用基板として、例えばシリコン基板１を用意する。このシリコン基板１を真空プロセスシステムの堆積室１０３に搬送する。堆積室１０３において、真空蒸着法又はスパッタ法、原子層堆積法（Atomic Layer Deposition：ＡＬＤ法）等により、シリコン基板１上に第１層２ａ、第２層２ｂ、及び第３層２ｃを順次積層する。 First, as shown in FIG. 1A, a base 2 is formed on a silicon substrate 1.
Specifically, for example, a silicon substrate 1 is prepared as a growth substrate. The silicon substrate 1 is transferred to the deposition chamber 103 of the vacuum process system. In the deposition chamber 103, the first layer 2a, the second layer 2b, and the third layer 2c are sequentially stacked on the silicon substrate 1 by vacuum deposition, sputtering, atomic layer deposition (ALD), or the like. To do.
　第１層２ａは、チタン窒化物（ＴｉＮ）、チタン酸化物（ＴｉＯ２）、タンタル窒化物（ＴａＮ）、タンタル酸化物（ＴａＯ２）のうちから選ばれた少なくとも１種であり、膜状に形成される。例えばＴａＮを１５ｎｍ程度の厚みに堆積し、第１層２ａが形成される。第１層２ａは、第２層２ｂ及び第３層２ｃの構成元素のシリコン基板１側への拡散を防止する機能を有している。 The first layer 2a is at least one selected from titanium nitride (TiN), titanium oxide (TiO 2 ), tantalum nitride (TaN), and tantalum oxide (TaO 2 ). It is formed. For example, TaN is deposited to a thickness of about 15 nm to form the first layer 2a. The first layer 2a has a function of preventing the constituent elements of the second layer 2b and the third layer 2c from diffusing to the silicon substrate 1 side.
　第２層２ｂは、チタン（Ｔｉ）、チタン窒化物（ＴｉＮ）、チタン酸化物（ＴｉＯ２）、ニオブ（Ｎｂ）、バナジウム（Ｖ）のうちから選ばれた少なくとも１種であり、膜状に形成される。例えばＴｉを０．５ｎｍ～１．５ｎｍ程度の厚みに堆積し、第２層２ｂが形成される。第２層２ｂは、第３層２ｃの第１層２ａとの密着機能を有している。 The second layer 2b is at least one selected from titanium (Ti), titanium nitride (TiN), titanium oxide (TiO 2 ), niobium (Nb), and vanadium (V), and has a film shape. It is formed. For example, Ti is deposited to a thickness of about 0.5 nm to 1.5 nm to form the second layer 2b. The second layer 2b has a close contact function with the first layer 2a of the third layer 2c.
　第３層２ｃは、コバルト（Ｃｏ）、ニッケル（Ｎｉ）、鉄（Ｆｅ）のうちから選ばれた少なくとも１種であり、形成直後は膜状となる。例えばＣｏを２ｎｍ～５ｎｍ程度の厚みに堆積し、第３層２ｃが形成される。第３層２ｃは、グラフェン成長の直接的な触媒機能を有する。 The third layer 2c is at least one selected from cobalt (Co), nickel (Ni), and iron (Fe), and has a film shape immediately after formation. For example, Co is deposited to a thickness of about 2 nm to 5 nm to form the third layer 2c. The third layer 2c has a direct catalytic function for graphene growth.
　続いて、横方向グラフェンと縦方向グラフェンとの一体構造を連続的に形成する。
　詳細には、シリコン基板１をＣＶＤ室１０４に搬送する。ＣＶＤ室１０４内に原料ガスを導入する。原料ガスとしては、アセチレン（Ｃ２Ｈ２）ガスを用いる。Ｃ２Ｈ２ガスの流量を５０ｓｃｃｍ程度とする。成長温度（ＣＶＤ法１０４内の環境温度）は、４００℃～４５０℃の低温範囲内の値、ここでは４５０℃程度に設定する。 Subsequently, an integrated structure of horizontal graphene and vertical graphene is continuously formed.
Specifically, the silicon substrate 1 is transferred to the CVD chamber 104. A source gas is introduced into the CVD chamber 104. As the source gas, acetylene (C 2 H 2 ) gas is used. The flow rate of C 2 H 2 gas is set to about 50 sccm. The growth temperature (environment temperature in the CVD method 104) is set to a value within a low temperature range of 400 ° C. to 450 ° C., here about 450 ° C.
　第３層２ｃのＣｏ膜を触媒として、シリコン基板１の表面に対して水平方向（横方向）にグラフェンが成長する。このグラフェンを横方向グラフェン３と呼ぶ。横方向グラフェン３は、１層乃至複数層に積層される。このときの様子を図１Ｂに示す。 Graphene grows in the horizontal direction (lateral direction) with respect to the surface of the silicon substrate 1 using the Co film of the third layer 2c as a catalyst. This graphene is referred to as lateral graphene 3. The lateral graphene 3 is stacked in one or more layers. The situation at this time is shown in FIG. 1B.
　横方向グラフェン３の成長が進むと、第３層２ｃのＣｏ膜が凝集してゆき、粒子状又は島状のＣｏとなる。この場合、第３層２ｃのＣｏが粒子状又は島状であるため、シリコン基板１の表面に対して垂直方向（縦方向）にグラフェンが成長する。このグラフェンを縦方向グラフェン４と呼ぶ。縦方向グラフェン４は、横方向グラフェン３と上部先端で接続して一体形成され、垂直方向に起立して稠密に重畳された複数層に積層される。このときの様子を図１Ｃに示す。 As the growth of the lateral graphene 3 progresses, the Co film of the third layer 2c aggregates to become particulate or island-shaped Co. In this case, since the Co of the third layer 2c is in the form of particles or islands, graphene grows in a direction perpendicular to the surface of the silicon substrate 1 (longitudinal direction). This graphene is called longitudinal graphene 4. The vertical graphene 4 is integrally formed with the horizontal graphene 3 connected at the top end, and is stacked in a plurality of layers standing upright in the vertical direction and densely superimposed. The state at this time is shown in FIG. 1C.
　以上のようにして、横方向グラフェン３と縦方向グラフェン４との一体構造が形成される。当該一体構造では、横方向グラフェン３下で複数枚の縦方向グラフェン４が極めて高密度で形成されることが確認された。 As described above, an integral structure of the lateral graphene 3 and the longitudinal graphene 4 is formed. In the integrated structure, it was confirmed that a plurality of longitudinal graphenes 4 were formed at a very high density under the lateral graphene 3.
　以上説明したように、本実施形態によれば、横方向グラフェン３と縦方向グラフェン４との一体構造を、連続した一工程で形成することができ、極めて高密度で積層された縦方向グラフェン４を得ることができる。 As described above, according to the present embodiment, the integrated structure of the lateral graphene 3 and the longitudinal graphene 4 can be formed in one continuous process, and the longitudinal graphene 4 stacked at an extremely high density. Can be obtained.
　（第２の実施形態）
　本実施形態では、第１の実施形態で開示した横方向グラフェンと縦方向グラフェンとの一体構造を、ＭＯＳトランジスタの配線構造に適用する場合を例示する。
　図３Ａ～図３Ｃ及び図４は、第２の実施形態によるＭＯＳトランジスタの製造方法を工程順に示す概略断面図である。 (Second Embodiment)
In this embodiment, the case where the integrated structure of the lateral graphene and the vertical graphene disclosed in the first embodiment is applied to the wiring structure of the MOS transistor is illustrated.
FIG. 3A to FIG. 3C and FIG. 4 are schematic cross-sectional views showing the MOS transistor manufacturing method according to the second embodiment in the order of steps.
　先ず、図３Ａに示すように、シリコン基板１０上に機能素子としてトランジスタ素子２０を形成する。
　詳細には、シリコン基板１０の表層に例えばＳＴＩ（Shallow Trench Isolation）法により素子分離構造１１を形成し、素子活性領域を確定する。
　次に、素子活性領域に所定の導電型の不純物をイオン注入し、ウェル１２を形成する。 First, as shown in FIG. 3A, a transistor element 20 is formed as a functional element on a silicon substrate 10.
Specifically, the element isolation structure 11 is formed on the surface layer of the silicon substrate 10 by, for example, the STI (Shallow Trench Isolation) method to determine the element active region.
Next, an impurity of a predetermined conductivity type is ion-implanted into the element active region to form the well 12.
　次に、素子活性領域に熱酸化等によりゲート絶縁膜１３を形成し、ゲート絶縁膜１３上にＣＶＤ法により多結晶シリコン膜及び膜厚例えばシリコン窒化膜を堆積し、シリコン窒化膜、多結晶シリコン膜、及びゲート絶縁膜１３をリソグラフィー及びそれに続くドライエッチングにより電極形状に加工することにより、ゲート絶縁膜１３上にゲート電極１４をパターン形成する。このとき同時に、ゲート電極１４上にはシリコン窒化膜からなるキャップ膜１５がパターン形成される。 Next, a gate insulating film 13 is formed in the element active region by thermal oxidation or the like, a polycrystalline silicon film and a film thickness such as a silicon nitride film are deposited on the gate insulating film 13 by a CVD method, and a silicon nitride film or a polycrystalline silicon film is deposited. The gate electrode 14 is patterned on the gate insulating film 13 by processing the film and the gate insulating film 13 into an electrode shape by lithography and subsequent dry etching. At the same time, a cap film 15 made of a silicon nitride film is patterned on the gate electrode 14.
　次に、キャップ膜１５をマスクとして素子活性領域にウェル１２と逆導電型の不純物をイオン注入し、いわゆるエクステンション領域１６を形成する。 Next, using the cap film 15 as a mask, an impurity having a conductivity type opposite to that of the well 12 is ion-implanted into the element active region to form a so-called extension region 16.
　次に、全面に例えばシリコン酸化膜をＣＶＤ法により堆積し、このシリコン酸化膜をいわゆるエッチバックすることにより、ゲート電極１４及びキャップ膜１５の側面のみにシリコン酸化膜を残してサイドウォール絶縁膜１７を形成する。 Next, for example, a silicon oxide film is deposited on the entire surface by the CVD method, and this silicon oxide film is so-called etched back, thereby leaving the silicon oxide film only on the side surfaces of the gate electrode 14 and the cap film 15 to form the sidewall insulating film 17. Form.
　次に、キャップ膜１５及びサイドウォール絶縁膜１７をマスクとして素子活性領域にエクステンション領域１６と同じ導電型の不純物をイオン注入し、エクステンション領域１６と重畳されるソース／ドレイン領域１８を形成する。以上により、トランジスタ素子２０が形成される。 Next, using the cap film 15 and the sidewall insulating film 17 as a mask, an impurity having the same conductivity type as that of the extension region 16 is ion-implanted into the element active region to form a source / drain region 18 overlapping the extension region 16. Thus, the transistor element 20 is formed.
　続いて、図３Ｂに示すように、層間絶縁膜１９を形成する。
　詳細には、トランジスタ素子２０を覆うように、例えばシリコン酸化物を堆積し、層間絶縁膜２１を形成する。層間絶縁膜１９は、ＣＭＰによりその表面を研磨する。 Subsequently, as shown in FIG. 3B, an interlayer insulating film 19 is formed.
Specifically, for example, silicon oxide is deposited so as to cover the transistor element 20, and the interlayer insulating film 21 is formed. The surface of the interlayer insulating film 19 is polished by CMP.
　続いて、図３Ｃに示すように、層間絶縁膜１９にコンタクト孔１９ａを形成する。
　詳細には、先ず、層間絶縁膜１９上にレジストを塗布し、レジストをリソグラフィーにより加工する。これにより、ソース／ドレイン領域１８に位置整合する部分に開口を有するレジストマスクが形成される。
　次に、上記のレジストマスクを用い、ソース／ドレイン領域１８をエッチングストッパーとして、ソース／ドレイン領域１８の表面の一部が露出するまで層間絶縁膜１９をドライエッチングする。これにより、層間絶縁膜２１にコンタクト孔１９ａが形成される。コンタクト孔１９ａは、その開口径が１０ｎｍ～３０ｎｍ程度、ここでは１０ｎｍ程度に形成される。 Subsequently, as shown in FIG. 3C, a contact hole 19 a is formed in the interlayer insulating film 19.
Specifically, first, a resist is applied on the interlayer insulating film 19, and the resist is processed by lithography. As a result, a resist mask having an opening in a portion aligned with the source / drain region 18 is formed.
Next, using the resist mask, the interlayer insulating film 19 is dry-etched using the source / drain region 18 as an etching stopper until a part of the surface of the source / drain region 18 is exposed. As a result, a contact hole 19 a is formed in the interlayer insulating film 21. The contact hole 19a is formed with an opening diameter of about 10 nm to 30 nm, here about 10 nm.
　続いて、コンタクト孔１９ａを、横方向グラフェンと縦方向グラフェンとの一体構造で埋め込む。
　本実施形態では、図２の真空プロセスシステムを用いて、触媒の形成工程、縦方向グラフェン及び横方向グラフェンの形成工程（図１Ａ～図１Ｃの全工程）を、真空一貫プロセスとして、in-situで行う。 Subsequently, the contact hole 19a is embedded with an integrated structure of horizontal graphene and vertical graphene.
In the present embodiment, using the vacuum process system of FIG. 2, the catalyst formation process, the vertical graphene formation process, and the horizontal graphene formation process (all processes in FIGS. 1A to 1C) are performed in-situ as an integrated vacuum process. To do.
　先ず、コンタクト孔１９ａの底部に、第１の実施形態で説明した下地２を形成する。
　シリコン基板１を真空プロセスシステムの堆積室１０３に搬送する。堆積室１０３において、真空蒸着法又はスパッタ法、ＡＬＤ法等により、コンタクト孔１９ａの底部に第１層２ａ、第２層２ｂ、及び第３層２ｃを順次積層する。ここでは、第１の実施形態と同様に、第１層２ａは、例えばＴａＮを１５ｎｍ程度の厚みに膜状に堆積する。第２層２ｂは、例えばＴｉを０．５ｎｍ～１．５ｎｍ程度の厚みに膜状に堆積する。第３層２ｃは、例えばＣｏを２ｎｍ～５ｎｍ程度の厚みに膜状に堆積する。 First, the base 2 described in the first embodiment is formed at the bottom of the contact hole 19a.
The silicon substrate 1 is transferred to the deposition chamber 103 of the vacuum process system. In the deposition chamber 103, the first layer 2a, the second layer 2b, and the third layer 2c are sequentially stacked on the bottom of the contact hole 19a by vacuum deposition, sputtering, ALD, or the like. Here, as in the first embodiment, the first layer 2a is formed by depositing, for example, TaN in a film shape with a thickness of about 15 nm. The second layer 2b deposits Ti, for example, in a film shape with a thickness of about 0.5 nm to 1.5 nm. The third layer 2c deposits, for example, Co in a film shape with a thickness of about 2 nm to 5 nm.
　次に、コンタクト孔１９ａ内に、第１の実施形態で説明した成長条件で、横方向グラフェン３と縦方向グラフェン４との一体構造を連続的に形成する。図４に示すように、コンタクト孔１９ａは、横方向グラフェン３と、高密度に成長した縦方向グラフェン４との一体構造により埋め込まれる。縦方向グラフェン４は、図５に示すように、垂直方向に起立して稠密に重畳されて形成されている。 Next, an integrated structure of the lateral graphene 3 and the longitudinal graphene 4 is continuously formed in the contact hole 19a under the growth conditions described in the first embodiment. As shown in FIG. 4, the contact hole 19 a is embedded by an integral structure of the lateral graphene 3 and the longitudinal graphene 4 grown at a high density. As shown in FIG. 5, the vertical graphene 4 stands up in the vertical direction and is densely superimposed.
　本実施形態では、層間絶縁膜１９上に形成された横方向グラフェン３を、リソグラフィー及びドライエッチングにより配線形状に加工し、配線として用いて良い。また、層間絶縁膜１９上に形成された横方向グラフェン３をエッチングで除去し、所期の導電材料を用いて配線を形成することも可能である。 In this embodiment, the lateral graphene 3 formed on the interlayer insulating film 19 may be processed into a wiring shape by lithography and dry etching and used as a wiring. In addition, the lateral graphene 3 formed on the interlayer insulating film 19 can be removed by etching, and a wiring can be formed using a desired conductive material.
　以上説明したように、本実施形態によれば、グラフェンが十分に高い密度で微細領域であるコンタクト孔内に成長してなる信頼性の高い配線構造を備えたＭＯＳトランジスタが実現する。 As described above, according to the present embodiment, a MOS transistor having a highly reliable wiring structure in which graphene is grown in a contact hole that is a fine region with a sufficiently high density is realized.
　なお、第１の実施形態で開示した横方向グラフェンと縦方向グラフェンとの一体構造は、ＬＳＩの配線構造のみならず、放熱機構等に適用することも可能である。 The integrated structure of the lateral graphene and the longitudinal graphene disclosed in the first embodiment can be applied not only to the LSI wiring structure but also to a heat dissipation mechanism.
　本発明によれば、グラフェンが十分に高い密度で所期の微細領域に成長してなる信頼性の高いグラフェン構造が実現する。 According to the present invention, it is possible to realize a highly reliable graphene structure in which graphene is grown in a desired fine region with a sufficiently high density.

Claims (10)

  1. 　基体と、
    　前記基体の上方に形成された下地と、
    　前記下地から成長した、前記基体表面に対して垂直方向に起立して稠密に重畳された垂直グラフェンと
    　を含むことを特徴とするグラフェン構造。     A substrate;
    A base formed above the substrate;
    A graphene structure comprising: vertical graphene grown from the base and standing in a vertical direction with respect to the substrate surface and densely superimposed thereon.
  2. 　前記垂直グラフェンの上部先端に接続して当該垂直グラフェンと一体形成されてなる、前記基体表面に対して水平方向に成長した水平グラフェンを更に含むことを特徴とする請求項１に記載のグラフェン構造。 The graphene structure according to claim 1, further comprising horizontal graphene that is connected to an upper end of the vertical graphene and is integrally formed with the vertical graphene and that is grown in a horizontal direction with respect to the substrate surface.
  3. 　前記下地は、第１層、第２層、及び第３層が順次積層されてなり、
    　前記第１層は、膜状であって、前記第２層及び前記第３層の構成元素の前記基体側への拡散を防止する機能を有しており、
    　前記第２層は、膜状であって、前記第３層の前記第１層との密着機能を有しており、
    　前記第３層は、島状であって、グラフェン成長の直接的な触媒機能を有することを特徴とする請求項１に記載のグラフェン構造。     The base is formed by sequentially laminating a first layer, a second layer, and a third layer,
    The first layer is in the form of a film, and has a function of preventing the constituent elements of the second layer and the third layer from diffusing to the substrate side,
    The second layer is in a film form and has a close contact function with the first layer of the third layer,
    The graphene structure according to claim 1, wherein the third layer has an island shape and has a direct catalytic function for graphene growth.
  4. 　前記第１層は、チタン窒化物、チタン酸化物、タンタル窒化物、タンタル酸化物のうちから選ばれた少なくとも１種であり、
    　前記第２層は、チタン、チタン窒化物、チタン酸化物、ニオブ、バナジウムのうちから選ばれた少なくとも１種であり、
    　前記第３層は、コバルト、ニッケル、鉄のうちから選ばれた少なくとも１種であることを特徴とする請求項３に記載のグラフェン構造。     The first layer is at least one selected from titanium nitride, titanium oxide, tantalum nitride, and tantalum oxide,
    The second layer is at least one selected from titanium, titanium nitride, titanium oxide, niobium, and vanadium,
    The graphene structure according to claim 3, wherein the third layer is at least one selected from cobalt, nickel, and iron.
  5. 　基体の上方に下地を形成する工程と、
    　前記下地を用いて、前記基体表面に対して垂直方向に起立して稠密に重畳された垂直グラフェンを成長する工程と
    　を含むことを特徴とするグラフェン構造の製造方法。     Forming a base above the substrate;
    And growing a vertical graphene that stands upright in a direction perpendicular to the surface of the substrate and densely superimposes on the substrate surface using the base.
  6. 　前記下地を用いて、前記基体表面に対して水平方向に水平グラフェンを成長し、前記水平グラフェン下に当該水平グラフェンと上部先端で接続して一体形成されてなる前記垂直グラフェンを成長することを特徴とする請求項５に記載のグラフェン構造の製造方法。 Using the foundation, horizontal graphene is grown in a horizontal direction with respect to the substrate surface, and the vertical graphene formed integrally by connecting the horizontal graphene and an upper end under the horizontal graphene is grown. A method for producing a graphene structure according to claim 5.
  7. 　前記下地は、第１層、第２層、及び第３層が順次積層されてなり、
    　前記第１層は、膜状であって、前記第２層及び前記第３層の構成元素の前記基体側への拡散を防止する機能を有しており、
    　前記第２層は、膜状であって、前記第３層の前記第１層との密着機能を有しており、
    　前記第３層は、島状であって、グラフェン成長の直接的な触媒機能を有することを特徴とする請求項５に記載のグラフェン構造の製造方法。     The base is formed by sequentially laminating a first layer, a second layer, and a third layer,
    The first layer is in the form of a film, and has a function of preventing the constituent elements of the second layer and the third layer from diffusing to the substrate side,
    The second layer is in a film form and has a close contact function with the first layer of the third layer,
    6. The method for producing a graphene structure according to claim 5, wherein the third layer is island-shaped and has a direct catalytic function for graphene growth.
  8. 　前記第１層は、チタン窒化物、チタン酸化物、タンタル窒化物、タンタル酸化物のうちから選ばれた少なくとも１種であり、
    　前記第２層は、チタン、チタン窒化物、チタン酸化物、ニオブ、バナジウムのうちから選ばれた少なくとも１種であり、
    　前記第３層は、コバルト、ニッケル、鉄のうちから選ばれた少なくとも１種であることを特徴とする請求項７に記載のグラフェン構造の製造方法。     The first layer is at least one selected from titanium nitride, titanium oxide, tantalum nitride, and tantalum oxide,
    The second layer is at least one selected from titanium, titanium nitride, titanium oxide, niobium, and vanadium,
    The method for producing a graphene structure according to claim 7, wherein the third layer is at least one selected from cobalt, nickel, and iron.
  9. 　グラフェン成長の処理温度が４００℃～４５０℃の範囲内の値であることを特徴とする請求項５に記載のグラフェン構造の製造方法。 6. The method for producing a graphene structure according to claim 5, wherein the processing temperature of graphene growth is a value within a range of 400 ° C. to 450 ° C.
  10. 　前記各工程を、所定の真空状態で一貫したin-situで行うことを特徴とする請求項５に記載のグラフェン構造の製造方法。 The method for producing a graphene structure according to claim 5, wherein each of the steps is performed in-situ consistently in a predetermined vacuum state.
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