Classifications

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  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K50/00—Organic light-emitting devices
  • H10K50/30—Organic light-emitting transistors
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  • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
  • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
  • H10H20/062—Light-emitting semiconductor devices having field effect type light-emitting regions, e.g. light-emitting High-Electron Mobility Transistors
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  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K50/00—Organic light-emitting devices
  • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
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  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K50/00—Organic light-emitting devices
  • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
  • H10K50/11—OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers
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  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K50/00—Organic light-emitting devices
  • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
  • H10K50/14—Carrier transporting layers
  • H10K50/15—Hole transporting layers
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  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K50/00—Organic light-emitting devices
  • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
  • H10K50/14—Carrier transporting layers
  • H10K50/16—Electron transporting layers
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  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K50/00—Organic light-emitting devices
  • H10K50/80—Constructional details
  • H10K50/805—Electrodes
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/10—Details of semiconductor or other solid state devices to be connected
  • H01L2924/11—Device type
  • H01L2924/12—Passive devices, e.g. 2 terminal devices
  • H01L2924/1204—Optical Diode
  • H01L2924/12044—OLED
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  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
  • H10K2102/301—Details of OLEDs
  • H10K2102/302—Details of OLEDs of OLED structures
  • H10K2102/3023—Direction of light emission
  • H10K2102/3035—Edge emission
• • H—ELECTRICITY
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  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
  • H10K85/60—Organic compounds having low molecular weight
  • H10K85/631—Amine compounds having at least two aryl rest on at least one amine-nitrogen atom, e.g. triphenylamine
  • H10K85/636—Amine compounds having at least two aryl rest on at least one amine-nitrogen atom, e.g. triphenylamine comprising heteroaromatic hydrocarbons as substituents on the nitrogen atom

Definitions

• OLED organic light- emitting diodes
• OLET Organic light-emitting transistor
• electroluminescent light-emitting material has been shown to achieve much higher external quantum efficiency (EQE) in an OLET than in an equivalent OLED.
• a trilayer heterostructure OLET has been reported with a maximum EQE of about 5%.
• the reported trilayer heterostructure OLET includes, from bottom to top, a transparent substrate, a gate electrode, a gate dielectric, an active layer consisting of the superposition of three organic layers, and source and drain electrodes on top of the active layer.
• the trilayer active layer includes a light-emitting host-guest matrix sandwiched between an electron-transporting (n-type) semiconductor and a hole-transporting (p-type) semiconductor.
• n-type electron-transporting
• p-type hole-transporting
• the present teachings provide light-emitting transistors having novel structures that can lead to enhanced device brightness, specifically, via incorporation of one or more electrically insulating elements between a charge injection electrode (for carriers of a particular charge) and a charge transport layer (for carriers of the opposite charge), to favor charge localization and in turn carrier recombination, and exciton formation.
• the present teachings also relate to methods of fabricating the OLETs described herein.
• one or more electrically insulating elements can be incorporated within the channel layer of the present OLETs by a process selected from the group consisting of thermal evaporation, sputtering, atomic layer deposition, chemical vapor deposition, solution processing, spin-coating, spray coating, slot die coating, and printing.
• Figure 1 shows a cross-section view of (a) a bottom-gate top-contact light-emitting transistor 10a, (b) a bottom-gate bottom-contact light-emitting transistor 10b, (c) a top-gate bottom-contact light-emitting transistor 10c, and (d) a top-gate top-contact light-emitting transistor lOd, wherein the channel layer 8 comprises a trilayer heterostructure including a first charge transport sublayer 8a, a second charge transport sublayer 8c, and an emissive sublayer 8b sandwiched therebetween.
• Figure 2 shows a cross section view of (a) a bottom-gate top-contact light-emitting transistor 20a including electrically insulating elements 22 and 24, wherein the electrically insulating elements 22 and 24 and the hole and electron electrode 12 and 14 are in contact with a different charge transport sublayer; (b) a bottom-gate top-contact light-emitting transistor 20b including electrically insulating elements 22 and 24, wherein the electrically insulating elements 22 and 24 and the hole and electron electrode 12 and 14 are in contact with opposite surfaces of a charge transport sublayer; (c) a top-gate bottom-contact light- emitting transistor 20c including electrically insulating elements 22 and 24, wherein the electrically insulating elements 22 and 24 and the hole and electron electrode 12 and 14 are in contact with opposite surfaces of a charge transport sublayer; and (d) a top-gate bottom- contact light-emitting transistor 20d including electrically insulating elements 22 and 24, wherein the electrically insulating elements 22 and 24 and the hole and electron electrode 12 and 14 are in contact with
• Figure 3 shows a cross section view of (a) a bottom-gate light-emitting transistor 30a and (b) a top-gate light-emitting transistor 30b according to the present teachings, wherein the source and drain contacts (hole and electron electrodes 12, 14) are offset vertically from each other.
• Figure 4 illustrates different embodiments of OLETs according to the present teachings, wherein the hole electrode 12 is positioned within the hole transport sublayer 8a, and the electron electrode 14 is positioned (a and b) within the emissive sublayer 8b, (c) within the electron transport sublayer 8c, or (d) on top of the channel layer in contact with the electron transport sublayer 8c.
• Figure 5 illustrates different embodiments of OLETs according to the present teachings, wherein the hole electrode 12 is positioned within the emissive sublayer 8b in contact with the hole transport sublayer 8a, and the electron electrode 14 is positioned (a) within the hole transport sublayer 8a, (b) within the emissive sublayer 14 but not in contact with the hole transport sublayer 8a, (c) within the electron transport sublayer 8c, or (d) on top of the channel layer 8.
• Figure 6 illustrates different embodiments of OLETs according to the present teachings, wherein the hole electrode 12 is positioned within the hole transport sublayer 8a, and the electron electrode 14 is positioned (a) within the electron transport sublayer 8c, (b and c) within the emissive sublayer 8b, or (d) on top of the channel layer 8.
• the hole transport sublayer 8a is the top sublayer
• the electron transport sublayer 8c is in contact with the gate insulating (dielectric) layer 6.
• Figure 7 illustrates different embodiments of OLETs according to the present teachings, wherein the hole electrode 12 is positioned on top of the channel layer 8 in contact with the hole transport layer 8a, and the electron electrode is positioned (a) within the electron transport sublayer 8c, (b and c) within the emissive sublayer 8b, or (d) within the hole transport sublayer 8a.
• the hole transport sublayer 8a is the top sublayer
• the electron transport sublayer 8c is in contact with the dielectric layer 6.
• Figure 8 compares the charge transport/light generating mechanisms of (a) a conventional trilayer OLET with planar hole and electron electrodes against (b) a trilayer OLET having nonplanar hole and electron electrodes according to the present teachings.
• Figure 9 illustrates how a nonplanar source-drain electric field can lead to increased exciton formation.
• Figure 10 illustrates how a trilayer OLET having electrically insulating elements according to the present teachings can lead to reduced leakage currents and enhanced exciton formation due to charge localization within the channel region between the hole electrode and the electron electrode (particularly, within an aperture between the two electrically insulating elements).
• Figure 11 illustrates a hypothetical distribution of charge carriers and excitons within the channel layer for an OLET without electrically insulating elements according to the present teachings.
• Figure 12 illustrates a hypothetical distribution of charge carriers and excitons within the channel layer for an OLET having electrically insulating elements according to the present teachings. Compared to the device illustrated in Figure 11, a higher density of excitons (stars) is expected within an aperture between the electrically insulating elements 22 and 24 in the present OLET.
• Figure 13 illustrates how an OLET having electrically insulating elements according to the present teachings can allow more precise spatial control of where light is generated by varying the lengths of the electrically insulating elements (and in turn, the location of the aperture between the electrically insulating elements).
• Figure 14 provides a schematic of a bottom-gate OLET according to the present teachings having a pair of nonplanar hole electrode 12 and electron electrode 14 and a corresponding pair of nonplanar electrically insulating elements 22 and 24.
• Figure 15 illustrates (a) a bottom-gate OLET and (b) a top-gate OLET according to the present teachings, wherein a pair of nonplanar electrically insulating elements 22 and 24 are positioned with the emissive sublayer 8b.
• Figure 16 illustrates two different bottom-gate OLETs according to the present teachings, wherein an electrically insulating element 22 and an electrically insulating element 24 are in contact with different sides of the emissive sublayer 8b.
• the electrically insulating element 22 is deposited on the hole transport sublayer 8a and the electrically insulating element 24 is deposited on the emissive sublayer 8b in contact with the electron transport sublayer 8c.
• at least one of the electrically insulating elements can be positioned in contact with one of the hole electrode and the electron electrode.
• Figure 17 illustrates two different top-gate OLETs according to the present teachings, wherein an electrically insulating element 22 and an electrically insulating element 24 are in contact with different sides of the emissive sublayer 8b.
• the electrically insulating element 22 is deposited on the hole transport sublayer 8a and the electrically insulating element 24 is deposited on the emissive sublayer 8b in contact with the electron transport sublayer 8c.
• at least one of the electrically insulating elements can be positioned in contact with one of the hole electrode and the electron electrode.
• Figure 18 illustrates different embodiments of OLETs according to the present teachings, wherein the electrically insulating elements 22 and 24 together with the emissive sublayer 8b form a single planar sublayer.
• Figure 18a shows a bottom-gate OLET with nonplanar hole electrode and electron electrode.
• Figure 18b shows a bottom-gate OLET with planar hole electrode and electron electrode.
• Figure 18c shows a top-gate OLET with planar hole electrode and electron electrode.
• Figure 18d shows a top-gate OLET with nonplanar hole electrode and electron electrode.
• compositions are described as having, including, or comprising specific components, or where processes are described as having, including, or comprising specific process steps, it is contemplated that compositions of the present teachings also consist essentially of, or consist of, the recited components, and that the processes of the present teachings also consist essentially of, or consist of, the recited process steps.
• a "p-type semiconductor material,” “p-type semiconductor” or a “p-type OSC” refers to a semiconductor material or a semiconducting compound having holes as the majority current or charge carriers.
• a p-type semiconductor material when deposited on a substrate, it can provide a hole mobility in excess of about 10 ⁇ 5 cm 2 /Vs.
• a p-type semiconductor when deposited on a substrate, it can provide a hole mobility in excess of about 10 ⁇ 5 cm 2 /Vs. In the case of field-effect devices, a p-type semiconductor can also exhibit a current on/off ratio of greater than about 10.
• a p-type OSC can be characterized by a highest occupied molecular orbital (HOMO) energy that is higher than or about -6.4 V, preferably higher than or about -6.2 V, and more preferably, higher than or about -6.0 V.
• HOMO highest occupied molecular orbital
• an "n-type semiconductor material,” an “n-type semiconductor” or an “n-type OSC” refers to a semiconductor material or a semiconducting compound having electrons as the majority current or charge carriers.
• an n-type semiconductor material when deposited on a substrate, it can provide an electron mobility in excess of about 10 "5 cm 2 /Vs.
• an n-type semiconductor can also exhibit a current on/off ratio of greater than about 10.
• an n-type OSC can be characterized by a lowest unoccupied molecular orbital (LUMO) energy that is lower than or about -3.2 V, preferably lower than or about -3.6 V, and more preferably, lower than or about -4.0 V.
• LUMO lowest unoccupied molecular orbital
• mobility refers to a measure of the velocity with which charge carriers, for example, holes (or units of positive charge) in the case of a p-type semiconductor material and electrons in the case of an n-type semiconductor material, move through the material under the influence of an electric field.
• This parameter which depends on the device architecture, can be measured using a field-effect device or space-charge current measurements.
• solution-processable refers to compounds, materials, or compositions that can be used in various solution-phase processes including spin-coating, printing (e.g., inkjet printing, screen printing, pad printing, offset printing, gravure printing, flexographic printing, lithographic printing, mass-printing and the like), spray coating, electrospray coating, drop casting, dip coating, and blade coating.
• printing e.g., inkjet printing, screen printing, pad printing, offset printing, gravure printing, flexographic printing, lithographic printing, mass-printing and the like
• spray coating e.g., inkjet printing, screen printing, pad printing, offset printing, gravure printing, flexographic printing, lithographic printing, mass-printing and the like
• electrospray coating e.g., electrospray coating, drop casting, dip coating, and blade coating.
• a conventional organic light-emitting transistor typically has a stacked structure that includes a substrate 2, a gate electrode 4, a gate insulating (dielectric) layer 6 coupled to the gate electrode, an active channel layer 8, and a hole electrode 12 and an electron electrode 14 both in contact with the active channel layer.
• the hole electrode 12 and the electron electrode 14 are positioned on the same plane and are spaced apart at a distance that defines the length of the channel region (L).
• the active channel layer can include one or more organic semiconductor materials that individually or in combination can perform the function of electron transport, hole transport, and light emission.
• the active channel layer 8 can include sublayers 8a and 8c which, respectively, are adapted to allow transport of charge carriers of opposite types, and sublayer 8b which is adapted to facilitate recombination of holes and electrons to generate light.
• the hole electrode, the electron electrode, and the gate electrode can have different arrangements in relation to the channel layer.
• Figure la shows a bottom-gate top-contact OLET 10a, wherein the gate electrode 4 is positioned below the channel layer 8 (in contact with the substrate 2), and the hole electrode 12 and the electron electrode 14 are positioned on top of the channel layer 8 (in contact with a first (top) side 16 of the channel layer 8).
• Figure lb shows a bottom-gate bottom-contact OLET 10b, wherein the gate electrode 4 is positioned below the channel layer 8 (in contact with the substrate 2), and the hole electrode 12 and the electron electrode 14 are positioned at the interface between the dielectric layer 6 and a second (bottom) side 18 of the channel layer 8.
• Figure lc shows a top-gate bottom- contact OLET 10c, wherein the gate electrode 4 is positioned on top of the channel layer 8, and the hole electrode 12 and the electron electrode 14 are positioned at the interface between the substrate 2 and a second (bottom) side 18 of the channel layer 8.
• Figure Id shows a top- gate top-contact OLET lOd, wherein the gate electrode 4 is positioned on top of the channel layer 8, and the hole electrode 12 and the electron electrode 14 are positioned at the interface between the dielectric layer 6 and a first (top) side 16 of the channel layer 8.
• conventional OLETs have coplanar hole electrode 12 and electron electrode 14 through which positive charge carriers (holes) and negative charge carriers (electrons), respectively, are injected into the active channel layer 8.
• holes positive charge carriers
• electrostatically attracted into the emissive sublayer Only the holes from the hole transport sublayer and the electrons from the electron transport sublayer that are electrostatically attracted into the emissive sublayer will recombine to form excitons.
• holes and electrons that are within the channel region between the hole electrode and the electron electrode have a much larger likelihood to recombine to form excitons than holes and electrons that are located in portions of the channel layer lying directly below or above the electrodes.
• novel OLET structures having one or more electrically insulating elements positioned within the channel layer.
• the one or more electrically insulating elements can be arranged in various ways in relation to each other and in relation to the different sublayers of the channel layer, provided that individually or in combination the electrically insulating element(s) do not extend the entire length of the channel region.
• the electrically insulating element(s) provide a physical barrier against charge carriers from moving into areas directly below or above the hole electrode and/or the electron electrode, thereby forcing more charge carriers to be localized within the channel region between the hole electrode and the electron electrode.
• the electrically insulating elements can be embedded within or otherwise positioned in contact with the emissive sublayer of the channel layer.
• an electrically insulating element can be present directly above or below each of the hole electrode and the electron electrode.
• the channel layer can include a first electrically insulating element 22 positioned between the hole electrode 12 and a second charge transport sublayer 8a, and/or a second electrically insulating element 24 positioned between the electron electrode 14 and the second charge transport sublayer 8a.
• first and second electrically insulating elements can be embedded within any of sublayers 8a, 8b, or 8c, for ease of fabrication (e.g., keeping the number of
• the first and second electrically insulating elements can be deposited either on top of the charge transport sublayer 8a ( Figure 2a) or on top of the emissive sublayer 8b ( Figure 2b).
• the channel layer can include a first electrically insulating element 22 positioned between the hole electrode 12 and a second charge transport sublayer 8a, and/or a second electrically insulating element 24 positioned between the electron electrode 14 and the second charge transport sublayer 8a.
• first and second electrically insulating elements can be embedded within any of sublayers 8a, 8b, or 8c; however, for ease of fabrication, the first and second electrically insulating elements can be deposited either on top of the charge transport sublayer 8c ( Figure 2c) or on top of the emissive sublayer 8b ( Figure 2d).
• the present OLETs can have non-planar hole electrode and electron electrode.
• the hole electrode and the electron electrode can function, respectively, as the source electrode and the drain electrode (or vice versa) depending on the polarity of the gate voltage. Briefly, because the source electrode is typically grounded (0 V), if the gate voltage is -100V and the drain voltage is - 80V, then the source electrode is the hole electrode (negatively biased) and the drain electrode is the electron electrode (positively biased). On the other hand, if the gate voltage is +100V, the source electrode is the electron electrode and the drain electrode is the hole electrode. Therefore, the present OLETs also can be described as having non-planar source electrode and drain electrode.
• an OLET 30a or 30b can have a hole electrode 12 and an electron electrode 14 that are offset vertically from each other.
• both the hole electrode 12 and the electron electrode 14 typically are positioned either on top of a first side 16 of the channel layer 8 or in contact with a second side 18 of the channel layer 8.
• sublayer 8a can comprise a first
• the hole electrode 12 and the electron electrode 14 can be positioned within different sublayers of the channel layer 8.
• dl can be 0 (within sublayer 8a in contact with the second side 18 of the channel layer 8)
• d2 can be dsi (within sublayer 8b in contact with sublayer 8a) or d2 can be dsi + ds (within sublayer 8c in contact with sublayer 8b).
• the gate electrode can have a length (LG) equal to or greater than the channel length (L), which is the distance between the edge 32 of the hole electrode 12 adjacent to the channel region and the edge 34 of the electron electrode 14 adjacent to the channel region.
• the gate electrode can have a length LG that is the same as the length of the channel region L and can be located within a space that is aligned with the channel region.
• the gate electrode 4 can be deposited on the substrate 2, and the dielectric layer 6 can be formed over the gate electrode 4.
• the hole electrode 12 and the electron electrode 14 can be patterned on the dielectric layer 6 in a way such that an edge 32 of the hole electrode 12 and an edge 34 of the electron electrode 14 are aligned with the edges of the gate electrode 4.
• the hole electrode 12 and the electron electrode 14 first can be patterned on the substrate 2.
• the active channel layer 8 can be formed (e.g. via sequential deposition of sublayers 8a, 8b, and 8c) over the hole electrode 12 and the electron electrode 14, followed by the deposition of the dielectric layer 6 over the channel layer 8.
• the gate electrode 4 can be patterned on the dielectric layer, such that the edges of the gate electrode 4 are aligned with an edge 32 of the hole electrode 12 and an edge 34 of the electron electrode 14.
• L can be between about 2 ⁇ and about 500 ⁇ , preferably between about 5 ⁇ and about 20 ⁇ .
• the hole electrode and the electron electrode, respectively can have a length L h and a length L e that independently are between about 50 ⁇ and about 300 ⁇ , preferably between about 100 ⁇ and about 200 ⁇ .
• the overlap b and b' of the gate electrode with either the hole electrode and/or the electron electrode can be 0 ⁇ and up to the length (L h or L e ) of the hole electrode and/or the electron electrode (i.e., 0 ⁇ b ⁇ L h , 0 ⁇ b' ⁇ L e ), but preferably, the overlap is between about 0 ⁇ and about 100 ⁇ .
• the length L G of the gate electrode can be between about 50 ⁇ and about 500 ⁇ , preferably between about 100 ⁇ and about 200 ⁇ .
• the thickness dsi and ds 2 of the two charge transport sublayers can be between about 5 ⁇ and about 100 ⁇ , whereas the thickness ⁇ 1E of the emissive sublayer can be between about 2 ⁇ and about 50 ⁇ .
• FIG. 4-7 illustrate various embodiments of OLETs having nonplanar hole and electron electrodes according to the present teachings.
• the source-drain electric field spans across the emissive sublayer 8b (as indicated by the direction of the arrow), that is, both hole and electron currents flow into the emissive sublayer. This results in a much greater probability for holes and electrons to meet in the emissive sublayer to form a larger number of excitons 26. Furthermore, referring back to Figure 8a, because both the hole electrode and the electron electrode are deposited on the same surface and are in contact with a sublayer that favors the transport of only one type of charge carriers, large contact resistance inevitably results for one of the contacts.
• the contact resistance can be reduced drastically by positioning the hole electrode 12 in contact with sublayer 8a composed of a p-type semiconductor which facilitates hole transport, and positioning the electron electrode 14 in contact with sublayer 8c composed of an n-type semiconductor which facilitates electron transport.
• n e _(ex) n e _(total) - n e _(ch) - n e _(leak)l - n e _(leak)2
• ii h+ (total) and n e- (total) respectively represent the total number of charges injected from the hole electrode and the electron electrode
• n(ch) represents the number of charges in the channel region that do not get electrostatically attracted into the emissive sublayer
• n(leak)l and n(leak)2 represent the number of charges crossing the emissive sublayer under or above the electrode areas.
• n e- (leak)l « n h+ (leak)2 and n h+ (leak)l « n e- (leak)2) charge carriers in these areas are unlikely to form excitons, and n e- (leak)l, n e- (leak)2, n h+ (leak)l and n h+ (leak)2 can be considered leakage currents.
• electrically insulating elements 22 and/or 24 these leakage currents can be reduced and/or eliminated, thus it is expected that the density of charge carriers of opposite type crossing the emissive sublayer 8b in the channel region will increase, thereby maximizing the chance to form excitons.
• FIG. 12 which shows an OLET including electrically insulating elements 22 and 24, holes injected from the hole electrode 12 are expected to be localized in the hole transport sublayer 8a between the hole electrode 12 and the area above the electrically insulating element 24 while electrons injected from the electron electrode 14 are expected to be localized in the electron transport sublayer 8c between the electron electrode 14 and the area below the electrically insulating element 22.
• the OLET shown in Figure 12 is expected to have a higher density of both holes and electrons within the channel region between the hole electrode 12 and the electron electrode 14, more specifically, between the electrically insulating elements 22 and 24, and in turn enhanced exciton formation can be expected.
• the incorporation of electrically insulating elements within the channel layer also allows more precise spatial control of where light is generated, and with less dependence upon gate voltage.
• an OLET according to the present teachings 100 can have a first electrically insulating element 22 and/or a second electrically insulating element 24 within the channel layer, and optionally a hole electrode 12 and an electron electrode 14 that are offset vertically from each other.
• the hole electrode 14 can be positioned vertically away from a side (e.g., the bottom side 18) of the channel layer at a distance dl, while the electron electrode 14 can be positioned vertically away from the same side of the channel layer at a distance d2.
• the distances dl and d2 can be the same or different. For example, in some embodiments, both dl and d2 can be 0, thereby providing a bottom-contact device.
• both dl and d2 can be dsi + d E + ds 2 (where dsi is the thickness of the first charge transport sublayer 8a, d E is the thickness of the emissive sublayer 8b, and ds 2 is the thickness of the second charge transport sublayer 8c), thereby providing a top-contact device.
• dl can be 0 (within sublayer 8a in contact with the bottom side 18 of the channel layer 8), while d2 can be dsi (within emissive sublayer 8b in contact with first charge transport sublayer 8a) or d2 can be dsi + d E (within second charge transport sublayer 8c in contact with emissive sublayer 8b).
• the hole electrode 12 has a thickness d h and a length L h
• the electron electrode 14 has a thickness d e and a length L e .
• the hole electrode 12 is embedded within or otherwise positioned in contact with the hole transport sublayer 8a
• the electron electrode 14 is embedded within or otherwise positioned in contact with the electron transport sublayer 8c.
• d2 > dl given that the hole transport sublayer 8a is positioned above the electron transport sublayer 8c.
• the electrically insulating element 22 which has a thickness du can be positioned away from the bottom side 18 of the channel layer at a distance d3, where d3 > dl + d h .
• the electrically insulating element 24 which has a thickness di 2 can be positioned away from the bottom side 18 of the channel layer at a distance d4, where d4 ⁇ d2.
• d3 is no greater than d4, and d4 is no less than d3.
• the length Ln of the electrically insulating element 22 typically is between L h /2 and L h + L/3 si + ds, while the length Li 2 of the electrically insulating element 24 can be between L e /2 and L e + L/3.
• L can be between about 2 ⁇ and about 500 ⁇ , preferably between about 5 ⁇ and about 20 ⁇ .
• the hole electrode and the electron electrode, respectively, can have a length L h and a length L e that independently are between about 50 ⁇ and about 300 ⁇ , preferably between about 100 ⁇ and about 200 ⁇ .
• Ln and L K can be between about 50 ⁇ and about 133 ⁇ .
• the thickness du and di 2 of the electrically insulating elements can be between about 5 ⁇ and about 50 ⁇ .
• FIGS 15-17 illustrate several preferred embodiments of OLETs according to the present teachings.
• Each of these OLETs has electrically insulating elements 22 and 24 below or above a pair of nonplanar hole electrode 12 and electron electrode 14.
• the hole electrode 12 is positioned in contact with the hole transport sublayer 8a, while the electron electrode 14 is positioned in contact with the electron transport sublayer 8c, to allow the best charge injection and transport.
• the electrically insulating elements are positioned in contact with the emissive sublayer 8b to maximize charge flow into the emissive sublayer within the channel region between the hole electrode and the electron electrode, thereby enhancing charge localization and device brightness.
• the electrically insulating elements 22 and 24 can be positioned on the same plane, and used in combination with planar or nonplanar hole electrode and electron electrode.
• the OLETs shown in Figures 2a, 2b, 2c, and 2d each have planar hole electrode and electron electrode, and the electrically insulating elements can be deposited on one of the charge transport sublayers 8a ( Figure 2a) or 8c ( Figure 2c), or on the emissive sublayer 8b ( Figures 2b and 2d).
• the devices shown in Figure 2 can be fabricated with fewer shadow masks, deposition, and/or photo lithography/etching steps, which in turn can result in lower fabrication costs.
• the electrically insulating elements 22 and 24 can have the same thickness as the emissive sublayer 8b, and the electrically insulating elements 22 and 24 together with the emissive sublayer 8b can form a single planar sublayer sandwiched between the two charge transport sublayers 8a and 8c.
• the electrically insulating elements tend to provide a smoother surface for further processing than the emissive material (which often comprises a mixture of host materials and emitters), the semiconductor film deposited thereon can be expected to have better morphology and the device as a whole can be expected to have better stack planarization.
• the OLETs described herein also can include charge injection layers.
• the hole electrode and the electron electrode can be coated with a hole injection layer and an electron injection layer, respectively, to further reduce contact resistance. More generally, a hole injection layer can be deposited between the hole transport sublayer and the hole electrode, and an electron injection layer can be deposited between the electron electrode and the electron transport sublayer.
• the present OLETs can include a surface-modified substrate, wherein the substrate is coated with a surface-modifier to allow improved processing such as better adhesion with the layer to be deposited thereon.
• the present OLETs also can include a passivation layer coupled to the top (first) side of the channel layer.
• the top charge transport sublayer comprises a metal oxide semiconductor, it may be preferred to have the metal oxide semiconductor layer covered by a passivation layer to improve device stability.
• OLETs can be fabricated using various deposition processes known in the art.
• an optional planarization or surface-modifying layer can be formed onto a transparent substrate, e.g., by spin-coating.
• a metallic thin film can be thermally evaporated thereon, followed by etching or other patterning techniques to form the gate electrode.
• the dielectric layer depending on its composition, can be deposited by a solution-phase process such as spin- coating or by chemical or physical vapor deposition. This can be followed by the formation of the active channel layer via sequential deposition of the first charge transport sublayer, the emissive sublayer, and the second charge transport sublayer.
• the hole electrode and the electron electrode can be formed using similar or different techniques as the gate electrode.
• at least one of the first charge transport sublayer, the emissive sublayer, and the second charge transport sublayer can be deposited in multiple steps, allowing formation of the electrically insulating elements within the channel layer.
• the electrically insulating elements can be formed by sputtering, ion-assisted deposition (IAD), atomic layer deposition, chemical vapor deposition, physical vapor deposition, different types of printing techniques (e.g., flexo printing, litho printing, gravure printing, ink-jetting, pad printing, and so forth), drop casting, dip coating, doctor blading, roll coating, and spin-coating.
• both the channel layer and the dielectric layer can be formed from a solution-phase process such as spin-coating, slot coating, or printing.
• Electrical contacts can be formed by processes such as, but not limited to, thermal evaporation and radiofrequency or e-beam sputtering, as well as various deposition processes, including but not limited to those described immediately above (e.g., flexo printing, litho printing, gravure printing, ink-jetting, pad printing, screen printing, drop casting, dip coating, doctor blading, roll coating, and spin-coating).
• the present OLETs can be fabricated on various substrates, including plastic, flexible substrates that have a low temperature resistance.
• flexible substrates include polyesters such as polyethylene terephthalate, polyethylene naphthalate, polycarbonate; polyolefms such as polypropylene, polyvinyl chloride, and polystyrene; polyphenylene sulfides such as polyphenylene sulfide; polyamides; aromatic polyamides; polyether ketones; polyimides; acrylic resins; polymethylmethacrylate, and blends and/or copolymers thereof.
• the substrate can be a rigid transparent substrate such as glass, quartz and VYCOR®.
• Substrate-gate materials commonly used in thin-film transistors also can be used. Examples include doped silicon wafer, tin-doped indium oxide (ITO) on glass, tin-doped indium oxide on polyimide or mylar film, aluminum or other metals alone or coated on a polymer such as polyethylene terephthalate, a doped
• the source/drain electrodes (or hole/electron electrodes) as well as the gate electrode can be made using various deposition techniques.
• the electrodes can be deposited through a mask, or can be deposited then etched or lifted off (photolithography). Suitable deposition techniques include electrodeposition, vaporization, sputtering, electroplating, coating, laser ablation and offset printing, from metal or metal alloy including copper, aluminum, gold, silver, molybdenum, platinum, palladium, and/or nickel, or an electrically conductive polymer such as polyethylenethioxythiophene (PEDOT).
• PEDOT polyethylenethioxythiophene
• Charge carrier injection can be facilitated by the use of a material for the injection electrode (hole electrode or electron electrode) that has a low barrier against injection of a charge carrier type into the hole transport sublayer and the electron transport sublayer, respectively.
• the hole electrode can comprise at least one material selected from the group consisting of Au, indium tin oxide, Cr, Cu, Fe, Ag, poly(3,4-ethylenedioxthiophene) combined with poly(styrenesulfonate) (PEDOT:PSS), and a perovskite manganite (Rei_ x A x Mn03).
• the hole electrode and the electron electrode can be made of conductors with different work functions to favor both hole and electron injection.
• the dielectric layer can be composed of inorganic (e.g., oxides such as Si0 2 , A1 2 0 3 , or Hf0 2 ; and nitrides such as Si 3 N 4 ), organic (e.g., polymers such as polycarbonate, polyester, polyimide, polystyrene, polyhaloethylene, polymethylmethacrylate), or hybrid organic/inorganic materials.
• inorganic e.g., oxides such as Si0 2 , A1 2 0 3 , or Hf0 2 ; and nitrides such as Si 3 N 4
• organic e.g., polymers such as polycarbonate, polyester, polyimide, polystyrene, polyhaloethylene, polymethylmethacrylate
• hybrid organic/inorganic materials e.g., polymers such as polycarbonate, polyester, polyimide, polystyrene, polyhaloethylene, polymethylmethacrylate
• hybrid organic/inorganic materials e.g.,
• the dielectric layer can be formed via the growth of self-assembled nanodielectric materials (such as those described in Yoon et al, PNAS, 102 (13): 4678-4682 (2005), and Ha et al, Chem. Mater., 21(7): 1173-1175 (2009)); solution- processing of inorganic/organic hybrid materials (e.g., as described in Ha et al, J. Am. Chem. Soc, 132 (49): 17428-17434 (2010)); and low-temperature solution-processing of metal oxides (e.g., as described in International Publication Number WO 2012/103528).
• self-assembledielectric materials such as those described in Yoon et al, PNAS, 102 (13): 4678-4682 (2005), and Ha et al, Chem. Mater., 21(7): 1173-1175 (2009)
• solution- processing of inorganic/organic hybrid materials e.g., as described in Ha et al, J. Am. Chem. Soc
• the dielectric material can be in the form of a bilayer composed of different materials, for example, a combination of inorganic/organic materials, materials with different dielectric constants, or materials that can be processed by different techniques (e.g., solution- processing and vapor deposition). Any materials and methods of processing for gate dielectrics known in the art can be used in connection with the present electrically insulating elements.
• the channel layer can comprise small molecule materials, polymers, and/or metal complexes.
• Suitable materials for the electron transport (n-type) sublayer can include one class of n-type organic semiconductors (OSCs) that relates to oligomers, homopolymers or copolymers of thiophenes, particularly those substituted with fluorocarbons.
• OSCs n-type organic semiconductors
• ⁇ , ⁇ -diperfluorohexylquaterhiophenes and other fluorocarbon-substituted thiophene oligomers are described in U.S. Patent No. 6,585,914.
• n-type OSCs relates to fused ring tetracarboxylic diimides and their derivatives.
• cyanated perylene diimides and cyanated naphthalene diimides more specifically, N,N'-bis-substituted-(l,7 & l,6)-di-cyano-perylene-3,4:9,10- bis(dicarboximide)s and ⁇ , ⁇ ' -bis-substituted 2,6-dicyanonaphthalene-l,4,5,8- bis(dicarboximide)s such as those described in U.S. Patent Nos.
• n- type semiconductors include N,N'-bis(cyclohexyl)-(l,7 & 1 ,6)-dicyano- perylene-3,4:9,10-bis(dicarboximide) (CN 2 PDI); N,N'-bis(lH-perfluorobutyl)-(l,7 & l,6)-di- cyano-perylene-3,4:9,10-bis(dicarboximide); N,N'-bis(n-octyl)-(l,7 & l,6)-di-cyano- perylene-3,4:9,10-bis(dicarboximide) (PDI-8CN 2 ); N,N'-bis(n-octyl)-2,6-di- cyanonaphthalene-l,4,5,8
• Another class of n-type semiconductors relates to dicyanomethylene-substituted conjugated systems.
• U.S. Patent No. 7,928,249 describes dicyanomethylene- substituted fused ring compounds such as 2,8-di-(3-dodecylthien-2-yl)-indeno[l,2- b]fluorene-6,12-dimalonitrile; 2,8-dithien-2-yl-tetraphenylenedimalonitrile; and 2,8-di-(4'- dodecylthien-2'-yl]-4-dodecylthien-2-yl)-indeno[l,2-b]fluorene-6,12-dimalono-nitrile.
• Dicyanomethylene-substituted diketopyrrolopyrrole-containing quinoidal small molecules also have been investigated as n-type semiconductors. See Qiao et ah,
• Thionated aromatic bisimides also can be used as n-type semiconductors. Examples include those described in International Publication Nos. WO2011/082234 such as (S,S)- PDISi lMP, (S,S)-cw-PDIS 2 lMP, (S,S)-tra/?s-PDIS 2 lMP, (S,S)-PDIS 3 1MP, (S,S)-PDIS- 4 1MP, (S,S)-tra/?s-PDIS 2 lMhex, (R,R)-tra/?s-PDIS 2 lMhex, (S,R)-tra/?s-PDIS 2 lMhex, (R,S)- tra/?s-PDIS 2 lMhex, (R,S)-tra/?s-PDIS 2 lMhex, (R,R)-tra/?s-PDIS 2 lMhex, (R,R)-tra/?s-PDIS 2 lMhept, (S
• N-type semiconducting polymers also can be used according to the present teachings.
• n-type semiconducting polymers include oligomers, homopolymers and copolymers of naphthalenediimides described in U.S. Patent Application Publication No.
• US 2010/0326527 such as poly ⁇ N,N'-bis(2-ethylhexyl)-l,4,5,8-naphthalene diimide-2,6- diyl]-alt-5,5 '-(2,2'-bithiophene) ⁇ ; poly ⁇ N,N'-bis(2-ethylhexyl)-l ,4,5, 8-naphthalene diimide- 2,6-diyl]-alt-5,5'-(2,5-thiophene) ⁇ ; poly ⁇ N,N'-bis(2-octyldodecyl)-l,4,5,8-naphthalene diimide-2,6-diyl]-alt-5,5'-(2,2'-bithiophene) ⁇ ; poly ⁇ N,N'-bis(l-methylhexyl)-l,4,5,8- naphthalene diimide-2,6-diyl]-alt-5,5 '-(
• heteroarenes including those substituted with alkylcarbonyl, arylcarbonyl, cyano and/or alkyl groups also can be suitable n-type semiconductor materials for use according to the present teachings.
• inorganic n-type OSCs can be used.
• solution- processable metal oxides e.g., ITO, indium oxide, indium zinc oxide, indium gallium zinc oxide
• chalcogenides e.g., CdSe
• Suitable materials for the hole transport (p-type) sublayer can include one class of p- type organic semiconductors (OSCs) that relates to oligothiophenes and polythiophenes.
• OSCs p- type organic semiconductors
• a dihexylquaterhiophene and other alkyl-substituted thiophene oligomers are described in Gamier et al., "Dihexylquaterthiophene, A Two-Dimensional Liquid Crystal- Like Organic Semiconductor with High Transport Properties," Chem. Mater., 10 (11): 3334- 3339 (1998).
• Polythiophenes such as regioregular poly(3-hexylthiophene) (rr-P3HT) also can be used.
• Another class of p-type OSCs relates to soluble pentacene compounds such as those described in U.S. Patent No. 7,125,989.
• Soluble pentacene compounds as exemplified by pentacene-N-sulfinyl-tert-butylcarbamate, can be obtained from Diels-Alder reaction of pentacene with hetero dienophiles.
• Another pentacene derivative, 6,13-bis(triisopropyl- silylethynyl)pentacene (TIPS pentacene) also has been shown to have reasonable solubility in common organic solvents.
• thienocoronene-based compounds described in International Publication No. WO2012/030662. Specific examples include 1PB- thienocoronene, 2BO-thienocoronene, IMP-thienocoronene, (S)-2MB-thienocoronene, undecanoxy-thienocoronene, and dodecyl-thienocoronene.
• naphtha[2,l-b:6,5-b']difuran A Versatile Motif Available for Solution-Processed Single- Crystal Organic Field-Effect Transistors with High Hole Mobility
• J. Am. Chem. Soc, 134: 5448-5451 (2012) Yet another class of small molecule p-type OSCs relates to fluorinated anthradithiophene derivatives. See Subramanian et al, "Chromophore Fluorination Enhances Crystallization and Stability of Soluble Anthradithiophene Semiconductors," J. Am. Chem. Soc, 130(9): 2706-2707 (2008).
• p-type semiconductors include phthalimide-based polymers, certain diketopyrrolopyrrole-based polymers, isoindigo-based conjugated polymers, See International Publication No. WO2010/117449; Li et al, "A High Mobility P- Type DPP-Thieno[3,2-b]thiophene Copolymer for Organic Thin-Film Transistors," Adv. Mater., 22: 4862-4866 (2010), Li et al, "Annealing-Free High-Mobility
• hetero arenes including those substituted with alkyl and/or alkoxy groups also can be suitable p-type semiconductor materials for use according to the present teachings.
• the energy difference between the highest occupied molecular orbital (HOMO) of the hole-transporting semiconductor material and the lowest unoccupied molecular orbital (LUMO) of the electron-transporting semiconductor material should be, at a minimum, between about 1.6V and about 1.8 eV.
• the energy difference between the HOMO of the hole -transporting semiconductor material and the LUMO of the electron-transporting semiconductor material has to be, at a minimum, between about 2.2 eV and about 2.5 eV.
• the energy difference between the HOMO of the hole- transporting semiconductor material and the LUMO of the electron-transporting semiconductor material has to be, at a minimum, between about 2.8 eV and about 3.2 eV.
• the emissive sublayer can be a blend that includes a host material and a guest emitter selected from a fluorescent emitter and a phosphorescent emitter.
• the emissive sublayer can be prepared from a single-component host- emitting material. Suitable organic electroluminescent light-emitting materials include those having been used in OLED applications.
• the emissive sublayer can be composed of a blend of host tris(8-hydroxyquinolinato)aluminium (Alq 3 ) and guest 4- (dicyanomethylene)-2-methyl-6-(p-dimethylaminostyryl)-4H-pyran (DCM).
• Some exemplary host materials include polymers such as poly(/?-phenylene vinylene), poly(alkyphenylphenylvinylene), poly(alkyphenylphenylvinylene-co- alkoxyphenylenevinylene), polyfluorene, poly(n-vinylcarbazole), and copolymers thereof.
• polymers such as poly(/?-phenylene vinylene), poly(alkyphenylphenylvinylene), poly(alkyphenylphenylvinylene-co- alkoxyphenylenevinylene), polyfluorene, poly(n-vinylcarbazole), and copolymers thereof.
• Various carbazole compounds, triphenylamine compounds, including hybrids with oxadiazole or benzimidazole also have been used as host materials.
• Some exemplary guest emitters include fluorescent dyes such as various perylene derivatives, anthracene derivatives, rubrene derivatives, carbazole dervatives, fluorene derivatives, and quinacridone derivatives, and phosphorescent emitters such as various transition metal complexes including Ir, Os, or Pt.
• Some exemplary host-emitting materials include phosphorescent host-emitting compounds based on carbazole derivatives, fluorene derivatives, or 9-naphthylanthracene derivatives, and fluorescent host-emitting compounds based on organometallic chelates such as tris(8-quinolinol) aluminum complexes.
• the hole and electron injection layers can be prepared by self-assembly of thiolates, phosphonates, or aliphatic or aromatic carboxylates; by thermal evaporation of various charge transfer complexes and other heteroaromatic or organometallic complexes; or by thermal evaporation or sputtering of various metal oxides, fluorides, or carbonates.
• the hole injection layer and the electron injection layer can be made of materials that provide a staircase of electronic levels between the energy level of the hole electrode and the electron electrode, and the energy level required for injection into the hole transport sublayer and the electron transport sublayer, respectively.
• the present OLETs can be operated by applying a first appropriate bias voltage to the gate electrode, and injecting electrons from the electron electrode and holes from the hole electrode, while maintaining a second bias voltage between the latter two electrodes.
• the first and second bias voltages can be continuous voltages. Alternatively, the first and second bias voltages also can be pulsed voltages.
• a plurality of OLETs according to the present teachings can be arranged in a matrix to provide a display device.
• the display device can include optional driving and switching elements, compensating transistor elements, capacitors, and/or light-emitting diodes.

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