Classifications

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  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K50/00—Organic light-emitting devices
  • H10K50/30—Organic light-emitting transistors
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  • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
  • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
  • H10H20/062—Light-emitting semiconductor devices having field effect type light-emitting regions, e.g. light-emitting High-Electron Mobility Transistors
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  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K50/00—Organic light-emitting devices
  • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
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  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K50/00—Organic light-emitting devices
  • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
  • H10K50/11—OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers
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  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K50/00—Organic light-emitting devices
  • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
  • H10K50/14—Carrier transporting layers
  • H10K50/15—Hole transporting layers
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  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K50/00—Organic light-emitting devices
  • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
  • H10K50/14—Carrier transporting layers
  • H10K50/16—Electron transporting layers
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  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K50/00—Organic light-emitting devices
  • H10K50/80—Constructional details
  • H10K50/805—Electrodes
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  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
  • H10K2102/301—Details of OLEDs
  • H10K2102/302—Details of OLEDs of OLED structures
  • H10K2102/3023—Direction of light emission
  • H10K2102/3035—Edge emission
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  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
  • H10K85/60—Organic compounds having low molecular weight
  • H10K85/631—Amine compounds having at least two aryl rest on at least one amine-nitrogen atom, e.g. triphenylamine
  • H10K85/636—Amine compounds having at least two aryl rest on at least one amine-nitrogen atom, e.g. triphenylamine comprising heteroaromatic hydrocarbons as substituents on the nitrogen atom

Definitions

• OLED organic light- emitting diodes
• OLET Organic light-emitting transistor
• electroluminescent light-emitting material has been shown to achieve much higher external quantum efficiency (EQE) in an OLET than in an equivalent OLED.
• a trilayer heterostructure OLET has been reported with a maximum EQE of about 5%.
• the reported trilayer heterostructure OLET includes, from bottom to top, a transparent substrate, a gate electrode, a gate dielectric, an active layer consisting of the superposition of three organic layers, and source and drain electrodes on top of the active layer.
• the trilayer active layer includes a light-emitting host-guest matrix sandwiched between an electron-transporting (n-type) semiconductor and a hole-transporting (p-type) semiconductor.
• n-type electron-transporting
• p-type hole-transporting
• the present teachings provide light-emitting transistors having novel structures that can lead to enhanced device brightness, specifically, via new arrangements of electrodes that can favor charge injection from the electrodes, carrier recombination, and exciton formation.
• the present teachings provide a light-emitting transistor that includes a substrate, a gate electrode, a channel layer including one or more organic sublayers, a dielectric layer positioned between the gate electrode and the channel layer, and a hole electrode and an electron electrode that independently are coupled to the channel layer but are positioned relative to each other in a staggered or nonplanar configuration.
• the channel layer can have a first side and a second side, and each of the hole electrode and the electron electrode can be positioned either within the channel layer or on top of the first side of the channel layer.
• the hole electrode is positioned away from the second side of the channel layer at a distance dl and the electron electrode is positioned away from the second side of the channel layer at a distance d2 that is different from dl .
• the channel layer can include one or more organic sublayers, typically including an electron transport sublayer comprising an electron- transporting (n-type) semiconductor material, a hole transport sublayer comprising a hole- transporting (p-type) semiconductor material, and an emissive sublayer comprising an organic electroluminescent semiconductor material that is sandwiched between the electron transport sublayer and the hole transport sublayer.
• organic sublayers typically including an electron transport sublayer comprising an electron- transporting (n-type) semiconductor material, a hole transport sublayer comprising a hole- transporting (p-type) semiconductor material, and an emissive sublayer comprising an organic electroluminescent semiconductor material that is sandwiched between the electron transport sublayer and the hole transport sublayer.
• the n-type semiconductor material and the p-type semiconductor material can be selected from organic semiconductor materials (e.g., small molecule semiconductors, polymeric semiconductors, or combinations thereof) and inorganic semiconductor materials (e.g., metal oxides or chalcogenides).
• organic semiconductor materials e.g., small molecule semiconductors, polymeric semiconductors, or combinations thereof
• inorganic semiconductor materials e.g., metal oxides or chalcogenides
• one of the hole electrode and the electron electrode can be positioned on top of the channel layer, while the other of the hole electrode and the electron electrode can be positioned within the channel layer. In other embodiments, the hole electrode and the electron electrode can be positioned in a different sublayer within channel layer. [0009] In certain embodiments, one of the hole electrode and the electron electrode can be positioned within the first sublayer (e.g., the hole transport sublayer), while the other of the hole electrode and the electron electrode can be positioned within the third sublayer (the emissive sublayer) and in contact with the first sublayer.
• the first sublayer e.g., the hole transport sublayer
• the other of the hole electrode and the electron electrode can be positioned within the third sublayer (the emissive sublayer) and in contact with the first sublayer.
• one of the hole electrode and the electron electrode can be positioned within the first sublayer, while the other of the hole electrode and the electron electrode can be positioned within the third sublayer but not in contact with the first sublayer. In certain embodiments, one of the hole electrode and the electron electrode can be positioned within the first sublayer, and the other of the hole electrode and the electron electrode can be positioned on top of the channel layer and in contact with the second sublayer (e.g., the electron transport sublayer).
• one of the hole electrode and the electron electrode can be positioned within the third sublayer and in contact with the first sublayer, and the other of the hole electrode and the electron electrode can be positioned within the third sublayer but not in contact with the first sublayer. In certain embodiments, one of the hole electrode and the electron electrode can be positioned within the third sublayer and in contact with the first sublayer, while the other of the hole electrode and the electron electrode can be positioned within the second sublayer. In certain embodiments, one of the hole electrode and the electron electrode can be positioned within the third sublayer and in contact with the first sublayer, while the other of the hole electrode and the electron electrode can be positioned on top of the channel layer and in contact with the second sublayer.
• one of the hole electrode and the electron electrode can be positioned within the second sublayer and in contact with the third sublayer, while the other of the hole electrode and the electron electrode can be positioned within the third sublayer. In certain embodiments, one of the hole electrode and the electron electrode can be positioned within the second sublayer and in contact with the third sublayer, while the other of the hole electrode and the electron electrode can be positioned on top of the channel layer and in contact with the second sublayer.
• one of the hole electrode and the electron electrode can be positioned on top of the first channel layer and in contact with the second sublayer, while the other of the hole electrode and the electron electrode can be positioned within the third sublayer.
• the present OLET can further include an electron-injection layer deposited between the electron transport sublayer and the electron electrode.
• the present OLET can further include a hole-injection layer deposited between the hole transport sublayer and the hole electrode.
• the present OLET can have a bottom-gate structure, wherein the gate electrode is coupled to the substrate.
• the present OLET can have a top-gate structure, wherein the channel layer is coupled to the substrate.
• the gate electrode can have a length (L G ) that is identical to L, and wherein the edges of the gate electrode are aligned with an edge of the hole electrode and an edge of the electron electrode. In other embodiments, the gate electrode can have a length (L G ) that is greater than L, and wherein at least one edge of the gate electrode overlaps with one of the hole electrode and the electron electrode.
• the hole electrode can be positioned in contact with the hole transport sublayer, and the electron electrode can be positioned in contact with the electron transport sublayer, to minimize contact resistance.
• the present teachings provide a light-emitting transistor that includes a substrate, a gate electrode, a channel layer including one or more organic sublayers, a dielectric layer positioned between the gate electrode and the channel layer, and a hole electrode and an electron electrode that are coupled to the channel layer and are spaced apart from each other to define a channel region having a length (L), wherein the gate electrode is not aligned with the channel region.
• the gate electrode is offset from an edge of either the hole electrode or the electron electrode towards the other of the hole electrode and the electron electrode such that the gate electrode overlaps partially or entirely with the other of the hole electrode and the electron electrode (i.e., occupying the same space or an overlapping space but on a different plane within the vertical stack).
• the gate electrode can include a length (L G ) that is identical to or greater than L, and the gate electrode is positioned in a way such that an edge of the gate electrode is spaced apart from an edge of the hole electrode at a planar distance (d) that is greater than 0 but less than or equal to L, thereby resulting in an overlap with electron electrode.
• the present OLET with the offset gate electrode can include coplanar hole and electron electrodes.
• the present OLET with the offset gate electrode can include nonplanar hole and electron electrodes.
• the present OLET can have a gate electrode that overlaps with the electron electrode, and wherein the electron electrode is positioned on top of the electron transport sublayer while the hole electrode can be either coplanar with the electron electrode, or deposited on the emissive sublayer and in contact with the electron transport sublayer, or deposited within the emissive sublayer, or deposited on the hole transport sublayer and in contact with the emissive sublayer, or deposited on the dielectric layer in contact with the hole transport layer.
• the present OLET can have a gate electrode that overlaps with the electron electrode, and wherein the electron electrode is positioned within the electron transport sublayer, while the hole electrode can be either positioned on top of the channel layer, or coplanar with the electron electrode, or deposited within the emissive sublayer, or deposited on the hole transport sublayer and in contact with the emissive sublayer, or deposited on the dielectric layer in contact with the hole transport layer.
• the present OLET can have a gate electrode that overlaps with the electron electrode, and wherein the electron electrode is positioned within the emissive sublayer, while the hole electrode can be either positioned on top of the channel layer, or positioned within the electron transport sublayer, or coplanar with the electron electrode, or deposited on the hole transport sublayer and in contact with the emissive sublayer, or deposited on the dielectric layer in contact with the hole transport layer.
• the present OLET can have a gate electrode that overlaps with the electron electrode, and wherein the electron electrode is deposited on the electron transport sublayer in contact with the emissive sublayer, while the hole electrode can be either positioned on top of the channel layer in contact with the hole transport sublayer, or positioned within the hole transport sublayer, or deposited within the emissive layer, or coplanar with the electron electrode, or deposited on the dielectric layer in contact with the electron transport layer.
• the hole transport sublayer can be the top sublayer, and the electron transport sublayer can be in contact with the dielectric layer.
• the present OLET can have a gate electrode that overlaps with the electron electrode, and wherein the electron electrode is deposited on the dielectric layer in contact with the electron transport sublayer, while the hole electrode can be either positioned on top of the channel layer in contact with the hole transport sublayer, or positioned within the hole transport sublayer, or deposited within the emissive layer, or deposited on the electron transport sublayer in contact with the emissive sublayer, or coplanar with the electron electrode.
• the hole transport sublayer can be the top sublayer, and the electron transport sublayer can be in contact with the dielectric layer.
• the present OLET can have a hole electrode and an electron electrode that are positioned in a nonplanar arrangement, and a gate electrode that is offset from the channel region to overlap with either the hole electrode and the electron electrode.
• the hole electrode can be positioned in contact with the hole transport sublayer, and the electron electrode can be positioned in contact with the electron transport sublayer, to minimize contact resistance.
• the gate electrode in a bottom-gate configuration can be offset to overlap with the hole electrode or the electron electrode that is positioned further away from the dielectric layer.
• a hole injection layer can be positioned between the hole electrode and the hole transport sublayer, and an electron injection layer can be positioned between the electron electrode and the hole transport sublayer.
• any of the electrodes and/or any of the sublayers of the channel layer of the present OLETs can be fabricated by a process selected from the group consisting of thermal evaporation, sputtering, atomic layer deposition, chemical vapor deposition, solution processing, spin-coating, spray coating, slot die coating, and printing.
• Figure 1 shows a cross section view of (a) a prior art top-contact light-emitting transistor 10, wherein coplanar source and drain contacts (hole and electron electrodes 12, 14) are positioned on top of the active layer 8 and (b) a prior art bottom-contact light emitting transistor 20, wherein coplanar source and drain contacts (hole and electron electrodes 12, 14) are positioned within (underneath) the active layer 8.
• Figure 2 shows a cross section view of (a) a bottom-gate light-emitting transistor 100 and (b) a top-gate light-emitting transistor 200 according to the present teachings, wherein the source and drain contacts (hole and electron electrodes 12, 14) are offset vertically from each other.
• Figure 3 illustrates different embodiments of OLETs according to the present teachings, wherein the hole electrode 12 is positioned within the hole transport sublayer 8a, and the electron electrode 14 is positioned (a and b) within the emissive sublayer 8b, (c) within the electron transport sublayer 8c, or (d) on top of the channel layer in contact with the electron transport sublayer 8c.
• Figure 4 illustrates different embodiments of OLETs according to the present teachings, wherein the hole electrode 12 is positioned within the emissive sublayer 8b in contact with the hole transport sublayer 8a, and the electron electrode 14 is positioned (a) within the hole transport sublayer 8a, (b) within the emissive sublayer 14 but not in contact with the hole transport sublayer 8a, (c) within the electron transport sublayer 8c, or (d) on top of the channel layer 8 in contact with the electron transport sublayer 8c.
• Figure 5 illustrates different embodiments of OLETs according to the present teachings, wherein the hole electrode 12 is positioned within the hole transport sublayer 8a, and the electron electrode 14 is positioned (a) within the electron transport sublayer 8c, (b and c) within the emissive sublayer 8b, or (d) on top of the channel layer 8.
• the hole transport sublayer 8a is the top sublayer
• the electron transport sublayer 8c is in contact with the dielectric layer 6.
• Figure 6 illustrates different embodiments of OLETs according to the present teachings, wherein the hole electrode 12 is positioned on top of the channel layer 8 in contact with the hole transport layer 8a, and the electron electrode is positioned (a) within the electron transport sublayer 8c, (b and c) within the emissive sublayer 8b, or (d) within the hole transport sublayer 8a.
• the hole transport sublayer 8a is the top sublayer
• the electron transport sublayer 8c is in contact with the dielectric layer 6.
• Figure 7 compares the charge transport/light generating mechanisms of (a) a conventional trilayer OLET against (b) a trilayer OLET according to the present teachings.
• Figure 8 illustrates how a nonplanar source-drain electric field can lead to increased exciton formation.
• Figure 9 shows a cross section view of a light-emitting transistor according to the present teachings, wherein the gate electrode overlaps with one of the source and drain contacts (or one of the hole and electron electrodes).
• Figure 10 illustrates different embodiments of OLETs according to the present teachings having a gate electrode 4 that overlaps with the electron electrode 14, and wherein the electron electrode 14 is positioned on top of the electron transport sublayer 8c while the hole electrode 12 is (a) coplanar with the electron electrode 14, (b) deposited on the emissive sublayer 8b and in contact with the electron transport sublayer 8c, (c) deposited within the emissive sublayer 8b, (d) deposited on the hole transport sublayer 8a and in contact with the emissive sublayer 8b, and (e) deposited on the dielectric layer 6 in contact with the hole transport layer 8a.
• Figure 11 illustrates different embodiments of OLETs according to the present teachings having a gate electrode 4 that overlaps with the electron electrode 14, and wherein the electron electrode 14 is positioned within the electron transport sublayer 8c, while the hole electrode 12 is (a) positioned on top of the channel layer 8, (b) coplanar with the electron electrode 14, (c) deposited within the emissive sublayer 8b, (d) deposited on the hole transport sublayer 8a and in contact with the emissive sublayer 8b, and (e) deposited on the dielectric layer 6 in contact with the hole transport layer 8a.
• Figure 12 illustrates different embodiments of OLETs according to the present teachings having a gate electrode 4 that overlaps with the electron electrode 14, and wherein the electron electrode 14 is positioned within the emissive sublayer 8b, while the hole electrode 12 is (a) positioned on top of the channel layer 8, (b) positioned within the electron transport sublayer 8c, (c) coplanar with the electron electrode 14, (d) deposited on the hole transport sublayer 8a and in contact with the emissive sublayer 8b, and (e) deposited on the dielectric layer 6 in contact with the hole transport layer 8a.
• Figure 13 illustrates different embodiments of OLETs according to the present teachings having a gate electrode 4 that overlaps with the electron electrode 14, and wherein the electron electrode 14 is deposited on the electron transport sublayer 8c in contact with the emissive sublayer 8b, while the hole electrode 12 is (a) positioned on top of the channel layer in contact with the hole transport sublayer 8a, (b) positioned within the hole transport sublayer 8a, (c) deposited within the emissive layer 8b, (d) coplanar with the electron electrode 14, and (e) deposited on the dielectric layer 6 in contact with the electron transport layer 8c.
• the hole transport sublayer 8a is the top sublayer
• the electron transport sublayer 8c is in contact with the dielectric layer 6.
• Figure 14 illustrates different embodiments of OLETs according to the present teachings having a gate electrode 4 that overlaps with the electron electrode 14, and wherein the electron electrode 14 is deposited on the dielectric layer 6 in contact with the electron transport sublayer 8c, while the hole electrode 12 is (a) positioned on top of the channel layer in contact with the hole transport sublayer 8a, (b) positioned within the hole transport sublayer 8a, (c) deposited within the emissive layer 8b, (d) deposited on the electron transport sublayer 8c in contact with the emissive sublayer 8b, and (e) coplanar with the electron electrode 14.
• the hole transport sublayer 8a is the top sublayer
• the electron transport sublayer 8c is in contact with the dielectric layer 6.
• Figure 15 compares the carrier density within the charge transport layers in (a) a conventional trilayer OLET against (b) a trilayer OLET according to the present teachings.
• Figure 16 illustrates how an offset gate electrode can lead to dissimilar charge accumulations for holes and electrons, which can result in a greater probability for charges to recombine.
• Figure 17 illustrates an embodiment of the present OLET that includes a hole injection layer 32 and an electron injection layer 34.
• compositions are described as having, including, or comprising specific components, or where processes are described as having, including, or comprising specific process steps, it is contemplated that compositions of the present teachings also consist essentially of, or consist of, the recited components, and that the processes of the present teachings also consist essentially of, or consist of, the recited process steps.
• a "p-type semiconductor material,” “p-type semiconductor” or a “p-type OSC” refers to a semiconductor material or a semiconducting compound having holes as the majority current or charge carriers.
• a p-type semiconductor material when deposited on a substrate, it can provide a hole mobility in excess of about 10 "5 cm 2 /Vs.
• a p-type semiconductor can also exhibit a current on/off ratio of greater than about 10.
• a p-type OSC can be characterized by a highest occupied molecular orbital (HOMO) energy that is higher than or about -6.4 V, preferably higher than or about -6.2 V, and more preferably, higher than or about -6.0 V.
• HOMO highest occupied molecular orbital
• an "n-type semiconductor material,” an “n-type semiconductor” or an “n-type OSC” refers to a semiconductor material or a semiconducting compound having electrons as the majority current or charge carriers.
• an n-type semiconductor material when deposited on a substrate, it can provide an electron mobility in excess of about 10 "5 cm 2 /Vs.
• an n-type semiconductor can also exhibit a current on/off ratio of greater than about 10.
• an n-type OSC can be characterized by a lowest unoccupied molecular orbital (LUMO) energy that is lower than or about -3.2 V, preferably lower than or about -3.6 V, and more preferably, lower than or about -4.0 V.
• LUMO lowest unoccupied molecular orbital
• “mobility” refers to a measure of the velocity with which charge carriers, for example, holes (or units of positive charge) in the case of a p-type semiconductor material and electrons (or units of negative charge) in the case of an n-type semiconductor material, move through the material under the influence of an electric field. This parameter, which depends on the device architecture, can be measured using a field-effect device or space-charge current measurements.
• solution-processable refers to compounds, materials, or compositions that can be used in various solution-phase processes including spin-coating, printing (e.g., inkjet printing, screen printing, pad printing, offset printing, gravure printing, flexographic printing, lithographic printing, mass-printing and the like), spray coating, electrospray coating, drop casting, dip coating, and blade coating.
• printing e.g., inkjet printing, screen printing, pad printing, offset printing, gravure printing, flexographic printing, lithographic printing, mass-printing and the like
• spray coating e.g., inkjet printing, screen printing, pad printing, offset printing, gravure printing, flexographic printing, lithographic printing, mass-printing and the like
• electrospray coating e.g., electrospray coating, drop casting, dip coating, and blade coating.
• a conventional organic light-emitting transistor typically has a vertically stacked structure that includes a substrate 2, a gate electrode 4, a dielectric layer 6 in contact with the gate electrode, an active channel layer 8, and a hole electrode 12 and an electron electrode 14 that are in contact with the active channel layer.
• the active channel layer can include one or more organic semiconductor materials that individually or in combination can perform the function of electron transport, hole transport, and light emission.
• the active channel layer 8 can include sublayers 8a and 8c which, respectively, are adapted to allow transport of charge carriers of opposite types, and sublayer 8b
• sublayers 8a and 8c sandwiched between sublayers 8a and 8c which is adapted to facilitate recombination of holes and electrons to generate light.
• conventional OLETs have coplanar hole electrode 12 and electron electrode 14 through which positive charge carriers (holes) and negative charge carriers (electrons), respectively, are injected into the active channel layer 8.
• the hole electrode 12 and the electron electrode 14 can be deposited on top of the active channel layer 8 as illustrated in the top-contact device 10 shown in Figure la, or the active channel layer 8 can be deposited over the hole electrode 12 and the electron electrode 14 as illustrated in the bottom-contact device 20 shown in Figure lb.
• the in-plane hole and electron electrodes are spaced apart at a distance that defines the length of the channel region.
• the gate electrode 4 typically has a length approximating the channel length and is aligned with the channel region.
• the present teachings relate to OLETs having novel architectures characterized by (1) non-planar hole electrode and electron electrode and/or (2) a gate electrode which is offset from the channel region.
• the present OLETs can exhibit enhanced device brightness compared to conventional OLETs as explained in more detail below.
• an aspect of the present teachings relates to OLETs having nonplanar hole electrode and electron electrode.
• the hole electrode and the electron electrode can function, respectively, as the source electrode and the drain electrode (or vice versa) depending on the polarity of the gate voltage.
• the source electrode is typically grounded (0 V)
• the gate voltage is -100V and the drain voltage is -80V
• the source electrode is the hole electrode (negatively biased) and the drain electrode is the electron electrode (positively biased).
• the gate voltage is +100V
• the source electrode is the electron electrode and the drain electrode is the hole electrode. Therefore, the present OLETs also can be described as having nonplanar source electrode and drain electrodes.
• an OLET 100 can have a hole electrode 12 and an electron electrode 14 that are offset vertically from each other.
• both the hole electrode 12 and the electron electrode 14 typically are positioned either on top of a first side 16 of the channel layer 8 or in contact with a second side 18 of the channel layer 8.
• dl refers to the distance from which the hole electrode is positioned away from the second side 18 of the channel layer
• d2 refers to the distance from which the electron electrode is positioned away from the second side 18 of the channel layer
• sublayer 8a can comprise a first
• the hole electrode 12 and the electron electrode 14 can be positioned within different sublayers of the channel layer 8.
• dl can be 0 (within sublayer 8a in contact with the second side 18 of the channel layer 8), while d2 can be dsi (within sublayer 8b in contact with sublayer 8a) or d2 can be dsi + ⁇ 1E (within sublayer 8c in contact with sublayer 8b).
• the gate electrode can have a length (L G ) equal to or greater than the channel length (L), which is the distance between the edge 22 of the hole electrode 12 adjacent to the channel region and the edge 24 of the electron electrode 24 adjacent to the channel region.
• the gate electrode can have a length LG that is the same as the length of the channel region L and can be located within a space that is aligned with the channel region.
• the gate electrode 4 can be deposited on the substrate 2, and the dielectric layer 6 can be formed over the gate electrode 4.
• the hole electrode 12 and the electron electrode 14 can be patterned on the dielectric layer 6 in a way such that an edge 22 of the hole electrode 12 and an edge 24 of the electron electrode 14 are aligned with the edges of the gate electrode 4.
• the hole electrode 12 and the electron electrode 14 first can be patterned on the substrate 2.
• the active channel layer 8 can be formed (e.g. via sequential deposition of sublayers 8a, 8b, and 8c) over the hole electrode 12 and the electron electrode 14, followed by the deposition of the dielectric layer 6 over the channel layer 8.
• the gate electrode 4 can be patterned on the dielectric layer, such that the edges of the gate electrode 4 are aligned with an edge 22 of the hole electrode 12 and an edge 24 of the electron electrode 14.
• L can be between about 2 ⁇ and about 500 ⁇ , preferably between about 5 ⁇ and about 20 ⁇ .
• the hole electrode and the electron electrode, respectively can have a length Ls and a length LD that independently are between about 50 ⁇ and about 300 ⁇ , preferably between about 100 ⁇ and about 200 ⁇ .
• the overlap b and b' of the gate electrode with either the hole electrode and/or the electron electrode can be 0 um and up to the length (Ls or LD) of the hole electrode and/or the electron electrode (i.e., 0 ⁇ b ⁇ L s , 0 ⁇ b' ⁇ L D ), but preferably, the overlap is between about 0 ⁇ and about 100 ⁇ .
• the length L G of the gate electrode can be between about 50 ⁇ and about 500 ⁇ , preferably between about 100 ⁇ and about 200 ⁇ .
• the thickness dsi and ds 2 of the two charge transport sublayers can be between about 5 ⁇ and about 100 ⁇ , whereas the thickness ⁇ 1E of the emissive sublayer can be between about 2 ⁇ and about 50 ⁇ .
• Figures 3-6 illustrate various embodiments of OLETs having nonplanar hole and electron electrodes according to the present teachings.
• the source-drain electric field spans across the emissive sublayer 8b (as indicated by the direction of the arrow), that is, both hole and electron currents flow into the emissive sublayer. This results in a much greater probability for holes and electrons to meet in the emissive sublayer to form a larger number of excitons 26. Furthermore, referring back to Figure 7a, because both the hole electrode and the electron electrode are deposited on the same surface and are in contact with a sublayer that favors the transport of only one type of charge carriers, large contact resistance inevitably results for one of the contacts.
• the contact resistance can be reduced drastically by positioning the hole electrode 12 in contact with sublayer 8a composed of a p-type semiconductor which facilitates hole transport, and positioning the electron electrode 14 in contact with sublayer 8c composed of an n-type semiconductor which facilitates electron transport.
• OLETs having a gate electrode offset from the channel region, such that the gate electrode overlaps in the same vertical space with either the hole electrode or the electron electrode, but not both of them.
• the gate electrode typically has a length LG that is the same as the length of the channel region L, and the gate electrode is located within a space that is aligned with the channel region.
• the gate electrode 4 is offset from the edge 22 of the hole electrode 12 or the edge 24 of the electron electrode 14, so that the gate electrode overlaps with either the hole electrode 12 or the electron electrode 14.
• the gate electrode 4 can be offset from the edge 22 of the hole electrode 12 by a distance LI, such that the gate electrode 4 overlaps with the electron electrode 14 by a distance L2 (as measured from the edge 24 of the electron electrode 14).
• the length of the gate electrode LG can approximate the length of the hole electrode (Ls) or the length of the electron electrode (L D ), which typically are between about 50 ⁇ and about 300 ⁇ , preferably between about 100 ⁇ and about 200 ⁇ .
• the gate electrode can have a length LG that is slightly longer or shorter than either Ls or LD, provided that LG ⁇ L + Ls or L + LD.
• the offset distance LI is greater than 0 and can be equal to L, i.e., 0 ⁇ LI ⁇ L. In some embodiments, LI can be 0.5 L. In preferred
• the gate electrode 4 can be offset from the edge 24 of the electron electrode 14, such that it overlaps with the hole electrode 12.
• the hole electrode 12 and the electron electrode 14 are not in the same plane, i.e., dl ⁇ d2, as described hereinabove.
• FIGS 10-14 illustrate various embodiments of OLETs having a gate electrode overlapping with the electron electrode according to the present teachings.
• the gate electrode can be positioned to overlap with the hole electrode analogously.
• the charge transport layer that is farther away from the dielectric layer has a lower carrier mobility due to poorer morphology.
• the hole transport sublayer 8a is the top layer.
• the gate electrode 4 can be offset to overlap with the hole electrode 12.
• OLETs described herein can further include charge injection layers.
• a hole injection layer 32 can be deposited between the hole transport sublayer 8a and the hole electrode 12, and an electron injection layer 34 can be deposited between the electron electrode 14 and the electron transport sublayer 8c.
• the present OLET can include a staggered source-drain architecture with an offset gate electrode, in which the hole electrode 12 is positioned in contact with the hole transport sublayer 8a, and the electron electrode 14 is positioned in contact with the electron transport sublayer 8c.
• an example of such embodiments is illustrated in Figure 17.
• the gate electrode 4 can be positioned to overlap with the electrode that is located on the top most surface which, in the embodiment shown in Figure 17, is the hole electrode 12. This helps to compensate for the lower charge carrier mobility attributed to the top most semiconductor layer due to the expected poorer film morphology.
• the electrodes can be coated with a hole injection layer 32 and an electron injection layer 34, respectively, to further reduce contact resistance. In this configuration, it is desirable that the gate electrode (or the overlapping electrode) is a transparent electrode because it is expected that most of the light being generated will be close to the electrodes.
• OLETs can be fabricated using various deposition processes known in the art.
• an optional planarization or surface-modifying layer can be formed onto a transparent substrate, e.g., by spin-coating.
• a metallic thin film can be thermally evaporated thereon, followed by etching or other patterning techniques to form the gate electrode.
• the dielectric layer depending on its composition, can be deposited by a solution-phase process such as spin- coating or by chemical or physical vapor deposition. This can be followed by the formation of the active channel layer via sequential deposition of the first charge transport sublayer, the emissive sublayer, and the second charge transport sublayer.
• the hole electrode and the electron electrode can be formed using similar or different techniques as the gate electrode. Additional techniques that can be used to form the channel layer and/or the dielectric layer include sputtering, ion-assisted deposition (IAD), chemical vapor deposition, physical vapor deposition, different types of printing techniques (e.g., flexo printing, litho printing, gravure printing, ink-jetting, pad printing, and so forth), drop casting, dip coating, doctor blading, roll coating, spray coating and spin-coating. In preferred embodiments, both the channel layer and the dielectric layer can be formed from a solution-phase process such as spin-coating, slot coating, spray coating or printing.
• Electrical contacts can be formed by processes such as, but not limited to, thermal evaporation and radiofrequency or e-beam sputtering, as well as various deposition processes, including but not limited to those described immediately above (e.g., flexo printing, litho printing, gravure printing, ink-jetting, pad printing, screen printing, drop casting, dip coating, doctor blading, roll coating, and spin-coating).
• processes such as, but not limited to, thermal evaporation and radiofrequency or e-beam sputtering, as well as various deposition processes, including but not limited to those described immediately above (e.g., flexo printing, litho printing, gravure printing, ink-jetting, pad printing, screen printing, drop casting, dip coating, doctor blading, roll coating, and spin-coating).
• the present OLETs can be fabricated on various substrates, including plastic, flexible substrates that have a low temperature resistance.
• flexible substrates include polyesters such as polyethylene terephthalate, polyethylene naphthalate, polycarbonate; polyolefms such as polypropylene, polyvinyl chloride, and polystyrene;
• the substrate can be a rigid transparent substrate such as glass, quartz and VYCOR®.
• Substrate-gate materials commonly used in thin-film transistors also can be used. Examples include doped silicon wafer, tin-doped indium oxide (ITO) on glass, tin-doped indium oxide on polyimide or mylar film, aluminum or other metals alone or coated on a polymer such as polyethylene terephthalate, a doped polythiophene, and the like.
• the source/drain electrodes (or hole/electron electrodes) as well as the gate electrode can be made using various deposition techniques.
• the electrodes can be deposited through a mask, or can be deposited then etched or lifted off (photolithography). Suitable deposition techniques include electrodeposition, vaporization, sputtering, electroplating, coating, laser ablation and offset printing, from metal or metal alloy including copper, aluminum, gold, silver, molybdenum, platinum, palladium, and/or nickel, or an electrically conductive polymer such as polyethylenethioxythiophene (PEDOT).
• PEDOT polyethylenethioxythiophene
• Charge carrier injection can be facilitated by the use of a material for the injection electrode (hole electrode or electron electrode) that has a low barrier against injection of a charge carrier type into the hole transport sublayer and the electron transport sublayer, respectively.
• the hole electrode can comprise at least one material selected from the group consisting of Au, indium tin oxide, Cr, Cu, Fe, Ag, poly(3,4-ethylenedioxthiophene) combined with poly(styrenesulfonate) (PEDOT:PSS), and a perovskite manganite (Rei_ x A x Mn03).
• the hole electrode and the electron electrode can be made of conductors with different work functions to favor both hole and electron injection.
• the dielectric layer can be composed of inorganic (e.g., oxides such as Si0 2 , A1 2 0 3 , or Hf0 2 ; and nitrides such as Si 3 N 4 ), organic (e.g., polymers such as polycarbonate, polyester, polyimide, polystyrene, polyhaloethylene, polymethylmethacrylate), or hybrid organic/inorganic materials.
• inorganic e.g., oxides such as Si0 2 , A1 2 0 3 , or Hf0 2 ; and nitrides such as Si 3 N 4
• organic e.g., polymers such as polycarbonate, polyester, polyimide, polystyrene, polyhaloethylene, polymethylmethacrylate
• hybrid organic/inorganic materials e.g., polymers such as polycarbonate, polyester, polyimide, polystyrene, polyhaloethylene, polymethylmethacrylate
• hybrid organic/inorganic materials e.g.,
• the dielectric layer can be formed via the growth of self-assembled nanodielectric materials (such as those described in Yoon et al, PNAS, 102 (13): 4678-4682 (2005), and Ha et al, Chem. Mater., 21(7): 1173-1175 (2009)); solution- processing of inorganic/organic hybrid materials (e.g., as described in Ha et al, J. Am. Chem. Soc, 132 (49): 17428-17434 (2010)); and low-temperature solution-processing of metal oxides (e.g., as described in International Publication Number WO 2012/103528).
• self-assembledielectric materials such as those described in Yoon et al, PNAS, 102 (13): 4678-4682 (2005), and Ha et al, Chem. Mater., 21(7): 1173-1175 (2009)
• solution- processing of inorganic/organic hybrid materials e.g., as described in Ha et al, J. Am. Chem. Soc
• the dielectric material can be in the form of a bilayer composed of different materials, for example, a combination of inorganic/organic materials, materials with different dielectric constants, or materials that can be processed by different techniques (e.g., solution- processing and vapor deposition).
• the channel layer can comprise small molecule materials, polymers, and/or metal complexes.
• Suitable materials for the electron transport (n-type) sublayer can include one class of n-type organic semiconductors (OSCs) that relates to oligomers, homopolymers or copolymers of thiophenes, particularly those substituted with fluorocarbons.
• OSCs n-type organic semiconductors
• ⁇ , ⁇ -diperfluorohexylquaterhiophenes and other fluorocarbon-substituted thiophene oligomers are described in U.S. Patent No. 6,585,914.
• n-type OSCs relates to fused ring tetracarboxylic diimides and their derivatives.
• cyanated perylene diimides and cyanated naphthalene diimides more specifically, N,N'-bis-substituted-(l,7 & l,6)-di-cyano-perylene-3,4:9,10- bis(dicarboximide)s and ⁇ , ⁇ ' -bis-substituted 2,6-dicyanonaphthalene-l,4,5,8- bis(dicarboximide)s such as those described in U.S. Patent Nos.
• n- type semiconductors include N,N'-bis(cyclohexyl)-( 1,7 & 1 ,6)-dicyano- perylene-3,4:9,10-bis(dicarboximide) (CN 2 PDI); N,N'-bis(lH-perfluorobutyl)-(l,7 & l,6)-di- cyano-perylene-3,4:9,10-bis(dicarboximide); N,N'-bis(n-octyl)-(l,7 & l,6)-di-cyano- perylene-3,4:9,10-bis(dicarboximide) (PDI-8CN 2 ); N,N'-bis(n-octyl)-2,6-di- cyanonaphthalene-l,4,5,8-
• n-type semiconductors relate to dicyanomethylene-substituted conjugated systems.
• U.S. Patent No. 7,928,249 describes dicyanomethylene- substituted fused ring compounds such as 2,8-di-(3-dodecylthien-2-yl)-indeno[l,2- b]fluorene-6,12-dimalonitrile; 2,8-dithien-2-yl-tetraphenylenedimalonitrile; and 2,8-di-(4'- dodecylthien-2'-yl]-4-dodecylthien-2-yl)-indeno[l,2-b]fluorene-6,12-dimalono-nitrile.
• Dicyanomethylene-substituted diketopyrrolopyrrole-containing quinoidal small molecules also have been investigated as n-type semiconductors. See Qiao et ah,
• Thionated aromatic bisimides also can be used as n-type semiconductors. Examples include those described in International Publication Nos. WO2011/082234 such as (S,S)- PDISi lMP, (S,S)-cw-PDIS 2 lMP, (S,S)-tra/?s-PDIS 2 lMP, (S,S)-PDIS 3 1MP, (S,S)-PDIS- 4 1MP, (S,S)-tra/?s-PDIS 2 lMhex, (R,R)-tra/?s-PDIS 2 lMhex, (S,R)-tra/?s-PDIS 2 lMhex, (R,S)- tra/?s-PDIS 2 lMhex, (R,S)-tra/?s-PDIS 2 lMhex, (R,R)-tra/?s-PDIS 2 lMhex, (R,R)-tra/?s-PDIS 2 lMhept, (S
• N-type semiconducting polymers also can be used according to the present teachings.
• n-type semiconducting polymers include oligomers, homopolymers and copolymers of naphthalenediimides described in U.S. Patent Application Publication No.
• US 2010/0326527 such as poly ⁇ N,N'-bis(2-ethylhexyl)-l,4,5,8-naphthalene diimide-2,6- diyl]-alt-5,5 '-(2,2'-bithiophene) ⁇ ; poly ⁇ N,N'-bis(2-ethylhexyl)-l ,4,5, 8-naphthalene diimide- 2,6-diyl]-alt-5,5'-(2,5-thiophene) ⁇ ; poly ⁇ N,N'-bis(2-octyldodecyl)-l,4,5,8-naphthalene diimide-2,6-diyl]-alt-5,5'-(2,2'-bithiophene) ⁇ ; poly ⁇ N,N'-bis(l-methylhexyl)-l,4,5,8- naphthalene diimide-2,6-diyl]-alt-5,5 '-(
• heteroarenes including those substituted with alkylcarbonyl, arylcarbonyl, cyano and/or alkyl groups also can be suitable n-type semiconductor materials for use according to the present teachings.
• inorganic n-type OSCs can be used.
• solution- processable metal oxides e.g., ITO, indium oxide, indium zinc oxide, indium gallium zinc oxide
• chalcogenides e.g., CdSe
• Suitable materials for the hole transport (p-type) sublayer can include one class of p- type organic semiconductors (OSCs) that relates to oligothiophenes and polythiophenes.
• OSCs p- type organic semiconductors
• a dihexylquaterhiophene and other alkyl-substituted thiophene oligomers are described in Gamier et al., "Dihexylquaterthiophene, A Two-Dimensional Liquid Crystal- Like Organic Semiconductor with High Transport Properties," Chem. Mater., 10 (11): 3334- 3339 (1998).
• Polythiophenes such as regioregular poly(3-hexylthiophene) (rr-P3HT) also can be used.
• Another class of p-type OSCs relates to soluble pentacene compounds such as those described in U.S. Patent No. 7,125,989.
• Soluble pentacene compounds as exemplified by pentacene-N-sulfinyl-tert-butylcarbamate, can be obtained from Diels-Alder reaction of pentacene with hetero dienophiles.
• Another pentacene derivative, 6,13-bis(triisopropyl- silylethynyl)pentacene (TIPS pentacene) also has been shown to have reasonable solubility in common organic solvents.
• thienocoronene-based compounds described in International Publication No. WO2012/030662. Specific examples include 1PB- thienocoronene, 2BO-thienocoronene, IMP-thienocoronene, (S)-2MB-thienocoronene, undecanoxy-thienocoronene, and dodecyl-thienocoronene.
• naphtha[2,l-b:6,5-b']difuran A Versatile Motif Available for Solution-Processed Single- Crystal Organic Field-Effect Transistors with High Hole Mobility
• J. Am. Chem. Soc, 134: 5448-5451 (2012) Yet another class of small molecule p-type OSCs relates to fluorinated anthradithiophene derivatives. See Subramanian et al, "Chromophore Fluorination Enhances Crystallization and Stability of Soluble Anthradithiophene Semiconductors," J. Am. Chem. Soc, 130(9): 2706-2707 (2008).
• p-type semiconductors include phthalimide-based polymers, certain diketopyrrolopyrrole-based polymers, isoindigo-based conjugated polymers, See International Publication No. WO2010/117449; Li et al, "A High Mobility P- Type DPP-Thieno[3,2-b]thiophene Copolymer for Organic Thin-Film Transistors," Adv. Mater., 22: 4862-4866 (2010), Li et al, "Annealing-Free High-Mobility
• hetero arenes including those substituted with alkyl and/or alkoxy groups also can be suitable p-type semiconductor materials for use according to the present teachings.
• the energy difference between the highest occupied molecular orbital (HOMO) of the hole-transporting semiconductor material and the lowest unoccupied molecular orbital (LUMO) of the electron-transporting semiconductor material should be, at a minimum, between about 1.6 eV and about 1.8 eV.
• the energy difference between the HOMO of the hole -transporting semiconductor material and the LUMO of the electron-transporting semiconductor material has to be, at a minimum, between about 2.2 eV and about 2.5 eV.
• the energy difference between the HOMO of the hole- transporting semiconductor material and the LUMO of the electron-transporting semiconductor material has to be, at a minimum, between about 2.8 eV and about 3.2 eV.
• the emissive sublayer can be a blend that includes a host material and a guest emitter selected from a fluorescent emitter and a phosphorescent emitter.
• the emissive sublayer can be prepared from a single-component host- emitting material. Suitable organic electroluminescent light-emitting materials include those having been used in OLED applications.
• the emissive sublayer can be composed of a blend of host tris(8-hydroxyquinolinato)aluminium (Alq 3 ) and guest 4- (dicyanomethylene)-2-methyl-6-(p-dimethylaminostyryl)-4H-pyran (DCM).
• Some exemplary host materials include polymers such as poly(/?-phenylene vinylene), poly(alkyphenylphenylvinylene), poly(alkyphenylphenylvinylene-co- alkoxyphenylenevinylene), polyfluorene, poly(n-vinylcarbazole), and copolymers thereof.
• polymers such as poly(/?-phenylene vinylene), poly(alkyphenylphenylvinylene), poly(alkyphenylphenylvinylene-co- alkoxyphenylenevinylene), polyfluorene, poly(n-vinylcarbazole), and copolymers thereof.
• Various carbazole compounds, triphenylamine compounds, including hybrids with oxadiazole or benzimidazole also have been used as host materials.
• Some exemplary guest emitters include fluorescent dyes such as various perylene derivatives, anthracene derivatives, rubrene derivatives, carbazole dervatives, fluorene derivatives, and quinacridone derivatives, and phosphorescent emitters such as various transition metal complexes including Ir, Os, or Pt.
• Some exemplary host-emitting materials include phosphorescent host-emitting compounds based on carbazole derivatives, fluorene derivatives, or 9-naphthylanthracene derivatives, and fluorescent host-emitting compounds based on organometallic chelates such as tris(8-quinolinol) aluminum complexes.
• the hole and electron injection layers can be prepared by self-assembly of thiolates, phosphonates, or aliphatic or aromatic carboxylates; by thermal evaporation of various charge transfer complexes and other heteroaromatic or organometallic complexes; or by thermal evaporation or sputtering of various metal oxides, fluorides, or carbonates.
• the hole injection layer and the electron injection layer can be made of materials that provide a staircase of electronic levels between the energy level of the hole electrode and the electron electrode, and the energy level required for injection into the hole transport sublayer and the electron transport sublayer, respectively.
• the OLETs according to the invention can be operated by applying a first appropriate bias voltage to the gate electrode, and injecting electrons from the electron electrode and holes from the hole electrode, while maintaining a second bias voltage between the latter two electrodes.
• the first and second bias voltages can be continuous voltages. Alternatively, the first and second bias voltages also can be pulsed voltages.
• a plurality of OLETs according to the present teachings can be arranged in a matrix to provide a display device.
• the display device can include optional driving and switching elements, compensating transistor elements, capacitors, and/or light-emitting diodes.

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