WO2014019227A1 - 一种液晶显示装置、阵列基板及其制作方法 - Google Patents

一种液晶显示装置、阵列基板及其制作方法 Download PDF

Info

Publication number
WO2014019227A1
WO2014019227A1 PCT/CN2012/079670 CN2012079670W WO2014019227A1 WO 2014019227 A1 WO2014019227 A1 WO 2014019227A1 CN 2012079670 W CN2012079670 W CN 2012079670W WO 2014019227 A1 WO2014019227 A1 WO 2014019227A1
Authority
WO
WIPO (PCT)
Prior art keywords
insulating layer
thin film
electrode
film transistor
conductive layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2012/079670
Other languages
English (en)
French (fr)
Inventor
陈政鸿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US13/582,746 priority Critical patent/US20140034952A1/en
Publication of WO2014019227A1 publication Critical patent/WO2014019227A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to a liquid crystal display device, an array substrate, and a method of fabricating the same.
  • the manufacturing process of the liquid crystal display panel is generally divided into an Array process, a Cell process, and a Module process.
  • the array process mainly produces a thin film transistor glass substrate (also referred to as an array substrate), which is the first process of the liquid crystal display panel manufacturing process, and the resulting thin film transistor glass substrate has a great influence on the subsequent process, and even Decide whether the LCD panel is good or bad.
  • the array process is typically subjected to a five-mask process (5PEP) to form a thin film transistor or the like on the glass without any impurities.
  • a first metal layer 11 is plated on the glass 1, and the first metal layer 11 is used to form a gate and a scan line as a thin film transistor;
  • Process SP2 forming an insulating layer on the first metal layer 11 (Isolator Layer 12, and forming a semiconductor layer 13 on the insulating layer 12 corresponding to the first metal layer 11 for forming the gate of the thin film transistor;
  • the third process SP3 the insulating layer 12 and the semiconductor layer 13
  • a second metal layer 14 is plated thereon for forming a data line, a source and a drain of the thin film transistor; and in a fourth process SP4, a semiconductor layer not covered by the second metal layer 14 and the second metal layer 14 13 and forming a passivation layer on the insulating layer 12 (Passivation Layer, PV) 15, and a via hole
  • the first metal layer 11 is used to form the gates of the scan lines and the thin film transistors
  • the second metal layer 14 is used to form the data lines, the sources and drains of the thin film transistors.
  • the scan lines and the data lines are interlaced with each other, so that the first metal layer 11 and the second metal layer 14 overlap to form overlapping regions that cross each other.
  • the overlapping structure of the first metal layer 11 and the second metal layer 14 is generally used in a large amount, so that the same signal is simultaneously transmitted to reduce The resistance of the signal line and test line and reduce the delay of the signal.
  • the via hole 151 is formed on the passivation layer 15, it is usually dry etching (Dry Etch) is carried out in such a manner that the passivation layer 15 is etched by a chemical reaction of plasma to form via holes 151.
  • the first metal layer 11 and the second metal layer 14 do not have a path that is electrically connected to each other, so that a difference in potential is generated between the first metal layer 11 and the second metal layer 14 which overlap each other due to the action of plasma.
  • the potential difference is large, there is a possibility that the insulating layer 12 between the first metal layer 11 and the second metal layer 14 collapses to cause electrostatic fatigue or cause the two metal layers to be short-circuited up and down.
  • the technical problem to be solved by the present invention is to provide a liquid crystal display device, an array substrate, and a manufacturing method thereof, which can greatly reduce the probability of electrostatic damage during the fabrication of the array substrate and improve the yield of the array substrate.
  • a technical solution adopted by the present invention is to provide a method for fabricating an array substrate, comprising: forming a first conductive layer, a first insulating layer, a second conductive layer, and a second in order from bottom to top on a substrate.
  • An insulating layer wherein the first conductive layer is used to form a scan line electrically connected to each other and a control electrode of the switch tube, and the number of the second conductive layer is at least one, for forming an input electrode, an output electrode, and a transparent pixel electrode of the switch tube, The output electrode is electrically connected to the pixel electrode; the second insulating layer is dry etched to form a via hole; a third conductive layer is formed on the second insulating layer, and the third conductive layer is electrically connected to the input electrode of the switch tube through the via hole Connecting, the third conductive layer is used to form a data line; wherein the step of sequentially forming the first conductive layer, the first insulating layer, the second conductive layer, and the second insulating layer from bottom to top on the substrate comprises: forming a a metal layer; etching the first metal layer to form a scan line electrically connected to each other and a gate of the thin film transistor as a switch transistor; at the gate of the thin film transistor and
  • the step of forming a first insulating layer over the gate of the thin film transistor and the scan line includes: forming a semiconductor layer on the first insulating layer corresponding to the gate of the thin film transistor, and making the source and drain of the thin film transistor Connected to the semiconductor layer separately.
  • the step of performing dry etching on the second insulating layer corresponding to the source of the thin film transistor includes dry etching on the second insulating layer corresponding to the source of the thin film transistor by dry etching using reactive ion etching.
  • the step of forming a third conductive layer on the second insulating layer, and electrically connecting the third conductive layer to the input electrode of the switch tube through the via hole comprises: forming a second metal layer on the second insulating layer; The metal layer is etched to form a data line, and the data line is electrically connected to the source of the thin film transistor through the via hole.
  • an array substrate including a substrate, a scan line electrically connected to each other and a control electrode of the switch tube disposed on the substrate, and a scan line and a switch tube.
  • the switching transistor is a thin film transistor
  • the control electrode is a gate of the thin film transistor
  • the input electrode and the output electrode are respectively a source and a drain of the thin film transistor.
  • the source, the drain and the pixel electrode of the thin film transistor belong to the same layer of transparent conductive layer.
  • a liquid crystal display device including an array substrate; the array substrate includes: a substrate; and mutually connected scan lines and control electrodes of the switch tubes disposed on the substrate a first insulating layer disposed on the control electrode of the scan line and the switch tube; an input electrode, an output electrode, and a transparent pixel electrode of the switch tube disposed on the first insulating layer, the output electrode being electrically connected to the pixel electrode, and the output electrode a semiconductor is disposed between the input electrode; a second insulating layer disposed on the input electrode, the output electrode, and the pixel electrode of the switch tube; and a conductive via is disposed on the second insulating layer corresponding to the input electrode of the switch tube; The data line of the via area is electrically connected to the second insulating layer, and the data line is electrically connected to the input electrode of the switch tube through the via hole.
  • the switching transistor is a thin film transistor
  • the control electrode is a gate of the thin film transistor
  • the input electrode and the output electrode are respectively a source and a drain of the thin film transistor.
  • the source, the drain and the pixel electrode of the thin film transistor belong to the same layer of transparent conductive layer.
  • the invention has the beneficial effects that the first conductive layer of the control electrode as the scan line and the switch tube is first formed on the substrate, and then the first insulating layer, the second conductive layer and the second insulating layer are sequentially formed, and the second The insulating layer is dry etched to form a via hole, and finally a third conductive layer is formed on the second insulating layer for forming a data line. Since the via hole is formed by dry etching the second insulating layer, it is not formed yet. The third conductive layer of the data line is formed, so that there is no overlapping area of the scan line and the data line during dry etching, thereby greatly reducing the probability of electrostatic damage during the fabrication of the array substrate and improving the yield of the array substrate.
  • FIG. 1 is a schematic plan view showing a planar structure of an array substrate in the prior art
  • Figure 2 is a cross-sectional view of the array substrate of Figure 1 taken along line AB;
  • FIG. 3 is a schematic view showing a process of five masks of the array substrate of FIG. 1;
  • FIG. 4 is a flow chart showing an embodiment of a method of fabricating an array substrate of the present invention.
  • FIG. 5 is a schematic view showing a process of five masks of the array substrate of FIG. 4;
  • FIG. 6 is a first conductive layer, a first conductive layer, a second conductive layer, and a second layer on the substrate from bottom to top on the substrate when the first conductive layer is the first metal layer and the second conductive layer is the transparent conductive layer.
  • FIG. 7 is a flow chart showing an embodiment of forming a third conductive layer on the second insulating layer when the third conductive layer is the second metal layer in FIG. 4;
  • FIG. 8 is a schematic plan view showing an embodiment of an array substrate of the present invention.
  • Figure 9 is a cross-sectional view of the array substrate of Figure 8 taken along the CD direction.
  • the liquid crystal display device, the array substrate and the manufacturing method thereof of the invention can greatly reduce the probability of electrostatic damage during the fabrication of the array substrate and improve the yield of the array substrate.
  • an embodiment of a method for fabricating an array substrate of the present invention includes:
  • Step S401 forming a first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer in order from bottom to top on the substrate, wherein the first conductive layer is used to form a scan line electrically connected to each other and a control electrode of the switch tube
  • the number of the second conductive layers is at least one, and is used to form an input electrode, an output electrode, and a transparent pixel electrode of the switch tube, and the output electrode is electrically connected to the pixel electrode.
  • the scan lines, data lines, pixel electrodes, and switch tubes are the main components of the circuit in the array substrate, and a clean, smooth surface glass is used as the base material for the array substrate.
  • a main component such as a scanning line, a data line, a pixel electrode, and a switching tube is formed on a substrate by a process such as plating, etching, or the like on a substrate.
  • the switching transistor is a thin film transistor, and the control electrode, the input electrode, and the output electrode of the switching transistor respectively correspond to a gate, a source, and a drain of the thin film transistor.
  • the specific production process includes the following sub-steps:
  • Sub-step S501 First, a first conductive layer 101 is formed on the substrate 100, and the first conductive layer 101 is used to form the scan line 1011 and the gate electrode 1012 of the thin film transistor, so that the two are electrically connected to each other (the connection relationship is not shown) To provide a scan signal to the gate 1012 of the thin film transistor through the scan line 1011 in a subsequent process.
  • Sub-step S502 After the scan line 1011 and the gate electrode 1012 of the thin film transistor are formed, the first insulating layer 102 is formed on the scan line 1011 and the gate electrode 1012 of the thin film transistor.
  • a semiconductor layer 103 is formed on the corresponding first insulating layer 102 of the gate electrode 1012 of the thin film transistor.
  • Sub-step S503 forming a second conductive layer 104 on the first insulating layer 102, and the scan line 1011 and the gate electrode 1012 of the thin film transistor and the second conductive layer 104 are electrically insulated by the first insulating layer 102.
  • the second conductive layer 104 is used to form the transparent pixel electrode 1041 and the source 1042 and the drain 1043 of the thin film transistor, and the source electrode 1042 and the drain 1043 of the thin film transistor are respectively connected to the semiconductor layer 103 during formation.
  • the thin film transistor realizes the function of a switch through the semiconductor layer 103.
  • the gate 1012 of the thin film transistor serves as a control electrode.
  • the semiconductor layer 103 When the scan line 1011 supplies a scan signal to the gate 1012 of the thin film transistor, the semiconductor layer 103 is turned on, so that the thin film transistor is turned on as a source of the input electrode of the thin film transistor.
  • the pole 1042 and the drain 1043 as the output electrode are electrically connected through the semiconductor layer 103; when the gate signal of the thin film transistor 1012 is not input, the semiconductor layer 103 is not turned on, so that the thin film transistor is turned off, the source 1042 and the drain
  • the pole 1043 is electrically insulated.
  • the second conductive layer 104 electrically connects the pixel electrode 1041 and the drain electrode 1043 of the thin film transistor when forming the transparent pixel electrode 1041 to input a display signal to the pixel electrode 1041 through the drain 1043 in a subsequent process.
  • Sub-step S504 After the second conductive layer 104 is completed, the second insulating layer 105 is formed on the second conductive layer 104.
  • the second insulating layer 105 may be a passivation layer or other insulating layer having insulating properties, and is not specifically limited herein.
  • Step S402 dry etching the second insulating layer to form via holes.
  • the second insulating layer 105 is such that the source 1042 of the thin film transistor is covered with an insulating layer (ie, the second insulating layer 105), and the source 1042 is used as a thin film transistor.
  • the input electrode needs to be input to the desired display signal. Therefore, dry etching is performed on the second insulating layer 105 corresponding to the source 1042 of the thin film transistor, so that the via hole 1051 corresponding to the source 1042 of the thin film transistor is formed on the second insulating layer 105 to facilitate the source 1042. Enter the display signal.
  • dry etching refers to a technique of performing plasma etching using plasma.
  • the second insulating layer 105 is physically bombarded and chemically reacted by reactive ions in a dry etching manner to form a via hole corresponding to the source 1042 of the thin film transistor on the second insulating layer 105. 1051.
  • the second insulating layer 105 may be etched by a dry etching method using physical etching or chemical etching to form the via hole 1051, which is not specifically limited.
  • Step S403 forming a third conductive layer on the second insulating layer, and electrically connecting the third conductive layer to the input electrode of the switch tube through the via hole, and the third conductive layer is used to form the data line.
  • Sub-step S505 forming a third conductive layer 106 in a region where the via hole 1051 of the second insulating layer 105 is located, so that the third conductive layer 106 can pass through the via hole 1051 and the source 1042 of the thin film transistor as a switch transistor. connection.
  • the third conductive layer 106 is used to form a data line.
  • the scan line 1011, the data line (formed by the third conductive layer 106), and the pixel electrode 1041 are formed on the substrate 100, and the formed semiconductor layer 103, the gate 1012, the source 1042, and the drain 1043 are formed.
  • the thin film transistor required for the substrate 100 is formed.
  • the first conductive layer 101 and the third conductive layer 106 are a first metal layer and a second metal layer, respectively, and the second conductive layer 104 is transparent. Conductive layer. Therefore, the specific steps of sequentially forming the first conductive layer 101, the first insulating layer 102, the second conductive layer 104, and the second insulating layer 105 from bottom to top on the substrate 100 include:
  • Step S601 forming a first metal layer on the substrate
  • Step S602 etching the first metal layer to form a scan line electrically connected to each other and a gate of the thin film transistor as a switch tube;
  • Step S603 forming a first insulating layer over the gate of the thin film transistor and the scan line;
  • Step S604 forming a transparent conductive layer on the first insulating layer
  • Step S605 etching the transparent conductive layer to form a source, a drain, and a pixel electrode of the thin film transistor, and electrically connecting the drain of the thin film transistor to the pixel electrode;
  • Step S606 forming a second insulating layer over the source, the drain and the pixel electrode of the thin film transistor.
  • the source 1042 and the drain 1043 of the thin film transistor may be formed of a metal conductive layer. Therefore, the number of the second conductive layers 104 may be two, including a transparent conductive layer for forming the pixel electrode 1041 and a third metal layer (not shown) for forming the source 1042 and the drain 1043 of the thin film transistor.
  • the third metal layer forming the drain electrode 1043 of the thin film transistor and the transparent conductive layer forming the pixel electrode 1041 are electrically connected to realize electrical connection of the drain electrode 1043 of the thin film transistor and the pixel electrode 1041.
  • the second insulating layer is dry etched to form via holes.
  • the specific steps of forming a third conductive layer on the second insulating layer and electrically connecting the third conductive layer to the input electrode of the switch tube through the via hole include:
  • Step S701 forming a second metal layer on the second insulating layer
  • Step S702 etching the second metal layer to form a data line, and electrically connecting the data line to the source of the thin film transistor through the via hole.
  • the first conductive layer 101 as the scan line 1011 and the gate electrode 1012 of the thin film transistor is formed on the substrate 100, and then the first insulating layer 102 and the second layer are sequentially formed.
  • the conductive layer 104 and the second insulating layer 105 are dry etched to form the via hole 1051, and finally a third conductive layer 106 is formed on the second insulating layer 105 for forming a data line. Since the third conductive layer 106 for forming the data line is not formed when the via hole 1051 is formed by dry etching the second insulating layer 105, there is no overlap region of the scan line 1011 and the data line at the time of dry etching. Therefore, the probability of electrostatic damage during the fabrication of the array substrate can be greatly reduced, and the yield of the array substrate can be improved.
  • an embodiment of the array substrate of the present invention includes: a substrate 800; a scan line 8011 electrically connected to the substrate 800 and a control electrode 8012 of the switch tube; and a scan line 8011 and a switch tube.
  • the output electrode 8043 is electrically connected to the pixel electrode 8041.
  • a semiconductor 803 is disposed between the electrode 8042 and the output electrode 8043; a second insulating layer 805 disposed on the input electrode 8042 of the switch tube, the output electrode 8043, and the pixel electrode 8041, and the input of the switch tube corresponding to the second insulating layer 805
  • the electrode 8042 is provided with a via hole 8051; a data line 806 disposed on the second insulating layer 805 in the region of the via hole 8051, and the data line 806 is electrically connected to the input electrode 8042 of the switch transistor through the via hole 8051.
  • the planar structure diagram of the array substrate shown in FIG. 8 is a schematic structural view, and the first insulating layer 802 and the second insulating layer 805 are not in the The input electrode 8042 and the via 8051 of the switch tube, which is covered under the data line 806, are shown together in FIG.
  • the switching transistor of the present embodiment is a thin film transistor
  • the control electrode 8012 is the gate of the thin film transistor
  • the input electrode 8042 and the output electrode 8043 are the source and the drain of the thin film transistor, respectively.
  • the source and drain of the thin film transistor and the pixel electrode 8041 belong to the same layer of transparent conductive layer.
  • the data line 806 is finally disposed on the region of the second insulating layer 805 where the via hole 8051 is located, so that the data line 806 is not formed when the via hole 8051 is disposed on the second insulating layer 805. Therefore, the overlapping region of the scan line 8011 and the data line 806 is formed when the via hole 8051 is disposed, which can greatly reduce the probability of electrostatic damage during the fabrication of the array substrate and improve the yield of the array substrate.
  • the present invention also provides an embodiment of a liquid crystal display device, which includes any of the above embodiments of the array substrate of the present invention, and details are not described herein again.

Landscapes

  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Description

一种液晶显示装置、阵列基板及其制作方法
【技术领域】
本发明涉及液晶显示技术领域，特别是涉及一种液晶显示装置、阵列基板及其制作方法。
【背景技术】
液晶显示面板的制作过程一般分为阵列（Array）制程、组立（Cell）制程以及模组（Module）制程。其中，阵列制程主要是产生薄膜晶体管玻璃基板（也称为阵列基板），其作为液晶显示面板制作过程的第一道工序，所产生的薄膜晶体管玻璃基板的好坏对后续制程有着重大影响，甚至决定液晶显示面板的好坏。
阵列制程一般经过五道光罩制程（5PEP），以在没有任何杂质的玻璃上形成薄膜晶体管等结构。参阅图1-图3，第一道制程SP1中，首先在玻璃1上镀上第一金属层11，第一金属层11用于形成作为薄膜晶体管的栅极和扫描线；然后进入第二道制程SP2，在第一金属层11上形成绝缘层（Isolator Layer）12，并在用于形成薄膜晶体管的栅极的第一金属层11所对应的绝缘层12上形成一层半导体层13；在第三道制程SP3中，在绝缘层12以及半导体层13上镀上第二金属层14，用于形成数据线、薄膜晶体管的源极和漏极；在第四道制程SP4中，在第二金属层14、第二金属层14所没有覆盖的半导体层13以及绝缘层12上形成钝化层（Passivation Layer，PV）15，并在钝化层15对应的用于形成薄膜晶体管的漏极的第二金属层14的位置形成导通孔151；在第五道制程SP5中，在钝化层15上形成透明导电层16，透明导电层16用于形成像素电极，并且使透明导电层16通过导通孔151与用于形成薄膜晶体管的漏极的第二金属层14电性连接，以实现像素电极通过导通孔151与薄膜晶体管的漏极电性连接。
在上述五道光罩制程中，第一金属层11用于形成扫描线和薄膜晶体管的栅极，第二金属层14用于形成数据线、薄膜晶体管的源极和漏极。在液晶显示面板中，扫描线和数据线会相互交错，因此第一金属层11和第二金属层14会重叠，形成相互跨线的重叠区域。而在设计液晶显示面板周边线路时，为了降低信号线路和测试线路的阻值，通常会大量地使用第一金属层11和第二金属层14的重叠结构，使其同时传导相同的信号以降低信号线路和测试线路的阻值并减小信号的延迟。
但是，在五道光罩制程的第四道制程SP4中，在钝化层15上形成导通孔151时，通常是以干式蚀刻（Dry Etch）的方式进行，即利用等离子的化学反应方式去蚀刻钝化层15以形成导通孔151。此时，第一金属层11和第二金属层14并没有相互导通的路径，使得相互重叠的第一金属层11和第二金属层14之间会因为等离子的作用而产生电位差异。当电位差异较大时有可能会造成第一金属层11和第二金属层14之间的绝缘层12崩溃而引起静电炸伤或造成两金属层上下短路。
【发明内容】
本发明主要解决的技术问题是提供一种液晶显示装置、阵列基板及其制作方法，能够大大降低阵列基板制作过程中静电炸伤的机率，提高阵列基板的良率。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板的制作方法，包括在基底上由下至上依次形成第一导电层、第一绝缘层、第二导电层以及第二绝缘层，第一导电层用于形成相互电连接的扫描线和开关管的控制电极，第二导电层的数量至少为一，用于形成开关管的输入电极、输出电极以及透明的像素电极，输出电极与像素电极电连接；对第二绝缘层进行干蚀刻以形成导通孔；在第二绝缘层上形成第三导电层，使第三导电层通过导通孔与开关管的输入电极电连接，第三导电层用于形成数据线；其中，在基底上由下至上依次形成第一导电层、第一绝缘层、第二导电层以及第二绝缘层的步骤包括：在基底上形成第一金属层；对第一金属层进行蚀刻，形成相互电连接的扫描线和作为开关管的薄膜晶体管的栅极；在薄膜晶体管的栅极和扫描线之上形成第一绝缘层；在第一绝缘层上形成透明导电层；对透明导电层进行蚀刻，形成薄膜晶体管的源极、漏极以及像素电极，并且薄膜晶体管的漏极与像素电极电连接；在薄膜晶体管的源极、漏极与像素电极之上形成第二绝缘层；对第二绝缘层进行干蚀刻以形成导通孔的步骤包括：在薄膜晶体管的源极对应的第二绝缘层上进行干蚀刻，以在第二绝缘层和薄膜晶体管的源极之间形成导通孔。
其中，在薄膜晶体管的栅极和扫描线之上形成第一绝缘层之后的步骤包括：在薄膜晶体管的栅极对应的第一绝缘层上形成一半导体层，使薄膜晶体管的源极和漏极分别与半导体层连接。
其中，在薄膜晶体管的源极对应的第二绝缘层上进行干蚀刻的步骤包括：利用反应离子刻蚀的干蚀刻方式在薄膜晶体管的源极对应的第二绝缘层上进行干蚀刻。
其中，在第二绝缘层上形成第三导电层，使第三导电层通过导通孔与开关管的输入电极电连接的步骤包括：在第二绝缘层上形成第二金属层；对第二金属层进行蚀刻，形成数据线，使数据线通过导通孔与薄膜晶体管的源极电性连接。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板，包括基底；设置于基底上的相互电连接的扫描线和开关管的控制电极；设置于扫描线和开关管的控制电极上的第一绝缘层；设置于第一绝缘层上的开关管的输入电极、输出电极以及透明的像素电极，输出电极与像素电极电连接，输出电极与输入电极之间设置有半导体；设置于开关管的输入电极、输出电极以及像素电极之上的第二绝缘层，第二绝缘层上对应开关管的输入电极的位置设置有导通孔；设置于第二绝缘层上导通孔区域的数据线，数据线通过导通孔与开关管的输入电极电连接。
其中，开关管是薄膜晶体管，控制电极是薄膜晶体管的栅极，输入电极、输出电极分别为薄膜晶体管的源极、漏极。
其中，薄膜晶体管的源极、漏极以及像素电极同属于一层透明导电层。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种液晶显示装置，包括阵列基板；阵列基板包括：基底；设置于基底上的相互电连接的扫描线和开关管的控制电极；设置于扫描线和开关管的控制电极上的第一绝缘层；设置于第一绝缘层上的开关管的输入电极、输出电极以及透明的像素电极，输出电极与像素电极电连接，输出电极与输入电极之间设置有半导体；设置于开关管的输入电极、输出电极以及像素电极之上的第二绝缘层，第二绝缘层上对应开关管的输入电极的位置设置有导通孔；设置于第二绝缘层上导通孔区域的数据线，数据线通过导通孔与开关管的输入电极电连接。
其中，开关管是薄膜晶体管，控制电极是薄膜晶体管的栅极，输入电极、输出电极分别为薄膜晶体管的源极、漏极。
其中，薄膜晶体管的源极、漏极以及像素电极同属于一层透明导电层。
本发明的有益效果是：本发明首先在基底上形成作为扫描线和开关管的控制电极的第一导电层，然后依次形成第一绝缘层、第二导电层和第二绝缘层，对第二绝缘层进行干蚀刻以形成导通孔，最后在第二绝缘层上形成第三导电层以用于形成数据线，由于在对第二绝缘层进行干蚀刻形成导通孔时，还未形成用于形成数据线的第三导电层，因此在干蚀刻时并未有扫描线和数据线的重叠区，由此能够大大降低阵列基板制作过程中静电炸伤的机率，提高阵列基板的良率。
【附图说明】
图1是现有技术中一种阵列基板的平面结构示意图；
图2是图1的阵列基板沿AB方向的截面图；
图3是图1的阵列基板的五道光罩制程的示意图；
图4是本发明阵列基板的制作方法的一实施方式的流程图；
图5是图4的阵列基板的五道光罩制程的示意图；
图6是图4中第一导电层为第一金属层以及第二导电层为透明导电层时在基底上由下至上依次形成第一导电层、第一绝缘层、第二导电层以及第二绝缘层的一实施方式的流程图；
图7是图4中第三导电层为第二金属层时在第二绝缘层上形成第三导电层的一实施方式的流程图；
图8是本发明阵列基板的一实施方式的平面结构示意图；
图9是图8中的阵列基板沿CD方向的截面图。
【具体实施方式】
本发明的液晶显示装置、阵列基板及其制作方法，能够大大降低阵列基板制作过程中静电炸伤的机率，提高阵列基板的良率。
下面将结合实施方式和附图对本发明进行详细说明。
参阅图4和图5，本发明阵列基板的制作方法的一实施方式包括：
步骤S401：在基底上由下至上依次形成第一导电层、第一绝缘层、第二导电层以及第二绝缘层，第一导电层用于形成相互电连接的扫描线和开关管的控制电极，第二导电层的数量至少为一，用于形成开关管的输入电极、输出电极以及透明的像素电极，输出电极与像素电极电连接。
扫描线、数据线、像素电极和开关管是阵列基板中电路的主要元件，而一片干净的、表面平滑的玻璃则作为阵列基板的基底材料。以玻璃为基底，通过在基底上进行镀膜、蚀刻等工艺，从而在基底上形成扫描线、数据线、像素电极和开关管等主要元件。本实施方式中，开关管为薄膜晶体管，开关管的控制电极、输入电极以及输出电极分别对应为薄膜晶体管的栅极、源极以及漏极。
具体的制作过程，如图5所示，包括如下子步骤：
子步骤S501：首先，在基底100上形成第一导电层101，第一导电层101用于形成扫描线1011和薄膜晶体管的栅极1012，使两者相互电连接（图中未示连接关系），以在后续制程中通过扫描线1011向薄膜晶体管的栅极1012提供扫描信号。
子步骤S502：在形成扫描线1011和薄膜晶体管的栅极1012后，在扫描线1011和薄膜晶体管的栅极1012上形成第一绝缘层102。
进一步地，在扫描线1011和薄膜晶体管的栅极1012之上形成第一绝缘层102后，在薄膜晶体管的栅极1012对应的第一绝缘层102上形成一层半导体层103。
子步骤S503：在第一绝缘层102上形成第二导电层104，扫描线1011和薄膜晶体管的栅极1012与第二导电层104之间通过第一绝缘层102电性绝缘。第二导电层104用于形成透明的像素电极1041以及薄膜晶体管的源极1042、漏极1043，并且，在形成过程中，使得薄膜晶体管的源极1042和漏极1043分别与半导体层103连接。薄膜晶体管通过半导体层103实现开关的作用。具体地，薄膜晶体管的栅极1012作为控制电极，当扫描线1011向薄膜晶体管的栅极1012提供扫描信号时，半导体层103导通，使薄膜晶体管处于打开状态，作为薄膜晶体管的输入电极的源极1042和作为输出电极的漏极1043通过半导体层103电性连接；当薄膜晶体管的栅极1012没有输入扫描信号时，半导体层103不导通，使薄膜晶体管处于关闭状态，源极1042和漏极1043电性绝缘。
此外，第二导电层104在形成透明的像素电极1041时，使像素电极1041和薄膜晶体管的漏极1043电连接，以在后续制程中通过漏极1043向像素电极1041输入显示信号。
子步骤S504：在完成第二导电层104后，在第二导电层104上形成第二绝缘层105。本实施方式中，第二绝缘层105可以是钝化层，也可以是其他具有绝缘特性的绝缘层，在此不做具体限制。
步骤S402：对第二绝缘层进行干蚀刻以形成导通孔。
在第二导电层104上形成第二绝缘层105后，第二绝缘层105使得薄膜晶体管的源极1042覆上了一层绝缘层（即第二绝缘层105），而源极1042作为薄膜晶体管的输入电极，需要对其输入所需的显示信号。因此，需在薄膜晶体管的源极1042对应的第二绝缘层105上进行干蚀刻，使得在第二绝缘层105上形成对应薄膜晶体管的源极1042的导通孔1051，以方便对源极1042输入显示信号。
其中，干蚀刻是指利用等离子进行薄膜刻蚀的技术。本实施方式中，采用反应离子刻蚀的干蚀刻方式通过活性离子对第二绝缘层105进行物理轰击和化学反应，以在第二绝缘层105上形成对应薄膜晶体管的源极1042的导通孔1051。而在本发明的备选实施方式中，也可以利用物理性蚀刻或化学性蚀刻的干蚀刻方式对第二绝缘层105进行蚀刻以形成导通孔1051，在此不进行具体限制。
步骤S403：在第二绝缘层上形成第三导电层，使第三导电层通过导通孔与开关管的输入电极电连接，第三导电层用于形成数据线。
子步骤S505：在第二绝缘层105的导通孔1051所在的区域，形成第三导电层106，使第三导电层106能通过导通孔1051与作为开关管的薄膜晶体管的源极1042电连接。第三导电层106用于形成数据线。
经过上述步骤后，基底100上已形成了扫描线1011、数据线（由第三导电层106形成）以及像素电极1041，而所形成的半导体层103、栅极1012、源极1042以及漏极1043则构成了基底100所需的薄膜晶体管。在扫描线1011向薄膜晶体管的栅极1012输入扫描信号时，半导体层103导通，使薄膜晶体管打开，数据线通过导通孔1051向薄膜晶体管的源极1042输入显示信号，显示信号从漏极1043输出至像素电极1041。
值得注意的是，参阅图6并结合图5，在一具体实施方式中，第一导电层101和第三导电层106分别是第一金属层和第二金属层，第二导电层104是透明导电层。因此，在基底100上由下至上依次形成第一导电层101、第一绝缘层102、第二导电层104以及第二绝缘层105的具体步骤包括：
步骤S601：在基底上形成第一金属层；
步骤S602：第一金属层进行蚀刻，形成相互电连接的扫描线和作为开关管的薄膜晶体管的栅极；
步骤S603：在薄膜晶体管的栅极和扫描线之上形成第一绝缘层；
步骤S604：在第一绝缘层上形成透明导电层；
步骤S605：对透明导电层进行蚀刻，形成薄膜晶体管的源极、漏极以及像素电极，并且薄膜晶体管的漏极与像素电极电连接；
步骤S606：在薄膜晶体管的源极、漏极与像素电极之上形成第二绝缘层。
在本发明的备选实施方式中，薄膜晶体管的源极1042和漏极1043可以是金属导电层形成。因此，第二导电层104的数量可以为二，包括用于形成像素电极1041的透明导电层以及用于形成薄膜晶体管的源极1042和漏极1043的第三金属层（图未示），使形成薄膜晶体管的漏极1043的第三金属层和形成像素电极1041的透明导电层电性连接，以实现薄膜晶体管的漏极1043和像素电极1041的电性连接。
形成第二绝缘层之后，对第二绝缘层进行干蚀刻以形成导通孔。
参阅图7，在第二绝缘层上形成第三导电层、使第三导电层通过导通孔与开关管的输入电极电连接的具体步骤包括：
步骤S701：在第二绝缘层上形成第二金属层；
步骤S702：对第二金属层进行蚀刻，形成数据线，使数据线通过导通孔与薄膜晶体管的源极电性连接。
本领域技术人员在阅读上述关于图4和图5的阐述后，应能轻易地了解图6与图7中所示的方法是如何实施的，出于简洁的目的，在此不再赘述。
综上所述，本实施方式的阵列基板的制作方法，首先在基底100上形成作为扫描线1011和薄膜晶体管的栅极1012的第一导电层101，然后依次形成第一绝缘层102、第二导电层104和第二绝缘层105，对第二绝缘层105进行干蚀刻以形成导通孔1051，最后在第二绝缘层105上形成第三导电层106以用于形成数据线。由于在对第二绝缘层105进行干蚀刻形成导通孔1051时，还未形成用于形成数据线的第三导电层106，因此在干蚀刻时并未有扫描线1011和数据线的重叠区，由此能够大大降低阵列基板制作过程中静电炸伤的机率，提高阵列基板的良率。
参阅图8和图9，本发明阵列基板的一实施方式包括：基底800；设置于基底800上的相互电连接的扫描线8011和开关管的控制电极8012；设置于扫描线8011和开关管的控制电极8012上的第一绝缘层802；设置于第一绝缘层802上的透明的像素电极8041以及开关管的输入电极8042、输出电极8043，其中，输出电极8043与像素电极8041电连接，输入电极8042与输出电极8043之间设置有半导体803；设置于开关管的输入电极8042、输出电极8043以及像素电极8041之上的第二绝缘层805，并且第二绝缘层805上对应开关管的输入电极8042的位置设置有导通孔8051；设置于第二绝缘层805上导通孔8051区域的数据线806，数据线806通过导通孔8051与开关管的输入电极8042电连接。
值得注意的是，为了能够清楚示意本发明阵列基板电路中的主要元件结构分布，图8所示的阵列基板的平面结构示意图为简略结构图，第一绝缘层802以及第二绝缘层805没有在图8中示出，并且将覆盖在数据线806之下的开关管的输入电极8042和导通孔8051一并示出。
其中，本实施方式的开关管是薄膜晶体管，控制电极8012是薄膜晶体管的栅极，输入电极8042、输出电极8043分别是薄膜晶体管的源极、漏极。并且，薄膜晶体管的源极、漏极以及像素电极8041同属于一层透明导电层。
本实施方式的阵列基板，通过将数据线806最后设置于第二绝缘层805上导通孔8051所在的区域，使得在第二绝缘层805上设置导通孔8051时还未形成数据线806，由此避免了在设置导通孔8051时形成扫描线8011和数据线806的重叠区，能够大大降低阵列基板制作过程中静电炸伤的机率，提高阵列基板的良率。
本发明还提供液晶显示装置实施方式，其包括上述本发明阵列基板任一实施方式，在此不再赘述。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (10)

  1. 一种阵列基板的制作方法，其中，包括：
    在基底上由下至上依次形成第一导电层、第一绝缘层、第二导电层以及第二绝缘层，所述第一导电层用于形成相互电连接的扫描线和开关管的控制电极，所述第二导电层的数量至少为一，用于形成开关管的输入电极、输出电极以及透明的像素电极，所述输出电极与像素电极电连接；
    对所述第二绝缘层进行干蚀刻以形成导通孔；
    在所述第二绝缘层上形成第三导电层，使所述第三导电层通过导通孔与开关管的输入电极电连接，所述第三导电层用于形成数据线；
    其中，所述在基底上由下至上依次形成第一导电层、第一绝缘层、第二导电层以及第二绝缘层的步骤包括：
    在所述基底上形成第一金属层；
    对所述第一金属层进行蚀刻，形成相互电连接的扫描线和作为开关管的薄膜晶体管的栅极；
    在所述薄膜晶体管的栅极和扫描线之上形成第一绝缘层；
    在所述第一绝缘层上形成透明导电层；
    对所述透明导电层进行蚀刻，形成所述薄膜晶体管的源极、漏极以及像素电极，并且所述薄膜晶体管的漏极与像素电极电连接；
    在所述薄膜晶体管的源极、漏极与像素电极之上形成第二绝缘层；
    所述对所述第二绝缘层进行干蚀刻以形成导通孔的步骤包括：
    在所述薄膜晶体管的源极对应的第二绝缘层上进行干蚀刻，以在第二绝缘层和薄膜晶体管的源极之间形成导通孔。
  2. 根据权利要求1所述的方法，其中，
    所述在所述薄膜晶体管的栅极和扫描线之上形成第一绝缘层之后的步骤包括：
    在所述薄膜晶体管的栅极对应的第一绝缘层上形成一半导体层，使所述薄膜晶体管的源极和漏极分别与所述半导体层连接。
  3. 根据权利要求1所述的方法，其中，
    所述在薄膜晶体管的源极对应的第二绝缘层上进行干蚀刻的步骤包括：
    利用反应离子刻蚀的干蚀刻方式在所述薄膜晶体管的源极对应的第二绝缘层上进行干蚀刻。
  4. 根据权利要求3所述的方法，其中，
    所述在所述第二绝缘层上形成第三导电层，使所述第三导电层通过导通孔与开关管的输入电极电连接的步骤包括：
    在所述第二绝缘层上形成第二金属层；
    对所述第二金属层进行蚀刻，形成数据线，使所述数据线通过导通孔与薄膜晶体管的源极电性连接。
  5. 一种阵列基板，其中，包括：
    基底；
    设置于所述基底上的相互电连接的扫描线和开关管的控制电极；
    设置于所述扫描线和开关管的控制电极上的第一绝缘层；
    设置于所述第一绝缘层上的开关管的输入电极、输出电极以及透明的像素电极，所述输出电极与像素电极电连接，所述输出电极与输入电极之间设置有半导体；
    设置于所述开关管的输入电极、输出电极以及像素电极之上的第二绝缘层，所述第二绝缘层上对应开关管的输入电极的位置设置有导通孔；
    设置于所述第二绝缘层上导通孔区域的数据线，所述数据线通过导通孔与开关管的输入电极电连接。
  6. 根据权利要求5所述的阵列基板，其中，
    所述开关管是薄膜晶体管，所述控制电极是薄膜晶体管的栅极，所述输入电极、输出电极分别为薄膜晶体管的源极、漏极。
  7. 根据权利要求6所述的阵列基板，其中，
    所述薄膜晶体管的源极、漏极以及像素电极同属于一层透明导电层。
  8. 一种液晶显示装置，其中，包括阵列基板；
    所述阵列基板包括：
    基底；
    设置于所述基底上的相互电连接的扫描线和开关管的控制电极；
    设置于所述扫描线和开关管的控制电极上的第一绝缘层；
    设置于所述第一绝缘层上的开关管的输入电极、输出电极以及透明的像素电极，所述输出电极与像素电极电连接，所述输出电极与输入电极之间设置有半导体；
    设置于所述开关管的输入电极、输出电极以及像素电极之上的第二绝缘层，所述第二绝缘层上对应开关管的输入电极的位置设置有导通孔；
    设置于所述第二绝缘层上导通孔区域的数据线，所述数据线通过导通孔与开关管的输入电极电连接。
  9. 根据权利要求8所述的液晶显示装置，其中，
    所述开关管是薄膜晶体管，所述控制电极是薄膜晶体管的栅极，所述输入电极、输出电极分别为薄膜晶体管的源极、漏极。
  10. 根据权利要求9所述的液晶显示装置，其中，
    所述薄膜晶体管的源极、漏极以及像素电极同属于一层透明导电层。
PCT/CN2012/079670 2012-07-31 2012-08-03 一种液晶显示装置、阵列基板及其制作方法 Ceased WO2014019227A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/582,746 US20140034952A1 (en) 2012-07-31 2012-08-03 Liquid Crystal Display Device, Array Substrate and Manufacturing Method Thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201210269093.9A CN102768991B (zh) 2012-07-31 2012-07-31 一种液晶显示装置、阵列基板及其制作方法
CN201210269093.9 2012-07-31

Publications (1)

Publication Number Publication Date
WO2014019227A1 true WO2014019227A1 (zh) 2014-02-06

Family

ID=47096332

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2012/079670 Ceased WO2014019227A1 (zh) 2012-07-31 2012-08-03 一种液晶显示装置、阵列基板及其制作方法

Country Status (2)

Country Link
CN (1) CN102768991B (zh)
WO (1) WO2014019227A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103472638B (zh) * 2013-09-12 2016-06-15 南京中电熊猫液晶显示科技有限公司 一种四道光罩制作的阵列基板及液晶面板
CN106773401A (zh) * 2016-12-28 2017-05-31 深圳市华星光电技术有限公司 阵列基板的制作方法及阵列基板
CN110426904B (zh) * 2019-06-27 2021-11-05 惠科股份有限公司 阵列基板和显示设备
CN112909065B (zh) * 2021-02-05 2025-02-25 合肥京东方卓印科技有限公司 阵列基板和显示装置
CN117476696A (zh) * 2023-05-31 2024-01-30 深圳市华星光电半导体显示技术有限公司 驱动基板及显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001264802A (ja) * 2000-03-15 2001-09-26 Toshiba Corp マトリクスアレイ基板
US20020180897A1 (en) * 2001-06-05 2002-12-05 Chae Gee Sung Liquid crystal display and fabricating method thereof
CN1388405A (zh) * 2001-05-29 2003-01-01 Lg.菲利浦Lcd株式会社 用喷墨系统形成液晶层的方法
CN101552277A (zh) * 2008-04-03 2009-10-07 上海广电Nec液晶显示器有限公司 薄膜晶体管阵列基板及其制造方法
CN101828212A (zh) * 2007-10-24 2010-09-08 株式会社神户制钢所 显示装置及该显示装置使用的Cu合金膜
CN102034750A (zh) * 2009-09-25 2011-04-27 北京京东方光电科技有限公司 阵列基板及其制造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08122819A (ja) * 1994-10-25 1996-05-17 Mitsubishi Electric Corp 液晶表示装置及びその製造方法
TW588462B (en) * 2003-03-31 2004-05-21 Quanta Display Inc Method of fabricating a thin film transistor array panel

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001264802A (ja) * 2000-03-15 2001-09-26 Toshiba Corp マトリクスアレイ基板
CN1388405A (zh) * 2001-05-29 2003-01-01 Lg.菲利浦Lcd株式会社 用喷墨系统形成液晶层的方法
US20020180897A1 (en) * 2001-06-05 2002-12-05 Chae Gee Sung Liquid crystal display and fabricating method thereof
CN101828212A (zh) * 2007-10-24 2010-09-08 株式会社神户制钢所 显示装置及该显示装置使用的Cu合金膜
CN101552277A (zh) * 2008-04-03 2009-10-07 上海广电Nec液晶显示器有限公司 薄膜晶体管阵列基板及其制造方法
CN102034750A (zh) * 2009-09-25 2011-04-27 北京京东方光电科技有限公司 阵列基板及其制造方法

Also Published As

Publication number Publication date
CN102768991A (zh) 2012-11-07
CN102768991B (zh) 2015-07-15

Similar Documents

Publication Publication Date Title
CN103489877B (zh) 阵列基板及其制造方法和显示装置
WO2016201729A1 (zh) 一种阵列基板及其制作方法、液晶显示器
WO2018196112A1 (zh) Ltps阵列基板及其制作方法
WO2019041476A1 (zh) 一种阵列基板及其制作方法、显示面板
WO2018006479A1 (zh) 阵列基板及其制作方法、以及液晶显示面板
WO2014019252A1 (zh) 液晶显示装置、阵列基板及其制作方法
WO2018133134A1 (zh) Coa基板及液晶显示面板
WO2017118073A1 (zh) 阵列基板及其制备方法和显示装置
WO2014019227A1 (zh) 一种液晶显示装置、阵列基板及其制作方法
WO2017054191A1 (zh) 一种tft阵列基板及其制作方法
WO2013177790A1 (zh) 阵列基板及其制备方法和液晶显示面板
WO2019052008A1 (zh) 一种阵列基板及其制备方法、显示装置
WO2017067062A1 (zh) 一种双栅极薄膜晶体管及其制作方法、以及阵列基板
CN106373967B (zh) 阵列基板及其制备方法、显示装置
CN103295906B (zh) 一种薄膜晶体管的制作方法和薄膜晶体管
WO2019029007A1 (zh) 一种tft基板的制备方法、tft基板以及oled显示面板
WO2021031532A1 (zh) 触控阵列基板及其制备方法
WO2018152874A1 (zh) 一种阵列基板及阵列基板的制作方法
WO2017128597A1 (zh) 液晶显示面板、tft基板及其制造方法
WO2016078112A1 (zh) 薄膜晶体管基板的制作方法及制造设备
WO2017049663A1 (zh) 一种彩膜阵列基板及其制造方法、显示装置
WO2016149958A1 (zh) 液晶显示面板、阵列基板及其薄膜晶体管的制造方法
WO2016090690A1 (zh) 一种ltps像素单元及其制造方法
WO2017063207A1 (zh) 阵列基板及其制造方法
WO2018214210A1 (zh) 一种阵列基板及其制作方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 13582746

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12882509

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12882509

Country of ref document: EP

Kind code of ref document: A1