WO2014013571A1 - 半導体装置の検査装置、検査システム、検査方法、及び、検査済半導体装置の生産方法 - Google Patents
半導体装置の検査装置、検査システム、検査方法、及び、検査済半導体装置の生産方法 Download PDFInfo
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- WO2014013571A1 WO2014013571A1 PCT/JP2012/068230 JP2012068230W WO2014013571A1 WO 2014013571 A1 WO2014013571 A1 WO 2014013571A1 JP 2012068230 W JP2012068230 W JP 2012068230W WO 2014013571 A1 WO2014013571 A1 WO 2014013571A1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
- G01R31/2863—Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
Definitions
- the technology disclosed in this specification relates to a semiconductor device.
- Patent Document 1 discloses a burn-in inspection method for semiconductor devices.
- a plurality of semiconductor devices are connected to a common ammeter.
- this inspection method by controlling a signal input to each semiconductor device, only one selected semiconductor device is turned on, and the other semiconductor devices are not turned on. As a result, the energization current of the selected semiconductor device is detected by the ammeter, and it is tested whether or not the selected semiconductor device operates properly.
- another semiconductor device is selected and the semiconductor device is inspected. In this way, all semiconductor devices are inspected.
- a semiconductor device with poor conduction is a semiconductor device that is turned on (that is, conducted) even though a signal that is not turned on is input. That is, when a semiconductor device with poor conduction is included, even the semiconductor device with poor conduction that is not selected is turned on during the inspection of the selected semiconductor device. Then, in addition to the energizing current of the selected semiconductor device, the energizing current of the semiconductor device with poor conduction flows through the ammeter. For this reason, the energization current of the selected semiconductor device cannot be detected, and an accurate inspection cannot be performed.
- the inspection apparatus disclosed in this specification inspects an output signal of a semiconductor device.
- This inspection apparatus has a monitor line, a monitor apparatus for detecting a signal on the monitor line, and a plurality of inspection circuits connected to the monitor line.
- Each inspection circuit can be provided with a semiconductor device, a semiconductor device support having a signal terminal to which a signal is input from the installed semiconductor device, and a first resistor connected between the signal terminal and the monitor line And a first diode connected between the signal terminal and the selector terminal so that the selector terminal side becomes a cathode.
- FIG. 1 shows an embodiment of the inspection apparatus described above as an example.
- reference numeral 100 is a monitor device
- reference numeral 102 is a monitor line
- reference numeral 104 is an inspection circuit.
- two inspection circuits 104a and 104b are shown, but two or more inspection circuits may be connected to the monitor line.
- Reference numeral 110 is a semiconductor device support
- reference numeral 112 is a semiconductor device
- reference numeral 114 is a first resistor
- reference numeral 116 is a first diode
- reference numeral 118 is a selector terminal.
- reference numeral 120 is a signal terminal.
- one semiconductor device is selected from the semiconductor devices installed in the inspection apparatus, and a first potential is applied to the selector terminal of the inspection circuit having the selected semiconductor device. To do. A second potential lower than the first potential is applied to selector terminals of other inspection circuits.
- the semiconductor device 112a is selected in FIG. 1
- the first potential V1 is applied to the selector terminal 118a
- the second potential V2 is applied to the selector terminal 118b.
- the first potential V1 is applied to the selector terminal 118a
- the first diode 116a is not turned on. Therefore, a signal output from the semiconductor device 112 a to the signal terminal 120 a is output on the monitor line 102.
- the monitor device 100 can accurately detect the output signal of the selected semiconductor device 112a.
- each semiconductor device can be correctly inspected.
- the present specification provides an inspection method for inspecting an output signal of a semiconductor device using an inspection apparatus.
- the inspection apparatus has a monitor line and a plurality of inspection circuits connected to the monitor line.
- Each inspection circuit can install a semiconductor device, a semiconductor device support having a signal terminal to which a signal is input from the installed semiconductor device, and a first resistor connected between the signal terminal and the monitor line And a first diode connected between the signal terminal and the selector terminal so that the selector terminal side becomes a cathode.
- the inspection method includes the steps of installing a semiconductor device on each semiconductor device support, applying a first potential to a first selector terminal of a plurality of selector terminals, and applying a first potential lower than the first potential to the other selector terminals.
- the present specification also provides a method for producing an inspected semiconductor device.
- This production method includes a step of forming a structure of a semiconductor device and a step of inspecting the formed semiconductor device.
- the inspection apparatus used in the inspection step has a monitor line and a plurality of inspection circuits connected to the monitor line.
- Each inspection circuit can install a semiconductor device, a semiconductor device support having a signal terminal to which a signal is input from the installed semiconductor device, and a first resistor connected between the signal terminal and the monitor line And a first diode connected between the signal terminal and the selector terminal so that the selector terminal side becomes a cathode.
- the step of inspecting includes the step of installing a semiconductor device on each semiconductor device support, applying a first potential to a first selector terminal of a plurality of selector terminals, and applying the first potential to other selector terminals than the first potential.
- the circuit diagram of the inspection system of other examples. The circuit diagram of the inspection system of other examples.
- the forward voltage of the diode means a voltage generated between the anode and cathode of the diode when a rated current is passed.
- the upper potential of the signal means the potential in the highest potential state among a plurality of potential states that the signal can take.
- the lower potential of a signal means a potential in the lowest potential state among a plurality of potential states that the signal can take.
- the high potential is the upper potential and the low potential is the lower potential.
- the open potential electrode Since the open potential electrode is in a floating state, the potential is determined by the surrounding environment. In general, the open potential is lower than the high potential and higher than the low potential. Also in this case, the high potential is the upper potential and the low potential is the lower potential. In a signal that transitions between a high potential and an open potential, the high potential is an upper potential and the open potential is a lower potential. In a signal that transitions between an open potential and a low potential, the open potential is an upper potential and the low potential is a lower potential.
- the condition for not turning on the first diode 116a is V1> Vout1-VF11 (Vout1 is the potential of the signal terminal 120a).
- Vout1 is the potential of the signal terminal 120a.
- the potential Vout1 does not become higher than the upper potential VH1. Therefore, as long as V1> VH1-VF11 is satisfied, the first diode 116a can be always turned off during the inspection of the selected semiconductor device 112a.
- the condition for turning on the second diode 116b is V2 ⁇ Vout2-VF12 (Vout2 is the potential of the signal terminal 120b).
- Each inspection circuit has a second diode connected in parallel to the first resistor so that the monitor line side becomes a cathode.
- FIG. 2 shows an embodiment of the feature 3 configuration. 2 is obtained by adding the second diode 122 to FIG. According to such a configuration, when the output signal from the selected semiconductor device 112a is the upper potential, the diode 122a is turned on. Thereby, a signal is transmitted from the semiconductor device 112a to the monitor line. According to such a configuration, since the signal is transmitted to the monitor line 102 via the first resistor 114a and the diode 122a as compared with the case where the signal is transmitted to the monitor line 102 only through the first resistor 114a, the semiconductor device 112a. Thus, the potential of the monitor line 102 when the output signal from is at the upper potential can be increased. Therefore, the SN ratio of the signal on the monitor line 102 can be increased.
- the selected semiconductor device 112a when the selected semiconductor device 112a outputs the lower potential VL1, the potential of the monitor line 102 becomes substantially equal to the lower potential VL1.
- the first diode 116b is turned on before the second diode 122b. Therefore, according to this feature, even if the semiconductor device 112b outputs a high potential, the potential can be prevented from being output to the monitor line 102 via the second diode 122b.
- Each test circuit has a second resistor connected between a connection portion connecting the anode of the first diode and the first resistor and the signal terminal.
- Each semiconductor device support has a high potential terminal for supplying a high potential to the installed semiconductor device and a low potential terminal for supplying a low potential to the installed semiconductor device.
- Each of the plurality of inspection circuits has a third resistor connected between the high potential terminal and the signal terminal.
- a semiconductor device that outputs an open potential and a low potential can be inspected more accurately.
- Each semiconductor device support has a high potential terminal for supplying a high potential to the installed semiconductor device and a low potential terminal for supplying a low potential to the installed semiconductor device.
- Each inspection circuit has a fourth resistor connected between the low potential terminal and the signal terminal.
- a semiconductor device that outputs an open potential and a high potential can be inspected more accurately.
- the burn-in inspection system 10 shown in FIG. 3 operates the IC in a high temperature environment and inspects the output signal of the IC.
- the burn-in inspection system 10 includes a control unit 20 and a burn-in board 30.
- monitor line 42 On the substrate of the burn-in board 30, a monitor line 42 extending in the horizontal direction in FIG. 3 is formed.
- the n monitor lines 42 are arranged in the vertical direction of FIG.
- the monitor line 42 existing in the j-th row is represented as a monitor line 42-j (j is an arbitrary integer, 1 ⁇ j ⁇ n).
- selector line 44 On the substrate of the burn-in board 30, a selector line 44 extending in the vertical direction of FIG. 3 is formed. M selector lines 44 are arranged in the horizontal direction of FIG.
- the selector lines 44 existing in the k columns are represented as selector lines 44-k (k is an arbitrary integer, 1 ⁇ k ⁇ m).
- a selector terminal 46 is formed at the end of the selector line 44. That is, there are m selector terminals 46.
- the selector terminal 46 connected to the selector line 44-k is referred to as a selector terminal 46-k.
- a large number of inspection circuits 40 are formed on the substrate of the burn-in board 30.
- M inspection circuits 40 are arranged in the horizontal direction in FIG. 3, and n inspection circuits 40 are arranged in the vertical direction in FIG. That is, m ⁇ n inspection circuits 40 are formed on the substrate of the burn-in board 30.
- the inspection circuit 40 existing in the j row and the k column may be expressed as an inspection circuit 40-jk.
- each component in the inspection circuit 40 may be represented by the same notation.
- the inspection circuit 40-jk is connected to the monitor line 42-j and the selector line 44-k.
- Each inspection circuit 40 includes an IC socket 32, a resistor 34, and a diode 36.
- reference numerals such as an IC socket, a resistor, and a diode are attached only to the inspection circuit 40-11 and the inspection circuit 40-12 in consideration of easy viewing. ing. Since the configuration of each test circuit 40 is the same, the configuration of one test circuit 40 will be described below.
- An IC is attached to the IC socket 32 of the inspection circuit 40.
- the IC socket 32 includes a large number of terminals.
- the IC socket 32 has a terminal 32 a connected to the power supply wiring 50 and a terminal 32 b connected to the ground wiring 52.
- the IC socket 32 has a signal terminal 32 c connected to the output wiring 54.
- a signal is input from the IC installed in the IC socket 32 to the signal terminal 32c.
- the signal transitions between the power supply potential Vcc and the ground potential V0.
- the IC installed in the IC socket 32 is controlled by a control signal input from a terminal (not shown).
- a resistor 34 is connected between the output wiring 54 and the monitor line 42.
- a diode 36 is connected between the output wiring 54 and the selector line 44. The diode 36 is connected so that the selector line 44 side becomes a cathode.
- the control unit 20 has n monitor devices 22. Each monitor device 22 is connected to a corresponding monitor line 42. Hereinafter, the monitor device 22 connected to the monitor line 42-j is referred to as a monitor device 22-j.
- the monitor device 22-j detects a signal (potential) on the monitor line 42-j.
- the control unit 20 has a selector device 24.
- the selector device 24 controls the potentials of the m selector terminals 46-1 to 46-m.
- the burn-in inspection system 10 is used in IC production lines.
- the IC production method will be described below.
- the IC production method includes a step of forming an IC structure and a step of inspecting the IC.
- a semiconductor circuit is formed in the semiconductor wafer by ion implantation or the like.
- the semiconductor wafer is divided into semiconductor chips by dicing.
- the semiconductor chip is fixed to the lead frame, and the semiconductor chip and the lead frame are connected by wire bonding or the like. Thereafter, the semiconductor chip is resin-molded together with the lead frame. Thereby, the IC before the inspection is completed.
- the above-described inspection system 10 is used to inspect the IC.
- an IC is installed in each IC socket 32 of the inspection system 10.
- m ⁇ n ICs are installed in the inspection system 10.
- the IC installed in the socket 32-jk is referred to as IC-jk.
- the burn-in board 30 is heated to a predetermined temperature. Each IC is inspected while the burn-in board 30 is heated.
- step S2 all the ICs are operated. As a result, a signal is output to the signal terminal 32 c of each IC socket 32. The subsequent steps are performed while each IC is operating.
- step S4 the selector device 24 selects a column to be inspected.
- the first column ie, IC-11 to IC-n1 is selected.
- step S6 the selector device 24 first applies the low potential Vlo to the selector terminal 46 corresponding to the unselected column.
- the selector device 24 applies the high potential Vhi to the selector terminal 46 corresponding to the selected column.
- Each monitor device 22 detects a signal on the corresponding monitor line 42. Since the first column is selected in the first step S4, in the first step S6, the high potential Vhi is applied to the selector terminal 46-1 and the low potential Vlo is applied to the selector terminals 46-2 to 46-m.
- the operation of each of the inspection circuits 40-11 to 40-1m connected to the monitor line 42-1 in this case will be described.
- the low potential Vlo is applied to the selector line 44-2.
- the low potential Vlo is substantially equal to the ground potential V0.
- the low potential Vlo, the upper potential Vcc of the signal output from the IC-12 (that is, the power supply potential Vcc), and the forward voltage VF36 of the diode 36-12 satisfy the relationship of Vlo ⁇ Vcc-VF36.
- the diode 36-12 is turned on. Therefore, in the inspection circuit 40-12, the potential of the signal terminal 32c is substantially fixed at the potential V0.
- the inspection circuits 40-13 to 40-1m operate in the same manner as the inspection circuit 40-12 (in this embodiment, the upper potentials Vcc of the output signals of all the ICs are substantially equal to each other, and all the diodes 36 are Forward voltages VF36 are substantially equal to each other). Therefore, no signal is transmitted on the monitor line 42-1 from the inspection circuits 40-13 to 40-1m.
- the high potential Vhi is applied to the selector line 44-1.
- the high potential Vhi is substantially equal to the power supply potential Vcc. Therefore, the high potential Vhi, the upper potential Vcc of the signal output from the IC-11, and the forward voltage VF36 of the diode 36-11 satisfy the relationship of Vhi> Vcc ⁇ VF36. Therefore, the diode 36-11 is not turned on, and the signal output from the IC-11 is output onto the monitor line 42-1 via the resistor 34-11. Therefore, the monitor device 22-1 detects the signal of the IC-11.
- FIG. 5 shows an equivalent circuit of each of the inspection circuits 40-11 to 40-1m connected to the monitor line 42-1. Since the diodes 36-12 to 36-1m are on, when the IC-11 outputs the potential Vcc to the signal terminal 32c, the signal terminal 32c of the IC-11 and other IC-12 to IC-1m The potential difference ⁇ V (see FIG. 5) between the signal terminals 32c is Vcc ⁇ (VF36 + Vlo). Therefore, the voltage applied to each of the resistors 34-12 to 34-1m is divided into the potential difference ⁇ V by the combined resistance value RN of the resistors 34-12 to 34-1m and the resistance value R11 of the resistor 34-11.
- Equation 1 the potential VM1 of the monitor line 42-1 when the IC-11 outputs the potential Vcc to the signal terminal 32c is: (Equation 1) It becomes. However, It is. As described above, since the potential Vlo is substantially equal to the ground potential V0 (that is, 0 V), the above equation 1 can also be expressed as follows. (Equation 2)
- the potential VM2 of the monitor line 42-1 when the IC-11 outputs the potential V0 to the signal terminal 32c is substantially equal to the potential V0.
- the monitor device 22-1 detects a signal that transitions between the VM1 and the VM2.
- the monitor device 22-1 determines whether the IC-11 is normal by comparing the detected signal with an expected value.
- each inspection circuit 40 connected to the other monitor lines 42-2 to 42-n operates in the same manner as each inspection circuit 40 connected to the monitor line 42-1. Accordingly, the signals of IC-21 to IC-n1 are detected by the monitor devices 22-2 to 22-n, and the quality of these signals is determined.
- step S6 it is determined whether or not the inspection has been completed for all ICs (step S8). If not completed, the processing from step S4 is repeated again. In the next step S4, the next column after the previously selected column is selected. Therefore, by repeating steps S4 to S8, the test is performed up to the IC in the last column m. When the inspection for all the ICs is completed, the inspection system 10 ends the process.
- this inspection system 10 it is possible to prevent a signal from being output to the monitor line 42 from an IC in a non-selected column. Therefore, the selected IC can be accurately inspected. Further, since no signal is output from the IC in the non-selected column to the monitor line 42, the IC in the selected column can be inspected while continuing the operation of the IC in the non-selected column. Further, even if there is a failure or the like in the IC in the non-selected column, the inspection result of the IC in the selected column is not affected. For example, even if an unselected IC tries to output an abnormal potential to the signal terminal 32c due to a failure or the like, the potential of the signal terminal 32c does not rise. Therefore, an accurate inspection of the selected IC is possible.
- each inspection circuit 40 belonging to the selected column is connected to a different monitor line 42. Therefore, it is possible to inspect a plurality of ICs at a time.
- Some ICs output an open potential.
- the open potential is an unstable potential that varies depending on the surrounding environment, the inspection accuracy decreases. Therefore, another embodiment capable of suitably inspecting an IC that outputs an open potential will be described below.
- FIG. 6 shows an embodiment suitable for an IC that outputs an open potential and a power supply potential Vcc.
- a resistor 38 for connecting the signal terminal 32 c and the ground wiring 52 is added to each inspection circuit 40 as compared with FIG. 3.
- the selected IC inputs the power supply potential Vcc to the signal terminal 32c
- the potential is output to the monitor line 42 as in the above-described embodiment.
- the selected IC outputs an open potential to the signal terminal 32c
- the signal terminal 32c since the signal terminal 32c is connected to the ground wiring 52 by the resistor 38, the signal terminal 32c becomes the ground potential V0.
- the potential of the monitor line 42 becomes the ground potential V0 in the same manner as in the above-described embodiment.
- the potential of the signal terminal 32c is fixed to the ground potential V0, so that a clearer signal can be detected by the monitor device 22. Therefore, the inspection can be performed more accurately.
- FIG. 7 shows an embodiment suitable for an IC that outputs an open potential and a ground potential V0.
- a resistor 39 for connecting the signal terminal 32 c and the power supply wiring 50 is added to each inspection circuit 40 as compared with FIG. 3.
- the selected IC inputs an open potential to the signal terminal 32c
- the signal terminal 32c becomes the power supply potential Vcc. Therefore, a potential is output to the monitor line 42 as in the above-described embodiment.
- the selected IC outputs the ground potential V0 to the signal terminal 32c
- the potential of the monitor line 42 becomes the ground potential V0 as in the above-described embodiment.
- an IC that outputs the open potential and the ground potential V0 can be appropriately inspected.
- FIG. 8 shows an embodiment in which unselected ICs and diodes 36 can be protected from overcurrent.
- the power supply terminal 32 a and the signal terminal 32 c are short-circuited due to an IC failure, current flows from the power supply wiring 50 to the selector line 44 via the IC and the diode 36. Since there is no load in this path, an overcurrent flows and the IC or the diode 36 may be damaged.
- a resistor 37 is added between the signal terminal 32 c and the diode 36. For this reason, even if an IC short circuit occurs, an extremely large current is prevented from flowing. If an overcurrent protection circuit or the like is formed in the IC, the resistor 37 shown in FIG. 8 is not necessarily required.
- FIG. 9 shows an embodiment in which a diode 35 connected in parallel to the resistor 34 of each inspection circuit 40 is added.
- the diode 35 is connected so that the monitor line 42 side becomes a cathode.
- the diode 35 may be turned on.
- the non-selected inspection circuit 40 needs to be set so that the diode 36 is turned on before the diode 35.
- the diode 35 of the non-selected inspection circuit 40 is turned on when the potential of the signal terminal 32c exceeds V0 + VF35 (note that the voltage VF35 is a forward voltage of the diode 35).
- the diode 36 is turned on when the potential of the signal terminal 32c exceeds Vlo + VF36. Therefore, if V0 + VF35> Vlo + VF36 is satisfied, the diode 36 is turned on before the diode 35 when the potential of the signal terminal 32c of the non-selected inspection circuit 40 rises.
- the low potential Vlo is lower than the ground potential V0.
- the forward voltage VF35 of the diode 35 is substantially equal to the forward voltage VF36 of the diode 36. Therefore, the above relationship is satisfied, and a signal is prevented from being transmitted to the monitor line 42 from the non-selected inspection circuit 40.
- FIG. 10 shows an equivalent circuit of each inspection circuit 40 connected to the monitor line 42-1 of FIG.
- Vcc the power supply potential
- the potential VM2 of the monitor line 42-1 is substantially equal to the potential V0 as in the other embodiments described above.
- Equation 3 Compare Equation 3 with Equation 1 (or Equation 2).
- Equation 1 described above ie, the embodiment of FIG. 3
- the combined resistance RN decreases as the number of test circuits 40 connected to the monitor line 42-1 increases.
- the selected IC outputs the power supply potential Vcc
- the potential obtained on the monitor line 42-1 is lowered.
- the signal-to-noise ratio of the signal appearing on the monitor line 42-1 is lowered, and the inspection accuracy is lowered.
- the voltage VM1 is not affected by the combined resistance RN.
- FIG. 11 shows an embodiment in which the embodiment of FIG. 8 and the embodiment of FIG. 9 are combined. According to such a combination, the technical effects of both FIG. 8 and FIG. 9 can be obtained.
- FIG. 12 shows an embodiment in which the embodiment of FIG. 6, the embodiment of FIG. 8, and the embodiment of FIG. 9 are combined. Even in this combination, the effects of FIGS. 6, 8, and 9 can be obtained.
- the embodiments can be combined in other modes.
- FIG. 13 shows a configuration in which the selector line 44 extends in the horizontal direction and the monitor line 42 extends in the vertical direction.
- the physical arrangement of each component may be changed.
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Abstract
Description
(数1)
となる。但し、
である。なお、上記の通り、電位Vloはグランド電位V0(すなわち、0V)と略等しいので、上記数1は、以下のように表すこともできる。
(数2)
(数3)VM1=Vcc-VF35
となる。
本明細書または図面に説明した技術要素は、単独であるいは各種の組み合わせによって技術的有用性を発揮するものであり、出願時請求項記載の組み合わせに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成するものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。
Claims (11)
- 半導体装置の出力信号を検査する検査装置であって、
モニタラインと、
モニタライン上の信号を検出するモニタ装置と、
モニタラインに接続されている複数の検査回路、
を有しており、
各検査回路が、
半導体装置を設置可能であり、設置された半導体装置から信号が入力される信号端子を有する半導体装置支持具と、
信号端子とモニタラインの間に接続されている第1抵抗器と、
セレクタ端子と、
信号端子とセレクタ端子の間にセレクタ端子側がカソードとなるように接続されている第1ダイオード、
を有している検査装置。 - 複数のセレクタ端子のうちの第1のセレクタ端子に第1電位を印加し、他のセレクタ端子に第1電位よりも低い第2電位を印加する動作と、複数のセレクタ端子のうちの第2のセレクタ端子に第1電位を印加し、他のセレクタ端子に第2電位を印加する動作とを実行可能なセレクタ装置をさらに備える請求項1の検査装置。
- 第1電位V1と、
第1電位の印加対象のセレクタ端子に対応する信号端子に入力される信号の高電位VH1と、
第1電位の印加対象のセレクタ端子に対応する第1ダイオードの順電圧VF11が、
V1>VH1-VF11
の関係を満たし、
第2電位V2と、
第2電位の印加対象のセレクタ端子に対応する信号端子に入力され得る信号の高電位VH2と、
第2電位の印加対象のセレクタ端子に対応する第1ダイオードの順電圧VF12が、
V2<VH2-VF12
の関係を満たす、
請求項2の検査装置。 - 各検査回路が、第1抵抗器に対して並列に、モニタライン側がカソードとなるように接続されている第2ダイオードを有している請求項1~3のいずれか一項の検査装置。
- 第1電位の印加対象のセレクタ端子に対応する信号端子に入力される信号の低電位VL1と、
第2電位V2と、
第2電位の印加対象のセレクタ端子に対応する第1ダイオードの順電圧VF12と、
第2電位の印加対象のセレクタ端子に対応する第2ダイオードの順電圧VF22が、
V2+VF12<VL1+VF22
の関係を満たす請求項4の検査装置。 - 各検査回路が、第1ダイオードのアノードと第1抵抗器とを接続している接続部と信号端子との間に接続されている第2抵抗器を有している請求項1~5のいずれか一項の検査装置。
- 各半導体装置支持具が、設置された半導体装置に高電位を供給する高電位端子と、設置された半導体装置に低電位を供給する低電位端子を有しており、
複数の検査回路の各々が、高電位端子と信号端子の間に接続されている第3抵抗器を有している請求項1~6のいずれか一項の検査装置。 - 各半導体装置支持具が、設置された半導体装置に高電位を供給する高電位端子と、設置された半導体装置に低電位を供給する低電位端子を有しており、
複数の検査回路の各々が、低電位端子と信号端子の間に接続されている第4抵抗器を有している請求項1~6のいずれか一項の検査装置。 - 請求項1の検査装置を複数個有しており、
各検査装置のモニタライン及びモニタ装置が独立しており、
各検査装置が有するセレクタ端子が、他の検査装置のセレクタ端子と共通化されている、
検査システム。 - 検査装置を用いて半導体装置の出力信号を検査する検査方法であって、
検査装置は、
モニタラインと、
モニタラインに接続されている複数の検査回路、
を有しており、
各検査回路が、
半導体装置を設置可能であり、設置された半導体装置から信号が入力される信号端子を有する半導体装置支持具と、
信号端子とモニタラインの間に接続されている第1抵抗器と、
セレクタ端子と、
信号端子とセレクタ端子の間にセレクタ端子側がカソードとなるように接続されている第1ダイオード、
を有しており、
各半導体装置支持具に半導体装置を設置するステップと、
複数のセレクタ端子のうちの第1のセレクタ端子に第1電位を印加し、他のセレクタ端子に第1電位よりも低い第2電位を印加した状態で、モニタライン上の信号を検出するステップと、
複数のセレクタ端子のうちの第2のセレクタ端子に第1電位を印加し、他のセレクタ端子に第2電位を印加した状態で、モニタライン上の信号を検出するステップ、
を有する検査方法。 - 検査済半導体装置を生産する方法であって、
半導体装置の構造を形成する工程と、
形成された半導体装置を検査する工程、
を有しており、
前記検査する工程で用いる検査装置は、
モニタラインと、
モニタラインに接続されている複数の検査回路、
を有しており、
各検査回路が、
半導体装置を設置可能であり、設置された半導体装置から信号が入力される信号端子を有する半導体装置支持具と、
信号端子とモニタラインの間に接続されている第1抵抗器と、
セレクタ端子と、
信号端子とセレクタ端子の間にセレクタ端子側がカソードとなるように接続されている第1ダイオード、
を有しており、
前記検査する工程が、
各半導体装置支持具に半導体装置を設置するステップと、
複数のセレクタ端子のうちの第1のセレクタ端子に第1電位を印加し、他のセレクタ端子に第1電位よりも低い第2電位を印加した状態で、モニタライン上の信号を検出するステップと、
複数のセレクタ端子のうちの第2のセレクタ端子に第1電位を印加し、他のセレクタ端子に第2電位を印加した状態で、モニタライン上の信号を検出するステップ、
を有する製造方法。
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PCT/JP2012/068230 WO2014013571A1 (ja) | 2012-07-18 | 2012-07-18 | 半導体装置の検査装置、検査システム、検査方法、及び、検査済半導体装置の生産方法 |
KR1020157001274A KR101652648B1 (ko) | 2012-07-18 | 2012-07-18 | 반도체 장치의 검사 장치, 검사 시스템, 검사 방법, 및 검사가 완료된 반도체 장치의 생산 방법 |
US14/402,951 US9379029B2 (en) | 2012-07-18 | 2012-07-18 | Inspection apparatus, inspection system, inspection method of semiconductor devices, and manufacturing method of inspected semiconductor devices |
JP2014525604A JP5812200B2 (ja) | 2012-07-18 | 2012-07-18 | 半導体装置の検査装置、検査システム、検査方法、及び、検査済半導体装置の生産方法 |
CN201280003753.7A CN103688180B (zh) | 2012-07-18 | 2012-07-18 | 半导体装置的检验装置、检验系统、检验方法、以及检验完成的半导体装置的生产方法 |
TW102117213A TWI471576B (zh) | 2012-07-18 | 2013-05-15 | The inspection apparatus, the inspection system, the inspection method, and the inspection method of the semiconductor device of the semiconductor device |
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KR (1) | KR101652648B1 (ja) |
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0634719A (ja) * | 1992-07-13 | 1994-02-10 | Fujitsu Ltd | 半導体集積回路の試験装置 |
JP2006105738A (ja) * | 2004-10-04 | 2006-04-20 | Canon Inc | 半導体集積回路検査装置、半導体集積回路検査方法、及びプログラム |
WO2008044391A1 (fr) * | 2006-10-05 | 2008-04-17 | Advantest Corporation | Dispositif de contrôle, procédé de contrôle et procédé de fabrication |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02118470A (ja) | 1988-10-28 | 1990-05-02 | Nec Corp | バーンイン装置 |
JP2001296335A (ja) | 2000-04-14 | 2001-10-26 | Nec Corp | 半導体装置の検査方法及び検査装置 |
TW573128B (en) * | 2001-05-15 | 2004-01-21 | Semiconductor Energy Lab | Voltage measuring method, electrical test method and apparatus, semiconductor device manufacturing method and device substrate manufacturing method |
JP2003121500A (ja) | 2001-10-10 | 2003-04-23 | Mitsubishi Electric Corp | 半導体装置の試験装置及び試験方法 |
JP2004226115A (ja) * | 2003-01-20 | 2004-08-12 | Elpida Memory Inc | 半導体装置及びその試験方法 |
JP2004257921A (ja) | 2003-02-27 | 2004-09-16 | Sharp Corp | 半導体装置の検査装置および半導体装置の検査方法 |
JP2005122574A (ja) * | 2003-10-17 | 2005-05-12 | Renesas Technology Corp | 半導体集積回路 |
US7317324B2 (en) | 2003-11-04 | 2008-01-08 | Canon Kabushiki Kaisha | Semiconductor integrated circuit testing device and method |
JP2006189340A (ja) | 2005-01-06 | 2006-07-20 | Nec Electronics Corp | 半導体デバイスの検査システムおよび検査方法 |
JP4794896B2 (ja) | 2005-04-22 | 2011-10-19 | シャープ株式会社 | 半導体回路、半導体デバイス、および、該半導体回路の検査方法 |
JP2007171114A (ja) | 2005-12-26 | 2007-07-05 | Yamaha Corp | 半導体試験基板および接触不良判定方法 |
JP4623659B2 (ja) * | 2006-02-23 | 2011-02-02 | パナソニック株式会社 | 半導体装置 |
JP2007315789A (ja) | 2006-05-23 | 2007-12-06 | Fujifilm Corp | 半導体集積回路およびその実装検査方法 |
CN201017308Y (zh) * | 2007-03-07 | 2008-02-06 | 青岛海信电器股份有限公司 | 一种i2c总线信号的通讯调试装置 |
CN201035124Y (zh) * | 2007-04-19 | 2008-03-12 | 清华大学 | 集成电路测试仪 |
KR101563904B1 (ko) * | 2008-09-29 | 2015-10-28 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 |
US8400176B2 (en) * | 2009-08-18 | 2013-03-19 | Formfactor, Inc. | Wafer level contactor |
JP2012226794A (ja) * | 2011-04-18 | 2012-11-15 | Elpida Memory Inc | 半導体装置、及び半導体装置の制御方法。 |
-
2012
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0634719A (ja) * | 1992-07-13 | 1994-02-10 | Fujitsu Ltd | 半導体集積回路の試験装置 |
JP2006105738A (ja) * | 2004-10-04 | 2006-04-20 | Canon Inc | 半導体集積回路検査装置、半導体集積回路検査方法、及びプログラム |
WO2008044391A1 (fr) * | 2006-10-05 | 2008-04-17 | Advantest Corporation | Dispositif de contrôle, procédé de contrôle et procédé de fabrication |
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CN103688180B (zh) | 2016-07-06 |
TW201411151A (zh) | 2014-03-16 |
JP5812200B2 (ja) | 2015-11-11 |
KR101652648B1 (ko) | 2016-08-30 |
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