WO2014012425A1 - Procédé de fabrication d'un igbt à diaphragme de champ - Google Patents

Procédé de fabrication d'un igbt à diaphragme de champ Download PDF

Info

Publication number
WO2014012425A1
WO2014012425A1 PCT/CN2013/078528 CN2013078528W WO2014012425A1 WO 2014012425 A1 WO2014012425 A1 WO 2014012425A1 CN 2013078528 W CN2013078528 W CN 2013078528W WO 2014012425 A1 WO2014012425 A1 WO 2014012425A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
protective layer
wafer
igbt
front side
Prior art date
Application number
PCT/CN2013/078528
Other languages
English (en)
Chinese (zh)
Inventor
张硕
芮强
王根毅
邓小社
Original Assignee
无锡华润上华半导体有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 无锡华润上华半导体有限公司 filed Critical 无锡华润上华半导体有限公司
Publication of WO2014012425A1 publication Critical patent/WO2014012425A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT

Definitions

  • the present invention relates to the field of Insulated Gate Bipolar Transistors (IGBT), and relates to field stop (FS) IGBTs, and more particularly to forming a protective layer on the back surface of a wafer to implement a field stop layer of an IGBT.
  • IGBT Insulated Gate Bipolar Transistors
  • FS field stop
  • Background technique
  • the IGBT is a common power type device that includes an FS-IGBT.
  • the FS layer is usually formed on the back side of the wafer, and then the conventional IGBT front process flow is performed, and finally the back electrode is formed on the FS layer on the back side (for example, it is used as a collector.
  • the front process the process is complicated and the steps are numerous.
  • the FS layer on the back side of the wafer is easily damaged during the flow process of the front side process, for example, the surface is scratched, thereby causing local damage to the FS layer. This damage will not only reduce the fabrication yield of the FS-IGBT, but also negatively affect the performance of the FS-IGBT.
  • the object of the present invention is to achieve good protection of the back FS layer during the preparation of the FS-IGBT.
  • the present invention provides a method of fabricating a field termination insulated gate bipolar transistor comprising the steps of:
  • a back electrode is formed on the field stop layer.
  • the protective layer is a multi-silicon protective layer.
  • a protective layer is simultaneously formed in the On the front side of the wafer, after a protective layer is formed on the back side of the wafer, the protective layer on the front side of the wafer is removed.
  • the field stop layer doping is performed by an ion implantation doping method.
  • the field stop layer doping is subjected to a push-trap process to form a field stop layer.
  • the field stop layer has a doping concentration ranging from 1E12 ions/cm 3 to 1E19 ions/cm 3
  • a lattice damage to the semiconductor substrate is prevented on the back surface of the wafer for preventing ion implantation.
  • the polysilicon protective layer is formed by a low pressure chemical vapor deposition (LPCVD) method.
  • LPCVD low pressure chemical vapor deposition
  • the polysilicon protective layer has a thickness ranging from 100 nm to 2000 nm.
  • the removal of the protective layer is performed by a dry etching method.
  • completing the front side process stream at least completes the front side isolation dielectric layer preparation.
  • the technical effect of the invention is that the protective layer used in the preparation process realizes the protection of the field stop layer in the front side process flow, and prevents the FS layer from being partially damaged in the front side process flow, thereby facilitating the improvement of the performance of the FS-IGBT and Yield.
  • FIG. 1 is a flow chart showing a method of fabricating an FS-IGBT according to an embodiment of the present invention.
  • 2 to 7 are schematic structural changes corresponding to the flow of the method corresponding to the embodiment shown in Fig. 1.
  • the back side is defined as one side for forming the FS layer
  • the front side is defined as at least one side for forming the gate end of the FS-IGBT.
  • Fig. 1 is a flow chart showing a method of fabricating an FS-IGBT according to an embodiment of the present invention.
  • 2 to 7 are schematic views showing the structural changes of the method flow corresponding to the embodiment shown in Fig. 1.
  • the direction perpendicular to the wafer surface and directed from the back side of the wafer toward the front side of the wafer is defined as the z direction, parallel to the wafer surface and defined as the X direction below the channel end.
  • the lithography method of the embodiment of the present invention will be described below with reference to Figs. 1 through 7.
  • step S10 a wafer for preparing an FS-IGBT and performing doping of the FS layer on the back side thereof is provided.
  • the wafer 100 is an N-doped semiconductor substrate having a doping concentration of a doping concentration of the drift layer of the IGBT to be formed. Therefore, the doping concentration range of the wafer 100 is selected to be 8E12 ions/cm. 3 to 1E13 ion/cm 3 , for example, 9E12 ion/cm 3 . Ion implantation doping is required on the back surface of the wafer 100 to form an FS layer.
  • a thin oxide layer 120 is formed on the back surface of the wafer 100 in order to prevent lattice damage of the semiconductor substrate caused by backside ion implantation. In particular, it may be inevitable to simultaneously form a thin oxide layer 120 (as shown) on the front side of the wafer 100. In other embodiments, a specific process may be employed to form a thin oxide layer 120 on the back side of the wafer. A thin oxide layer 120 is not formed on the front side of the wafer. The thickness of the thin oxide layer 120 ranges from 10 nm to 100 nm (for example, 100 nm, and the thickness thereof is thin, so that it is difficult to achieve back surface protection.
  • a relatively highly doped FS layer 110a is formed, after which In the step, the impurities in the FS layer 110a are activated by the push-trap process.
  • a polysilicon protective layer is deposited on the back surface of the wafer and the FS is formed. Layer doping is performed to push the well.
  • a polysilicon protective layer 130 is formed on the back side of the wafer, which can be formed by various thin film deposition processes, for example, by LPCVD. Specifically, the thickness thereof ranges from 100 nm to 2000 nm, for example, 500 nm.
  • the FS layer 110a is further subjected to a push-trap process to finally form the FS layer 110, and the polysilicon protective layer 130 is formed on the thin oxide layer 120 to protect the FS layer 110.
  • the doping concentration of the FS layer 110 may range from 1E12 ions/cm 3 to 1E19 ions/cm 3 , for example, 1E18 ions/cm 3 .
  • the polysilicon protective layer 130 when the polysilicon protective layer 130 is deposited on the back side of the wafer, the polysilicon protective layer 130 is inevitably formed on the front side of the wafer, and the front polysilicon protective layer 130 does not achieve protection.
  • a specific deposition process may be employed to deposit a polysilicon protective layer 130 on the backside of the wafer while forming a polysilicon protective layer 130 on the back side of the wafer.
  • step S30 the polysilicon layer and the thin oxide layer formed on the front surface of the wafer are removed.
  • the polysilicon layer 130 and the thin oxide layer 120 on the front side of the wafer are not protected during the subsequent process, and therefore, they are removed in this step to expose the semiconductor substrate for the front side process.
  • the polysilicon layer 130 and the thin oxide layer 120 may be removed by dry etching.
  • step S40 the front side process flow is completed on the front side of the wafer.
  • a P-body region 140, an emitter 150, a gate dielectric layer 160, a polysilicon gate electrode 170, and an isolation dielectric layer 180 are formed on the front surface of the wafer (for implementing the emitter electrode (ie, the front isolation medium)
  • the layer, not shown in the figure) is electrically isolated from the polysilicon gate electrode, thereby completing the front side process.
  • the front side process at least completes the isolation dielectric layer 180 so that the damage to the front device surface is small in the subsequent backside process.
  • the specific device structure formed by the front side of the wafer is not limited by the embodiment of the present invention, and the specific process flow method is not limited.
  • the choice of the specific material of the protective layer on the back side of the wafer needs to be considered compatible with the front side process flow, for example, temperature parameters, etch selectivity, and the like.
  • the protective layer is preferably made of a polysilicon protective layer 130.
  • the polysilicon material is easily compatible with the front side process flow. For example, when the gate dielectric layer 160 is patterned, there is good etching selectivity between the two.
  • those skilled in the art may also select other materials for use as a protective layer on the back side of the wafer, for example, it may also be selected as a SiN material.
  • step S50 the polysilicon protective layer on the back side of the wafer and the thin oxide layer are removed. As shown in FIG. 6, after the protection of the polysilicon protective layer 130 is completed, it is removed. In this embodiment, the thin oxide layer 120 can be simultaneously removed. The removal of the polysilicon protective layer 130 can be removed by dry etching to minimize damage to the FS layer.
  • a collector layer is doped on the FS layer, and a back electrode is formed thereon.
  • the FS layer 110 is doped with ion implantation to form a collector layer 190, and a back electrode metal layer 195 (for example, an aluminum metal or alloy) is formed on the collector layer 190.
  • Collector layer 190 is a relatively high concentration of P-type dopant.
  • the FS-IGBT has been basically formed.
  • the polysilicon protective layer 130 used therein protects the FS layer in the front process flow, and prevents the FS layer from being locally damaged, thereby contributing to improving the performance and yield of the FS-IGBT.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Formation Of Insulating Films (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

La présente invention porte sur un procédé de fabrication d'un transistor bipolaire à grille isolée à diaphragme de champ (FS-IGBT), relatif au domaine technique des IGBT. Le procédé de fabrication comprend les étapes suivantes : la disposition d'une puce destinée à être utilisée dans la fabrication du FS-IGBT et dans l'achèvement, sur le côté arrière de celle-ci, d'un dopage de couche FS; la formation d'une couche de protection sur le côté arrière de la puce; l'achèvement d'un traitement de technique de côté avant pour le côté avant de la puce; le retrait de la couche de protection; et la formation d'une électrode arrière sur la couche FS. Le procédé de fabrication est capable d'empêcher des dommages locaux sur la couche FS durant le traitement de technique de côté avant, facilitant ainsi des performances et un rendement augmentés du FS-IGBT.
PCT/CN2013/078528 2012-07-19 2013-06-29 Procédé de fabrication d'un igbt à diaphragme de champ WO2014012425A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201210250435.2A CN103578980A (zh) 2012-07-19 2012-07-19 场终止绝缘栅双极型晶体管的制备方法
CN201210250435.2 2012-07-19

Publications (1)

Publication Number Publication Date
WO2014012425A1 true WO2014012425A1 (fr) 2014-01-23

Family

ID=49948259

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2013/078528 WO2014012425A1 (fr) 2012-07-19 2013-06-29 Procédé de fabrication d'un igbt à diaphragme de champ

Country Status (2)

Country Link
CN (1) CN103578980A (fr)
WO (1) WO2014012425A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003059856A (ja) * 2001-08-09 2003-02-28 Fuji Electric Co Ltd 半導体装置の製造方法
JP2006324585A (ja) * 2005-05-20 2006-11-30 Nissan Motor Co Ltd 炭化珪素半導体装置及びその製造方法
US20100197127A1 (en) * 2009-02-04 2010-08-05 Fuji Electric Systems Co., Ltd. Method of manufacturing a semiconductor device
CN202282352U (zh) * 2011-07-27 2012-06-20 江苏物联网研究发展中心 通过外延方法形成fs层的高压igbt

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3559971B2 (ja) * 2001-12-11 2004-09-02 日産自動車株式会社 炭化珪素半導体装置およびその製造方法
CN102420133B (zh) * 2011-09-30 2013-07-24 上海华虹Nec电子有限公司 Igbt器件的制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003059856A (ja) * 2001-08-09 2003-02-28 Fuji Electric Co Ltd 半導体装置の製造方法
JP2006324585A (ja) * 2005-05-20 2006-11-30 Nissan Motor Co Ltd 炭化珪素半導体装置及びその製造方法
US20100197127A1 (en) * 2009-02-04 2010-08-05 Fuji Electric Systems Co., Ltd. Method of manufacturing a semiconductor device
CN202282352U (zh) * 2011-07-27 2012-06-20 江苏物联网研究发展中心 通过外延方法形成fs层的高压igbt

Also Published As

Publication number Publication date
CN103578980A (zh) 2014-02-12

Similar Documents

Publication Publication Date Title
TWI577013B (zh) 具有共面下凹閘極層之半導體結構及製造方法
CN103177950B (zh) 制造鳍器件的结构和方法
TWI565074B (zh) 半導體結構與其製備方法
KR101797961B1 (ko) 반도체 장치의 제조 방법
US9368512B1 (en) Double diamond shaped unmerged epitaxy for tall fins in tight pitch
TWI785126B (zh) 半導體裝置結構及其形成方法
US9793274B2 (en) CMOS transistors including gate spacers of the same thickness
US10483377B2 (en) Devices and methods of forming unmerged epitaxy for FinFet device
US8962430B2 (en) Method for the formation of a protective dual liner for a shallow trench isolation structure
US20120264286A1 (en) Methods of manufacturing semiconductor devices
KR102309993B1 (ko) 얇은 절연체 상의 반도체(soi) 기판을 형성하기 위한 방법
EP3316289B1 (fr) Procédé pour améliorer la qualité d'une couche dielectrique à permittivité k élevée
WO2011088687A1 (fr) Procédé de fabrication d'un transistor à effet de champ à tunnel
US10658489B2 (en) Semiconductor structure and fabrication method thereof
KR101611761B1 (ko) 절연층의 형성 방법
CN103779222A (zh) Mosfet的制造方法
WO2013006989A1 (fr) Procédé de fabrication d'un transistor à effet de champ à aileron et à grilles multiples en silicium massif, à grille métallique entièrement siliciurée
WO2014012425A1 (fr) Procédé de fabrication d'un igbt à diaphragme de champ
JP5553256B2 (ja) ３次元構造のｍｏｓｆｅｔ及びその製造方法
TWI539559B (zh) 記憶元件及其製造方法
US9337104B1 (en) Method for chemical mechanical polishing of high-K metal gate structures
WO2014012426A1 (fr) Procédé de fabrication d'un igbt à diaphragme de champ
US11710656B2 (en) Method of forming semiconductor-on-insulator (SOI) substrate
US10651092B2 (en) Semiconductor device and fabrication method thereof
US20220336265A1 (en) Method of forming semiconductor-on-insulator (soi) substrate

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13819509

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13819509

Country of ref document: EP

Kind code of ref document: A1