WO2014012425A1

WO2014012425A1 - Method for manufacturing field stop igbt

Info

Publication number: WO2014012425A1
Application number: PCT/CN2013/078528
Authority: WO
Inventors: 张硕; 芮强; 王根毅; 邓小社
Original assignee: 无锡华润上华半导体有限公司
Priority date: 2012-07-19
Filing date: 2013-06-29
Publication date: 2014-01-23
Also published as: CN103578980A

Abstract

Provided in the present invention is a method for manufacturing a field stop insulated-gate bipolar transistor (FS-IGBT), related to the technical field of IGBT. The manufacturing method comprises the following steps: providing a chip for use in manufacturing the FS-IGBT and in completing on the rear side thereof a FS layer doping; forming a protective layer on the rear side of the chip; completing a front-side technique process for the front side of the chip; removing the protective layer; and, forming a rear electrode on the FS layer. The manufacturing method is capable of preventing the FS layer from local damages during the front-side technique process, thus facilitating increased performance and yield of the FS-IGBT.

Description

Field termination IGBT manufacturing method

Technical field

The present invention relates to the field of Insulated Gate Bipolar Transistors (IGBT), and relates to field stop (FS) IGBTs, and more particularly to forming a protective layer on the back surface of a wafer to implement a field stop layer of an IGBT. Protected IGBT manufacturing method. Background technique

The IGBT is a common power type device that includes an FS-IGBT. in

In the conventional manufacturing method of the FS-IGBT, the FS layer is usually formed on the back side of the wafer, and then the conventional IGBT front process flow is performed, and finally the back electrode is formed on the FS layer on the back side ( For example, it is used as a collector. In the front process, the process is complicated and the steps are numerous. The FS layer on the back side of the wafer is easily damaged during the flow process of the front side process, for example, the surface is scratched, thereby causing local damage to the FS layer. This damage will not only reduce the fabrication yield of the FS-IGBT, but also negatively affect the performance of the FS-IGBT.

Therefore, achieving good protection of the back FS layer during the preparation of the FS-IGBT is a technical problem that is urgently needed in the art. Summary of the invention

The object of the present invention is to achieve good protection of the back FS layer during the preparation of the FS-IGBT.

To achieve the above or other objects, the present invention provides a method of fabricating a field termination insulated gate bipolar transistor comprising the steps of:

Providing a wafer for preparing a field termination insulated gate bipolar transistor and performing field termination layer doping on the back side thereof;

Forming a protective layer on the back side of the wafer;

Performing a front side process on the front side of the wafer;

Removing the protective layer;

A back electrode is formed on the field stop layer.

Preferably, the protective layer is a multi-silicon protective layer.

According to a manufacturing method of an embodiment of the present invention, a protective layer is simultaneously formed in the On the front side of the wafer, after a protective layer is formed on the back side of the wafer, the protective layer on the front side of the wafer is removed.

According to a manufacturing method of an embodiment of the present invention, the field stop layer doping is performed by an ion implantation doping method.

Further, after forming a protective layer on the back surface of the wafer, the field stop layer doping is subjected to a push-trap process to form a field stop layer.

Preferably, the field stop layer has a doping concentration ranging from 1E12 ions/cm ³ to 1E19 ions/cm ³

Preferably, a lattice damage to the semiconductor substrate is prevented on the back surface of the wafer for preventing ion implantation.

Preferably, the polysilicon protective layer is formed by a low pressure chemical vapor deposition (LPCVD) method.

Preferably, the polysilicon protective layer has a thickness ranging from 100 nm to 2000 nm. Preferably, the removal of the protective layer is performed by a dry etching method.

Further, completing the front side process stream at least completes the front side isolation dielectric layer preparation.

The technical effect of the invention is that the protective layer used in the preparation process realizes the protection of the field stop layer in the front side process flow, and prevents the FS layer from being partially damaged in the front side process flow, thereby facilitating the improvement of the performance of the FS-IGBT and Yield. DRAWINGS

The above and other objects and advantages of the present invention will be more fully understood from the aspects of the appended claims.

1 is a flow chart showing a method of fabricating an FS-IGBT according to an embodiment of the present invention. 2 to 7 are schematic structural changes corresponding to the flow of the method corresponding to the embodiment shown in Fig. 1.

detailed description

The following is a description of some of the various possible embodiments of the present invention, which are intended to provide a basic understanding of the invention and are not intended to identify key or critical elements of the invention. It is to be understood that, in accordance with the technical scope of the present invention, those skilled in the art can propose other implementations that are interchangeable without departing from the spirit of the invention. Therefore, the following detailed description and the accompanying drawings are merely illustrative of the embodiments of the invention, and are not intended to

In the drawings, the thickness of layers and regions are exaggerated for clarity, and the shape features such as rounding due to etching are not illustrated in the drawings.

Herein, in the wafer for preparing the FS-IGBT, the back side is defined as one side for forming the FS layer, and the front side is defined as at least one side for forming the gate end of the FS-IGBT.

In the description, components of various embodiments described using directional terms (eg, "upper", "lower", "bottom," and "bottom", etc.) and similar terms are used to mean the directions shown in the drawings or can be The directional terms are used for relative description and clarification, and are not intended to limit the orientation of any embodiment to a particular orientation or orientation.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a flow chart showing a method of fabricating an FS-IGBT according to an embodiment of the present invention. 2 to 7 are schematic views showing the structural changes of the method flow corresponding to the embodiment shown in Fig. 1. In the embodiment as shown, the direction perpendicular to the wafer surface and directed from the back side of the wafer toward the front side of the wafer is defined as the z direction, parallel to the wafer surface and defined as the X direction below the channel end. The lithography method of the embodiment of the present invention will be described below with reference to Figs. 1 through 7.

First, in step S10, a wafer for preparing an FS-IGBT and performing doping of the FS layer on the back side thereof is provided. As shown in FIG. 2, the wafer 100 is an N-doped semiconductor substrate having a doping concentration of a doping concentration of the drift layer of the IGBT to be formed. Therefore, the doping concentration range of the wafer 100 is selected to be 8E12 ions/cm. ³ to 1E13 ion/cm ³ , for example, 9E12 ion/cm ³ . Ion implantation doping is required on the back surface of the wafer 100 to form an FS layer. In this embodiment, a thin oxide layer 120 is formed on the back surface of the wafer 100 in order to prevent lattice damage of the semiconductor substrate caused by backside ion implantation. In particular, it may be inevitable to simultaneously form a thin oxide layer 120 (as shown) on the front side of the wafer 100. In other embodiments, a specific process may be employed to form a thin oxide layer 120 on the back side of the wafer. A thin oxide layer 120 is not formed on the front side of the wafer. The thickness of the thin oxide layer 120 ranges from 10 nm to 100 nm (for example, 100 nm, and the thickness thereof is thin, so that it is difficult to achieve back surface protection. By ion implantation on the back surface of the wafer 100, a relatively highly doped FS layer 110a is formed, after which In the step, the impurities in the FS layer 110a are activated by the push-trap process.

Further, in step S20, a polysilicon protective layer is deposited on the back surface of the wafer and the FS is formed. Layer doping is performed to push the well. As shown in FIG. 3, a polysilicon protective layer 130 is formed on the back side of the wafer, which can be formed by various thin film deposition processes, for example, by LPCVD. Specifically, the thickness thereof ranges from 100 nm to 2000 nm, for example, 500 nm. In this embodiment, the FS layer 110a is further subjected to a push-trap process to finally form the FS layer 110, and the polysilicon protective layer 130 is formed on the thin oxide layer 120 to protect the FS layer 110. The doping concentration of the FS layer 110 may range from 1E12 ions/cm ³ to 1E19 ions/cm ³ , for example, 1E18 ions/cm ³ .

It should be understood that, in this embodiment, when the polysilicon protective layer 130 is deposited on the back side of the wafer, the polysilicon protective layer 130 is inevitably formed on the front side of the wafer, and the front polysilicon protective layer 130 does not achieve protection. In other embodiments, a specific deposition process may be employed to deposit a polysilicon protective layer 130 on the backside of the wafer while forming a polysilicon protective layer 130 on the back side of the wafer.

Further, in step S30, the polysilicon layer and the thin oxide layer formed on the front surface of the wafer are removed. As shown in FIG. 4, the polysilicon layer 130 and the thin oxide layer 120 on the front side of the wafer are not protected during the subsequent process, and therefore, they are removed in this step to expose the semiconductor substrate for the front side process. . In this embodiment, the polysilicon layer 130 and the thin oxide layer 120 may be removed by dry etching.

Further, in step S40, the front side process flow is completed on the front side of the wafer. As shown in FIG. 5, at least a P-body region 140, an emitter 150, a gate dielectric layer 160, a polysilicon gate electrode 170, and an isolation dielectric layer 180 are formed on the front surface of the wafer (for implementing the emitter electrode (ie, the front isolation medium) The layer, not shown in the figure) is electrically isolated from the polysilicon gate electrode, thereby completing the front side process. In this embodiment, the front side process at least completes the isolation dielectric layer 180 so that the damage to the front device surface is small in the subsequent backside process.

It is to be understood that the specific device structure formed by the front side of the wafer is not limited by the embodiment of the present invention, and the specific process flow method is not limited. However, the choice of the specific material of the protective layer on the back side of the wafer needs to be considered compatible with the front side process flow, for example, temperature parameters, etch selectivity, and the like. In the embodiment of the present invention, the protective layer is preferably made of a polysilicon protective layer 130. The polysilicon material is easily compatible with the front side process flow. For example, when the gate dielectric layer 160 is patterned, there is good etching selectivity between the two. Based on the above revelation, those skilled in the art may also select other materials for use as a protective layer on the back side of the wafer, for example, it may also be selected as a SiN material.

Further, in step S50, the polysilicon protective layer on the back side of the wafer and the thin oxide layer are removed. As shown in FIG. 6, after the protection of the polysilicon protective layer 130 is completed, it is removed. In this embodiment, the thin oxide layer 120 can be simultaneously removed. The removal of the polysilicon protective layer 130 can be removed by dry etching to minimize damage to the FS layer.

Further, in step S60, a collector layer is doped on the FS layer, and a back electrode is formed thereon. As shown in FIG. 7, the FS layer 110 is doped with ion implantation to form a collector layer 190, and a back electrode metal layer 195 (for example, an aluminum metal or alloy) is formed on the collector layer 190. Collector layer 190 is a relatively high concentration of P-type dopant.

So far, the FS-IGBT has been basically formed. In the above method, the polysilicon protective layer 130 used therein protects the FS layer in the front process flow, and prevents the FS layer from being locally damaged, thereby contributing to improving the performance and yield of the FS-IGBT.

The above examples mainly illustrate the manufacturing method of the FS-IGBT of the present invention. Although only a few of the embodiments of the present invention have been described, it will be understood by those skilled in the art that the present invention may be embodied in many other forms without departing from the spirit and scope of the invention. Accordingly, the present invention is to be construed as illustrative and not restrictive, and the invention may cover various modifications without departing from the spirit and scope of the invention as defined by the appended claims With replacement.

Claims

Rights request

A method of fabricating a field termination IGBT, comprising the steps of: providing a wafer for preparing a field termination insulated gate bipolar transistor and performing field termination layer doping on a back side thereof;

Forming a protective layer on the back side of the wafer;

Performing a front side process on the front side of the wafer;

Removing the protective layer;

A back electrode is formed on the field stop layer.

The method according to claim 1, wherein the protective layer is a polysilicon protective layer.

3. The manufacturing method according to claim 1, wherein a protective layer is simultaneously formed on a front surface of the wafer, and after a protective layer is formed on a back surface of the wafer, a protective layer on a front surface of the wafer is removed. .

The method according to claim 1, wherein the field stop layer is doped by ion implantation doping.

The method according to claim 4, wherein after the protective layer is formed on the back surface of the wafer, the field stop layer doping is subjected to a push-trap process to form a field stop layer.

The method according to claim 1 or 5, wherein the field stop layer has a doping concentration ranging from 1E12 ions/cm ³ to 1E19 ions/cm ³ .

The method according to claim 4, wherein a lattice damage of the semiconductor substrate is prevented from being formed on the back surface of the wafer to prevent ion implantation.

The method according to claim 2, wherein the polysilicon protective layer is formed by a low pressure chemical vapor deposition method.

The method according to claim 2, wherein the polysilicon protective layer has a thickness ranging from 100 nm to 2000 nm.

The manufacturing method according to claim 1 or 3, wherein the removal of the protective layer is performed by a dry etching method.

11. The method of manufacturing of claim 1 wherein completing the front side process comprises at least completing a front side isolation dielectric layer preparation.