WO2013178011A1 - 接触孔硅凹槽蚀刻方法 - Google Patents

接触孔硅凹槽蚀刻方法 Download PDF

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Publication number
WO2013178011A1
WO2013178011A1 PCT/CN2013/075368 CN2013075368W WO2013178011A1 WO 2013178011 A1 WO2013178011 A1 WO 2013178011A1 CN 2013075368 W CN2013075368 W CN 2013075368W WO 2013178011 A1 WO2013178011 A1 WO 2013178011A1
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contact hole
etching
photoresist
mask
hole silicon
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PCT/CN2013/075368
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English (en)
French (fr)
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丁佳
李明
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无锡华润上华科技有限公司
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Publication of WO2013178011A1 publication Critical patent/WO2013178011A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

Definitions

  • the present invention relates to semiconductor processes, and more particularly to a contact hole silicon trench etching method.
  • the contact hole is a through hole in the component that connects the first metal layer and the active region, and penetrates the interlayer dielectric (ILD).
  • Contact silicon recess etch means that after the contact hole is etched through the interlayer dielectric, a portion of the silicon is etched down to form a contact hole silicon recess.
  • a contact hole silicon recess etching method includes the following steps: providing a wafer with a photoresist as a mask and etching an interlayer dielectric to form a contact hole; removing the photoresist; using an oxide layer on the surface of the interlayer dielectric The mask is etched by a contact hole silicon recess.
  • the step of providing a wafer with a contact hole by etching an interlayer dielectric using a photoresist as a mask is: depositing the interlayer dielectric; forming the layer on the interlayer dielectric a photoresist; the interlayer dielectric is etched using the photoresist as a mask to form the contact hole.
  • the etching the interlayer dielectric is by dry etching.
  • the polymer on the wafer due to interlayer dielectric etching is removed together.
  • the step of etching the contact hole silicon recess by using the oxide layer on the surface of the interlayer dielectric as a mask further comprises the step of performing etching cleaning.
  • the step of removing the photoresist comprises first performing dry degumming followed by wet degumming.
  • the contact hole silicon recess is etched into a dry etch.
  • the plasma source in the dry etch comprises sulfur hexafluoride.
  • the above-mentioned contact hole silicon recess etching method can perform contact hole silicon groove etching by using the oxide layer of the surface of the ILD as a hard mask after removing the photoresist, and can obtain more than the conventional technique using the photoresist as a mask. Good contact hole silicon groove topography.
  • DRAWINGS 1 is a flow chart of a method for etching a contact hole silicon recess in an embodiment
  • FIG. 2 is a photograph of a contact hole silicon groove profile obtained by etching a contact hole silicon groove by using a photoresist as a mask in a conventional process
  • Figure 3 is a photograph of a contact hole silicon groove cross section of the present invention under a microscope
  • FIG. 4 is a schematic view showing a polymer produced by etching an interlayer dielectric in a conventional contact hole etching process
  • FIG. 5 is a bridge hole etching process in which a contact hole silicon groove etching is blocked by a polymer to form bridging.
  • FIG. 6 is a flow chart of a method of etching a contact hole silicon recess in another embodiment.
  • FIG. 1 is a flow chart of a method for etching a contact hole silicon recess in an embodiment, including the following steps:
  • the photoresist is coated on the interlayer dielectric (ILD) by a conventional process, the photoresist is used as a mask, and the contact hole is formed by dry etching (contacts in which the interlayer dielectric may include a silicon oxynitride SiON layer, borophosphosilicon). Glass (BPSG) layer and tetraethyl orthosilicate (TEOS) layer.
  • BPSG silicon oxynitride SiON layer
  • TEOS tetraethyl orthosilicate
  • the photoresist is removed using a conventional degumming process.
  • the oxide layer on the surface of the interlayer dielectric (ILD) is used as a hard mask.
  • the photoresist is used as a mask to obtain a better groove morphology and reduce the aspect ratio.
  • 2 is a photograph of a contact hole silicon groove profile obtained by etching a contact hole silicon groove using a photoresist as a mask in a conventional process
  • FIG. 3 is a photo of a contact hole silicon groove profile of the present invention under a microscope. .
  • the polymer 11 into the contact hole blocks the etching, resulting in an unclean etching that affects the yield of the product. Since the properties of the polymer are similar to those of the photoresist, in one embodiment, the polymer can be removed together when the photoresist is removed in step S320. That is, in step S322: the photoresist is removed, and the polymer on the wafer which is etched by the interlayer dielectric is removed together. As shown in Figure 6.
  • the step of removing the photoresist is accomplished by first performing dry stripping and then wet stripping.
  • the two-step de-glue process removes the photoresist and polymer more cleanly.
  • the removal of the polymer is mainly by wet degumming. Process, therefore, according to the generated polymer composition, the appropriate degumming solution is selected to achieve the purpose of simultaneously removing the polymer and the photoresist.
  • the above-mentioned contact hole silicon recess etching method increases a process of removing impurities (polymer) generated by reacting with the photoresist during etching of the interlayer dielectric, after etching the interlayer dielectric to form a contact hole, and etching the contact hole silicon recess.
  • the photoresist is removed at the same time, thereby eliminating the influence of impurities on the etching in the subsequent etching of the contact hole silicon recess process, improving the yield of the product, and boosting the confidence of the FAB factory customers.
  • the oxide layer on the surface of the ILD is used as a hard mask, and a better contact hole silicon groove morphology can be obtained.
  • the above-mentioned contact hole silicon recess etching method does not change the structure of the device, and the process is simple and easy to implement, and the production cost is not increased due to the increase in the number of processes.
  • step S310 specifically includes the following three steps:
  • the inter-layer dielectric is etched using dry etching.
  • step S330 further includes a step S340 of performing an etch cleaning.
  • the contact hole silicon groove etching in step S330 is performed by a dry etching process. Since the use of carbon tetrafluoride as a plasma source produces a large amount of polymer, this embodiment does not employ carbon tetrafluoride CF4 as a plasma source in S330, and can be replaced with sulfur hexafluoride SF6. As a result, the polymer produced during the etching is greatly reduced, and the average cleaning interval (MTBC) of the etching machine chamber is prolonged (no more cleaning due to the large amount of polymer attached to the inner wall of the chamber) , saving the cost of cleaning. In the actual production, after the method of the present invention is employed, the average cleaning interval of the etching machine chamber is extended from about 10 hours to 50 hours.
  • MTBC average cleaning interval

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

提供了一种接触孔硅凹槽蚀刻方法，包括下列步骤：（S310）提供以光刻胶为掩膜，蚀刻层间介质形成接触孔的圆片；（S320）去除所述光刻胶；（S330）以层间介质表面的氧化层作为掩膜，进行接触孔硅凹槽蚀刻。通过将光刻胶去除后采用ILD表面的氧化层作为硬掩膜进行接触孔硅凹槽蚀刻，相对于使用光刻胶作为掩膜的传统技术，可以获得更好的接触孔硅凹槽形貌。

Description

接触孔硅凹槽蚀刻方法
技术领域
本发明涉及半导体工艺， 特别是涉及一种接触孔硅凹槽蚀刻方法。
背景技术
接触孔（contact)是元器件中连通第一层金属层与有源区的通孔，其贯穿层间介质（ILD)。 接触孔硅凹槽蚀刻 （contact Si recess etch), 是指接触孔蚀刻穿层间介质后， 再向下将一部分 硅蚀刻掉形成接触孔硅凹槽。
传统的接触孔蚀刻工艺中， 形成的接触孔硅凹槽的形貌较差， 以致影响器件的性能， 可 能会成为一个致命缺陷导致晶圆验收测试 （WAT) 中漏极饱和电流 （Idss ) 测试不通过。 发明内容
基于此， 有必要针对传统接触孔蚀刻工艺形成的接触孔硅凹槽形貌不好的问题， 提供一 种接触孔硅凹槽蚀刻方法。
一种接触孔硅凹槽蚀刻方法， 包括下列步骤： 提供以光刻胶为掩膜， 蚀刻层间介质形成 接触孔的圆片； 去除所述光刻胶； 以层间介质表面的氧化层作为掩膜， 进行接触孔硅凹槽蚀 刻。
在其中一个实施例中， 所述提供以光刻胶为掩膜， 蚀刻层间介质形成接触孔的圆片的步 骤是： 淀积所述层间介质； 在所述层间介质上形成所述光刻胶； 以所述光刻胶为掩膜对所述 层间介质进行蚀刻， 形成所述接触孔。
在其中一个实施例中， 所述对所述层间介质进行蚀刻是采用干法蚀刻。
在其中一个实施例中， 所述去除所述光刻胶的步骤中， 所述圆片上因层间介质蚀刻产生 的聚合物被一并去除。
在其中一个实施例中， 所述以层间介质表面的氧化层作为掩膜， 进行接触孔硅凹槽蚀刻 的步骤后还包括进行蚀刻清洁的步骤。
在其中一个实施例中， 所述去除所述光刻胶的步骤包括先进行干法去胶， 再进行湿法去 胶。
在其中一个实施例中， 所述接触孔硅凹槽蚀刻为干法蚀刻。
在其中一个实施例中， 所述干法蚀刻中的等离子源包括六氟化硫。
上述接触孔硅凹槽蚀刻方法， 通过将光刻胶去除后采用 ILD表面的氧化层作为硬掩膜进 行接触孔硅凹槽蚀刻， 相对于使用光刻胶作为掩膜的传统技术， 可以获得更好的接触孔硅凹 槽形貌。
附图说明 图 1是一实施例中接触孔硅凹槽蚀刻方法的流程图；
图 2是传统工艺中采用光刻胶作为掩膜蚀刻接触孔硅凹槽得到的接触孔硅凹槽剖面在显 微镜下的照片；
图 3是本发明的接触孔硅凹槽剖面在显微镜下的照片；
图 4是传统的接触孔蚀刻工艺中对层间介质进行蚀刻后产生聚合物的示意图； 图 5是传统的接触孔蚀刻工艺中接触孔硅凹槽蚀刻被聚合物所阻挡形成桥接 （bridging) 的示意图；
图 6是另一实施例中接触孔硅凹槽蚀刻方法的流程图。
具体实施方式
为使本发明的目的、 特征和优点能够更为明显易懂， 下面结合附图对本发明的具体实施 方式做详细的说明。
图 1是一实施例中接触孔硅凹槽蚀刻方法的流程图， 包括下列步骤：
S310, 提供以光刻胶为掩膜， 蚀刻层间介质形成了接触孔的圆片。
可以使用传统工艺在层间介质 （ILD) 上涂覆光刻胶后， 以光刻胶为掩膜， 干法蚀刻形 成接触孔 （contacts 其中层间介质可以包括氮氧化硅 SiON层、 硼磷硅玻璃 （BPSG) 层以 及正硅酸乙酯 （TEOS) 层。
S320, 去除光刻胶。
使用习知的去胶工艺去除光刻胶。
S330, 以层间介质表面的氧化层作为掩膜， 进行接触孔硅凹槽蚀刻。
以层间介质 （ILD) 表面的氧化层作为硬掩膜 （hard mask) 相对于传统工艺中以光刻胶 作为掩膜， 可以获得更好的凹槽形貌， 减小宽高比 （aspect ratio )。 图 2是传统工艺中采用光 刻胶作为掩膜蚀刻接触孔硅凹槽得到的接触孔硅凹槽剖面在显微镜下的照片， 图 3是本发明 的接触孔硅凹槽剖面在显微镜下的照片。
另外， 在传统的接触孔蚀刻工艺中， 一般采用四氟化碳和 /或溴化氢进行干法蚀刻， 四氟 化碳的等离子体会与硅反应产生大量聚合物 （polymer), 例如聚四氟乙烯。 参见图 4和图 5， 聚合物 11落入接触孔中会对蚀刻进行阻挡， 导致蚀刻不干净， 影响产品的良率。 由于该聚合 物的性质与光刻胶相近， 因此在其中一个实施例中， 可以于步骤 S320去除光刻胶时将聚合物 一并去除。 即步骤 S322: 去除光刻胶， 圆片上因层间介质蚀刻产生的聚合物被一并去除。 如 图 6所示。
在其中一个实施例中， 去除光刻胶的步骤是通过先进行干法去胶， 再进行湿法去胶来完 成。 两步去胶工艺可以将光刻胶及聚合物去除得更干净。 去除聚合物主要是通过湿法去胶的 工艺， 因此要根据生成的聚合物成分相应选择合适的去胶液， 达到同时去除聚合物和光刻胶 的目的。
上述接触孔硅凹槽蚀刻方法， 通过在蚀刻层间介质形成接触孔后、 蚀刻接触孔硅凹槽之 前， 增加去除层间介质蚀刻时与光刻胶反应产生的杂质 （聚合物） 的工艺， 同时一并去除光 刻胶， 因此消除了后续蚀刻接触孔硅凹槽工序中杂质对蚀刻的影响， 提高了产品的良率， 可 以提振 FAB厂客户的信心。另外光刻胶去除后采用 ILD表面的氧化层作为硬掩膜， 可以获得 更好的接触孔硅凹槽形貌。 上述接触孔硅凹槽蚀刻方法没有对器件的结构做出改变， 工艺简 单易于实现， 不会因工序的增加造成生产成本的增加。
参见图 6， 为另一实施例中接触孔硅凹槽蚀刻方法的流程图。 在该实施例中， 步骤 S310 具体包括以下三个步骤：
S311 , 淀积层间介质。
S313, 在层间介质上形成光刻胶。
S315, 以光刻胶为掩膜对层间介质进行蚀刻， 形成接触孔。
在本实施例中， 蚀刻层间介质是采用干法蚀刻。
在本实施例中， 步骤 S330之后还包括进行蚀刻清洁的步骤 S340。
在本实施例中， 步骤 S330的接触孔硅凹槽蚀刻采用干法蚀刻工艺。 由于使用四氟化碳作 为等离子源会产生大量聚合物， 因此本实施例在 S330中不采用四氟化碳 CF4作为等离子源， 可以采用六氟化硫 SF6替代。 如此一来， 蚀刻中产生的聚合物就会大幅减少， 蚀刻机台腔室 的平均清洁间隔时间 （MTBC) 得到延长 （不会再因为大量的聚合物附着于腔室内壁上导致 需要经常清洁）， 节省了清洁的成本。 实际生产中在采用了本发明的方法后， 蚀刻机台腔室的 平均清洁间隔时间由 10小时左右延长为 50小时。
以上所述实施例仅表达了本发明的几种实施方式， 其描述较为具体和详细， 但并不能因 此而理解为对本发明专利范围的限制。 应当指出的是， 对于本领域的普通技术人员来说， 在 不脱离本发明构思的前提下， 还可以做出若干变形和改进， 这些都属于本发明的保护范围。 因此， 本发明专利的保护范围应以所附权利要求为准。

Claims

权利要求书
1、 一种接触孔硅凹槽蚀刻方法， 包括下列步骤：
提供以光刻胶为掩膜， 蚀刻层间介质形成接触孔的圆片；
去除所述光刻胶；
以层间介质表面的氧化层作为掩膜， 进行接触孔硅凹槽蚀刻。
2、根据权利要求 1所述的接触孔硅凹槽蚀刻方法， 其特征在于， 所述提供以光刻胶为掩 膜， 蚀刻层间介质形成接触孔的圆片的步骤是：
淀积所述层间介质；
在所述层间介质上形成所述光刻胶；
以所述光刻胶为掩膜对所述层间介质进行蚀刻， 形成所述接触孔。
3、根据权利要求 2所述的接触孔硅凹槽蚀刻方法， 其特征在于， 所述对所述层间介质进 行蚀刻是采用干法蚀刻。
4、根据权利要求 1所述的接触孔硅凹槽蚀刻方法， 其特征在于， 所述去除所述光刻胶的 步骤中， 所述圆片上因层间介质蚀刻产生的聚合物被一并去除。
5、根据权利要求 1所述的接触孔硅凹槽蚀刻方法， 其特征在于， 所述以层间介质表面的 氧化层作为掩膜， 进行接触孔硅凹槽蚀刻的步骤后还包括进行蚀刻清洁的步骤。
6、 根据权利要求 1-5中任意一项所述的接触孔硅凹槽蚀刻方法， 其特征在于， 所述去除 所述光刻胶的步骤包括先进行干法去胶， 再进行湿法去胶。
7、 根据权利要求 1-5中任意一项所述的接触孔硅凹槽蚀刻方法， 其特征在于， 所述接触 孔硅凹槽蚀刻为干法蚀刻。
8、根据权利要求 7所述的接触孔硅凹槽蚀刻方法， 其特征在于， 所述干法蚀刻中的等离 子源包括六氟化硫。
9、根据权利要求 8所述的接触孔硅凹槽蚀刻方法， 其特征在于， 所述干法蚀刻中的等离 子源不包括四氟化碳。
PCT/CN2013/075368 2012-05-31 2013-05-09 接触孔硅凹槽蚀刻方法 WO2013178011A1 (zh)

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