WO2013164961A1 - イメージセンサ、及び、イメージセンサの制御方法 - Google Patents
イメージセンサ、及び、イメージセンサの制御方法 Download PDFInfo
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- WO2013164961A1 WO2013164961A1 PCT/JP2013/061891 JP2013061891W WO2013164961A1 WO 2013164961 A1 WO2013164961 A1 WO 2013164961A1 JP 2013061891 W JP2013061891 W JP 2013061891W WO 2013164961 A1 WO2013164961 A1 WO 2013164961A1
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- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
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- H04N25/10—Circuitry of solid-state image sensors [SSIS]; Control thereof for transforming different wavelengths into image signals
- H04N25/11—Arrangement of colour filter arrays [CFA]; Filter mosaics
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Definitions
- the present technology relates to an image sensor and a method for controlling the image sensor, and in particular, for each color regardless of whether the image sensor shares a plurality of color pixels and without adding a circuit to the pixel.
- the present invention relates to an image sensor that can measure the illuminance of the image sensor and a method for controlling the image sensor.
- CMOS ComplementaryCompMetal Oxide Semiconductor
- the present technology has been made in view of such a situation, and in an image sensor, regardless of whether or not pixels of a plurality of colors are shared, and without adding a circuit to the pixels, for each color. It makes it possible to measure illuminance.
- An image sensor includes a photoelectric conversion unit that performs photoelectric conversion of light of a predetermined color that is incident via a color filter, and a charge that is obtained by photoelectric conversion of the photoelectric conversion unit, for each color.
- the image sensor reads the charge from the photoelectric conversion unit through the transfer transistor and the reset transistor, and supplies a voltage corresponding to the charge to the AD conversion unit connected to the reset transistor.
- a control method includes a photoelectric conversion unit that performs photoelectric conversion of light of a predetermined color that is incident via a color filter, and a charge that is obtained by photoelectric conversion of the photoelectric conversion unit, for each color.
- the transfer transistor of the image sensor including a plurality of pixel units having a pixel including a controllable transfer transistor and an AD conversion unit that performs AD (Analog-to-Digital) conversion and resets the charge. Reading the charge from the photoelectric conversion unit through the transfer transistor and the reset transistor under control, and supplying a voltage corresponding to the charge to the AD conversion unit connected to the reset transistor It is a control method of an image sensor.
- the pixel unit includes a pixel and a reset transistor that resets the charge, and the pixel performs photoelectric conversion of light of a predetermined color incident through the color filter.
- the transfer transistor which can be controlled for every color is included.
- An AD conversion unit that performs AD conversion is connected to the reset transistor. Then, under the control of the transfer transistor, the charge is read from the photoelectric conversion unit through the transfer transistor and the reset transistor, and a voltage corresponding to the charge is connected to the reset transistor. Supplied to the converter.
- the image sensor may be an independent device or an internal block constituting one device.
- the image sensor can measure the illuminance for each color.
- FIG. 1 It is a block diagram showing an example of composition of an embodiment of an image sensor to which this art is applied. It is a circuit diagram which shows the structural example of pixel unit 11 m, n . Pixel unit 11 m of the imaging mode is a diagram showing a state of n. Pixel unit 11 m luminometer mode is a diagram showing a state of n. 3 is a block diagram illustrating a configuration example of a conversion control unit 31.
- FIG. It It is a timing chart explaining operation
- FIG. 10 is a diagram showing a change in voltage of the power supply line 51 when a voltage VDD # 2 obtained by stepping down the voltage VDD # 1 is applied to the power supply line 51; It is a figure explaining the clamp part.
- 3 is a circuit diagram illustrating a configuration example of a clamp unit 32.
- FIG. 5 is a diagram for explaining a pixel control line 41 m connected to the pixel driving unit 21.
- FIG. 2 is a block diagram illustrating a first configuration example of a pixel driving unit 21.
- FIG. 4 is a block diagram illustrating a second configuration example of the pixel driving unit 21.
- FIG. FIG. 6 is a diagram for explaining the operation of the pixel drive unit 21. It is a timing chart which shows the voltage of the control line TRG controlled by the TRG driver 100 q when obtaining the illuminance data for each color in the illuminometer mode.
- FIG. 6 is a circuit diagram illustrating another configuration example of the pixel unit 11 m, n in FIG. 1.
- FIG. 18 is a block diagram illustrating a configuration example of an embodiment of a computer to which the present technology is applied.
- FIG. 1 is a block diagram illustrating a configuration example of an embodiment of an image sensor to which the present technology is applied.
- the image sensor of FIG. 1 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) sensor used in a digital still camera, a digital video camera, or the like, but the image sensor to which the present technology is applied is limited to the CMOS sensor. It is not a thing.
- CMOS Complementary Metal Oxide Semiconductor
- the image sensor is, for example, a one-chip semiconductor chip, and includes a pixel array 10, a pixel driving unit 21, selectors 22 and 23, ADCs 24 1 to 24 N , a conversion control unit 31, a clamping unit 32, and an ADC. (Analog to Digital Converter) 33.
- the pixel array 10 includes M ⁇ N pixel units 11 1 , 1 1 , 11 1 , 2 ,..., 11 1, N 1 , 11 2, 1 1 , 11 2. a 2, ⁇ , 11 2, N , ⁇ , 11 M, 1, 11 M, 2, ⁇ , 11 M, and N.
- M ⁇ N pixel units 11 1, 1 to 11 M, N are arranged in a matrix (lattice) of M rows and N columns, and are connected to power supply lines 51 and 52 for supplying power. .
- pixel control line 41 m is connected extending.
- a vertical signal line 42 n extending in the vertical direction is connected.
- the pixel unit 11 m, n has a pixel described later, and performs photoelectric conversion in the pixel. Furthermore, the pixel unit 11 m, n outputs the electric charge (corresponding voltage) obtained by the photoelectric conversion of the pixel according to the control from the pixel driving unit 21 via the pixel control line 41 m .
- the pixels included in the pixel unit 11 m, n perform photoelectric conversion of light of a predetermined color that enters through a color filter such as a Bayer array.
- the color filter is not limited to the Bayer color filter, but in the following, the Bayer color filter is adopted as the color filter.
- R (Red) is arranged in the upper left and lower left
- G (Green) is arranged in the lower right
- B (Blue) is arranged in the lower right.
- the four pixels are repeatedly arranged in each of the row direction and the column direction.
- G in upper right of Bayer array unit
- G on the left side of B (lower left in Bayer array unit) is written as Gb.
- the image sensor has a pixel (open pixel) where light from the outside is incident and a pixel (non-open pixel) where the light is not incident.
- the present technology is intended only for the aperture pixel where light is incident.
- the pixel drive unit 21 controls the pixel units 11 m, 1 to 11 m, N connected to the pixel control line 41 m via the pixel control line 41 m .
- the pixel drive unit 21 operates by receiving power from a power supply (analog power supply) of voltage VDD # 1 (hereinafter also referred to as power supply VDD # 1).
- the power supply VDD # 1 is the main power supply of the image sensor.
- the selector 22 is connected to a power supply having a voltage VDD # 1 (power supply VDD # 1) and a power supply having a voltage VDD # 3 (power supply VDD # 3).
- the voltage VDD # 3 is lower than the voltage VDD # 1.
- the selector 22 is connected to a power supply line 52 connected to M ⁇ N pixel units 111,1 to 11M , N.
- the selector 22 selects one of the power supplies VDD # 1 and VDD # 3 according to the operation mode of the image sensor and connects it to the power supply line 52, whereby the power supply VDD # 1 and VDD # 3.
- a voltage (power) is supplied from the power source connected to the power source line 52 to the pixel units 11 1, 1 to 11 M, N via the power source line 52.
- the operation mode of the image sensor includes an imaging mode for capturing an image (normal imaging) and an illuminometer mode for causing the image sensor to function as an illuminometer for measuring illuminance. .
- the selector 22 selects the power supply VDD # 1 in the imaging mode, and selects the power supply VDD # 3 in the illuminometer mode.
- the operation mode of the image sensor can be instructed from the outside, for example.
- the selector 23 is connected to the power supply VDD # 3 and N ADCs 24 1 , 24 2 ,..., 24 N.
- the selector 23 is connected to the vertical signal line 41 n connected to the M pixel units 111 , n to 11M, n arranged in the column direction.
- the selector 23 selects the power supply VDD # 3 and one of the N ADCs 24 1 to 24 N according to the operation mode of the image sensor, and connects it to the vertical signal lines 41 1 to 41 N.
- the selector 23 selects N ADCs 24 1 to 24 N and connects the ADC 24 n and the vertical signal line 41 n .
- the pixel unit 11 m, n is a pixel included in the outputs on the vertical signal line 41 n, the voltage corresponding to the charge accumulated in the pixel, via the selector 23, is supplied to the ADC 24 n.
- the selector 23, in the luminometer mode, select the power VDD # 3, is connected with its power supply VDD # 3, and a vertical signal line 41 1 through 41 N.
- the ADC 24 n performs CDS (Correlated Double Sampling) and AD conversion of the voltage supplied via the vertical signal line 41 n and the selector 23 from the pixel of the pixel unit 11 m, n , and obtains the result.
- the digital data is output as the pixel value (pixel data) of the color of the pixel of the pixel unit 11m, n .
- the conversion control unit 31 is connected to the power supply VDD # 1 and the power supply line 51.
- the conversion control unit 31 connects the power supply VDD # 1 and the power supply line 51, so that the M ⁇ N pixel units 11 1, 1 to 11 M, N connected to the power supply line 51 are connected.
- the power supply VDD # 1 is supplied.
- the conversion control unit 31 sets the power supply line 51 in a floating state, and the floating power supply line 51 stores the pixels included in the pixel units 11 m and n connected to the power supply line 51. By causing the charge to flow in, voltage conversion is performed to convert the charge into a corresponding voltage.
- the voltage obtained by the voltage conversion by the conversion control unit 31 is supplied to an ADC 33 (described later) connected to the power line 51.
- the clamp unit 32 is connected to the power supply (power supply VDD # 4) of the voltage VDD # 4 and the power supply line 51, and clamps the power supply line 51 to the voltage VDD # 4 in the illuminometer mode.
- the voltage VDD # 4 is lower than the voltage VDD # 1, but the magnitude relationship with the voltage VDD # 3 is not particularly limited. In the present embodiment, the voltages VDD # 3 and VDD # 4 are the same voltage.
- the ADC 33 is connected to the power supply line 51.
- the ADC 33 operates by receiving power from the power supply VDD # 1, and in the illuminometer mode, the voltage corresponding to the charge accumulated in the pixels of the pixel units 11m, n supplied via the power supply line 51.
- CDS Correlated Double Sampling
- AD Analog to Digital Converter
- the ADC 33 outputs digital data obtained as a result of CDS and AD conversion as illuminance data representing the illuminance of ambient light.
- FIG. 2 is a circuit diagram showing a configuration example of the pixel unit 11m, n in FIG.
- the pixel unit 11 m, n includes one pixel 60 and, for example, an nMOS (negative channel MOS) FET (Field Effect Transistor), a reset transistor 63, an amplification transistor 64, and a selection transistor 65.
- nMOS negative channel MOS
- FET Field Effect Transistor
- the pixel 60 includes a PD (Photo-Diode) 61 and a transfer transistor 62.
- the connected pixel control line 41 m in the pixel driver 21 (FIG. 1)
- the control line RST for controlling the reset transistor 63 the control line TRG for controlling the transfer transistors 62
- controls the selection transistor 65 There is a control line SEL to do.
- the control line RST is connected to the gate of the reset transistor 63, and the control line TRG is connected to the gate of the transfer transistor 62.
- the control line SEL is connected to the gate of the selection transistor 65.
- a control signal for controlling the reset transistor 63 that flows on the control line RST is also referred to as a control signal RST.
- a control signal for controlling the transfer transistor 62 flowing on the control line TRG is also referred to as a control signal TRG
- a control signal for controlling the selection transistor 65 flowing on the control line SEL is also referred to as a control signal SEL.
- the anode of the PD 61 is grounded to GND (ground), and the cathode is connected to the source of the transfer transistor 62, for example.
- the transfer transistor 62 is, for example, an nMOS FET, and its drain is connected to the gate of the amplification transistor 64.
- the source of the reset transistor 63 is connected to the drain of the transfer transistor 62, and the drain of the reset transistor 63 is connected to the power supply line 51.
- the drain of the amplification transistor 64 is connected to the power supply line 52, and the source of the amplification transistor 64 is connected to the drain of the selection transistor 65.
- the source of the selection transistor 65 is connected to the vertical signal line 42 n .
- FIG. 3 is a diagram illustrating a state of the pixel units 11m, n in the imaging mode.
- the selector 22 selects the power supply VDD # 1 and connects to the power supply line 52.
- the voltage VDD # 1 is applied to the drain of the amplification transistor 64 through the power line 52.
- the conversion control unit 31 connects the power supply VDD # 1 to the power supply line 51, whereby the voltage VDD # 1 is applied to the drain of the reset transistor 63 via the power supply line 51.
- the same voltage VDD # 1 is applied to the drains of the reset transistor 63 and the amplification transistor 64.
- the same voltage VDD # 1 is applied to the drains of the reset transistor 63 and the amplification transistor 64.
- the voltages need not be the same voltage. That is, for example, the voltage VDD # 1 can be applied to the drain of the amplification transistor 64, and the voltage higher than the voltage VDD # 1 obtained by boosting the voltage VDD # 1 can be applied to the drain of the reset transistor 63. .
- the selector 23 selects the ADC 24 n, connected to the vertical signal line 42 n.
- the PD 61 receives light of a color incident thereon and performs photoelectric conversion, thereby accumulating charges according to the amount of received light.
- the transfer transistor 62 is temporarily turned on when a pulse as a control signal TRG which temporarily changes from L (Low) level to H (High) level is applied to the gate.
- the transfer transistor 62 When the transfer transistor 62 is turned on, the charge accumulated in the PD 61 is transferred from the source to the drain of the transfer transistor 62.
- the drain of the transfer transistor 62 is connected to the gate of the amplification transistor 64, and this connection point is called FD (Floating Diffusion). Therefore, the electric charge accumulated in the PD 61 is transferred to the FD via the transfer transistor 62.
- the reset transistor 63 is temporarily turned on when a pulse that temporarily changes from L level to H level as the control signal RST is applied to the gate.
- the reset transistor 63 is turned on immediately before the transfer transistor 62 is turned on, and the charge in the FD is transferred via the reset transistor 63 and the power supply line 51 before the charge is transferred from the PD 61 to the FD. Reset by sweeping to power supply VDD # 1.
- the amplification transistor 64 operates using the voltage VDD # 1 applied to the drain via the power line 52 as a power source.
- the amplification transistor 64 outputs the potential (voltage) of the FD immediately after reset to the source as a reset level, and then uses the potential of the FD immediately after the charge is transferred from the PD 61 as a pixel based on the reset level.
- the voltage (signal level) corresponding to the value is output to the source.
- the selection transistor 65 is temporarily turned on when a pulse that temporarily changes from L level to H level as the control signal SEL is applied to the gate.
- the drain of the selection transistor 65 is connected to the source of the amplification transistor 64, and the selection transistor 65 selects the reset level and the signal level that are output (appears) to the source of the amplification transistor 64.
- the signal is output onto the vertical signal line 42 n connected to the source of the transistor 65.
- Reset level output on the vertical signal line 42 n, and the signal level is supplied to the ADC 24 n.
- the ADC 24 n performs signal level CDS and AD conversion using the reset level, and digital data obtained as a result of the signal level CDS and AD conversion is output as pixel data.
- FIG. 4 is a diagram illustrating the state of the pixel units 11 m, n in the illuminometer mode.
- the selector 22 selects the power supply VDD # 3 and connects to the power supply line 52.
- the voltage VDD # 3 is applied to the drain of the amplification transistor 64 via the power line 52.
- the conversion control unit 31 temporarily puts the power line 51 in a floating state.
- the selector 23 selects the power supply VDD # 3, connected to the vertical signal line 42 n.
- the amplification transistor 64 and the selection transistor 65 are connected, the amplification transistor 64 and the selection transistor 65 are in a state where they do not function.
- the amplification transistor 64 and the selection transistor 65 become non-functional, so the drain of the amplification transistor 64 and Even if not the voltage VDD # 3 but the voltage VDD # 1 higher than the voltage VDD # 3 is applied to the source of the selection transistor 65, the amplification transistor 64 and the selection transistor 65 may be disabled. it can.
- the voltage VDD # 3 lower than the voltage VDD # 1 is applied to the drain of the amplification transistor 64 and the source of the selection transistor 65 in the illuminometer mode.
- control signals RST and SEL are always at the H level, and as a result, the reset transistor 63 and the selection transistor 65 are always on.
- the transfer transistor 62 is temporarily turned on when a pulse that temporarily changes from L level to H level as the control signal TRG is applied to the gate.
- the reset transistor 63 is always on. Therefore, when the transfer transistor 62 is on, the charge accumulated in the PD 61 passes through the transfer transistor 62, the reset transistor 63, and the power supply line 51. Thus, sweeping is performed to the conversion control unit 31 (power supply VDD # 2 described later), and the PD 61 is reset.
- the voltage of the power supply line 51 when the PD 61 is reset is supplied to the ADC 33 connected to the power supply line 51 as a reset level.
- the transfer transistor 62 is temporarily turned on again when a pulse that temporarily changes from the L level to the H level as the control signal TRG is given to the gate.
- the conversion control unit 31 sets the power supply line 51 in a floating state immediately before the transfer transistor 62 is turned on again.
- the transfer transistor 62 When the transfer transistor 62 is turned on after the power supply line 51 is in a floating state, the charge accumulated in the PD 61 flows into the power supply line 51 via the transfer transistor 62 and the reset transistor 63, and correspondingly. Converted to voltage.
- a voltage corresponding to the charge accumulated in the PD 61 that is, a voltage (signal level) corresponding to the illuminance with reference to the reset level is supplied to the ADC 33 connected to the power supply line 51.
- signal level CDS and AD conversion from the power supply line 51 is performed using the reset level from the power supply line 51, and digital data obtained as a result of the signal level CDS and AD conversion is output as illuminance data. Is done.
- M ⁇ N pixel units 11 1,1 to 11 M, N are selected by selecting a pixel that supplies the transfer transistor 62 with a control signal TRG that temporarily changes from L level to H level.
- TRG a control signal that temporarily changes from L level to H level.
- control signal TRG that temporarily changes from the L level to the H level is applied to all the transfer transistors 62 of the M ⁇ N pixel units 11 1, 1 to 11 M, N pixels 60, so that the color does not matter. Illuminance data can be obtained.
- control signal TRG that temporarily changes from the L level to the H level is sent to the R, G, or B pixel of the M ⁇ N pixel units 11 1, 1 to 11 M, N pixels 60.
- the transfer transistor 62 By providing the transfer transistor 62, the illuminance for each color, that is, the illuminance data of R, G, or B light can be obtained.
- FIG. 5 is a block diagram illustrating a configuration example of the conversion control unit 31.
- the pixel unit 11 m, n is also shown in addition to the conversion control unit 31, but the amplification transistor 64 and the selection transistor 65 are not shown in the pixel unit 11 m, n . is there.
- the conversion control unit 31 includes a switch unit 70 and a voltage step-down unit 73.
- the switch unit 70 is turned on / off according to a read enable signal SWEN supplied from the outside (for example, from a control unit (not shown)), and connects or disconnects between the power supply line 51 and the voltage step-down unit 73. .
- the switch unit 70 includes an inverter 71 and an FET 72.
- the enable signal SWEN is input to the inverter 72.
- the inverter 72 inverts the enable signal SWEN input thereto and applies it to the gate of the FET 72.
- the FET 72 is a pMOS (positive channel MOS) FET, the drain is connected to the power supply line 51, and the source is connected to the voltage step-down unit 73.
- the substrate of the FET 72 is connected to the power supply VDD # 1.
- the voltage VDD # 1 is applied to the voltage step-down unit 72.
- the voltage step-down unit 72 steps down the voltage VDD # 1 to a voltage (step-down voltage) VDD # 2 lower than the voltage VDD # 1 or does not step down the voltage VDD # 1 according to the operation mode. Is supplied to the switch unit 70 (the FET 72).
- the voltage step-down unit 72 supplies the voltage VDD # 1 to the switch unit 70 as it is without stepping down the voltage VDD # 1 in the imaging mode. Further, the voltage step-down unit 72 steps down the voltage VDD # 1 to the voltage VDD # 2 and supplies it to the switch unit 70 in the illuminometer mode.
- the voltage step-down unit 73 when the voltage step-down unit 73 is viewed from the switch unit 70 (from the power supply line 51 side), the voltage step-down unit 73 is used as the power source of the voltage VDD # 1 or the power source of the voltage VDD # 2 (power source # 2). Function.
- the voltage VDD # 4 at which the clamp unit 32 (FIG. 1) clamps the power supply line 51 is a predetermined voltage less than the voltage VDD # 2. Is the voltage.
- the read enable signal SWEN always at H level is supplied to the inverter 71 in the imaging mode.
- the output of the inverter 71 becomes the L level
- the L level is applied to the gate of the FET 72
- the FET 72 is turned on.
- the voltage step-down unit 72 supplies the voltage VDD # 1 to the switch unit 70 as it is without stepping down the voltage VDD # 1. Therefore, the voltage VDD # 1 supplied to the switch unit 70 is applied to the power supply line 51 via the FET 72 in the on state, and thereby the voltage VDD # 1 as the power supply is reset via the power supply line 51. Applied to the drain of the transistor 63.
- the voltage step-down unit 72 steps down the voltage VDD # 1 to the voltage VDD # 2 and supplies it to the switch unit 70.
- the read enable signal SWEN is initially set to H level and then set to L level.
- the output of the inverter 71 is at the L level, and the L level is applied to the gate of the FET 72. As a result, the FET 72 is turned on.
- the FET 72 When the FET 72 is in an off state, the voltage VDD # 2 supplied to the switch unit 70 is not applied to the power supply line 51. When the FET 72 is in the off state, the power supply line 51 connected to the FET 72 is in a floating state.
- FIG. 6 is a timing chart for explaining the operation of the image sensor in the illuminometer mode.
- FIG. 6 shows the read enable signal SWEN, the control signals RST, SEL, and TRG, and the voltage of the power supply line 51 in the illuminometer mode.
- processing for obtaining illuminance data includes a shutter phase, an accumulation phase, and a readout phase in time order.
- control signals RST and SEL are set to the H level in any of the shutter phase, the accumulation phase, and the readout phase.
- the reset transistor 63 and the selection transistor 65 are always in the on state. become.
- the read enable signal SWEN is changed to H level, and the control signal TRG is temporarily changed from L level to H level.
- the FET 72 (FIG. 5) is turned on, and the voltage VDD # 2 stepped down by the voltage step-down unit 73 is applied to the power line 51. That is, the power supply VDD # 2 is connected to the power supply line 51.
- the reset transistor 63 is always on, when the transfer transistor 62 is on in the shutter phase, the charge accumulated in the PD 61 is transferred to the transfer transistor 62, the reset transistor 63, and the power supply. It is swept out to the power supply VDD # 2 connected to the power supply line 51 of the conversion control unit 31 via the line 51, and the PD 61 is reset.
- the voltage of the power supply line 51 when the PD 61 is reset becomes the voltage VDD # 2 that is the voltage of the power supply VDD # 2 connected to the power supply line 51, and the voltage VDD # 2 is set as the reset level.
- the power is supplied to the ADC 33 connected to the power line 51.
- the read enable signal SWEN is kept at H level, and the control signal TRG is kept at L level (still).
- the FET 72 (FIG. 5) is turned on, and the power obtained by stepping down the voltage VDD # 1 by the voltage step-down unit 73 (FIG. 5), as in the shutter phase.
- VDD # 2 is connected to the power supply line 51.
- the voltage of the power supply line 51 becomes the voltage VDD # 2, and the voltage VDD # 2 is supplied to the ADC 33 connected to the power supply line 51 as a reset level.
- control signal TRG is at the L level
- the transfer transistor 62 is turned off, and charges are accumulated in the PD 61.
- the read enable signal SWEN is changed from H level to L level, and the control signal TRG is temporarily set to L level immediately after the read enable signal SWEN is changed from H level to L level. To H level.
- the ADC 33 performs the first reading of the voltage of the power supply line 51, as shown with a shadow in FIG. Then, the voltage of the power line 51 is acquired as a reset level.
- the FET 72 (FIG. 5) is in the on state, and the power line 51 is connected to the power source # 2.
- the voltage VDD # 2 is acquired as the reset level.
- the read enable signal SWEN is changed from the H level to the L level
- the control signal TRG is temporarily changed from the L level to the H level and returned to the L level.
- the ADC 33 reads the voltage of the power line 51 for the second time, and uses the voltage of the power line 51 as a voltage (signal level) corresponding to the illuminance with the reset level as a reference. get.
- the FET 72 (FIG. 5) is turned off. As a result, the power supply line 51 enters a floating state.
- the transfer transistor 62 to which the control signal TRG is supplied to the gate is temporarily turned on.
- the transfer transistor 62 When the transfer transistor 62 is turned on, the charge accumulated in the PD 61 during the accumulation phase (to be exact, from when the control signal TRG becomes L level in the shutter phase until it becomes H level in the readout phase) It flows into the power supply line 51 through the transfer transistor 62 and the reset transistor 63 and is converted into a corresponding voltage.
- the voltage of the power supply line 51 in the floating state fluctuates (drops) by the voltage (illuminance signal) corresponding to the charge accumulated in the PD 61 from the previous voltage VDD # 2, and the ADC 33
- the voltage after the fluctuation is acquired as a signal level (voltage corresponding to illuminance with reference to the reset level).
- the CDS and AD conversion of the signal level that is the voltage of the power line 51 acquired by the second reading uses the reset level that is the voltage (voltage VDD # 2) of the power line 51 acquired by the first reading.
- the digital data obtained as a result of CDS and AD conversion at the signal level is output as illuminance data.
- the pixel driving unit 21 (FIG. 1) sends the control signals RST and SEL to all of the M row of pixel units 111 , n to 11M, n . Simultaneously, the reset transistor 63 and the selection transistor 65 are turned on simultaneously.
- the pixel driving unit 21 sends a control signal TRG to the transfer transistor 62 of the M ⁇ N pixel units 11 1, 1 to 11 M, N pixels 60 for each color of light received by the pixels 60.
- the transfer transistor 62 of each pixel 60 can be controlled for each color.
- the pixel driving unit 21 transfers the control signal TRG that temporarily changes from the L level to the H level in the shutter phase and the readout phase to all the M ⁇ N pixel units 11 1, 1 to 11 M, N pixels 60.
- the ADC 33 By supplying the transistors 62 simultaneously, that is, by simultaneously turning on all the transfer transistors 62 of all the pixels 60 of the M ⁇ N pixel units 11 1, 1 to 11 M, N at the same time, the ADC 33 Then, illuminance data (illuminance data obtained by adding the light of each color) of light received by all the pixels 60 of the M ⁇ N pixel units 11 1, 1 to 11 M, N can be obtained. .
- the pixel driving unit 21 sends a control signal TRG that temporarily changes from the L level to the H level in the shutter phase and the readout phase to the M ⁇ N pixel units 11 1, 1 to 11 M, N pixels 60.
- a control signal TRG that temporarily changes from the L level to the H level in the shutter phase and the readout phase to the M ⁇ N pixel units 11 1, 1 to 11 M, N pixels 60.
- the ADC 33 allows the R pixel 60, Illuminance data for each of the R, G, and B colors of the light received by the G pixel 60 and the B pixel 60 can be obtained.
- FIG. 7 is a timing chart showing the control signal TRG given to the transfer transistor 62 when obtaining illuminance data for each color in the illuminometer mode.
- R, Gr, Gb, and B pixels 60 (R, Gr, Gb, and B pixels 60 that receive light of each light). ) Exists.
- FIG. 7 shows a control signal TRG to be given to the transfer transistor 62 when obtaining illuminance data for each color of R, Gr, Gb, and B.
- control signal TRG given to the transfer transistor 62 of the R pixel 60 is also referred to as a control signal TRG (R).
- control signals TRG given to the transfer transistors 62 of the Gr, Gb, and B pixels 60 are also referred to as control signals TRG (Gr), TRG (Gb), and TRG (B), respectively.
- the shutter phase is divided into, for example, an R shutter phase, a Gr shutter phase, a Gb shutter phase, and a B shutter phase in time order.
- the read phase is also divided into, for example, an R read phase, a Gr read phase, a Gb read phase, and a B read phase in time order.
- control signal TRG (R) of the control signals TRG (R), TRG (Gr), TRG (Gb), and TRG (B) is temporarily From L level to H level.
- the ADC 33 can obtain illuminance data for each color of R, Gr, Gb, and B in a time-sharing manner as in the case described with reference to FIG.
- the illuminance data not related to color and the illuminance data for each color are obtained by applying a voltage corresponding to the charge obtained from the pixels 60 of the M ⁇ N pixel units 111,1 to 11M , N to the vertical signal line. 42 1 to 42 N and, via the selector 23 (FIG. 1), it is supplied to the ADC 24 1 through 24 N, to the pixel data obtained by the CDS and the AD conversion at the ADC 24 1 to 24 N, all added It can also be obtained by adding each color.
- the illuminance data is obtained.
- the number of ADCs that need to be operated is only one of the ADCs 33, and the power consumption can be greatly reduced as compared with the case where all of the N ADCs 24 1 to 24 N are operated.
- FIG. 8 is a diagram for explaining noise generated by coupling between the control line TRG and the power supply line 51.
- FIG. 8 shows the read enable signal SWEN, the control signals RST, SEL, and TRG, and the voltage of the power supply line 51 in the illuminometer mode.
- the charge (signal charge) accumulated in the PD 61 is 0 (no light is incident on the PD 61 and is in a so-called dark state). .
- the power supply line 51 is connected to the voltage by the voltage step-down unit 73 (FIG. 5).
- the voltage VDD # 2 obtained by stepping down VDD # 1 is applied, in FIG. 8, the voltage VDD # 1 is applied to the power supply line 51 instead of the voltage VDD # 2.
- the power supply line 51 is brought into a floating state (after the readout enable signal SWEN is changed from the H level to the L level), and then applied to the transfer transistor 62.
- Control signal TRG is temporarily changed from L level to H level.
- control line TRG of the control signal TRG flows pixel control line 41 m
- the power supply line 51 are wired adjacent the control signal TRG flowing control line TRG is temporarily becomes H level
- noise is generated on the power supply line 51 due to coupling between the control line TRG and the power supply line 51 in a floating state, that is, the voltage of the power supply line 51 is reduced.
- the control signal TRG temporarily rises in conjunction with the H level temporarily.
- the switch unit 70 for bringing the power supply line 51 into a floating state includes the pMOS FET 72
- the voltage of the power supply line 51 connected to the drain of the FET 72 increases.
- the potential difference between the gate of the FET 72 and the power source line 51 becomes large (the portion where the power source line 51 of the FET 72 is connected appears as a source), Since the FET 72 is turned on, a current flows from the power line 51 to the FET 72 (source thereof).
- FIG. 9 is a diagram illustrating a change in the voltage of the power supply line 51 when the voltage VDD # 2 obtained by stepping down the voltage VDD # 1 is applied to the power supply line 51.
- the charge accumulated in the PD 61 is assumed to be 0 in order to simplify the description.
- the voltage VDD # 2 is lower than the voltage VDD # 1 by a voltage equal to or higher than the voltage corresponding to the increase of the voltage of the power supply line 51, which rises due to the coupling between the control line TRG and the power supply line 51. It is desirable to be.
- the voltage of the power supply line 51 in the floating state drops from the voltage VDD # 2 by a voltage (illuminance signal) corresponding to the charge accumulated in the PD 61 in the read phase.
- the voltage of the power supply line 51 cannot drop from the voltage VDD # 2 by the voltage corresponding to the charge accumulated in the PD 61, In particular, the total amount of charge (saturation charge amount) that can be accumulated in the PDs 61 of all the pixels used for illuminance measurement, and thus the dynamic range of the illuminance data is limited.
- a circuit having a variable step-down width (step-down width) for stepping down the voltage VDD # 1 can be employed.
- the step-down width in the voltage step-down unit 73 can be adjusted, for example, according to control from the outside.
- the voltage step-down unit 73 measures the increase in the voltage of the power supply line 51 due to the coupling with the control line TRG, and sets the step-down width to the increase or a value obtained by adding a predetermined margin to the increase. Can be adjusted.
- FIG. 10 is a diagram illustrating the clamp portion 32 of FIG.
- FIG. 10 is a timing chart showing the control signal TRG and the voltage of the power supply line 51 in the illuminometer mode.
- the transfer transistors 62 of all the pixels 60 of the M ⁇ N pixel units 11 1, 1 to 11 M, N are simultaneously turned on, By simultaneously turning on the transfer transistor 62 of only the R pixel 60, the Gr pixel 60, the Gb pixel 60, or the B pixel 60, illuminance data not related to color, R, Gr, Gb, Alternatively, B illuminance data can be obtained.
- the transfer transistor 62 is turned on in the readout phase, so that all the M ⁇ N pixel units 111,1 to 11M , N pixels 60 and R of the pixels 60 Charges (electrons) accumulated in the PD 61 flow from the pixel 60, the Gr pixel 60, the Gb pixel 60, or the B pixel 60 into the floating power supply line 51 all at once.
- electric charges are supplied to the floating power supply line 51 from all the pixels 60, a large number of pixels 60 such as the R pixel 60, the Gr pixel 60, the Gb pixel 60, or the B pixel 60.
- the voltage of the power supply line 51 may drop significantly from the voltage VDD # 2 as shown by the dotted line in FIG.
- the reliability of the pixel unit 11 m, n and thus the image sensor may be impaired.
- the clamp unit 32 (FIG. 1) clamps the voltage of the power supply line to the voltage VDD # 4 which is equal to or higher than the minimum value of the performance guarantee voltage lower than the voltage VDD # 2.
- FIG. 11 is a circuit diagram illustrating a configuration example of the clamp unit 32 of FIG.
- the clamp unit 32 includes an nMOS FET 81.
- the source of the FET 81 is connected to the power supply line 51, and the gate and drain thereof are connected to the power supply VDD # 4.
- the gate of the FET 81 is connected to the power supply VDD # 4. Therefore, the voltage of the power supply line 51 connected to the source of the FET 81 is less than the voltage VDD # 4 (more precisely, the voltage VDD # When the voltage is equal to or lower than the voltage obtained by subtracting the voltage V GS between the gate and the source of the FET 81 from # 4, the FET 81 is turned on. As a result, the power supply line 51 is connected to the power supply VDD # 4 via the FET 81 and clamped to the voltage VDD # 4.
- the voltage of the power supply line 51 drops from the voltage VDD # 2 by a certain amount or more.
- the voltage of the FD (gate of the amplification transistor 64) of the pixel unit 11m, n exceeds the range of the performance guarantee voltage.
- the image sensor can notify the outside that the measurement of illuminance is an error.
- FIG. 12 is a diagram illustrating the pixel control line 41 m connected to the pixel driving unit 21 in FIG.
- the pixel unit 11 m, n has one pixel 60, and hereinafter, the R pixel 60, the Gr pixel 60, the pixel 60 Gr, and the Gb pixel 60, as appropriate.
- the pixel 60Gb and the B pixel 60 are referred to as a pixel 60B, respectively.
- the pixel drive unit 21 supplies control lines TRG (R), TRG (Gr), TRG (Gb), and control lines TRG (Gr) through which the control signals TRG (R), TRG (Gr) and TRG (B) flow, respectively. ), TRG (Gb), and TRG (B).
- the pixel control line 412k-1 in the 2k-1 row that is an odd row includes two control lines TRG (R) and TRG (Gr) as the control line TRG, and the 2k-1 row in the even row is the 2k-1
- the pixel control line 412k in the row includes two control lines TRG (Gb) and TRG (B) as the control line TRG.
- FIG. 13 is a block diagram illustrating a first configuration example of the pixel driving unit 21 of FIG.
- FIG. 13 shows a first configuration example of a part of the pixel driving unit 21 that controls the transfer transistor 62.
- the pixel driving unit 21 includes 2M TRG drivers 90 1 to 90 2M and 2M driver control units 96 1 to 96 2M .
- the TRG driver 904k -3 controls the transfer transistor 62 of the pixel 60R among the pixels 60R and 60Gr in the 2k-1 row on the control line TRG (R) included in the pixel control line 412k -1. Control is performed by flowing the signal TRG (R).
- the TRG driver 904k -2 controls the transfer transistor 62 of the pixel 60Gr out of the pixels 60R and 60Gr in the 2k-1 row on the control line TRG (Gr) included in the pixel control line 412k -1. Control is performed by flowing a signal TRG (Gr).
- TRG driver 90 4k-1 is among the 2k-th row of pixels 60Gb and 60B, the transfer transistors 62 of the pixel 60Gb, on the control line TRG (Gb) included in the pixel control line 41 2k, the control signal TRG (Gb ).
- TRG driver 90 4k is of 2k-th row of pixels 60Gb and 60B, the transfer transistors 62 of the pixel 60B, on the control line TRG (B) included in the pixel control line 41 2k, the control signal TRG to (B) Control by flowing.
- connection point between the drains of the FETs 91 q and 92 q is connected to the control line TRG, and the connection point between the gates of the FETs 91 q and 92 q is connected to the driver control unit 96 q .
- connection point of the FET 91 q and 92 q is adapted to the output terminal of the TRG driver 90 q, a connection point of the gates to each other in the FET 91 q and 92 q are taken to the input terminal of the TRG driver 90 q Yes.
- the source of the pMOS FET 91 q is connected to the power supply VDD # 1 through a series circuit in which a plurality of resistors r are connected in series.
- the source of the nMOS FET 92 q is connected to a plurality of resistors (power supply wirings).
- the resistor (R) is connected to GND (ground) through a series circuit in which R is connected in series.
- a connection point between the source of the nMOS FET 92 q and a series circuit in which a plurality of resistors R are connected in series is also referred to as a node 93 q .
- the TRG driver 96 q controls the TRG driver 90 q in accordance with, for example, an external command, a predetermined sequence, or the like.
- the TRG driver 96 q applies, for example, the H level or the L level to the gates of the FETs 91 q and 92 q of the TRG driver 90 q .
- the node 93 q is connected to GND via a series circuit in which a plurality of resistors R are connected in series.
- the voltage (potential) of the node 93 q is a series circuit in which a plurality of resistors R are connected in series. As long as no current flows through the pin, it is equal to the GND potential.
- node 93 q to the connected TRG driver 90 q of the output terminal becomes the L level (GND potential)
- the control line TRG connected to the output terminal of the TRG driver 90 q is also at the L level.
- the output terminal of the TRG driver 90 q (the connection point between the drains of the FETs 91 q and 92 q ) is at the H level (voltage VDD # 1), and the control line TRG connected to the output terminal of the TRG driver 90 q Also goes H level.
- the control line TRG (R) connected to the transfer transistor 62 of the R pixel 60R is used in the TRG driver 904k -3 . All are temporarily set to H level all at once.
- control line TRG (R) connected to the transfer transistor 62 is set to the L level again after being set to the H level, but the control line TRG (R) is set to the L level again.
- 90 4k-3 nMOS FET 92 4k-3 is turned on.
- the charge of the gate of the transfer transistor 62 of the pixel 60R of R connected to the control line TRG (R) is the control line TRG (R), and, via the FET 92 4k-3 in the ON state, the node 93 4K- 3 , and further flows through a series circuit in which a plurality of resistors R are connected in series, connected to the node 934 4k-3 .
- TRG driver 90 4k-3 connected to the control line TRG (R) that temporarily becomes H level due to IR drop in a series circuit in which a plurality of resistors R are connected in series
- the TRG driver 90 4k-2 connected to the control line TGR (Gr) that is not at the H level (still at the L level), the node 93 4k-2 of the 4K-2 , and the TRG driver 90 connected to the control line TGR (Gb) node 93 4k-1 of 4k-1, and the node 93 4k voltage of the connected TRG driver 90 4k to the control line TGR (B) (potential) varies from the GND potential.
- control lines TRG (R) temporarily become H level all at once and then become L level, IR drop occurs in a series circuit in which a plurality of resistors R are connected in series.
- the control line TGR (Gr) connected to the control line TGR (Gr) which is not at the H level (still at the L level).
- TRG driver 90 4k-2 node 93 4k-2 TRG driver 90 4k-1 node 93 4k-1 connected to control line TGR (Gb), and TRG driver TRG connected to control line TGR (B)
- the voltage of the node 93 4k of the driver 90 4k simply rises by the amount of IR drop in a series circuit in which a plurality of resistors R are connected in series.
- the voltage at node 93 q is, when rising from a voltage of GND, the drain of the FET 92 q the source is connected to the node 93 q, and hence, the voltage of the control line TRG connected to its drain rises.
- TRG (R) is temporarily set to the H level
- another control line is caused by IR drop generated in a series circuit in which a plurality of resistors R are connected in series.
- the voltages of TRG (Gr), TRG (Gb), and TRG (B) increase.
- the transfer transistor 62 of the Gr pixel 60Gr connected to the control line TRG (Gr) is turned on, and the charge accumulated in the PD 61 is turned on. This leaks through the transfer transistor 62, and the accuracy of the illuminance data of the Gr color obtained by the ADC 33 deteriorates.
- FIG. 14 is a timing chart showing the voltage (control signal TRG) of the control line TRG when obtaining illuminance data for each color in the illuminometer mode.
- control line TRG (R) (voltage) is temporarily set to the H level
- the IR drop described with reference to FIG. 13 occurs when the control line TRG (R) returns from the H level to the L level.
- the voltages of the other control lines TRG (Gr), TRG (Gb), and TRG (B) rise.
- control line TRG (Gr) when the control line TRG (Gr) is temporarily set to the H level, when the control line TRG (Gr) returns from the H level to the L level, the IR drop described in FIG.
- the control lines TRG (R), TRG (Gb), and TRG (B) increase in voltage.
- FIG. 15 is a block diagram showing a second configuration example of the pixel driving unit 21 of FIG.
- FIG. 15 shows a second configuration example of a portion of the pixel driving unit 21 that controls the transfer transistor 62.
- the pixel drive unit 21 includes 2M TRG drivers 100 1 to 100 2M and 2M driver control units 111 1 to 111 2M .
- the TRG driver 100 4k-3 controls the transfer transistor 62 of the pixel 60R among the pixels 60R and 60Gr in the 2k-1 row on the control line TRG (R) included in the pixel control line 412k -1. Control is performed by flowing the signal TRG (R).
- the TRG driver 100 4k-2 controls the transfer transistor 62 of the pixel 60Gr among the pixels 60R and 60Gr in the 2k-1 row on the control line TRG (Gr) included in the pixel control line 412k -1. Control is performed by flowing a signal TRG (Gr).
- TRG driver 100 4k-1 is among the 2k-th row of pixels 60Gb and 60B, the transfer transistors 62 of the pixel 60Gb, on the control line TRG (Gb) included in the pixel control line 41 2k, the control signal TRG (Gb ).
- TRG driver 100 4k is of 2k-th row of pixels 60Gb and 60B, the transfer transistors 62 of the pixel 60B, on the control line TRG (B) included in the pixel control line 41 2k, the control signal TRG to (B) Control by flowing.
- the drains of the FETs 101 q , 102 q , and 103 q are connected to each other, and the connection point between the drains is connected to the control line TRG. Note that the connection point between the drains of the FETs 101 q , 102 q , and 103 q is an output terminal of the TRG driver 100 q .
- the source of the pMOS FET 101 q is connected to the power supply VDD # 1 through a series circuit in which a plurality of resistors r are connected in series.
- the source of the nMOS FET 102 q is connected to a plurality of resistors (power supply wirings). Resistor R is connected to GND via a series circuit connected in series. Further, the source of the nMOS FET 103 q is connected to GND (ground) through a series circuit in which a plurality of resistors (power supply wiring resistors) R ′ are connected in series.
- a connection point between the source and a series circuit in which a plurality of resistors R ′ are connected in series is referred to as a node 105 q .
- the node 104 q is connected to GND through a series circuit in which a plurality of resistors R are connected in series. Therefore, the voltage GND # 1 of the node 104 q has a plurality of resistors R connected in series. As long as no current flows through the series circuit, it is equal to the GND potential.
- the node 105 q is connected to GND via a series circuit in which a plurality of resistors R ′ are connected in series.
- the voltage GND # 2 of the node 105 q is connected to a plurality of resistors R ′ in series. As long as no current flows through the connected series circuit, it is equal to the GND potential.
- the TRG driver 111 q controls the TRG driver 100 q in accordance with, for example, an external command, a predetermined sequence, or the like.
- the TRG driver 111 q applies the H level or the L level to the gates of the FETs 101 q , 102 q , and 103 q constituting the TRG driver 100 q , thereby enabling the FETs 101 q , 102 q , and 103 q is controlled to an on state or an off state.
- the output terminal of the TRG driver 100 q (the connection point between the drains of the FETs 101 q , 102 q , and 103 q ) is through the FET 101 q oN state is connected to the power supply VDD # 1.
- the output terminal of the TRG driver 100 q is at the H level (voltage VDD # 1), and the control line TRG connected to the output terminal of the TRG driver 100 q is also at the H level.
- FET 101 q and,, FET 103 q is in the off state, if the FET 102 q is set to the ON state, the output terminal of the TRG driver 100 q through the FET 102 q ON state, connected to the node 104 q Is done.
- the output terminal of the TRG driver 100 q is at L level (the voltage GND # 1 of the node 104 q ), and the control line TRG connected to the output terminal of the TRG driver 100 q is also at L level.
- FET 101 q and,, FET 102 q is in the off state, if the FET 103 q is set to the ON state, the output terminal of the TRG driver 100 q through the FET 103 q ON state, connected to the node 105 q Is done.
- the output terminal of the TRG driver 100 q is at L level (the voltage GND # 2 of the node 105 q ), and the control line TRG connected to the output terminal of the TRG driver 100 q is also at L level.
- FIG. 16 is a diagram for explaining the operation of the pixel driving unit 21 in FIG.
- FIG. 16 shows one pixel of R, Gr, Gb, and B when obtaining illuminance data for each color of R, Gr, Gb, and B, for example, R pixel 60R.
- the voltage of the control line (control signal) TRG when the charge is transferred from the PD 61 and when the charge is transferred from another PD, for example, the PD 61 of the B pixel 60B, and the TRG driver 100 q The state of the FETs 101 q to 103 q to be configured is shown.
- the control line TRG (R) connected to the transfer transistor 62 of the R pixel 60R is temporarily set to H level in the TRG driver 1004k -3 .
- the FET 101 4k-3 of the TRG driver 100 4k-3 that controls the R pixel 60R is changed from the off state to the on state, and thereafter Is turned off.
- the FET 102 4k-3 is switched from the on-state to the off-state, that is, from the on-state to the on-state after that of the FET 101 4k-3 .
- the FET 103 4k-3 is turned off (remains).
- the FET 101 4k-3 is turned off, the FET 102 4k-3 is turned on, and the FET 103 4k-3 is turned off.
- the output terminal of the TRG driver 100 4k-3 is connected to the node 104 4k-3 via the FET 102 4k-3 in the on state, it is connected to the output terminal of the TRG driver 100 4k-3 .
- the voltage of the control line TRG (R) becomes the potential GND # 1 of the node 1044k-3 , that is, the L level.
- the FET 101 4k-3 When the charge is transferred from the PD 61 of the R pixel 60R, the FET 101 4k-3 is turned on, the FET 102 4k-3 is turned off, and the FET 103 4k-3 is turned off.
- the control since the output terminal of the TRG driver 100 4k-3 is connected to the power supply VDD # 1 via the FET 101 4k-3 in the on state, the control connected to the output terminal of the TRG driver 100 4k-3 .
- the voltage of the line TRG (R) changes from the L level to the voltage VDD # 1, that is, the H level.
- the FET 101 4k-3 When the charge is transferred from the PD 61 of the R pixel 60R, the FET 101 4k-3 is turned off, the FET 102 4k-3 is turned on, and the FET 103 4k-3 is turned off.
- the output terminal of the TRG driver 100 4k-3 since the output terminal of the TRG driver 100 4k-3 is connected to the node 104 4k-3 via the FET 102 4k-3 in the on state, it is connected to the output terminal of the TRG driver 100 4k-3 .
- the voltage of the control line TRG (R) changes from the H level to the voltage GND # 1 of the node 1044k-3 , that is, the L level.
- a corresponding voltage drop occurs, and in addition to the node 104 4k-3 of the TRG driver 100 4k-3 that controls the R pixel 60R, TRG driver 100 4k-1 node 104 4k-1 for controlling the pixels 60Gb of TRG driver 100 node 104 4k-2 4k-2, Gb that controls the pixel 60Gr of Gr and, TRG driver for controlling the pixels 60B in the B 100 4k node 104 4k voltage GND # 1 rises by the amount of IR drop in a series circuit in which a plurality of resistors R are connected in series.
- the driver control unit 111 4k Under control, the FET 101 4k is turned off, the FET 102 4k is turned off, and the FET 103 4k is turned on.
- the output terminal of the TRG driver 100 4k via the FET 103 4k on-state is connected to the node 105 4k
- the voltage of the control line TRG (B) connected to the output terminal of the TRG driver 1004k becomes the potential GND # 2 of the node 1054k , that is, the L level.
- the voltage GND # 1 of the node 104 q (nodes 104 4k-3 , 104 4k-2 , 104 4k-1 , 104 4k ) has a plurality of resistors R in series.
- the output terminal of the TRG driver 100 4k that controls the B pixel 60B that is not the R pixel 60R but rises by the IR drop in the connected series circuit is connected to the node 105 4k instead of the node 104 4k. Therefore, the voltage of the control line TRG (B) connected to the output terminal of the TRG driver 1004k is not affected by the voltage GND # 1 of the node 1044k that increases by the IR drop.
- the control line TRG (Gr) connected to the output terminal of the TRG driver 100 4k-2 that controls the Gr pixel 60Gr and the output terminal of the TRG driver 100 4k-1 that controls the Gb pixel 60Gb are connected. The same applies to the control line TRG (Gb).
- control lines TRG (R) connected to the R pixel 60R to the H level
- the control lines TRG (Gr), TRG (Gb), and TRG (B) of other colors are used.
- the voltage of the control lines TRG (Gr), TRG (Gb), and TRG (B) increases as described with reference to FIG. 13, and the Gr pixels 60Gr, Gb pixels, as described above with reference to FIG. It is possible to prevent the accuracy of the illuminance data of each color from deteriorating due to leakage of charges accumulated in the 60Br and B pixels 60B.
- the TRG driver 100 q performs the same processing as when charges are transferred from the R pixels 60R.
- the FET 101 4k of the TRG driver 100 4k that controls the B pixel 60B is changed from the off state to the on state, and then turned off.
- the FET 102 4k is in a state opposite to the state of the FET 101 4k , that is, from the on state to the off state, and then turned on.
- the FET 101 4k When the charge is transferred from the B pixel 60B, the FET 101 4k is turned on, the FET 102 4k is turned off, and the FET 103 4k is turned off.
- the output terminal of the TRG driver 100 4k via the FET 101 4k on-state because it is connected to the power source VDD # 1, control line is connected to the output terminal of the TRG driver 100 4k TRG of (B)
- the voltage changes from L level to voltage VDD # 1 as H level.
- the FET 101 4k When the charge is transferred from the B pixel 60B, the FET 101 4k is turned off, the FET 102 4k is turned on, and the FET 103 4k is turned off.
- the voltage of the control line TRG (B) connected to the output terminal of the TRG driver 100 4k Changes from the H level to the voltage GND # 1 of the node 1044k as the L level.
- the voltage of the control line TRG (B) is, when consisting of H level to L level (the node 104 4k potential GND # 1), of the FET 101 4k to 103 4k, only FET 102 4k is turned on
- the charge of the gate of the transfer transistor 62 of the B pixel 60B connected to the control line TRG (B) is changed to the control line TRG (B), and, via the FET 102 4k on, the node 104 4k, furthermore, a node 104 connected to 4k, flows to a series circuit in which a plurality of resistors R are connected in series.
- an IR drop occurs in a series circuit in which a plurality of resistors R are connected in series, and the TRG driver 100 that controls the R pixel 60R in addition to the node 104 4k of the TRG driver 100 4k that controls the B pixel 60B. 4k-3 node 104 4k-3 , TRG driver 100 that controls Gr pixel 60Gr, 4k-2 node 104 4k-2 , and TRB driver 100 that controls Gb pixel 60Gb 4k-1 node 104 4k-1
- the voltage GND # 1 rises by the amount of IR drop in a series circuit in which a plurality of resistors R are connected in series.
- the TRG driver 100 4k-3 controlling the pixel 60R of R As shown in FIG. 16, the driver control unit 111 4K- 3 , the FET 101 4k-3 is turned off, the FET 102 4k-3 is turned off, and the FET 103 4k-3 is turned on.
- the output terminal of the TRG driver 100 4k-3 is in the ON state FET 103 4k-3 To the node 105 4k-3 . Therefore, the voltage of the control line TRG (R) connected to the output terminal of the TRG driver 100 4k-3 becomes the potential GND # 2 of the node 105 4k-3 as the L level.
- the nodes 104 q nodes 104 4k-3 , 104 4k-2 , 104 4k ⁇ 1 , 104 4k ) voltage GND # 1 rises by the amount of IR drop in the series circuit in which a plurality of resistors R are connected in series, but the TRG driver 100 4k controls the R pixel 60R that is not the B pixel 60B.
- the control line TRG (Gr) connected to the output terminal of the TRG driver 100 4k-2 that controls the Gr pixel 60Gr and the output terminal of the TRG driver 100 4k-1 that controls the Gb pixel 60Gb are connected. The same applies to the control line TRG (Gb).
- the control lines TRG (R), TRG (Gr), and TRG (Gb) of other colors are used.
- the voltages of the control lines TRG (R), TRG (Gr), and TRG (Gb) are increased, and the R pixel 60R and the Gr pixel are not increased. It is possible to prevent the accuracy of the illuminance data of each color from deteriorating due to leakage of charges accumulated in the 60 Gr and Gb pixels 60 Br.
- the TRG driver 100 q is connected to the control line TRG connected to its output terminal, and hence the transfer transistor 62 (of the pixel 60 connected to the control line TRG).
- the gate has two nodes 104 q and 105 q (first path and second path to GND) as a plurality connected to GND.
- the TRG driver 100 q ′ that controls the transfer transistor 62 so as to transfer charges among the TRG driver 100 q is one node of the two nodes 104 q ′ and 105 q ′.
- node 104 q ′ is used. That is, the TRG driver 100 q ′ that controls the transfer transistor 62 so as to transfer the charge sets the voltage of the control line TRG connecting the output terminal and the transfer transistor 62 (the gate thereof) to the L level.
- the control line TRG is connected to the node 104 q ′ of the voltage GND # 1.
- the TRG driver 100 q ′′ that does not control the transfer transistor 62 so as to transfer charges among the TRG driver 100 q is one of the two nodes 104 q ′′ and 105 q ′′ .
- the other one node, for example, node 105 q ′′ is used. That is, the TRG driver 100 q ′′ that does not control the transfer transistor 62 so as to transfer charges is connected to the control line TRG that connects the output terminal and the transfer transistor 62 (the gate thereof) with the node 105 q ′.
- the voltage of the control line TRG is set to the voltage GND # 2 of the node 105 q ′′ as the L level.
- FIG. 17 is a timing chart showing the voltage (control signal TRG) of the control line TRG controlled by the TRG driver 100 q of FIG. 15 when obtaining illuminance data for each color in the illuminometer mode.
- control line TRG (R) (voltage) is set to L level
- the control line TRG (R) is connected to the node 104 4k in the TRG driver 100 4k-3 .
- -3 to be the voltage GND # 1 of the node 104 4k-3 .
- the other control lines TRG (Gr), TRG (Gb), and TRG (B) are respectively connected to the nodes 105 4k-2 , 100 4k , 100 4k-2 , 100 4k-1 , 100 4k , respectively.
- 105 4k ⁇ 1 and 105 4k are connected to the voltage GND # 2 of the nodes 105 4k ⁇ 2 , 105 4k ⁇ 1 and 105 4k .
- the TRG driver 100 q ′ that controls the transfer transistor 62 to perform charge transfer and the TRG driver 100 q ′′ that does not control the transfer transistor 62 to perform charge transfer.
- the node 104 q ′ connected to GND through a series circuit in which a plurality of resistors R are connected in series
- the node 104 q ′ connected to GND through a series circuit in which a plurality of resistors R ′ are connected in series.
- the IR drop is This does not affect the control line TRG connected to the node 105 q ′′ of GND # 2 and further the transfer transistor 62 connected to the control line TRG.
- FIG. 18 is a circuit diagram showing another configuration example of the pixel unit 11m, n of FIG.
- the pixel units 11 m, n are common to those in FIG. 2 in that they include a reset transistor 63, an amplification transistor 64, and a selection transistor 65.
- the pixel unit 11 m, n in FIG. 18 includes a plurality of, for example, four pixels 130 1 , 130 2 , 130 3 , and 130 4 instead of one pixel 60, This is different from the case of FIG.
- the pixel unit 11 m, n in FIG. 18 employs a shared pixel configuration in which a plurality of four pixels 130 1 to 130 4 share the reset transistor 63, the amplification transistor 64, and the selection transistor 65. 2 is different from the case of FIG. 2 in which one pixel 60 uses the reset transistor 63, the amplification transistor 64, and the selection transistor 65.
- pixels 130 1 to 130 4 are arranged in 2 rows and 2 columns (2 ⁇ 2). That is, the pixel 130 1, the upper left position of the two rows and two columns, the pixel 130 2, the upper right position of the two rows and two columns, the pixel 130 3, the lower left position of the two rows and two columns, pixels 130 4 Are arranged at the lower right position of 2 rows and 2 columns.
- the pixel 130 1 for example, a pixel of R for receiving light of R of the Bayer array
- the pixel 130 2 is, for example, a pixel of Gr receiving light Gr in bayer array.
- the pixel control line 41 m connected to the pixel driver 21 includes a control line RST for controlling the reset transistor 63, a control line SEL for controlling the selection transistor 65, and a transfer transistor 132 i .
- a control line TRG to control.
- the control line RST is connected to the gate of the reset transistor 63, and the control line SEL is connected to the gate of the selection transistor 65.
- the control line TRG is connected to the gate of the transfer transistor 132 i .
- the control line TRG the control line is connected to the transfer transistor 132 1 of pixel 130 1 R TRG (R), the control line is connected to the transfer transistor 132 second pixel 130 2 Gr TRG (Gr), the Gb control lines are connected to the transfer transistor 132 third pixel 130 3 TRG (Gb), and, there is a control line TRG (B) connected to the transfer transistor 132 4 pixels 130 4 B.
- the anode of the PD 131 i is grounded to GND, and its cathode is connected to the source of the transfer transistor 132 i .
- the transfer transistor 132 i is an nMOS FET, and its drain is connected to a connection point between the source of the reset transistor 63 and the gate of the amplification transistor 64.
- the PD 131 i receives light of the color incident thereon and performs photoelectric conversion according to the amount of light received. Accumulate charge.
- the H level is temporarily given to the gate of the reset transistor 63 via the control line RST, and the reset transistor 63 is temporarily turned on.
- the charge in FD is transferred to reset transistor 63 and power supply line 51. Is reset to the power supply VDD # 1.
- the gate of the transfer transistor 132 1 of the R pixel 130 1 is temporarily given an H level via the control line TRG (R), and the transfer transistor 132 1 is temporarily turned on.
- the charge accumulated in the PD 131 1 is transferred to the FD via the transfer transistor 132 1 .
- the amplification transistor 64 a voltage corresponding to the potential of immediately after the reset FD, as a reset level, and outputs to the source, then the voltage charge from the PD 131 1 corresponds to the FD potential immediately after the transfer, reset level Is output to the source as a voltage (signal level) corresponding to the pixel value with reference to.
- the reset level and the signal level output to the source of the amplification transistor 64 are output onto the vertical signal line 42 n via the selection transistor 65.
- ADC 24 n CDS and AD conversion of the signal level is performed using the reset level, the digital data obtained as a result of the CDS and the AD conversion of the signal level is output as the pixel 130 1 of R pixel data.
- the reset transistor 63 is temporarily turned on again, and reset is performed to sweep out the electric charge in the FD to the power supply VDD # 1 via the reset transistor 63 and the power supply line 51.
- the gate of the transfer transistor 132 2 of the Gr pixel 130 2 is temporarily given an H level via the control line TRG (Gr), and the transfer transistor 132 1 is temporarily turned on.
- Amplifying transistor 64 a voltage corresponding to the potential of immediately after the reset FD, as a reset level, and outputs to the source, then the voltage charge from the PD 131 2 corresponding to the FD potential immediately transferred, based on the reset level As a signal level corresponding to the pixel value to be output to the source.
- the reset level and the signal level output to the source of the amplification transistor 64 are output onto the vertical signal line 42 n via the selection transistor 65.
- ADC 24 n CDS and AD conversion of the signal level is performed using the reset level, the digital data obtained as a result of the CDS and the AD conversion of the signal level is output as the Gr pixel 130 2 pixel data.
- control signals RST and SEL are always at the H level, and as a result, the reset transistor 63 and the selection transistor 65 are always on.
- the control line TRG (R) connected to the transfer transistor 132 1 of the R pixel 130 1 is temporarily set to the H level in the shutter phase, and the transfer transistor 132 1 is temporarily turned on.
- the voltage of the power supply line 51 when the PD 131 1 is reset, the reset level is supplied to ADC33 which is connected to the power supply line 51.
- control line TRG (R) connected to the transfer transistor 132 1 of the pixel 130 1 is temporarily set to the H level in the readout phase, and the transfer transistor 132 1 is temporarily turned on. .
- the voltage corresponding to the charge accumulated in the PD 131 1 is referenced to the reset level, as a voltage (signal level) corresponding to the illuminance, is supplied to ADC33 which is connected to the power supply line 51.
- the signal level of the CDS and the AD converter from the power line 51 is performed using the reset level from the power supply line 51, the digital data obtained as a result of the CDS and the AD conversion of the signal level, the pixel 130 1 It is output as illuminance data of the received R light.
- Gr pixel 130 2 of the transfer transistor 132 2 connected to the control line TRG (Gr) is temporarily to a H level, the transfer transistor 132 2 is temporarily turned on.
- the reset transistor 63 is always in the ON state, the transfer transistor 132 2 is turned on, electric charges accumulated in the PD 131 2 pixels 130 2 of Gr, the transfer transistor 132 2, the reset transistor 63, and, via a power line 51, the conversion control unit 31 (power supply VDD # 2) swept in (FIG. 5), PD 131 2 is reset.
- the voltage of the power supply line 51 when the PD 131 1 is reset, the reset level is supplied to ADC33 which is connected to the power supply line 51.
- the voltage corresponding to the charge accumulated in the PD 131 2 is referenced to the reset level, as a signal level corresponding to the illuminance, is supplied to ADC33 which is connected to the power supply line 51.
- the signal level of the CDS and the AD converter from the power line 51 is performed using the reset level from the power supply line 51, the digital data obtained as a result of the CDS and the AD conversion of the signal level, the pixel 130 2 It is output as illuminance data of Gr light received.
- the luminometer mode, the control line connected to the transfer transistor 132 third pixel 130 3 Gb TRG (Gb), and, B pixels 130 4 of the transfer transistors 132 4 connected to the control line TRG (B) also, at different timings, by being temporarily H level, the ADC 33, the pixel 130 3 illuminance data of light Gb of received light, and the illuminance data of light B which pixels 130 4 is received is acquired.
- the transfer transistor 132 i that transfers charges accumulated in the PD 131 i, R, Gr, Gb, and controls for each color of B, and different timings, temporarily by the ON state , R, Gr, Gb, and B color illuminance data can be obtained.
- the illuminance can be measured for each color regardless of whether the image sensor shares a plurality of color pixels. Further, when measuring the illuminance for each color, it is not necessary to add a circuit for that purpose to the pixel.
- the transfer transistor 132 i that transfers charges accumulated in the PD 131 i, R, Gr, Gb, and, regardless of the color of B, and the same timing, simultaneously, temporarily turned By doing so, illuminance data unrelated to color can be obtained.
- the pixel unit 11 m, n has a configuration of shared pixels of 2 ⁇ 2 pixels (pixels 130 1 to 130 4 ).
- the present invention can be applied to a pixel unit having a four-transistor configuration including a transfer transistor, a reset transistor, an amplification transistor, and a selection transistor that shares an arbitrary number of pixels.
- the image sensor described above can be simulated on a computer.
- the computer When the image sensor is simulated on a computer, the computer is connected to the image sensor, that is, the pixel array 10, the pixel driving unit 21, the selectors 22 and 23, the ADCs 24 1 to 24 N , the conversion control unit 31, the clamping unit 32, A simulation program for functioning as the ADC 33 is installed in the computer.
- FIG. 19 shows a configuration example of an embodiment of a computer on which a simulation program is installed.
- the program can be recorded in advance in a hard disk 205 or ROM 203 as a recording medium built in the computer.
- the program can be stored (recorded) in the removable recording medium 211.
- a removable recording medium 211 can be provided as so-called package software.
- examples of the removable recording medium 211 include a flexible disk, a CD-ROM (Compact Disc Read Only Memory), a MO (Magneto Optical) disc, a DVD (Digital Versatile Disc), a magnetic disc, and a semiconductor memory.
- the program can be installed on the computer from the removable recording medium 211 as described above, or downloaded to the computer via a communication network or a broadcast network, and installed on the built-in hard disk 205. That is, the program is transferred from a download site to a computer wirelessly via a digital satellite broadcasting artificial satellite, or wired to a computer via a network such as a LAN (Local Area Network) or the Internet. be able to.
- a network such as a LAN (Local Area Network) or the Internet.
- the computer incorporates a CPU (Central Processing Unit) 202, and an input / output interface 210 is connected to the CPU 202 via the bus 201.
- a CPU Central Processing Unit
- the CPU 202 executes a program stored in a ROM (Read Only Memory) 203 according to the command. .
- the CPU 202 loads a program stored in the hard disk 205 into a RAM (Random Access Memory) 204 and executes it.
- the CPU 202 performs processing according to the flowchart described above or processing performed by the configuration of the block diagram described above. Then, the CPU 202 outputs the processing result as necessary, for example, via the input / output interface 210, from the output unit 206, or from the communication unit 208, and further recorded in the hard disk 205.
- the input unit 207 includes a keyboard, a mouse, a microphone, and the like.
- the output unit 206 includes an LCD (Liquid Crystal Display), a speaker, and the like.
- the processing performed by the computer according to the program does not necessarily have to be performed in chronological order in the order described as the flowchart. That is, the processing performed by the computer according to the program includes processing executed in parallel or individually (for example, parallel processing or object processing).
- the program may be processed by one computer (processor), or may be distributedly processed by a plurality of computers. Furthermore, the program may be transferred to a remote computer and executed.
- only one ADC 33 is provided as an ADC for obtaining illuminance data.
- an ADC for obtaining illuminance data for example, an ADC connected to an R pixel.
- a plurality of ADCs such as an ADC connected to a G pixel (each or both of Gr and Gb) and an ADC connected to a B pixel can be provided.
- an ADC connected to the R pixel, an ADC connected to the G pixel, and an ADC connected to the B pixel each of the R, G, and B colors Illuminance data can be obtained simultaneously.
- the image sensor (FIG. 1) of the present embodiment only one ADC 33 is provided as an ADC for obtaining illuminance data, and the (array) pixel 60 constituting the pixel array 10 is included in the one ADC 33.
- a signal (added value) corresponding to all received light is supplied and AD converted. Therefore, it can be said that the image sensor of this embodiment has a circuit that can read out signals of all (opening) pixels of the image sensor by one AD conversion.
- the pixel unit 11 m, n can be configured without the selection transistor 65.
- this technique can take the following structures.
- a photoelectric conversion unit that performs photoelectric conversion of light of a predetermined color incident via a color filter, and a pixel that includes a transfer transistor that can be controlled for each color and transfers charges obtained by photoelectric conversion of the photoelectric conversion unit; , A plurality of pixel units connected to an AD conversion unit that performs AD (Analog to Digital) conversion, and having a reset transistor that resets the charge, Under the control of the transfer transistor, the charge is read from the photoelectric conversion unit through the transfer transistor and the reset transistor, and a voltage corresponding to the charge is supplied to the AD conversion unit connected to the reset transistor.
- Image sensor that performs photoelectric conversion of light of a predetermined color incident via a color filter, and a pixel that includes a transfer transistor that can be controlled for each color and transfers charges obtained by photoelectric conversion of the photoelectric conversion unit; , A plurality of pixel units connected to an AD conversion unit that performs AD (Analog to Digital) conversion, and having a reset transistor that resets the charge, Under the control of the transfer
- the AD converter is connected to a power line connecting the drain of the reset transistor and a power source, The power supply line is set in a floating state, and the charge is caused to flow into the power supply line in the floating state via the reset transistor, thereby converting the charge into a voltage, and the AD conversion connected to the power supply line
- the conversion control unit A step-down unit that generates a step-down voltage obtained by stepping down the voltage of the power source; The image sensor according to [3] or [4], wherein the step-down voltage is applied to the power supply line connected to the reset transistor in an on state, and then the power supply line is brought into a floating state.
- the pixel unit is Having a plurality of pixels, The image sensor according to any one of [1] to [6], wherein the plurality of pixels share the reset transistor.
- a photoelectric conversion unit that performs photoelectric conversion of light of a predetermined color incident via a color filter, and a pixel that includes a transfer transistor that can be controlled for each color and transfers charges obtained by photoelectric conversion of the photoelectric conversion unit; ,
- the charge from the photoelectric conversion unit is controlled by the transfer transistor of an image sensor that is connected to an AD conversion unit that performs AD (Analog to Digital) conversion and includes a plurality of pixel units having a reset transistor that resets the charge.
- a method of controlling an image sensor comprising: reading through the transfer transistor and the reset transistor, and supplying a voltage corresponding to the charge to the AD conversion unit connected to the reset transistor.
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Abstract
Description
色フィルタを介して入射する所定の色の光の光電変換を行う光電変換部、及び、前記光電変換部の光電変換によって得られる電荷を転送する、色ごとに制御可能な転送トランジスタを含む画素と、
AD(Analog to Digital)変換を行うAD変換部に接続され、前記電荷をリセットするリセットトランジスタと
を有する複数の画素ユニットを備え、
前記転送トランジスタの制御により、前記光電変換部から前記電荷を、前記転送トランジスタ及び前記リセットトランジスタを介して読み出し、その電荷に対応する電圧を、前記リセットトランジスタに接続されている前記AD変換部に供給する
イメージセンサ。
[2]
前記転送トランジスタを、色ごとに制御することにより、前記色ごとに、前記電荷に対応する電圧を、前記AD変換部に供給する
[1]に記載のイメージセンサ。
[3]
前記AD変換部は、前記リセットトランジスタのドレインと電源とを接続する電源線に接続され、
前記電源線をフローティング状態にし、そのフローティング状態の前記電源線に、前記リセットトランジスタを介して、前記電荷を流入させることにより、その電荷を電圧に変換し、前記電源線に接続された前記AD変換部に供給する変換制御部をさらに備える
[1]又は[2]に記載のイメージセンサ。
[4]
前記転送トランジスタを制御することにより、前記光電変換部から前記電荷を転送させるドライバと、
前記転送トランジスタのゲートをGNDに接続する複数のノードと
をさらに備え、
前記電荷の転送を行うように、前記転送トランジスタを制御しているドライバは、前記複数ノードのうちの1のノードを使用し、
前記電荷の転送を行うように、前記転送トランジスタを制御していないドライバは、前記複数のノードのうちの他の1のノードを使用する
[3]に記載のイメージセンサ。
[5]
前記変換制御部は、
前記電源の電圧を降圧した降圧電圧を生成する降圧部を有し、
前記降圧電圧を、オン状態の前記リセットトランジスタと接続された前記電源線に印加し、その後、前記電源線をフローティング状態にする
[3]又は[4]に記載のイメージセンサ。
[6]
前記電源線を、前記降圧電圧未満の所定の電圧にクランプするクランプ部をさらに備える
[5]に記載のイメージセンサ。
[7]
前記画素ユニットは、
複数の画素を有し、
前記複数の画素で、前記リセットトランジスタを共有する
[1]ないし[6]のいずれかに記載のイメージセンサ。
[8]
色フィルタを介して入射する所定の色の光の光電変換を行う光電変換部、及び、前記光電変換部の光電変換によって得られる電荷を転送する、色ごとに制御可能な転送トランジスタを含む画素と、
AD(Analog to Digital)変換を行うAD変換部に接続され、前記電荷をリセットするリセットトランジスタと
を有する複数の画素ユニットを備えるイメージセンサの
前記転送トランジスタの制御により、前記光電変換部から前記電荷を、前記転送トランジスタ及び前記リセットトランジスタを介して読み出し、その電荷に対応する電圧を、前記リセットトランジスタに接続されている前記AD変換部に供給する
ステップを含むイメージセンサの制御方法。
Claims (8)
- 色フィルタを介して入射する所定の色の光の光電変換を行う光電変換部、及び、前記光電変換部の光電変換によって得られる電荷を転送する、色ごとに制御可能な転送トランジスタを含む画素と、
AD(Analog to Digital)変換を行うAD変換部に接続され、前記電荷をリセットするリセットトランジスタと
を有する複数の画素ユニットを備え、
前記転送トランジスタの制御により、前記光電変換部から前記電荷を、前記転送トランジスタ及び前記リセットトランジスタを介して読み出し、その電荷に対応する電圧を、前記リセットトランジスタに接続されている前記AD変換部に供給する
イメージセンサ。 - 前記転送トランジスタを、色ごとに制御することにより、前記色ごとに、前記電荷に対応する電圧を、前記AD変換部に供給する
請求項1に記載のイメージセンサ。 - 前記AD変換部は、前記リセットトランジスタのドレインと電源とを接続する電源線に接続され、
前記電源線をフローティング状態にし、そのフローティング状態の前記電源線に、前記リセットトランジスタを介して、前記電荷を流入させることにより、その電荷を電圧に変換し、前記電源線に接続された前記AD変換部に供給する変換制御部をさらに備える
請求項2に記載のイメージセンサ。 - 前記転送トランジスタを制御することにより、前記光電変換部から前記電荷を転送させるドライバと、
前記転送トランジスタのゲートをGNDに接続する複数のノードと
をさらに備え、
前記電荷の転送を行うように、前記転送トランジスタを制御しているドライバは、前記複数ノードのうちの1のノードを使用し、
前記電荷の転送を行うように、前記転送トランジスタを制御していないドライバは、前記複数のノードのうちの他の1のノードを使用する
請求項3に記載のイメージセンサ。 - 前記変換制御部は、
前記電源の電圧を降圧した降圧電圧を生成する降圧部を有し、
前記降圧電圧を、オン状態の前記リセットトランジスタと接続された前記電源線に印加し、その後、前記電源線をフローティング状態にする
請求項3に記載のイメージセンサ。 - 前記電源線を、前記降圧電圧未満の所定の電圧にクランプするクランプ部をさらに備える
請求項5に記載のイメージセンサ。 - 前記画素ユニットは、
複数の画素を有し、
前記複数の画素で、前記リセットトランジスタを共有する
請求項3に記載のイメージセンサ。 - 色フィルタを介して入射する所定の色の光の光電変換を行う光電変換部、及び、前記光電変換部の光電変換によって得られる電荷を転送する、色ごとに制御可能な転送トランジスタを含む画素と、
AD(Analog to Digital)変換を行うAD変換部に接続され、前記電荷をリセットするリセットトランジスタと
を有する複数の画素ユニットを備えるイメージセンサの
前記転送トランジスタの制御により、前記光電変換部から前記電荷を、前記転送トランジスタ及び前記リセットトランジスタを介して読み出し、その電荷に対応する電圧を、前記リセットトランジスタに接続されている前記AD変換部に供給する
ステップを含むイメージセンサの制御方法。
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CN201380021833.XA CN104247404B (zh) | 2012-05-01 | 2013-04-23 | 图像传感器以及用于图像传感器的控制方法 |
US14/395,386 US9288411B2 (en) | 2012-05-01 | 2013-04-23 | Image sensor and control method for image sensor |
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EP (1) | EP2846537B1 (ja) |
JP (1) | JP6161599B2 (ja) |
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WO2018230113A1 (ja) * | 2017-06-14 | 2018-12-20 | ソニーセミコンダクタソリューションズ株式会社 | 制御装置、及び撮像装置 |
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JPWO2013164961A1 (ja) | 2015-12-24 |
EP2846537A4 (en) | 2015-09-09 |
US20150077609A1 (en) | 2015-03-19 |
CN107743206A (zh) | 2018-02-27 |
CN104247404B (zh) | 2017-10-24 |
US20160150172A1 (en) | 2016-05-26 |
US9288411B2 (en) | 2016-03-15 |
CN107743206B (zh) | 2019-07-05 |
TW201347530A (zh) | 2013-11-16 |
JP6161599B2 (ja) | 2017-07-12 |
EP2846537A1 (en) | 2015-03-11 |
EP2846537B1 (en) | 2016-12-14 |
US9648267B2 (en) | 2017-05-09 |
TWI527450B (zh) | 2016-03-21 |
CN104247404A (zh) | 2014-12-24 |
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