WO2013095544A1 - Boîtier de circuit intégré en 3d avec interposeur à fenêtre - Google Patents

Boîtier de circuit intégré en 3d avec interposeur à fenêtre Download PDF

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Publication number
WO2013095544A1
WO2013095544A1 PCT/US2011/066983 US2011066983W WO2013095544A1 WO 2013095544 A1 WO2013095544 A1 WO 2013095544A1 US 2011066983 W US2011066983 W US 2011066983W WO 2013095544 A1 WO2013095544 A1 WO 2013095544A1
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WIPO (PCT)
Prior art keywords
semiconductor die
die
interposer
substrate
disposed
Prior art date
Application number
PCT/US2011/066983
Other languages
English (en)
Inventor
Debendra Mallik
Ram S. Viswanath
Sriram Srinivasan
Mark T. Bohr
Andrew W. YEOH
Sairam Agraharam
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to CN201180075817.XA priority Critical patent/CN104011851B/zh
Priority to PCT/US2011/066983 priority patent/WO2013095544A1/fr
Priority to US13/995,917 priority patent/US9129958B2/en
Priority to KR1020147016940A priority patent/KR101639989B1/ko
Priority to DE201111105990 priority patent/DE112011105990T5/de
Priority to JP2014548771A priority patent/JP6014907B2/ja
Priority to TW101147493A priority patent/TWI512936B/zh
Publication of WO2013095544A1 publication Critical patent/WO2013095544A1/fr
Priority to US14/813,014 priority patent/US9391013B2/en

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    • H—ELECTRICITY
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    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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Definitions

  • Embodiments of the invention are in the field of semiconductor packages and, in particular, 3D integrated circuit packages with window interposers and methods to form such semiconductor packages.
  • Semiconductor packages are used for protecting an integrated circuit (IC) chip or die, and also to provide the die with an electrical interface to external circuitry. With the increasing demand for smaller electronic devices, semiconductor packages are designed to be even more compact and must support larger circuit density.
  • C4 solder ball connections have been used for many years to provide flip chip interconnections between semiconductor devices and substrates.
  • a flip chip or Controlled Collapse Chip Connection (C4) is a type of mounting used for semiconductor devices, such as integrated circuit (IC) chips, MEMS or components, which utilizes solder bumps instead of wire bonds.
  • the solder bumps are deposited on the C4 pads, located on the top side of the substrate package. In order to mount the semiconductor device to the substrate, it is flipped over - the active side facing down on the mounting area. The solder bumps are used to connect the
  • Newer packaging approaches such as through silicon via (TSV) and silicon interposer, are gaining much attention from designers for the realization of high performance Multi-Chip Module (MCM) and System in Package (SiP).
  • MCM Multi-Chip Module
  • SiP System in Package
  • Embodiments of the present invention include 3D integrated circuit packages with window interposers and methods to form such semiconductor packages.
  • a semiconductor package includes a substrate.
  • a top semiconductor die is disposed above the substrate.
  • An interposer having a window is disposed between and interconnected to the substrate and the top semiconductor die.
  • a bottom semiconductor die is disposed in the window of the interposer and interconnected to the top semiconductor die.
  • a semiconductor package in another embodiment, includes a substrate.
  • a top semiconductor die is disposed above the substrate.
  • An interposer is disposed between and interconnected to the substrate and the top semiconductor die.
  • a bottom semiconductor die is disposed in a same plane as the interposer and interconnected to the top semiconductor die.
  • a semiconductor die pairing includes a top semiconductor die.
  • An interposer is disposed below and interconnected to the top semiconductor die.
  • a bottom semiconductor die is disposed in a same plane as the interposer, and is interconnected to the top semiconductor die.
  • Figure 1A illustrates a plan view of a 3D integrated circuit package with a window interposer, in accordance with an embodiment of the present invention.
  • Figure IB illustrates a cross-sectional view of the 3D integrated circuit package with a window interposer of Figure 1 A, in accordance with an embodiment of the present invention.
  • Figure 2 illustrates a cross-sectional view of another 3D integrated circuit package with a window interposer, in accordance with another embodiment of the present invention.
  • Figures 3A and 3B illustrate a plan view and a cross-sectional view, respectively, of a semiconductor die pairing, in accordance with an embodiment of the present invention.
  • Figures 4A and 4B illustrate a plan view and a cross-sectional view, respectively, of another semiconductor die pairing, in accordance with another embodiment of the present invention.
  • Figures 5A and 5B illustrate a plan view and a cross-sectional view, respectively, of another semiconductor die pairing, in accordance with another embodiment of the present invention.
  • Figures 6A and 6B illustrate a plan view and a cross-sectional view, respectively, of another semiconductor die pairing, in accordance with another embodiment of the present invention.
  • Figures 7A and 7B illustrate a plan view and a cross-sectional view, respectively, of another semiconductor die pairing, in accordance with another embodiment of the present invention.
  • Figures 8A and 8B illustrate a plan view and a cross-sectional view, respectively, of another semiconductor die pairing, in accordance with another embodiment of the present invention.
  • Figure 9 illustrates a process flow for a method of fabricating a 3D integrated circuit package with a window interposer, in accordance with an embodiment of the present invention.
  • Figure 10 illustrates a process flow for another method of fabricating a 3D integrated circuit package with a window interposer, in accordance with another embodiment of the present invention.
  • Figure 11 is a schematic of a computer system, in accordance with an embodiment of the present invention.
  • a window interposer for three-dimensional (3D) integrated circuit (IC) packaging.
  • a silicon interposer may be used for 3D stacking of CPU and memory as well as other devices.
  • One or more embodiments are particularly useful for 10 nanometer node and beyond and beyond products.
  • Some embodiments incorporate a silicon interposer for high density interconnect (e.g., reroute and fan out) formation.
  • the silicon interposer may be processed in a manner similar to back end of line processing for interconnect layers on a semiconductor IC die.
  • a conventional silicon interposer typically occupies a full layer below an active die. Furthermore, conventional 3D stacked ICs typically require one or more through silicon vias (TSVs) formed through one of the active die. TSV through active die is expensive. Also, in a 3D stacked IC structure, a re-distribution layer (RDL) on the back of such a bottom active die is often required to manage placement of the TSV and die-die interconnect (e.g., the LMI pad). Long RDL interconnect lines may affect high speed I/O performance. Accordingly, one or more embodiments described herein enable 3D IC stacking without TSV in any of the active die. Also, in an embodiment, a silicon interposer is include and at least one of active die layers share a same vertical plane with the interposer, saving Z height.
  • a silicon interposer is included under a top active die (T) and provides a window under the top die so that a bottom active die (B) can be directly stacked below the top die.
  • the bottom active die and the interposer reside on the same vertical level in the 3D stack structure.
  • 3D IC stacking of two active die is achieved without requiring TSV in either of the active die.
  • the interposer is attached to the package substrate by a mid-level interconnect (MLI).
  • MLI mid-level interconnect
  • the interposer includes the TSV which provide vertical electrical paths between the package substrate to the active die.
  • MLI bumps are further included on the bottom active die. Benefits of a silicon interposer, such as bump pitch transformation, passives integration, ILD protection, etc., may be maintained in the new architectures described herein.
  • the interposer material is silicon.
  • glass, organic or ceramic may be used instead or as well.
  • a silicon interposer designed and assembled in a manner to provide a window beneath a top active die for direct stacking of bottom active die to top active die
  • an interposer and a bottom active die reside on the same vertical level in a 3D stack
  • 3D IC stacking achieved without requiring TSV in any of the active die
  • TSV on bottom die is optional, and (e)
  • Figure 1A illustrates a plan view of a 3D integrated circuit package with a window interposer, in accordance with an embodiment of the present invention.
  • Figure IB illustrates a cross-sectional view of the 3D integrated circuit package with a window interposer of Figure 1 A, in accordance with an embodiment of the present invention.
  • a semiconductor package 100 (or portion of a semiconductor package) includes a substrate 102.
  • a top semiconductor die 104 is disposed above the substrate 102.
  • An interposer 106 having a window 108 is disposed between and interconnected to the substrate 102 (e.g., by mid-level interconnects (MLI) 110) and the top semiconductor die 104 (e.g., by first level interconnects (FLI) 112).
  • a bottom semiconductor die 114 is disposed in the window 108 of the interposer 106 and interconnected to the top semiconductor die 104 (e.g., by interconnects 116).
  • the bottom semiconductor die 114 has no through silicon vias (TSVs) and is not interconnected directly to the substrate 102.
  • TSVs through silicon vias
  • an active side 118 of the bottom semiconductor die 114 faces an active side 120 of the top semiconductor die 104, and away from the substrate 102.
  • the bottom semiconductor die 114 is disposed in a closed window 108 of the interposer 106, in that the window 106 completely surrounds the bottom die 114, as depicted in Figure 1A.
  • the top semiconductor die 104 completely overlaps the bottom semiconductor die 114, as is also depicted in Figure 1A.
  • a 3D package includes no TSV in an active die and involves a face-to-face arrangement of the top and bottom die.
  • window interposer 106 is composed of silicon.
  • window interposer composed of materials such as, but not limited to glass, ceramic, or organic materials.
  • the window interposer 106 may or may not include passive devices.
  • the window interposer 106 has high density interconnects, through silicon vias (TSVs) and fin pitch micro-bumps.
  • the bottom active die 114 represents an unstacked
  • the bottom die 114 is an analogue or memory device.
  • the top active die 104 represents a single chip or side by side (e.g., multi chip package (MCP))
  • the top active die 104 is of full thickness or is thinned (or includes stacked die). In an embodiment, the top die 104 is a CPU or memory device.
  • TSV through active die is expensive, at least in part due to the costs associated with creating the TSVs themselves. Furthermore, costly die area may be consumed by the TSV plus the TSV keep out zone.
  • At least some of the embodiments herein provide a TSV-free approach to 3D packaging.
  • the top semiconductor die 104 is configured to provide power to the bottom semiconductor die 114.
  • the top semiconductor die 104 is configured to facilitate communication between the bottom semiconductor die 114 and the substrate 102, e.g., through routing in the substrate 102.
  • the bottom semiconductor die 104 has no through silicon vias (TSVs).
  • TSVs through silicon vias
  • connection between the bottom die 114 and substrate 102 is achieved indirectly through interconnect lines on the top die 104 as well as the interposer 106.
  • bottom and top active die are stacked face-to-face. It is to be understood, however, that, in an alternative embodiment, a bottom die may be connected directly by using TSV on the bottom die, as described in greater details below in association with Figure 2.
  • One or both of the semiconductor die 104 or 114 may be formed from a semiconductor substrate, such as a single crystalline silicon substrate. Other materials, such as, but not limited to, group ⁇ -V material and germanium or silicon germanium material substrates may also be considered.
  • the active side (120 or 118, respectively) of the semiconductor die 104 or 114 may be the side upon which semiconductor devices are formed. In an embodiment, the active side 120 or 118 of the semiconductor die 104 or 114, respectively, includes a plurality of
  • semiconductor devices such as but not limited to transistors, capacitors and resistors interconnected together by a die interconnection structure into functional circuits to thereby form an integrated circuit.
  • the device side of the semiconductor die includes an active portion with integrated circuitry and interconnections.
  • the semiconductor die may be any appropriate integrated circuit device including but not limited to a microprocessor (single or multi-core), a memory device, a chipset, a graphics device, an application specific integrated circuit according to several different embodiments.
  • Stacked die apparatus 100 may be particularly suitable for packaging a memory die with a logic die.
  • one of die 104 or 114 is a memory die.
  • the other die is a logic die.
  • the memory die is a memory device, such as but not limited to a static random access memory (SRAM), a dynamic access memory (DRAM), a nonvolatile memory (NVM) and the logic die is a logic device, such as but not limited to a microprocessor and a digital signal processor.
  • SRAM static random access memory
  • DRAM dynamic access memory
  • NVM nonvolatile memory
  • the logic die is a logic device, such as but not limited to a microprocessor and a digital signal processor.
  • one or more of die interconnect structures 112 or 116 or interposer 106 to substrate 102 interconnect structures 110 is composed of an array of metal bumps.
  • each metal bump is composed of a metal such as, but not limited to, copper, gold, or nickel.
  • Substrate 102 may be a flexible substrate or a rigid substrate, depending upon the specific application.
  • substrate 102 has a plurality of electrical traces disposed therein.
  • an external contact layer is also formed.
  • the external contact layer includes a ball grid array (BGA).
  • the external contact layer includes an array such as, but not limited to, a land grid array (LGA) or an array of pins (PGA).
  • the solder balls are used and are composed of lead or are lead free, such as alloys of gold and tin solder or silver and tin solder.
  • Figure 2 illustrates a cross-sectional view of another 3D integrated circuit package with a window interposer, in accordance with another embodiment of the present invention.
  • a semiconductor package 200 (or portion of a semiconductor package) includes a substrate 202.
  • a top semiconductor die 204 is disposed above the substrate 202.
  • An interposer 206 having a window 208 is disposed between and interconnected to the substrate 202 (e.g., by mid-level interconnects (MLI) 210) and the top semiconductor die 204 (e.g., by first level interconnects (FLI) 212).
  • a bottom semiconductor die 214 is disposed in the window 208 of the interposer 206 and interconnected to the top semiconductor die 204 (e.g., by interconnects 216).
  • the bottom semiconductor die 214 has through silicon vias (TSVs) 250 and is interconnected directly to the substrate 202, e.g., by interconnects 252. As such, an active side 218 of the bottom semiconductor die 214 faces away from an active side 220 of the top semiconductor die 204, and toward the substrate 202.
  • the bottom semiconductor die 214 is disposed in a closed window 208 of the interposer 206, in that the window 206 completely surrounds the bottom die 214.
  • the top semiconductor die 204 completely overlaps the bottom semiconductor die 214.
  • a 3D package includes a bottom die with TSV and MLI and a face to back orientation with respect to a top die. The characteristics and configurations of the packaged die and the materials of package 200 may be the same or similar to those described above for package 100.
  • a window-interposer is included in a 3D stacked IC package.
  • the interposer provides a window under a top active die for 3D stacking of top and bottom active die.
  • Figures 3A/3B, 4A/B, 5A/B, 6A/B, 7A/B and 8A/B illustrate various embodiments of stacked IC top and bottom die pairings with window interposers.
  • the pairings may ultimately be packaged on a substrate, as described in greater detail below in association with Figure 9.
  • FIGS. 3A and 3B illustrate a plan view and a cross-sectional view, respectively, of a semiconductor die pairing, in accordance with an embodiment of the present invention.
  • a semiconductor die pairing 300 includes a top semiconductor die 304.
  • An interposer 306 is disposed below and interconnected to the top semiconductor die 304 (e.g., by first level interconnects (FLI) 312).
  • a bottom semiconductor die 314 is disposed in a same plane as the interposer 306, and is interconnected to the top semiconductor die 304 (e.g., by interconnects 316).
  • the bottom semiconductor die 314 is disposed in a closed window 308 of the interposer 306.
  • the top semiconductor die 304 completely overlaps the bottom semiconductor die 314, as depicted in Figure 3A.
  • the characteristics and configurations of the die and the materials of die pairing 300 may be the same or similar to those described above for the die pairings of packages 100 or 200.
  • Figures 4A and 4B illustrate a plan view and a cross-sectional view, respectively, of another semiconductor die pairing, in accordance with another embodiment of the present invention.
  • a semiconductor die pairing 400 includes a top semiconductor die 404.
  • An interposer 406 is disposed below and interconnected to the top semiconductor die 404 (e.g., by first level interconnects (FLI) 412).
  • FLI first level interconnects
  • Four bottom semiconductor die 414, 460, 462 and 464 are disposed in a same plane as the interposer 406, and are interconnected to the top semiconductor die 404 (e.g., by interconnects 416).
  • the bottom semiconductor die 414, 460, 462 and 464 are each disposed in a respective closed window 408, 470, 472 and 474 of the interposer 406.
  • the top semiconductor die 404 completely overlaps the bottom semiconductor die 414, 460, 462 and 464, as depicted in Figure 4A.
  • the characteristics and configurations of the die and the materials of die pairing 400 may be the same or similar to those described above for the die pairings of packages 100 or 200.
  • FIGS. 5A and 5B illustrate a plan view and a cross-sectional view, respectively, of another semiconductor die pairing, in accordance with another embodiment of the present invention.
  • a semiconductor die pairing 500 includes a top semiconductor die 504.
  • An interposer 506 is disposed below and interconnected to the top semiconductor die 504 (e.g., by first level interconnects (FLI) 512).
  • a bottom semiconductor die 514 is disposed in a same plane as the interposer 506, and is interconnected to the top semiconductor die 504 (e.g., by interconnects 516).
  • the bottom semiconductor die 514 is disposed in an open window 508 of the interposer 506.
  • the top semiconductor die 504 only partially overlaps the bottom semiconductor die 514, as depicted in Figure 5A.
  • the bottom die is larger than the top die.
  • the characteristics and configurations of the die and the materials of die pairing 500 may be the same or similar to those described above for the die pairings of packages 100 or 200.
  • FIG. 6A and 6B illustrate a plan view and a cross-sectional view, respectively, of another semiconductor die pairing, in accordance with another embodiment of the present invention.
  • a semiconductor die pairing 600 includes a top semiconductor die 604.
  • An interposer 606 is disposed below and interconnected to the top semiconductor die 604 (e.g., by first level interconnects (FLI) 612).
  • a bottom semiconductor die 614 is disposed in a same plane as the interposer 606, and is interconnected to the top semiconductor die 604 (e.g., by interconnects 616).
  • the bottom semiconductor die 614 is disposed in a closed window 608 of the interposer 606.
  • One or more additional top semiconductor die 680 is included and disposed in a same plane as the top semiconductor die 604, and interconnected to the interposer (e.g., by first level interconnects (FLI) 613).
  • the top semiconductor die 604 completely overlaps the bottom semiconductor die 614, as depicted in Figure 6A.
  • the characteristics and configurations of the die and the materials of die pairing 600 may be the same or similar to those described above for the die pairings of packages 100 or 200.
  • a multiple-component interposer with a closed window is included.
  • Figures 7A and 7B illustrate a plan view and a cross-sectional view, respectively, of another
  • a semiconductor die pairing 700 includes a top semiconductor die 704.
  • An interposer 706 is disposed below and interconnected to the top semiconductor die 704 (e.g., by first level interconnects (FLI) 712).
  • the interposer 706 is composed of two or more discrete units (in this case, the four discrete units 706 A, 706B, 706C, and 707D).
  • semiconductor die 714 is disposed in a same plane as the interposer 706, and is interconnected to the top semiconductor die 704 (e.g., by interconnects 716).
  • the bottom semiconductor die 714 is disposed in a closed window 708 of the interposer 706.
  • the bottom semiconductor die 714 is disposed in a closed window 708 of the two or more discrete units (in this case, the four discrete units 706A, 706B, 706C, and 707D) of the interposer 706.
  • the top semiconductor die 704 completely overlaps the bottom semiconductor die 714, as depicted in Figure 7A.
  • the characteristics and configurations of the die and the materials of die pairing 700 may be the same or similar to those described above for the die pairings of packages 100 or 200.
  • a bottom die is included side by side, in the same plane, with an interposer.
  • Figures 8A and 8B illustrate a plan view and a cross- sectional view, respectively, of another semiconductor die pairing, in accordance with another embodiment of the present invention.
  • a semiconductor die pairing 800 includes a top semiconductor die 804.
  • An interposer 806 is disposed below and interconnected to the top semiconductor die 804 (e.g., by first level interconnects (FLI) 812).
  • a bottom semiconductor die 814 is disposed in a same plane as the interposer 806, and is interconnected to the top semiconductor die 804 (e.g., by interconnects 816).
  • the bottom semiconductor die 814 is disposed adjacent to, but not within, the interposer 806.
  • the top semiconductor die 804 only partially overlaps the bottom semiconductor die 814, as depicted in Figures 8A and 8B.
  • the characteristics and configurations of the die and the materials of die pairing 800 may be the same or similar to those described above for the die pairings of packages 100 or 200.
  • the respective bottom semiconductor die of each pairing has no through silicon vias (TSVs).
  • an active side of the bottom semiconductor die faces an active side of the top semiconductor die.
  • the respective bottom semiconductor die of each pairing has through silicon vias (TSVs).
  • an active side of the bottom semiconductor die faces away from an active side of the top semiconductor die.
  • Figure 9 illustrates a process flow 900 for a method of fabricating a 3D integrated circuit package with a window interposer, in accordance with an embodiment of the present invention.
  • a top die 902 portion of the flow includes providing a top die in a tape and reel format 910.
  • a bottom die 904 portion of the flow includes providing a bottom die in a tape and reel format 912.
  • Thermal compression bonding (TCB) is then used to stack the bottom die on the top die 914.
  • a window interposer 906 portion of the flow may include providing an interposer with a window and, possibly with TSVs, mid-level interconnect (MLI) bumps and first level interconnect (FLI) pads.
  • an interposer such as a silicon interposer
  • RDL re-distribution layer
  • Laser and/or water jet cutting may be used to provide a window.
  • the stack from 914 is bonded (e.g., by TCB) with the interposer.
  • a package substrate 908 portion of flow includes providing a package substrate, e.g., on a tray as in 920.
  • by CAM and/or copper underfill (CUF) of mid-level interconnects (MLI) on the window interposer is used to couple the die pairing with the window interposer on a package substrate.
  • CCF copper underfill
  • MLI mid-level interconnects
  • FLI is formed first by 3D stacking of bottom die, top die, and window interposer first, then MLI is used to attach the pairing to a package substrate.
  • the bottom die may or may not have MLI bumps.
  • the window interposer may be composed of multiple pieces. Also, additional die may be included in the pairing.
  • a die pairing including an interposer may be fabricated as a portion of a packaging process. Any of a variety of multiple die pairings including an interposer may then be coupled to a package substrate, as described in association with Figure 9.
  • a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer having a window is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in the window of the interposer and interconnected to the top semiconductor die.
  • the bottom semiconductor die is disposed in a closed window of the interposer, as described in association with Figures 3A and 3B.
  • the top semiconductor die completely overlaps the bottom semiconductor die, as is also described in association with Figures 3 A and 3B.
  • one or more additional bottom semiconductor die is included.
  • the one or more additional bottom semiconductor die is disposed in one or more additional closed windows of the interposer, as described in association with Figures 4A and 4B.
  • the top semiconductor die completely overlaps the bottom semiconductor die as well as the one or more additional bottom semiconductor die, as is also described in association with Figures 4A and 4B.
  • the bottom semiconductor die is disposed in an open window of the interposer, as described in association with Figures 5 A and 5B.
  • the top semiconductor die only partially overlaps the bottom semiconductor die, as is also described in association with Figures 5 A and 5B.
  • the one or more additional top semiconductor die is disposed above the substrate in a same plane as the top semiconductor die and is interconnected to the interposer, as described in association with Figures 6A and 6B.
  • the top semiconductor die completely overlaps the bottom semiconductor die, as is also described in association with Figures 6A and 6B.
  • the interposer is composed of two or more discrete units.
  • the bottom semiconductor die is disposed in a closed window of the two or more discrete units of the interposer, as described in association with Figures 7 A and 7B.
  • the top semiconductor die completely overlaps the bottom semiconductor die, as is also described in association with Figures 7 A and 7B.
  • a semiconductor package in another embodiment, includes a substrate.
  • a top semiconductor die is disposed above the substrate.
  • An interposer is disposed between and interconnected to the substrate and the top semiconductor die.
  • a bottom semiconductor die is disposed in a same plane as the interposer and interconnected to the top semiconductor die.
  • the bottom semiconductor die is disposed adjacent to, but not within, the interposer, as described in association with Figures 8 A and 8B.
  • the top semiconductor die only partially overlaps the bottom semiconductor die, as is also described in association with Figures 8 A and 8B.
  • the bottom semiconductor die has no through silicon vias (TSVs) and is not interconnected directly to the substrate.
  • an active side of the bottom semiconductor die faces an active side of the top semiconductor die, and away from the substrate.
  • the bottom semiconductor die has through silicon vias (TSVs) and is interconnected directly to the substrate.
  • an active side of the bottom semiconductor die faces away from an active side of the top semiconductor die, and toward the substrate.
  • Figure 10 illustrates a process flow 1000 for another method of fabricating a 3D integrated circuit package with a window interposer, in accordance with another embodiment of the present invention.
  • a top die 1002 portion of the flow includes providing a top die in a tape and reel format 1010.
  • a bottom die 1004 portion of the flow includes providing a bottom die in a tape and reel format 1012.
  • Thermal compression bonding (TCB) is then used to stack the bottom die on the top die 1014.
  • a window interposer 1006 portion of the flow may include providing an interposer with a window and, possibly with TSVs, mid-level interconnect (MLI) bumps and first level interconnect (FLI) pads.
  • an interposer such as a silicon interposer
  • RDL re-distribution layer
  • a package substrate 1008 portion of flow includes providing a package substrate, e.g., on a tray as in 1018.
  • the window interposer from 1016 is bonded (e.g., by TCB or CAM/CUF) with the substrate.
  • the stack from 1014 is bonded with the interposer/substrate combination (from 1020), e.g., by TCB or CAM and/or CUF.
  • MLI is formed first. It is to be understood that the bottom die may or may not have MLI bumps.
  • the window interposer may be composed of multiple pieces. Also, additional die may be included in the pairing.
  • Optimum options may depend on desired dimensional features such as relative die sizes for stack, overhang size, process reuse, etc.
  • top die thermal management includes the use of features such as, but not limited to, a heat sink or an integrated heat spreader (HIS) attached directly to the back of the top die.
  • HIS integrated heat spreader
  • Embodiments described herein may enable 3D IC packaging without requiring TSV in the active die. Furthermore, traditional benefits of a silicon interposer may be maintained.
  • first level interconnect (FLI) pitch transformation to a looser mid-level interconnect (MLI) pitch is performed for lower cost packaging and assembly technology.
  • passives component e.g., capacitors, resistors, or inductors
  • ILD active die interlayer dielectric
  • MLI multi-level interconnect
  • FLI bump pitch for the bottom die and window interposer is different, e.g., a finer pitch is used for bottom die/top die FLI (e.g., approximately 40 microns pitch) for high bandwidth and a looser pitch is used for window interposer/ top die FLI (e.g., approximately 90 microns pitch) for expected larger area for the FLI.
  • this approach creates a bimodal bump height distribution on the top die.
  • the bimodal bump height distribution may be manageable as the bottom die and the window interposer are independently attached to the corresponding top die.
  • solder on die for the top die or the bottom die/window interposer layer is used.
  • FLI underfill options include, but are not limited to, (a) WLUF on the top die, (b) window interposer and bottom die EF-TCB, (c) copper underfill (CUF), or (d) MUF.
  • One or more embodiments described herein may enable stacking various high bandwidth memory such as JEDEC Wide I/O memory, various other small devices under the CPU (or for that matter any other logic die).
  • use of the silicon interposer helps in reducing die size and package cost.
  • logic chips with I/O count growth due to memory bandwidth and/or due to new features such as in SoC are accommodated.
  • One or more embodiments of the present invention provide 3D IC stacking such as low cost CPU and memory stacking to meet high product performance at low power.
  • stacking of a CPU and eDRAM without TSV on active die is enabled and aids in achieving lower cost.
  • a silicon interposer is used to manage high I/O density on a logic die.
  • embodiments may be targeted at 3D IC stacking work to add memory on CPU/GPU.
  • an interposer is combined with a 3D IC in a cost effective way and enabled 3D stacking of active die using a silicon interposer without having TSV in an active die.
  • FIG 11 is a schematic of a computer system 1100, in accordance with an embodiment of the present invention.
  • the computer system 1100 (also referred to as the electronic system 1100) as depicted can embody a 3D integrated circuit packages with a window interposer according to any of the several disclosed embodiments and their equivalents as set forth in this disclosure.
  • the computer system 1100 may be a mobile device such as a netbook computer.
  • the computer system 1100 may be a mobile device such as a wireless smart phone.
  • the computer system 1100 may be a desktop computer.
  • the computer system 1100 may be a hand-held reader.
  • the electronic system 1100 is a computer system that includes a system bus 1120 to electrically couple the various components of the electronic system 1100.
  • the system bus 1120 is a single bus or any combination of busses according to various embodiments.
  • the electronic system 1100 includes a voltage source 1130 that provides power to the integrated circuit 1110. In some embodiments, the voltage source 1130 supplies current to the integrated circuit 1110 through the system bus 1120.
  • the integrated circuit 1110 is electrically coupled to the system bus
  • 1120 includes any circuit, or combination of circuits according to an
  • the integrated circuit 1110 includes a processor
  • the processor 1112 may mean any type of circuit such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor, or another processor.
  • the processor 1112 is a 3D integrated circuit package with a window interposer disclosed herein.
  • SRAM embodiments are found in memory caches of the processor.
  • Other types of circuits that can be included in the integrated circuit 1110 are a custom circuit or an application-specific integrated circuit (ASIC), such as a communications circuit 1114 for use in wireless devices such as cellular telephones, smart phones, pagers, portable computers, two-way radios, and similar electronic systems.
  • the processor 1110 includes on-die memory 1116 such as static random- access memory (SRAM).
  • the processor 1110 includes embedded on-die memory 1116 such as embedded dynamic random- access memory (eDRAM).
  • the integrated circuit 1110 is complemented with a subsequent integrated circuit 1111.
  • Useful embodiments include a dual processor
  • the dual integrated circuit 1110 includes embedded on- die memory 1117 such as eDRAM.
  • the electronic system 1100 also includes an external memory 1140 that in turn may include one or more memory elements suitable to the particular application, such as a main memory 1142 in the form of RAM, one or more hard drives 1144, and/or one or more drives that handle removable media 1146, such as diskettes, compact disks (CDs), digital variable disks (DVDs), flash memory drives, and other removable media known in the art.
  • the external memory 1140 may also be embedded memory 1148 such as a in a 3D integrated circuit package with a window interposer, according to an embodiment.
  • the electronic system 1100 also includes a display device 1150, an audio output 1160.
  • the electronic system 1100 includes an input device such as a controller 1170 that may be a keyboard, mouse, trackball, game controller, microphone, voice-recognition device, or any other input device that inputs information into the electronic system 1100.
  • an input device 1170 is a camera.
  • an input device 1170 is a digital sound recorder.
  • an input device 1170 is a camera and a digital sound recorder.
  • the integrated circuit 1110 can be implemented in a number of different embodiments, including a 3D integrated circuit package with a window interposer according to any of the several disclosed embodiments and their equivalents, an electronic system, a computer system, one or more methods of fabricating an integrated circuit, and one or more methods of fabricating an electronic assembly that includes a 3D integrated circuit package with a window interposer according to any of the several disclosed embodiments as set forth herein in the various embodiments and their art-recognized equivalents.
  • the elements, materials, geometries, dimensions, and sequence of operations can all be varied to suit particular I/O coupling requirements including array contact count, array contact configuration for a microelectronic die embedded in a processor mounting substrate according to any of the several disclosed 3D integrated circuit package with a window interposer embodiments and their equivalents.
  • a semiconductor package includes a substrate.
  • a top semiconductor die is disposed above the substrate.
  • An interposer having a window is disposed between and interconnected to the substrate and the top semiconductor die.
  • a bottom semiconductor die is disposed in the window of the interposer and interconnected to the top semiconductor die.
  • semiconductor package includes a substrate.
  • a top semiconductor die is disposed above the substrate.
  • An interposer is disposed between and interconnected to the substrate and the top semiconductor die.
  • a bottom semiconductor die is disposed in a same plane as the interposer and interconnected to the top semiconductor die.

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Abstract

L'invention concerne des boîtiers de circuit intégré en 3D avec des interposeurs à fenêtre et des procédés de formation de tels boîtiers de semi-conducteurs. Par exemple, un boîtier de semi-conducteur comprend un substrat. Une puce semi-conductrice supérieure est disposée au-dessus du substrat. Un interposeur possédant une fenêtre est disposé et interconnecté au substrat et à la puce semi-conductrice supérieure. Une puce semi-conductrice inférieure est disposée dans la fenêtre de l'interposeur et interconnectée à la puce semi-conductrice supérieure. Dans un autre exemple, le boîtier de semi-conducteur comprend un substrat. Une puce semi-conductrice supérieure est disposée au-dessus du substrat. Un interposeur est disposé entre et interconnecté au substrat et à la puce semi-conductrice supérieure. Une puce semi-conductrice inférieure est disposée dans le même plan que l'interposeur et interconnectée à la puce semi-conductrice supérieure.
PCT/US2011/066983 2011-12-22 2011-12-22 Boîtier de circuit intégré en 3d avec interposeur à fenêtre WO2013095544A1 (fr)

Priority Applications (8)

Application Number Priority Date Filing Date Title
CN201180075817.XA CN104011851B (zh) 2011-12-22 2011-12-22 具有窗口插入器的3d集成电路封装
PCT/US2011/066983 WO2013095544A1 (fr) 2011-12-22 2011-12-22 Boîtier de circuit intégré en 3d avec interposeur à fenêtre
US13/995,917 US9129958B2 (en) 2011-12-22 2011-12-22 3D integrated circuit package with window interposer
KR1020147016940A KR101639989B1 (ko) 2011-12-22 2011-12-22 윈도우 인터포저를 갖는 3d 집적 회로 패키지
DE201111105990 DE112011105990T5 (de) 2011-12-22 2011-12-22 Integriertes 3D-Schaltungspaket mit Fensterinterposer
JP2014548771A JP6014907B2 (ja) 2011-12-22 2011-12-22 ウィンドウインタポーザを有する３ｄ集積回路パッケージ
TW101147493A TWI512936B (zh) 2011-12-22 2012-12-14 具有視窗中介層的３ｄ積體電路封裝
US14/813,014 US9391013B2 (en) 2011-12-22 2015-07-29 3D integrated circuit package with window interposer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2011/066983 WO2013095544A1 (fr) 2011-12-22 2011-12-22 Boîtier de circuit intégré en 3d avec interposeur à fenêtre

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US13/995,917 A-371-Of-International US9129958B2 (en) 2011-12-22 2011-12-22 3D integrated circuit package with window interposer
US14/813,014 Continuation US9391013B2 (en) 2011-12-22 2015-07-29 3D integrated circuit package with window interposer

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JP (1) JP6014907B2 (fr)
KR (1) KR101639989B1 (fr)
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DE (1) DE112011105990T5 (fr)
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US20140191419A1 (en) 2014-07-10
US9129958B2 (en) 2015-09-08
TWI512936B (zh) 2015-12-11
KR20140098160A (ko) 2014-08-07
US9391013B2 (en) 2016-07-12
CN104011851B (zh) 2017-06-27
DE112011105990T5 (de) 2014-09-11
TW201342570A (zh) 2013-10-16
CN104011851A (zh) 2014-08-27

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