WO2013084947A1 - 光センサ回路の動作方法、および、当該光センサ回路を備えた表示装置の動作方法 - Google Patents
光センサ回路の動作方法、および、当該光センサ回路を備えた表示装置の動作方法 Download PDFInfo
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- WO2013084947A1 WO2013084947A1 PCT/JP2012/081526 JP2012081526W WO2013084947A1 WO 2013084947 A1 WO2013084947 A1 WO 2013084947A1 JP 2012081526 W JP2012081526 W JP 2012081526W WO 2013084947 A1 WO2013084947 A1 WO 2013084947A1
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- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0416—Control or interface arrangements specially adapted for digitisers
- G06F3/0418—Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J1/00—Photometry, e.g. photographic exposure meter
- G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
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- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0412—Digitisers structurally integrated in a display
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/042—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by opto-electronic means
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- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J1/00—Photometry, e.g. photographic exposure meter
- G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
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- G01J1/00—Photometry, e.g. photographic exposure meter
- G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
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- G01J2001/4446—Type of detector
- G01J2001/446—Photodiode
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
- G02F1/13312—Circuits comprising photodetectors for purposes other than feedback
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- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0237—Switching ON and OFF the backlight within one frame
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2360/00—Aspects of the architecture of display systems
- G09G2360/14—Detecting light within display terminals, e.g. using a single or a plurality of photosensors
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier
- H01L31/105—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PIN type
Definitions
- the present invention relates to an operation method of an optical sensor circuit using a photodiode, for example, an operation method of an optical sensor circuit mounted on a display device.
- a touch panel function and a function for maintaining and improving display quality are realized by mounting an optical sensor circuit on a display unit of a display device such as a liquid crystal display device or an organic EL display device.
- FIG. 27 is a diagram illustrating a configuration of the display device disclosed in Patent Document 1.
- FIG. 27 includes a video signal output circuit 152, a display unit 153, a writing scanning circuit 154, a sensor scanning circuit 155, and a sensor output detection circuit 156.
- the display unit 153 pixel circuits 121 1,1 to 121 N, M are arranged in a matrix, and the light receiving circuit 161 serving as an optical sensor circuit is arranged in one-to-one correspondence with the pixel circuit 121. 1,1 to 61 N, M are arranged in a matrix. As shown in FIG.
- the light receiving circuit 161 includes a sensor transistor T SE , a holding capacitor Cse, an output transistor T OUT by an n-channel TFT, and a read transistor T RS , and the light is received when the sensor transistor T SE is off. Functions as a sensor. That is, when the sensor transistor TSE is off, a leak current corresponding to the amount of received light flows to the gate of the output transistor TOUT .
- the sensor transistor TSE has a characteristic that when it is off, the leakage current increases or decreases according to the amount of received light. That is, if the amount of received light is large, the increase amount of the leakage current is large, and if it is small, the increase amount of the leakage current is small.
- the light detection circuit 161 outputs a light detection signal corresponding to the amount of received light via the sensor output line SOL.
- FIG. 29 A structure of a liquid crystal display device having the structure is shown in FIG.
- the liquid crystal display device shown in FIG. 29 includes a PIN diode 204, a thin film transistor (TFT) 206 for holding data, a storage capacitor Cint, and a light shielding film 210.
- TFT thin film transistor
- the TFT 206 is a TFT 206 that holds an electrical signal output from the PIN diode 204 as data, and is connected in proximity to the PIN diode 204.
- the light shielding film 210 is formed in the vicinity of the PIN diode 204 and the TFT 206 so as to shield light incident on the PIN diode 204 and the TFT 206 from the backlight. Further, a potential change due to charging of the storage capacitor Cint can be taken out as a sensor output.
- the light shielding film 210 blocks light directly incident from the backlight of the PIN diode 204 and prevents an OFF leak current due to light entering the TFT 206 and generating carriers.
- an optical sensor circuit configured using a photodiode
- the optical sensor circuit when the optical sensor circuit is driven (operated) in an environment where the amount of incident light exceeds a predetermined amount, the incident light is incident on the anode terminal and the cathode terminal of the photodiode.
- the potential of the terminal whose potential changes according to the amount of light causes a large shift to the extent that induces carriers in the intrinsic region (intrinsic region) of the photodiode with respect to the potential of the light shielding layer.
- the carriers accumulated in the intrinsic region do not completely disappear from the intrinsic region even in the reset process performed immediately before sensing, and cause a change in the photocurrent, which is the original data, during sensing following the reset process. .
- the present invention has been made in view of the above problems, and an object of the present invention is to perform accurate sensing of an optical sensor circuit using a photodiode without accumulating carriers in the intrinsic region of the photodiode. It is an object of the present invention to provide a method for operating an optical sensor circuit capable of performing the above and a method for operating a display device including the optical sensor circuit.
- an operation method of the optical sensor circuit according to the present invention is as follows.
- a light-shielding film formed in the vicinity of the optical sensor circuit Sensing incident light at regular intervals using the PIN diode, and performing this reset prior to each sensing, Between a certain main reset and the subsequent main reset, the potential immediately before the main reset of the terminal whose potential changes according to the amount of incident light of the anode terminal and the cathode terminal of the PIN diode is An auxiliary reset is performed so as to suppress the accumulation of carriers in the intrinsic region of the PIN diode within a predetermined range.
- the operation method of the photosensor circuit according to the present invention includes a PIN diode, a thin film transistor connected in proximity to the PIN diode and holding an electric signal output from the PIN diode as data, and a PIN diode from a certain direction.
- An optical sensor circuit operating method comprising at least a light-shielding film formed close to the PIN diode so as to shield incident light, and sensing the incident light using the PIN diode at a constant interval
- Each reset is performed prior to each sensing, and the incident light quantity of the anode terminal and the cathode terminal of the PIN diode is changed between the certain reset and the subsequent reset.
- the potential of the terminal whose potential changes changes the key to the intrinsic region of the PIN diode. It is characterized by performing the auxiliary reset so suppressed within a predetermined range that does not induce rear storage.
- FIG. 2 is a schematic diagram of a PIN diode mounted on an optical sensor circuit provided in the display unit shown in FIG. 1.
- FIG. 4 is a graph showing IV characteristics of the PIN diode shown in FIG. 2. It is a figure explaining the potential (mode A) of the intrinsic area
- FIG. 1 A circuit diagram showing a configuration of the photosensor circuit shown in FIG. 1, and (b) a timing chart when the photosensor circuit is operated in one mode of the operation method according to the present invention. It is a circuit diagram which shows the structure of the optical sensor circuit shown in FIG. It is a figure of the timing chart in the case of making it operate
- FIG. 17 is a timing chart when the amount of incident light is small when the optical sensor circuit shown in FIG. 16 is operated by a general operation method.
- FIG. 17 is a timing chart when the amount of incident light is large when the optical sensor circuit shown in FIG. 16 is operated by a general operation method. It is a figure which shows the problem at the time of making it operate
- FIG. 17 is a timing chart when the optical sensor circuit shown in FIG. 16 is operated in another mode of the operation method according to the present invention. It is a figure of the timing chart in the case of making it operate
- FIG. 25 is a timing chart showing the operation of the liquid crystal display device shown in FIG. It is the figure which showed the outline
- FIG. 1 is a diagram illustrating an in-pixel circuit configuration of a display unit of a liquid crystal display device.
- the liquid crystal display device is an active matrix display device, and includes a display unit 1, a gate driver as a scanning signal line driving circuit, a source driver as a data signal line driving circuit, an auxiliary capacitance wiring driving circuit, A gate driver, a source driver, an auxiliary capacitance wiring drive circuit, and an external drive circuit for driving and controlling the common electrode.
- This liquid crystal display device performs gate line inversion driving as AC driving.
- the display unit 1 includes a gate line GL as a plurality (n) of scanning signal lines, a source line SL as a plurality (m) of data signal lines intersecting with each of the gate lines GL, and a gate line GL. And a plurality of (n ⁇ m) picture elements PIX provided corresponding to the respective intersections of the source line SL and the auxiliary capacitance line CsL in parallel with the gate line GL, which are arranged in this direction.
- One auxiliary capacitance line CsL is allocated to each picture element row composed of m picture elements PIX.
- each picture element PIX includes a pixel TFT 21, a liquid crystal capacitor CL, and an auxiliary capacitor Cs.
- the gate of the pixel TFT 21 is connected to the gate line GL
- the source is connected to the source line SL
- the drain is connected to the pixel electrode.
- the liquid crystal capacitor CL is a capacitor in which a liquid crystal layer is disposed between a picture element electrode and a common electrode.
- the auxiliary capacitor Cs is a capacitor in which an insulating film is disposed between the pixel electrode and the auxiliary capacitor line CsL.
- a common potential generated by a power supply circuit provided in the external drive circuit is applied to the common electrode.
- the auxiliary capacitance line CsL includes a high level voltage and a low level voltage generated by a power supply circuit included in the external drive circuit and supplied to the auxiliary capacitance line drive circuit.
- the auxiliary capacitance potential generated is applied.
- the liquid crystal capacitor CL and the auxiliary capacitor Cs constitute a picture element capacity.
- As other capacity constituting the picture element capacity a parasitic capacity formed between the picture element electrode and the gate line GL, a common electrode, There are a parasitic capacitance formed between the source line SL and a parasitic capacitance formed between the auxiliary capacitance line CsL and the source line SL.
- Each pixel is provided with a photosensor circuit adjacent to the display circuit.
- one photosensor circuit 11 is provided for one display circuit 12 (one pixel) from three picture elements PIX of red (R), green (G), and blue (B). .
- R red
- G green
- B blue
- a drive circuit that receives and processes the output from the photosensor circuit 11 is mounted on the above-described liquid crystal display device. Note that this drive circuit may be formed on an FPC mounted on a liquid crystal display device or on an external substrate.
- the optical sensor circuit 11 includes a PIN diode 4, a data holding TFT 6 (thin film transistor), a storage capacitor Cint, a data writing TFT 9, and a light shielding layer 10.
- the PIN diode 4 has an anode terminal connected to the reset scanning line RST and a cathode terminal connected to the source of the data holding TFT 6, and the potential of the cathode terminal varies depending on the charge generated according to the amount of incident light.
- the electric charge is output from the PIN diode 4 as an electric signal and is held by the data holding TFT 6.
- the data holding TFT 6 has its source connected to the cathode terminal of the PIN diode 4, its gate connected to the signal line CLK that supplies the on / off signal of the data holding TFT 6, and its drain connected to the storage capacitor Cint. ing.
- the storage capacitor Cint is connected to the data holding TFT 6 and is provided to hold the electric charge held in the data holding TFT 6.
- the storage capacitor Cint is connected to the write signal line RW.
- the data writing TFT 9 has its gate connected to the data holding TFT 6 and the storage capacitor Cint.
- the data writing TFT 9 has its source connected to the power supply wiring VDD and its drain connected to the photosensor output line OUT.
- the power supply wiring VDD and the photosensor output line OUT are configured using the source line SL of the display circuit.
- the source of the data writing TFT 9 is connected to a power source and is designed to always operate in the saturation region. In the saturation region, the drain current of the data writing TFT 9 is controlled by the gate-source voltage. Therefore, when the storage capacitor Cint receives a write signal from the write signal line RW, the gate application voltage of the data write TFT 9 is changed and output in accordance with the storage node voltage.
- the light shielding layer 10 is formed close to the PIN diode 4 and the TFT 6 so as to shield light incident on the PIN diode 4 and the TFT 6 from a backlight provided as a light source device on the back surface of the display circuit.
- the light shielding layer 10 shields light directly incident from the backlight in the PIN diode 4 and can prevent an OFF leak current due to light entering the TFT 6 and generating carriers. That is, the OFF current during the data retention period of the TFT 6 can be reduced.
- the light shielding layer 10 and the PIN diode 4 will be described in detail with reference to FIG. It can be said that the light shielding layer 10 and the PIN diode 4 constitute a photodiode.
- the lowermost layer of the photodiode has a conductive light shielding layer 10 that blocks light incident from the back surface. 10 is connected to the light shielding layer fixed voltage Vls.
- a PIN diode 4 as a semiconductor layer made of a PIN junction is formed on the light shielding layer 10 with an insulating layer interposed therebetween.
- FIG. 3 is a graph showing the photodiode IV characteristics.
- the bias Vac applied to the photodiode changes from positive to negative, a reverse current starts to flow through the photodiode (region (C) in FIG. 3). It becomes substantially constant with respect to the bias Vac after exceeding a certain predetermined voltage V1 (region (B) in FIG. 3).
- of the bias Vac is further increased (greater than or equal to
- the area (B) in FIG. 3 is used.
- PIN Diode Operation Mode The potential of each region of the PIN diode 4 is determined by the applied voltages Va, Vc, Vls, and the inversion thresholds Vth_n and Vth_p in the intrinsic region of the PIN diode 4.
- Va, Vc, Vls, and the inversion thresholds Vth_n and Vth_p the potential relationship of each region and the intrinsic region of the PIN diode 4 will be described separately for three modes A, B, and C.
- FIG. 4 is a diagram for explaining the mode A.
- Va, Vc, Vls, Vth_n, and Vth_p are made to satisfy (Va + Vth_p) ⁇ Vls ⁇ (Vc + Vth_n).
- depletion regions (A and B in the figure) are formed on the N region side and the P region side in the intrinsic region, respectively, and the intrinsic region sandwiched between the P region and the N region exists as an intrinsic region. It is possible to realize a configuration to That is, if (Va + Vth_p) ⁇ Vls ⁇ (Vc + Vth_n), the region between the P region and the N region is an intrinsic region.
- diodes are provided at both ends of the intrinsic region as shown in the lower side of FIG.
- FIG. 5 is a diagram for explaining the mode B.
- Vls ⁇ (Va + Vth_p) ⁇ (Vc + Vth_n) is satisfied.
- the intrinsic region between the P region and the N region is mostly inverted to the P-type due to the influence of Vls, that is, the holes (holes) are accumulated. Only the region adjacent to is a depletion region (region indicated by Wdep in the figure).
- mode B is schematically shown, as shown in the lower side of FIG. 5, the region sandwiched between the P region and the N region is provided with a diode in a region close to the N region, A p-type TFT is provided between them.
- FIG. 6 is a diagram for explaining the mode C.
- the only difference from FIG. 4 is that in mode C, (Va + Vth_p) ⁇ (Vc + Vth_n) ⁇ Vls is satisfied.
- the intrinsic region between the P region and the N region is mostly inverted to the N type due to the influence of Vls, that is, the state where electrons are accumulated is adjacent to the P region. Only the region that is present becomes a depletion region (region indicated by Wdep in the figure).
- mode C is schematically shown, as shown in the lower side of FIG. 6, the region sandwiched between the P region and the N region is provided with a diode in a region close to the P region, The n-type TFT is provided between them.
- FIG. 7A is a circuit diagram showing the configuration of the photosensor circuit 11 shown in FIG. 1A.
- FIG. 7B shows a typical operation example of the photosensor circuit 11. It is a timing chart.
- Va -5V
- Vls-Vth_n ⁇ Vc ⁇ 0V
- Vls -1.5V.
- Va + Vth_p ⁇ 7V
- Vls ⁇ 1.5V ⁇ Vc + Vth_n
- the PIN diode operates in mode A.
- Va -5V, Vc ⁇ -5V ,
- the PIN diode When the amount of incident light is large as described above, the PIN diode is reset from the mode C state to the mode A state. At that time, the PIN diode is stored in the region that should be intrinsic in the mode C. There is a concern that the reset period may end with some remaining in the area. As a result, as shown in FIG. 9, the remaining charge (electrons) is superposed on the photocurrent (signal) generated by the incident light at the time of sensing after reset, and the current amount that should be originally (shown by a broken line in the graph). A current larger than (linear) is output.
- resetting is also performed at other timings, so that the potential of the cathode terminal whose potential shifts according to incident light is changed to the charge. Is suppressed to a certain predetermined range that does not induce accumulation.
- main reset a reset necessary prior to the above sensing
- auxiliary reset a reset performed at a timing different from the main reset
- FIG. 10 is a diagram for explaining a characteristic driving method (operation method) of the PIN diode 4 performed in the present embodiment.
- FIG. 10A is a circuit diagram showing the configuration of the photosensor circuit 11. (Same as FIG. 1 and FIG. 7A), and (b) in the figure is a timing chart for explaining a method of driving the PIN diode 4.
- an auxiliary reset is performed to supply a reset signal to the anode terminal of the PIN diode 4 via the reset scanning line RST.
- the auxiliary reset is started (time t 5 ) when the cathode potential Nint does not fall below Vls ⁇ Vth_n. Thereafter, the end of the auxiliary reset (time t 6 ) is performed after sufficiently discharging Nint, but the timing is a position where interference with other operations can be avoided. In FIG. It is desirable to perform this at a time before the writing voltage is supplied to Cint via the writing signal line RW and becomes High.
- the cathode potential Nint does not fall below Vls ⁇ Vth_n and becomes the reset potential (High).
- the PIN diode 4 can be prevented from entering the mode C described above.
- the current amount (the linearity shown by the broken line in the graph) can be output without superimposing the residual charge on the photocurrent (signal) generated by the incident light. it can.
- this reset is an operation of initializing the nodes (Nint and NHint) in which charges generated from the photodiode serving as a data signal prior to sensing are accumulated, that is, charging or discharging to the initial potential of sensing. That is. Based on the reset potential, the displacement of Nint and NHint due to subsequent sensing is recognized as a data signal. That is, in the circuit of FIG. 7A, the reset is performed when the holding transistor is in the on state.
- the auxiliary reset is performed in order to hold Nint at a predetermined potential or higher, and is an operation not related to the original data signal (accumulation which is a problem to be solved by the present invention).
- the effect of the remaining charge is not the original data signal). That is, in the circuit of FIG. 7A, the reset is performed when the holding transistor is in an off state.
- FIG. 11 is the same as the circuit shown in FIG. 7A.
- Cp1 is a sum of parasitic capacitances connected to Nint
- Cp2 is a parasitic capacitance connected to Nhint (excluding Cint).
- Ipd is a photocurrent flowing through the photodiode in the state of receiving the assumed maximum incident light
- Na1 and Na2 indicate generic names of the target nodes of the parasitic capacitance.
- the photodiode in FIG. 11 is assumed to operate in the region (B) of FIG.
- Each of the above-described embodiment and the first modification is a mode in which the auxiliary reset is performed once between the main reset and the next main reset.
- the present invention is not limited to this, and a plurality of auxiliary resets may be performed between the main reset and the next main reset.
- FIG. 13 shows a timing chart of the second modified example, in which an auxiliary reset is performed twice between the main reset and the next main reset.
- the lowering degree of Nint is different between the two.
- the degree of the decrease varies depending on the amount of incident light, Nint, and capacitance connected to NHint.
- the capacitance is uniquely determined by the circuit layout and device configuration.
- the photodiode current (Ipd) is uniquely determined by the amount of incident light and the photodiode capability (size and characteristics). Therefore, the capacitance is set to the minimum value in consideration of process variation, and Ipd is set to the maximum possible incident light and the maximum sensitivity within the capability variation.
- the auxiliary reset timing is set in consideration of the above.
- FIG. 14 is a diagram showing this modification.
- the first light shielding layer 10a that shields the PIN diode 4 and the second light shielding layer 10b that shields the data holding TFT 6 are provided.
- FIG. 14B is a diagram schematically showing the PIN diode 4 and the first light shielding layer 10a of this modification.
- FIG. 14C is a diagram showing the data holding TFT 6 of this modification.
- the 2nd light shielding layer 10b is shown typically.
- the threshold value of the data holding TFT 6 can be controlled by separating the light shielding layer and applying different voltages.
- the mode in which the PIN diode 4 and the data holding TFT 6 are shielded by the single light shielding layer 10 has been described.
- the present invention is not limited to this, and the gate electrode of the data holding TFT 6 is used. It can also be used as a light shielding layer. In this case, it is not necessary to separately provide a light shielding layer on the data holding TFT 6 (FIG. 15C), and the light shielding layer 10 ′ shields only the PIN diode 4 as shown in FIG. ((A) and (b) in FIG. 15).
- the cathode whose potential is changed according to the incident light quantity of the anode terminal and the cathode terminal of the PIN diode by performing the auxiliary reset.
- the potential of the terminal can be set within a predetermined range that does not induce the accumulation of electrons in the intrinsic region of the PIN diode, specifically, more than the value indicated by Vls ⁇ Vth_n, immediately before the reset.
- FIG. 16 is a circuit diagram showing a configuration of the photosensor circuit of the present embodiment.
- the potential of the cathode terminal of the PIN diode 4 is changed by the charge generated according to the amount of incident light.
- the photosensor circuit of the present embodiment has a configuration in which the potential of the anode terminal of the PIN diode 4 is changed by the charge generated according to the amount of incident light.
- the cathode terminal of the PIN diode 4 ' is connected to the reset scanning line RST, and the source of the data holding TFT 6 is connected to the anode terminal.
- each region of the PIN diode 4 ′ is determined by the applied voltages Va, Vc, Vls and the inversion thresholds Vth_n and Vth_p in the intrinsic region of the PIN diode 4 ′.
- the relationship between the potentials of the respective regions and the intrinsic region of the PIN diode 4 ' are the same as the three modes A, B, and C in FIGS. 4 to 6 described above.
- FIG. 17 is a timing chart of a general driving example of the optical sensor circuit 11 ′.
- the voltage is turned on is applied to the gate of the data holding TFT6 at time t 1.
- a time t 2 at time t 3 when the Low to the potential supplied through the reset scan line RST to the cathode terminal of the PIN diode 4, the anode potential of the PIN diode, and the storage node is discharged Set to initial potential.
- a voltage is applied to the gate of the data holding TFT 6 at time t1 to turn it on and reset it.
- Vc 0V
- -5V ⁇ Va ⁇ Vls-Vth_p -3.5 V
- Vc + Vth_n 2V
- Va + Vth_p ⁇ Vls ⁇ 3.5V
- the PIN diode operates in mode A.
- Vc 0V, Vls -Vth_p ⁇ Va
- Vls -3.5V
- Vc + Vth_n 2V
- PIN diode 4 ' is operated in mode B It will be.
- Vc 0V, Va ⁇ 0V
- Vc + Vth_n 2V
- the PIN diodes 4 ' operates in mode B It will be.
- the PIN diode When the amount of incident light is large in this way, the PIN diode is reset from the mode B state to the mode A state. At that time, the PIN diode is accumulated in the region that should be intrinsic in mode B. There is a concern that the reset period may end with some remaining in the area. As a result, as shown in FIG. 19, this remaining charge (hole) cancels the photocurrent (signal) generated by the incident light during sensing after reset, and the current amount that should be originally (shown by a broken line in the graph). A current smaller than (linear) is output.
- FIG. 20 is a characteristic timing chart of the PIN diode 4 ′ driving method (operating method) performed in the present embodiment.
- the auxiliary reset is started (time t 5 ) when the anode potential Nint does not exceed Vls ⁇ Vth_p. Thereafter, the end of the auxiliary reset (time t 6 ) is performed after sufficiently discharging Nint, but the timing is written to a position where interference with other operations can be avoided, in FIG. 20, in the storage capacitor Cint. It is desirable to perform this at a time before the writing voltage is supplied via the signal line RW and becomes High.
- the anode potential Nint does not exceed Vls ⁇ Vth_p and becomes the reset potential (Low).
- the anode potential is never exceed Vls-Vth_p, following the reset is performed. That is, according to the operation method of the present embodiment, it is possible to prevent the PIN diode 4 'from entering the mode B described above. As a result, the above-described problems can be solved, and the amount of current that should be originally (linear as indicated by the broken line in the graph) can be output without the remaining charge canceling out the photocurrent (signal) generated by the incident light. it can.
- the write period (from time t 5 the time t 6), immediately before the TFT6 next book immediately before resetting is turned on (time t 1) During this period, an auxiliary reset may be performed.
- an auxiliary reset may be performed.
- the next main reset is performed. It is possible to prevent the anode potential Nint from exceeding Vls ⁇ Vth_p before.
- Each of the above-described embodiment and the first modification is a mode in which the auxiliary reset is performed once between the main reset and the next main reset.
- the present invention is not limited to this, and a plurality of auxiliary resets may be performed between the main reset and the next main reset.
- FIG. 22 shows a timing chart of the second modified example, in which an auxiliary reset is performed twice between the main reset and the next main reset.
- the anode whose potential is changed according to the amount of incident light of the anode terminal and the cathode terminal of the PIN diode by performing an auxiliary reset.
- the potential of the terminal can be made smaller than a value indicated by Vls ⁇ Vth_p, specifically within a predetermined range that does not induce the accumulation of electrons in the intrinsic region of the PIN diode immediately before the reset.
- Vls ⁇ Vth_p a value indicated by Vls ⁇ Vth_p
- the difference between the first embodiment and the present embodiment lies in the processing method when receiving and processing the output from the optical sensor circuit.
- one display circuit 12 is constituted by three picture elements PIX of red (R), green (G), and blue (B), and one photosensor circuit is provided for the one display circuit 12.
- 11 is the same as that of the first embodiment, but in this embodiment, for each optical sensor circuit, a circuit that senses when the backlight of the liquid crystal display device is on and a circuit when the backlight is off. It differs from the configuration of the first embodiment in that it is divided into sensing circuits. The present embodiment will be described with reference to FIGS.
- FIG. 23 is a diagram showing an outline of optical sensing according to the present embodiment.
- the detection signal is in a state in which the signal light due to the backlight lighting and the ambient light are mixed. Therefore, as shown in FIG. 23, in this embodiment, the reflection from the object on the upper surface of the optical sensor circuit is detected in a state where the signal light and the ambient light due to backlight lighting (BL ON in the figure) are mixed.
- the difference between the detection result of the first sensing and the detection result of the second sensing is obtained.
- FIG. 24 is a diagram schematically showing a part of the display unit of the present embodiment and a circuit diagram of a photosensor circuit mounted on the display unit.
- pixels in which photosensor circuits that sense when the backlight is lit are mounted on adjacent pixels in the row direction and pixels that are mounted with photosensor circuits that are sensed when the backlight is extinguished alternately in the column direction.
- pixels on which a photosensor circuit that senses when the backlight is turned on are arranged are arranged.
- the photosensor circuit of the first embodiment described above is mounted on each pixel.
- the photosensor circuit of the second embodiment described above may be mounted on each pixel.
- FIG. 25 is a timing chart showing the operation of the liquid crystal display device of the present embodiment.
- the optical sensor circuit that senses when the backlight is turned on is reset.
- the optical sensor circuit described as the scanning line RST2, the signal line CLK2, and the output OUT2 is described as the reset scanning line RST1, the signal line CLK1, and the output OUT1.
- the backlight turn-off light sensor circuit and the backlight turn-on light sensor circuit are sequentially driven in one display frame, and each of them holds the incident light data. Thereafter, the held data is sequentially written out in units of rows.
- the driving order of the backlight-lighting photosensor circuit and the backlight-lighting photosensor circuit may be either one. Further, at the time of writing, one line unit or a plurality of line units may be used. However, in the case of writing in units of a plurality of lines, it is necessary to secure output wiring for data to be written simultaneously. Further, both sensing and writing are not limited to once in one display frame. By driving with this timing chart, it is possible to perform light sensing of the backlight differential method.
- a backlight extinction photosensor circuit (or a backlight illumination photosensor circuit) is arranged along the row direction of the display unit 1 ′ of the liquid crystal display device 50.
- the backlight extinction photosensor circuit (or backlight illumination photosensor circuit) may be arranged along the column direction ((2) in the figure).
- positioned the photosensor circuit for backlight extinction and the photosensor circuit for backlight lighting by a different number may be sufficient.
- the operation method of the optical sensor circuit according to the present invention is as follows: A PIN diode, a thin film transistor connected in proximity to the PIN diode and holding an electrical signal output from the PIN diode as data, and at least the PIN diode so as to shield light incident on the PIN diode from a certain direction A light-shielding film formed in the vicinity of the optical sensor circuit, Sensing incident light at regular intervals using the PIN diode, and performing this reset prior to each sensing, Between a certain main reset and the subsequent main reset, the potential immediately before the main reset of the terminal whose potential changes according to the amount of incident light of the anode terminal and the cathode terminal of the PIN diode is An auxiliary reset is performed so as to suppress the accumulation of carriers in the intrinsic region of the PIN diode within a predetermined range.
- auxiliary reset is performed, and the potential of the terminal whose potential changes according to the amount of incident light of the anode terminal and the cathode terminal of the PIN diode is not induced to accumulate carriers in the intrinsic region of the PIN diode. It can be suppressed within a predetermined range. Therefore, inconvenient accumulation of carriers in the intrinsic region does not occur. As a result, the relationship between the sensor output and the amount of incident light can be kept linear as described above without causing a change in the photocurrent that is the original data during sensing.
- this reset is an operation that initializes the nodes (Nint and NHint) in which charges generated from the photodiodes that become data signals prior to sensing are accumulated, that is, charges or discharges to the initial sensing potential. That is. Based on the reset potential, the displacement of Nint and NHint by subsequent sensing is recognized as a data signal. That is, in the circuit of FIG. 7A described later, this is a reset performed when the holding transistor is in an on state.
- the auxiliary reset is performed in order to hold Nint above or below a predetermined potential, and is an operation not related to the original data signal (accumulation which is a problem to be solved by the present invention).
- the effect of the remaining charge is not the original data signal). That is, in the circuit of FIG. 7A to be described later, the reset is performed when the holding transistor is in an off state.
- one mode of the operation method of the optical sensor circuit according to the present invention is as follows. It is preferable to perform the auxiliary reset a plurality of times between the main reset and the subsequent main reset.
- one mode of the operation method of the optical sensor circuit according to the present invention is as follows.
- the terminal whose potential changes according to the amount of incident light among the anode terminal and the cathode terminal of the PIN diode is a cathode terminal
- the potential of the cathode terminal immediately before the main reset is expressed by the following formula (1): Vls ⁇ Vth_n (1) (However, Vls in the above expression indicates a voltage for fixing the light shielding film, and Vth_n in the expression indicates a voltage threshold at which the intrinsic region is inverted to n-type) It is preferable to perform the auxiliary reset so as to be larger than the value indicated by.
- one mode of the operation method of the optical sensor circuit according to the present invention is as follows.
- the terminal whose potential changes according to the amount of incident light among the anode terminal and the cathode terminal of the PIN diode is an anode terminal
- the potential of the anode terminal immediately before the main reset is expressed by the following formula (2): Vls ⁇ Vth_p (2) (However, Vls in the above expression indicates a voltage for fixing the light shielding film, and Vth_p in the expression indicates a voltage threshold at which the intrinsic region is inverted to p-type) It is preferable to perform the auxiliary reset so as to be smaller than the value indicated by.
- an operation method of the display device is as follows.
- the optical sensor circuit is operated by the operation method of the optical sensor circuit described above.
- an auxiliary reset is performed to induce the accumulation of carriers in the intrinsic region of the PIN diode by causing the potential of the PIN diode anode terminal and the cathode terminal whose potential changes according to the amount of incident light. Can be kept within a predetermined range. Therefore, inconvenient accumulation of carriers in the intrinsic region does not occur. As a result, the relationship between the sensor output and the amount of incident light can be kept linear as described above without causing a change in the photocurrent that is the original data during sensing.
- the operation method of the display device according to the present invention is in addition to the above configuration.
- the display device further includes a backlight, A certain photosensor circuit performs sensing while the backlight is lit, and another photosensor circuit different from the certain photosensor circuit senses while the backlight is extinguished. It is preferable to operate in such a manner.
- the difference between the detection result of the optical sensor circuit that performs sensing while the backlight is turned on and the detection result of the optical sensor circuit that performs sensing while the backlight is turned off is obtained.
- accurate sensing that is not affected by ambient light can be realized.
- the present invention can be used for any device including a circuit that performs optical sensing using a diode.
Abstract
Description
PINダイオードと、上記PINダイオードに近接して接続され当該PINダイオードから出力される電気信号をデータとして保持する薄膜トランジスタと、或る方向から上記PINダイオードに入射する光を遮光するように少なくとも当該PINダイオードに近接して形成された遮光膜と、を備えた光センサ回路の動作方法であって、
上記PINダイオードを用いて入射光のセンシングを一定の間隔ごとにおこない、且つ、各当該センシングに先立って本リセットをおこない、
或る上記本リセットとその次に行う上記本リセットとの間に、上記PINダイオードのアノード端子とカソード端子のうちの入射光量に応じてその電位が変化する端子の本リセット直前の電位を、当該PINダイオードの真性領域へのキャリアの蓄積を誘起しない所定の範囲内に抑えるように補助リセットをおこなうことを特徴としている。
以下、本発明に係る光センサ回路の動作方法の一実施形態について説明する。まず、本実施形態の光センサ回路が実装された液晶表示装置の構成を説明する。
図1は、液晶表示装置の表示部の画素内回路構成を示す図である。ここで、液晶表示装置はアクティブマトリクス型の表示装置であり、表示部1と、走査信号線駆動回路としてのゲートドライバと、データ信号線駆動回路としてのソースドライバと、補助容量配線駆動回路と、ゲートドライバ、ソースドライバ、補助容量配線駆動回路、およびコモン電極を駆動制御するための外部駆動回路とを備えている。この液晶表示装置は、交流駆動としてゲートライン反転駆動を行う。そして、さらに、正極性データをパネルに供給する期間と負極性データをパネルに供給する期間とで、互いに補助容量配線CsLに印加する補助容量電位の極性を反転させる駆動を、補助容量配線CsLごとに行う。
また、PINダイオード4の各領域のポテンシャルは、印加電圧Va、Vc、Vls、および、PINダイオード4の真性領域における反転閾値Vth_nおよびVth_pによって決定される。以下では、各領域のポテンシャルの関係と、PINダイオード4の真性領域とについて、モードA、B、Cの3つのモードに分けて説明する。
続いて、図1に示した光センサ回路11の実駆動例(実動作例)におけるPINダイオード4の状態を説明する。ここで、まずは、一般的な駆動例(動作例)を説明する。一般的な動作例ではセンシングに先立つ蓄積ノードの初期化のためのリセット、それに続くセンシング、センシングした結果の保持、保持されているデータの書き出し、といった動作がシリーズに行われる。
そこで、本実施形態では、この問題を解決するために、PINダイオード4の真性領域に電荷(電子)が不都合に蓄積しないようなバイアス状態を維持することで、信号への影響を防ぐ。
ΔVsen=Ipd,max×Tsen/(Cp1+Cp2+Cint)
と表すことができ、センシング終了~補助リセット開始(t4~t5)期間TsraにおけるNintの電位変化ΔVsraは、
ΔVsra=Ipd,max×Tsra/Cp1
と表すことができる。したがって、n回目の本リセット終了後から(n+1)回目の本リセット開始期間中の総電位変化ΔVrrは、
ΔVrr=ΔVsen+ΔVsra
=Ipd,max×〔Tsen/(Cp1+Cp2+Cint)+Tsra/Cp1〕
と表すことができる。
上述した態様では、蓄積容量Cintにおいて電荷(=データ)が保持されている期間の後半、すなわち、蓄積容量Cintに書き出し信号線RWを介して書き出し電圧が供給されてHighとなる前に、補助リセットをおこなう態様を例示したが、本発明はこれに限定されるものではない。
ΔVras=Ipd,max×Tras/Cp1
で表され、算出されるΔVrasによる電位シフトを考慮した場合にモードAを維持できるようなタイミング(Tras)を設定することにより、真性領域への不都合な電荷の蓄積を防ぐことができる。
上述した実施形態および第1変形例はいずれも、本リセットと次の本リセットとの間に、補助リセットが1回実施される態様である。しかしながら、本発明はこれに限定されるものではなく、本リセットと次の本リセットとの間に複数回の補助リセットをおこなってもよい。
ΔVra12=Ipd,max×Tra12/Cp1
で表され、算出されるΔVra12による電位シフトを考慮した場合にモードAを維持できるようなタイミング(Tra12)を設定することにより、真性領域への不都合な電荷の蓄積を防ぐことができる。
本実施形態では、PINダイオード4およびデータ保持用TFT6を1つの遮光層10で遮光している形態について説明したが、本発明はこれに限定されるものではなく、遮光層をPINダイオード4用とデータ保持用TFT6用とに分離して別々の電圧を印加する形態としてもよい。図14は、本変形例を示した図であり、図14の(a)に示すように、PINダイオード4を遮光する第1遮光層10aと、データ保持用TFT6を遮光する第2遮光層10bとを備えている。そして、図14の(b)は、本変形例のPINダイオード4および第1遮光層10aを模式的に示した図であり、図14の(c)は、本変形例のデータ保持用TFT6および第2遮光層10bを模式的に示している。図14に示すように、遮光層を分離し、別々の電圧を印加する形態とすることによって、データ保持用TFT6のしきい値を制御することができる。
本実施形態では、PINダイオード4およびデータ保持用TFT6を1つの遮光層10で遮光している形態について説明したが、本発明はこれに限定されるものではなく、データ保持用TFT6のゲート電極を遮光層として用いることも可能である。この場合は、別途、データ保持用TFT6には別途遮光層を設ける必要はなく(図15の(c))、遮光層10´は、図15に示すように、PINダイオード4のみを遮光するように配置すればよい(図15の(a)および(b))。
以上のように、本実施形態の光センサ回路の駆動方法(動作方法)によれば、補助リセットをおこなってPINダイオードのアノード端子とカソード端子のうちの入射光量に応じてその電位が変化するカソード端子の電位を、特に本リセット直前において、PINダイオードの真性領域への電子の蓄積を誘起しない所定の範囲内、具体的にはVls-Vth_nで示される値よりも大きくすることができる。これにより、フォトダイオードの真性領域への電荷の不都合な蓄積を防止することができ、次のセンシング直前におこなわれる本リセットで、残存電荷は発生しない。よって、センシングの際に本来のデータであるフォト電流に残余電荷が重畳することを防ぐことができ、上述したようにセンサ出力と入射光量との関係を直線形に維持することができる。
以下、本発明に係る光センサ回路の動作方法の他の実施形態について説明する。なお、説明の便宜上、上記第1実施形態にて説明した部材と同じ機能を有するものは、同じ符号を付記し、その説明を省略する。
図16は、本実施形態の光センサ回路の構成を示した回路図である。上記第1実施形態では、PINダイオード4のカソード端子の電位が入射光量に応じて生じた電荷により変化する構成である。これに対して、本実施形態の光センサ回路は、PINダイオード4のアノード端子の電位が入射光量に応じて生じた電荷により変化する構成となっている。
本実施形態の光センサ回路においても、一般的な駆動例だと上述の第1実施形態中で説明したように入射光量によっては本来真性であるべき領域に蓄積されていた電荷(ホール)を全て当該領域から消失させることができない事態が生じる虞がある。この点、以下に説明する。
続いて、図16に示した光センサ回路11´の実駆動例(実動作例)におけるPINダイオード4の状態を説明する。ここで、以下に説明する一般的な駆動例(動作例)では、光センサ回路でのセンシングの直前に、蓄積ノードの初期化のためのリセットをおこなう。
そこで、本実施形態では、この問題を解決するために、PINダイオード4´の真性領域に電荷が蓄積しないようなバイアス状態を維持することで、蓄積電荷の信号への影響を防ぐ。具体的には、本実施形態では、上記のセンシングに先立って必要な本リセットに加えて、他のタイミングで補助リセットをおこなうことにより、入射光に応じて電位がシフトするアノード端子の電位を、電荷の蓄積を誘起しないある所定の範囲に抑える。
上述した態様では、蓄積容量Cintにおいて電荷(=データ)が保持されている期間の後半、すなわち、蓄積容量Cintに書き出し信号線RWを介して書き出し電圧が供給されてHighとなる前に、補助リセットをおこなう態様を例示したが、本発明はこれに限定されるものではない。
上述した実施形態および第1変形例はいずれも、本リセットと次の本リセットとの間に、補助リセットが1回実施される態様である。しかしながら、本発明はこれに限定されるものではなく、本リセットと次の本リセットとの間に複数回の補助リセットをおこなってもよい。
以上のように、本実施形態の表示装置(光センサ回路)の動作方法によれば、補助リセットをおこなってPINダイオードのアノード端子とカソード端子のうちの入射光量に応じてその電位が変化するアノード端子の電位を、特に本リセット直前において、PINダイオードの真性領域への電子の蓄積を誘起しない所定の範囲内、具体的にはVls-Vth_pで示される値よりも小さくすることができる。これにより、フォトダイオードの真性領域への電荷の不都合な蓄積を防止することができ、次のセンシング直前におこなわれる本リセットで、残存電荷は発生しない。よって、センシングの際に本来のデータであるフォト電流を残余ホールが相殺することを防ぐことができ、上述したようにセンサ出力と入射光量との関係を直線形に維持することができる。
以下、本発明に係る表示装置の動作方法の他の実施形態について説明する。なお、説明の便宜上、上記第1実施形態にて説明した部材と同じ機能を有するものは、同じ符号を付記し、その説明を省略する。
本発明に係る、光センサ回路の動作方法は、
PINダイオードと、上記PINダイオードに近接して接続され当該PINダイオードから出力される電気信号をデータとして保持する薄膜トランジスタと、或る方向から上記PINダイオードに入射する光を遮光するように少なくとも当該PINダイオードに近接して形成された遮光膜と、を備えた光センサ回路の動作方法であって、
上記PINダイオードを用いて入射光のセンシングを一定の間隔ごとにおこない、且つ、各当該センシングに先立って本リセットをおこない、
或る上記本リセットとその次に行う上記本リセットとの間に、上記PINダイオードのアノード端子とカソード端子のうちの入射光量に応じてその電位が変化する端子の本リセット直前の電位を、当該PINダイオードの真性領域へのキャリアの蓄積を誘起しない所定の範囲内に抑えるように補助リセットをおこなうことを特徴としている。
上記本リセットとその次に行う上記本リセットとの間に、複数回の上記補助リセットをおこなうことが好ましい。
上記PINダイオードのアノード端子とカソード端子のうちの入射光量に応じてその電位が変化する上記端子は、カソード端子であり、
上記本リセットの直前における上記カソード端子の電位が、次の式(1);
Vls-Vth_n ・・・(1)
(但し、上記式中のVlsは、上記遮光膜の固定用電圧を示し、式中のVth_nは、上記真性領域がn型に反転する電圧閾値を示す)
で示される値よりも大きくなるように上記補助リセットをおこなうことが好ましい。
上記PINダイオードのアノード端子とカソード端子のうちの入射光量に応じてその電位が変化する上記端子は、アノード端子であり、
上記本リセットの直前における上記アノード端子の電位が、次の式(2);
Vls-Vth_p ・・・(2)
(但し、上記式中のVlsは、上記遮光膜の固定用電圧を示し、式中のVth_pは、上記真性領域がp型に反転する電圧閾値を示す)
で示される値よりも小さくなるように上記補助リセットをおこなうことが好ましい。
PINダイオードと、上記PINダイオードに近接して接続され当該PINダイオードから出力される電気信号をデータとして保持する薄膜トランジスタと、或る方向から上記PINダイオードに入射する光を遮光するように少なくとも当該PINダイオードに近接して形成された遮光膜と、を備えた光センサ回路を、画素ごとに設けている表示装置の動作方法であって、
上記光センサ回路を、上記した光センサ回路の動作方法で動作させることを特徴としている。
上記表示装置は、バックライトを更に備えており、
或る上記光センサ回路は、上記バックライトが点灯している間にセンシングをおこない、或る上記光センサ回路とは異なる他の上記光センサ回路は、上記バックライトが消灯している間にセンシングをおこなうように動作する、ことが好ましい。
4、4´ PINダイオード
6 データ保持用TFT
9 データ書き出し用TFT
10、10´ 遮光層
10a 第1遮光層
10b 第2遮光層
11、11´ 光センサ回路
12 表示回路
21画素TFT
50 液晶表示装置
CL 液晶容量
CLK 信号線
Cint 蓄積容量
Cs 補助容量
CsL 補助容量配線
GL ゲートライン
NHint 蓄積ノード
Nint アノード電位、カソード電位
OUT 光センサ出力線
PIX 絵素
RST リセット走査線
RW 書き出し信号線
SL ソースライン
VDD 電源配線
Va アノード端子への印加電圧
Vac バイアス
Vc カソード端子への印加電圧
Vls 遮光層用固定電圧
Vth 反転閾値
i 真性領域
Claims (6)
- PINダイオードと、上記PINダイオードに近接して接続され当該PINダイオードから出力される電気信号をデータとして保持する薄膜トランジスタと、或る方向から上記PINダイオードに入射する光を遮光するように少なくとも当該PINダイオードに近接して形成された遮光膜と、を備えた光センサ回路の動作方法であって、
上記PINダイオードを用いて入射光のセンシングを一定の間隔ごとにおこない、且つ、各当該センシングに先立って本リセットをおこない、
或る上記本リセットとその次に行う上記本リセットとの間に、上記PINダイオードのアノード端子とカソード端子のうちの入射光量に応じてその電位が変化する端子の本リセット直前の電位を、当該PINダイオードの真性領域へのキャリアの蓄積を誘起しない所定の範囲内に抑えるように補助リセットをおこなうことを特徴とする、光センサ回路の動作方法。 - 上記本リセットとその次に行う上記本リセットとの間に、複数回の上記補助リセットをおこなうことを特徴とする請求項1に記載の光センサ回路の動作方法。
- 上記PINダイオードのアノード端子とカソード端子のうちの入射光量に応じてその電位が変化する上記端子は、カソード端子であり、
上記本リセットの直前における上記カソード端子の電位が、次の式(1);
Vls-Vth_n ・・・(1)
(但し、上記式中のVlsは、上記遮光膜の固定用電圧を示し、式中のVth_nは、上記真性領域がn型に反転する電圧閾値を示す)
で示される値よりも大きくなるように上記補助リセットをおこなうことを特徴とする請求項1または2に記載の光センサ回路の動作方法。 - 上記PINダイオードのアノード端子とカソード端子のうちの入射光量に応じてその電位が変化する上記端子は、アノード端子であり、
上記本リセットの直前における上記アノード端子の電位が、次の式(2);
Vls-Vth_p ・・・(2)
(但し、上記式中のVlsは、上記遮光膜の固定用電圧を示し、式中のVth_pは、上記真性領域がp型に反転する電圧閾値を示す)
で示される値よりも小さくなるように上記補助リセットをおこなうことを特徴とする請求項1または2に記載の光センサ回路の動作方法。 - PINダイオードと、上記PINダイオードに近接して接続され当該PINダイオードから出力される電気信号をデータとして保持する薄膜トランジスタと、或る方向から上記PINダイオードに入射する光を遮光するように少なくとも当該PINダイオードに近接して形成された遮光膜と、を備えた光センサ回路を、画素ごとに設けている表示装置の動作方法であって、
上記光センサ回路を、請求項1から4までの何れか1項に記載の動作方法で動作させることを特徴とする、表示装置の動作方法。 - 上記表示装置は、バックライトを更に備えており、
或る上記光センサ回路は、上記バックライトが点灯している間にセンシングをおこない、或る上記光センサ回路とは異なる他の上記光センサ回路は、上記バックライトが消灯している間にセンシングをおこなうように動作する、請求項5に記載の表示装置の動作方法。
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CN110391269A (zh) * | 2018-04-23 | 2019-10-29 | 京东方科技集团股份有限公司 | 显示装置、显示面板及其制备方法 |
WO2021021207A1 (en) * | 2019-08-01 | 2021-02-04 | Google Llc | Detection of blink period for ambient light sensing |
CN110660356B (zh) * | 2019-09-30 | 2021-03-19 | 京东方科技集团股份有限公司 | 一种显示基板及其制作方法、显示装置 |
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