WO2013039200A1 - 複合ウェーハの製造方法 - Google Patents
複合ウェーハの製造方法 Download PDFInfo
- Publication number
- WO2013039200A1 WO2013039200A1 PCT/JP2012/073629 JP2012073629W WO2013039200A1 WO 2013039200 A1 WO2013039200 A1 WO 2013039200A1 JP 2012073629 W JP2012073629 W JP 2012073629W WO 2013039200 A1 WO2013039200 A1 WO 2013039200A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- wafer
- handle
- composite
- donor
- wafers
- Prior art date
Links
- 239000002131 composite material Substances 0.000 title claims abstract description 46
- 238000000034 method Methods 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 235000012431 wafers Nutrition 0.000 claims abstract description 253
- 238000010438 heat treatment Methods 0.000 claims abstract description 22
- 239000010409 thin film Substances 0.000 claims abstract description 22
- 239000001257 hydrogen Substances 0.000 claims abstract description 18
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 18
- -1 hydrogen ions Chemical class 0.000 claims abstract description 17
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 claims abstract description 17
- 238000012546 transfer Methods 0.000 claims abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 39
- 239000010703 silicon Substances 0.000 claims description 39
- 229910052710 silicon Inorganic materials 0.000 claims description 39
- 239000010980 sapphire Substances 0.000 claims description 25
- 229910052594 sapphire Inorganic materials 0.000 claims description 25
- 239000010408 film Substances 0.000 claims description 17
- 238000005468 ion implantation Methods 0.000 claims description 13
- 239000010453 quartz Substances 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 238000001994 activation Methods 0.000 claims description 10
- 239000011521 glass Substances 0.000 claims description 10
- 230000001678 irradiating effect Effects 0.000 claims description 7
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- 229910002601 GaN Inorganic materials 0.000 claims description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 3
- 238000002347 injection Methods 0.000 abstract 2
- 239000007924 injection Substances 0.000 abstract 2
- 239000007789 gas Substances 0.000 description 11
- 238000012545 processing Methods 0.000 description 9
- 125000004429 atom Chemical group 0.000 description 7
- 230000004913 activation Effects 0.000 description 6
- 238000012360 testing method Methods 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 3
- 238000003776 cleavage reaction Methods 0.000 description 3
- 238000005336 cracking Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000007017 scission Effects 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 230000005465 channeling Effects 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- YZCKVEUIGOORGS-UHFFFAOYSA-N Hydrogen atom Chemical compound [H] YZCKVEUIGOORGS-UHFFFAOYSA-N 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 125000002887 hydroxy group Chemical group [H]O* 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000678 plasma activation Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000002195 synergetic effect Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2011—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate the substrate being of crystalline insulating material, e.g. sapphire
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
Definitions
- the present invention relates to a method for manufacturing a composite wafer.
- SOI silicon on insulator
- SOQ wafers are expected to be applied to optoelectronics utilizing the high transparency of quartz or high frequency devices utilizing low dielectric loss.
- the handle wafer is made of sapphire, SOS wafers have high thermal conductivity that cannot be obtained with glass or quartz, in addition to high transparency and low dielectric loss, so they can be applied to high-frequency devices that generate heat. There is expected.
- Such a composite wafer is generally manufactured by bonding two wafers (a donor wafer and a handle wafer).
- An SOS wafer can also be obtained by epitaxially growing silicon directly on the R surface of sapphire.
- the lattice constants of sapphire and silicon are different, in general, the crystal quality does not reach that of bulk silicon.
- the mainstream diameters of silicon wafer and sapphire are 6-12 inches and 2-4 inches, respectively.
- the mainstream diameters of silicon wafer and sapphire are 6-12 inches and 2-4 inches, respectively.
- an increase in wafer diameter and a structure miniaturization are simultaneously progressing. For this reason, when trying to obtain a wafer of excellent quality, a silicon wafer having a large diameter is inevitably selected.
- Patent Document 1 describes that by using a handle wafer and a donor wafer larger than the handle wafer, the area of the transferred layer can be enlarged. However, in Patent Document 1, since one donor wafer is bonded to one handle wafer, it is necessary to perform primary chamfering and secondary chamfering on both wafers.
- Patent Document 1 In the case of the two-step chamfering method described in Patent Document 1, the chamfering quality of both wafers determines the quality of the bonding. This is because if there are irregularities in the periphery of the chamfered portion, the periphery becomes defective. For this reason, the chamfering process takes a great deal of cost and time.
- Patent Document 1 is characterized in that a donor wafer having a slightly larger diameter than the handle wafer is used.
- wafer processing and semiconductor process equipment are usually standards determined by SEMI, JEIDA, etc. (diameter 2 inches (50-50.8 mm), diameter 3 inches (76-76.2 mm), diameter 4 inches (100 mm)).
- the present invention has been made in view of the above circumstances, and provides a method for producing a composite wafer that can obtain a plurality of composite wafers from one donor wafer and that can omit the chamfering process of the donor wafer.
- hydrogen ions are implanted from the surface of a donor wafer having a diameter equal to or larger than the sum of the diameters of at least two handle wafers to form a hydrogen ion implanted layer therein. Bonding the surface of the donor wafer and the surfaces of the at least two handle wafers to obtain a bonded wafer; and subjecting the bonded wafer to a heat treatment at a temperature of 200 to 400 ° C .; After the heat treatment, a peeling transfer step of peeling a thin film on the handle wafer along the hydrogen ion implanted layer to obtain a composite wafer having the thin film transferred on the handle wafer I will provide a.
- a plurality of composite wafers can be obtained from one donor wafer, and the chamfering step can be omitted.
- FIG. 2 (A) It is a figure which shows an example of the process of the manufacturing method of a composite wafer.
- One donor wafer (FIG. 2 (A)) and two handle wafers (FIG. 2 (B)) were bonded to one donor wafer, and the curvature of the donor wafer when heat-treated was shown.
- the at least two handle wafers used in the present invention include a silicon wafer, glass, quartz, sapphire, silicon carbide, or gallium nitride.
- the handle wafer is preferably cleaned by RCA cleaning or the like before a bonding process described later.
- at least two handle wafers can be selected from different materials, it is preferable to select the same wafer from the viewpoint of bonding and heat treatment described later.
- the diameter of each handle wafer is preferably 2 to 6 inches, more preferably 2, 3, 4, or 6 inches. With such a diameter, at least two or more composite wafers can be produced simultaneously. It is also possible to produce many composite wafers at once by combining handle wafers with different diameters.
- the donor wafer used in the present invention is preferably a silicon wafer, glass, quartz, sapphire, silicon carbide, or gallium nitride.
- the diameter of the donor wafer has a diameter that is equal to or greater than the sum of the diameters of at least two handle wafers. Further, it is twice or more the diameter of the handle wafer. A preferable upper limit of the magnification is 6 times.
- the diameter of the donor wafer is preferably 6-12 inches, more preferably 6, 8, or 12 inches. With such a diameter, at least two or more composite wafers can be produced simultaneously.
- the chamfering process applied to the donor wafer can be omitted. This is because the chamfered portion of the donor wafer, which can be a cause of bonding failure, is far away from the bonding location, and is not involved in the bonding quality.
- FIG. 1 is a diagram showing an example of steps of a method for manufacturing a composite wafer according to the present invention.
- FIG. 1 shows an example of a method for manufacturing two composite wafers from one donor wafer and two handle wafers.
- hydrogen ions are implanted from the surface 13s of the donor wafer 13 having a diameter that is twice or more the total length of the handle wafers 11 and 12, and hydrogen ions are implanted therein.
- Layer 14 is formed.
- the ion-implanted surface 13 s of the donor wafer 13 and the surfaces 11 s and 12 s of the two handle wafers 11 and 12 are bonded together to form a bonded wafer 15.
- the temperature of the donor wafer 13 is set to 250 to 400 ° C.
- a predetermined dose of hydrogen ions is implanted with an implantation energy capable of implanting hydrogen ions to a desired depth.
- the implantation energy may be 50 to 100 keV, and the implantation dose may be 2 ⁇ 10 16 to 1 ⁇ 10 17 / cm 2 .
- hydrogen ions (H + ) having a dose of 2 ⁇ 10 16 to 1 ⁇ 10 17 (atoms / cm 2 ), or 1 ⁇ 10 16 to 5 ⁇ 10 16 (atoms / cm 2 ).
- a hydrogen molecular ion (H 2 + ) with a dose amount of is preferable.
- the depth from the surface 13s of the donor wafer 13 implanted with hydrogen ions to the hydrogen ion implanted layer 14 depends on the desired thickness of the thin film 13B provided on the handle wafers 11 and 12, but is preferably 300 to 500 nm. Preferably, it is about 400 nm.
- the thickness of the hydrogen ion implanted layer 13 is such that it can be easily peeled off by mechanical impact, and is preferably about 200 to 400 nm, more preferably about 300 nm.
- a silicon wafer in which an oxide film is formed on the surface 13s may be used in addition to the above-described one. If such a silicon wafer having an oxide film formed on the surface 13s is used and ion implantation is performed through the oxide film, an effect of suppressing channeling of implanted ions can be obtained, and variations in ion implantation depth can be further suppressed. it can. Thereby, a thin film with high film thickness uniformity can be formed.
- the oxide film can be formed by a general thermal oxidation method. In general, it is obtained by heat treatment at 800 to 1100 ° C. under normal pressure in an oxygen atmosphere or a water vapor atmosphere.
- the thickness of the oxide film is preferably 50 to 500 nm. This is because it is difficult to control the oxide film thickness if it is too thin, and it takes too much time if it is too thick.
- the surface activation treatment can be performed using, for example, a plasma apparatus including an upper electrode and a lower electrode that are opposed to each other with a space therebetween.
- a donor wafer or a handle wafer is usually placed on the upper surface of the lower electrode, a processing gas is introduced, and high-frequency power is applied to at least one of the upper electrode or the lower electrode, so A high frequency electric field is formed, and plasma of the processing gas is formed by the high frequency electric field, and the donor wafer or the handle wafer is subjected to plasma processing.
- the surface plasma treatment is usually performed by placing a donor wafer or a handle wafer in a vacuum chamber, introducing a processing gas, and then exposing to a high-frequency plasma of about 100 W for about 5 to 30 seconds.
- a processing gas for example, when processing a silicon wafer having an oxide film formed on the surface, preferably, when processing a silicon wafer not forming an oxide film on the surface, preferably, plasma of oxygen gas, Hydrogen gas, argon gas, a mixed gas thereof, or a mixed gas of hydrogen gas and helium gas can be used. Further, an inert gas such as nitrogen gas may be used. When processing other donor wafers or handle wafers, any gas may be used.
- the surface of the wafer subjected to the surface activation process is activated by increasing the number of OH groups by performing the plasma process as described above. Therefore, in this state, if the surface of the donor wafer and the surface of the handle wafer are brought into close contact with each other, the wafer can be bonded more firmly by hydrogen bonding or the like. Moreover, the same effects as the plasma treatment as described above can be obtained by performing a treatment such as UV or ozone as the surface activation treatment.
- the bonded wafer 15 is subjected to a heat treatment H at a temperature of 200 to 400 ° C.
- the heat treatment time is determined according to the heat treatment temperature and the material, and is preferably selected from the range of 1 to 24 hours. If the heat treatment temperature is too high or the heat treatment time is too long, there is a risk of cracking, peeling, or the like.
- the heat treatment step can be preferably performed in the presence of argon, nitrogen, helium, or a mixed gas thereof.
- FIG. 2 shows a state in which one handle wafer 21 (FIG. 2A) and two handle wafers 21 (FIG. 2B) are bonded to one donor wafer 22 and subjected to heat treatment.
- 3 is a cross-sectional view of a composite wafer showing the warpage of a donor wafer 22.
- FIG. 2A when a single handle wafer is bonded, the stress distribution is concentric with the handle wafer, so that the donor wafer is uniformly stressed.
- FIG. 2A when a single handle wafer is bonded, the stress distribution is concentric with the handle wafer, so that the donor wafer is uniformly stressed.
- the thin film 13B on the handle wafers 11 and 12 is peeled along the hydrogen ion implantation layer 14, and the thin film 13B is transferred onto the handle wafers 11 and 12.
- the composite wafers 16 and 17 are obtained.
- the composite wafers 16 and 17 can be obtained by peeling and transferring the thin film 13B.
- the thin film portion 13b that is not bonded remains on the donor wafer. In the case of visible light irradiation from the transparent wafer side, which will be described later, the thin film portion 13b that is not bonded to the donor wafer can be more easily left by controlling the visible light irradiation range.
- the peeling transfer step preferably includes irradiating visible light from the transparent wafer side.
- the handle wafer is made of glass, quartz or sapphire, it is preferable that this peeling transfer step includes irradiating visible light from the handle wafer side.
- the silicon near the ion implantation interface formed inside the donor wafer is amorphized, so that it can be peeled off by a mechanism that easily absorbs visible light and easily accepts energy. It is.
- this peeling method is preferable because it is simpler than mechanical peeling.
- the visible light source is preferably a Rapid Thermal Annealer (RTA), a green laser light, or a flash lamp light.
- a wedge-shaped member for example, a wedge (wedge) is preferably inserted into the hydrogen ion implantation layer 14 (implantation interface), and the cleavage is caused by the deformation by the wedge to peel off.
- care should be taken to avoid generation of scratches and particles at the contact portion of the wedge, and substrate cracking due to excessive deformation of the wafer caused by driving the wedge.
- this peeling transfer step is performed by bringing a cleaving member into contact with the hydrogen ion implantation layer 14 in advance and irradiating visible light from the handle wafer side. It preferably includes applying a mechanical shock. According to this method, it is possible to obtain a synergistic effect between the light peeling by the light irradiation and the mechanical peeling.
- a jet of a fluid such as a gas or a liquid may be sprayed continuously or intermittently from the side surface of the wafer, but mechanical peeling occurs due to the impact.
- the method is not particularly limited.
- the composite wafers 16 and 17 can be manufactured by the process as described above. As described above, according to the composite wafer manufacturing method of the present invention, a plurality of composite wafers can be obtained from one donor wafer, and the donor wafer chamfering step can be omitted. In addition, since a plurality of composite wafers can be obtained from a single donor wafer, the cost can be significantly reduced.
- the process of the method for manufacturing a composite wafer according to the present invention has been described as an example of a method for manufacturing two composite wafers from one donor wafer and two handle wafers. Even when three handle wafers (FIG. 3), four handle wafers (FIG.
- the composite wafer according to the present invention is similarly applied. It is possible to implement this manufacturing method. Similarly, the composite wafer manufacturing method according to the present invention can be implemented by combining a plurality of handle wafers having different diameters.
- Test Example 1 (Comparative test with and without surface activation treatment when using wafers with different coefficients of thermal expansion)
- two 2-inch sapphire wafers were bonded to a 6-inch silicon wafer on which an oxide film was grown to 50 nm, followed by heat treatment at 250 ° C. for 24 hours.
- Test Example 2 two 2-inch sapphire wafers subjected to plasma activation treatment were bonded to a 6-inch silicon wafer having an oxide film grown to 50 nm, followed by heat treatment at 250 ° C. for 24 hours. .
- the sapphire wafer was peeled off from the silicon wafer, and the silicon wafer was damaged.
- Test Example 2 the sapphire wafer was firmly bonded to the silicon wafer. From this result, it was shown that the bonding strength can be increased by performing a surface activation treatment before bonding the sapphire wafer and the silicon wafer.
- Example 1 An oxide film is grown to 50 nm, and hydrogen ions are implanted at a dose of 7.0 ⁇ 10 16 atoms / cm 2 and energy of an acceleration voltage of 50 KeV. Three wafers were bonded together. After heat treatment at 250 ° C. for 24 hours, a wedge was inserted from the ion implantation interface and mechanical peeling was performed. In the obtained composite wafer, it was confirmed that the silicon thin film was transferred onto the sapphire wafer. From this result, it was shown that the lack of chamfering on the silicon wafer does not affect the transferred silicon thin film.
- Example 2 A 2 inch sapphire is grown on a 4 inch silicon wafer that has not been chamfered and has an oxide film grown by 50 nm and hydrogen ions are implanted at a dose of 7.0 ⁇ 10 16 atoms / cm 2 and an acceleration voltage of 50 KeV. Two wafers were bonded together. After heat treatment at 250 ° C. for 24 hours, the silicon thin film was peeled and transferred from the ion implantation interface by irradiating strong visible light from the sapphire wafer side. As a visible light source, RTA, green laser light, and flash lamp light were used. It was confirmed that the silicon thin film was successfully transferred onto the sapphire wafer with all light sources. From this result, it was shown that the lack of chamfering on the silicon wafer does not affect the transferred silicon thin film.
- Example 3 An oxide film was deposited to a thickness of 50 nm by CVD, and hydrogen ions were implanted at a dose of 9.8 ⁇ 10 16 atoms / cm 2 and an acceleration voltage of 70 KeV, on a 4-inch silicon carbide wafer that was not chamfered. Three 2-inch sapphire wafers were bonded together. After heat treatment at 250 ° C. for 24 hours, a wedge was inserted from the ion implantation interface and mechanical peeling was performed. In the obtained composite wafer, it was confirmed that the silicon thin film was transferred onto the sapphire wafer. From this result, it was shown that the lack of chamfering on the silicon wafer does not affect the transferred silicon thin film.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Recrystallisation Techniques (AREA)
- Element Separation (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
Description
また、特許文献1では、ハンドルウェーハよりも少し大きい直径を有するドナーウェーハを用いることを特徴としている。しかし、ウェーハ加工、半導体のプロセス装置は、通常、SEMIやJEIDA等で決められた規格(直径2インチ(50-50.8mm)、直径3インチ(76-76.2mm)、直径4インチ(100mm)、直径5インチ(125mm)、直径6インチ(150mm)、直径8インチ(200mm)、直径12インチ(300mm)等)のウェーハしか扱えないことが多い。そのため、イレギュラーなサイズのウェーハを扱うことは極めて困難であり、既存の装置の改造等に莫大な費用がかかることも現実的な問題である。
本発明は上記事情に鑑みてなされたものであって、1枚のドナーウェーハから複数枚の複合ウェーハを得ることができ、ドナーウェーハの面取り工程を省略可能な複合ウェーハの製造方法を提供する。
ハンドルウェーハのそれぞれの直径は、好ましくは2~6インチ、より好ましくは2、3、4、又は6インチである。このような直径であれば、同時に少なくとも2枚以上の複合ウェーハを作製することができる。また、異なる直径のハンドルウェーハを組み合わせることによって、一度に多くの複合ウェーハを作製することも可能である。
ドナーウェーハの直径は、少なくとも2枚のハンドルウェーハの直径の合計と同じか大きい直径を有する。また、ハンドルウェーハの直径の2倍以上の大きさである。倍率の好ましい上限値は、6倍である。
ドナーウェーハの直径は、好ましくは6~12インチ、より好ましくは6、8、又は12インチである。このような直径であれば、同時に少なくとも2枚以上の複合ウェーハを作製することができる。
上述したように、本発明で用いるドナーウェーハは、ハンドルウェーハの2倍以上の大きさであることから、ドナーウェーハに施す面取り工程を省くことが可能である。これは、貼り合わせの不良原因となり得るドナーウェーハの面取り部分が貼り合わせ箇所から遠く隔たっているため、貼り合わせの良否に関与しないからである。
図1は、本発明に係る複合ウェーハの製造方法の工程の一例を示す図である。図1では、1枚のドナーウェーハと2枚のハンドルウェーハから2枚の複合ウェーハを製造する方法の一例を示している。
まず、図1(A)に示すように、ハンドルウェーハ11、12の直径の長さの合計の2倍以上の直径を有するドナーウェーハ13の表面13sから水素イオンを注入して内部に水素イオン注入層14を形成させる。次に、図1(B)に示すように、ドナーウェーハ13のイオン注入された表面13sと、2枚の前記ハンドルウェーハ11、12の表面11s、12sとを貼り合わせて、貼り合わせウェーハ15を得る。
図1(A)に示すように、ドナーウェーハ13の表面13sから水素イオンを注入して水素イオン注入層14を形成する際、例えば、ドナーウェーハ13の温度を250~400℃とし、その表面から所望の深さに水素イオン注入できるような注入エネルギーで、所定の線量の水素イオンを注入する。このときの条件として、例えば注入エネルギーは50~100keV、注入線量は2×1016~1×1017/cm2とすることができる。
注入される水素イオンとしては、2×1016~1×1017(atoms/cm2)のドーズ量の水素イオン(H+)、又は1×1016~5×1016(atoms/cm2)のドーズ量の水素分子イオン(H2 +)が好ましい。特に好ましくは、8.0×1016(atoms/cm2)のドーズ量の水素イオン(H+)、又は4.0×1016(atoms/cm2)のドーズ量の水素分子イオン(H2 +)である。このドーズ量で作製したものが、後の剥離、転写の際に、好適な脆弱性を有するからである。
水素イオン注入されたドナーウェーハ13の表面13sから水素イオン注入層14までの深さは、ハンドルウェーハ11、12上に設ける薄膜13Bの所望の厚さに依存するが、好ましくは300~500nm、さらに好ましくは400nm程度である。また、水素イオン注入層13の厚さは、機械衝撃によって容易に剥離できる厚さがよく、好ましくは200~400nm、さらに好ましくは300nm程度である。
酸化膜の厚さは、好ましくは50~500nmである。これはあまり薄いと、酸化膜厚の制御が難しく、またあまり厚いと時間が掛かりすぎるためである。
表面活性化処理は、例えば、空間を隔てて対向する上部電極と下部電極を備えるプラズマ装置を用いて行うことができる。このプラズマ装置では、通常、下部電極の上面にドナーウェーハ又はハンドルウェーハを載置し、処理ガスを導入するとともに、上部電極又は下部電極のうち少なくとも一方に高周波電力を印加して、両電極間に高周波電界を形成し、この高周波電界により処理ガスのプラズマを形成してドナーウェーハ又はハンドルウェーハに対してプラズマ処理が施される。
可視光の光源は、Rapid Thermal Annealer(RTA)、グリーンレーザー光、又はフラッシュランプ光であることが好ましい。
以上説明したように、本発明の複合ウェーハの製造方法によれば、1枚のドナーウェーハから複数枚の複合ウェーハを得ることができ、ドナーウェーハの面取り工程を省略できる。また、1枚のドナーウェーハから複数枚の複合ウェーハを得ることができるため、大幅なコストダウンが可能となる。
なお、本明細書では、本発明に係る複合ウェーハの製造方法の工程について、1枚のドナーウェーハと2枚のハンドルウェーハから2枚の複合ウェーハを製造する方法の一例として説明したが、1枚のドナーウェーハに対して3枚のハンドルウェーハ(図3)、4枚のハンドルウェーハ(図4)、又はそれ以上の枚数のハンドルウェーハを用いた場合においても、同様に、本発明に係る複合ウェーハの製造方法を実施することが可能である。また、異なる直径のハンドルウェーハを複数枚組み合わせることによっても、同様に、本発明に係る複合ウェーハの製造方法を実施することが可能である。
試験例1として、酸化膜を50nm成長させた6インチのシリコンウェーハ上に、2インチのサファイアウェーハを2枚貼り合わせた後、250℃で24時間の熱処理を行った。
試験例2として、酸化膜を50nm成長させた6インチのシリコンウェーハ上に、プラズマ活性化処理を行った2インチのサファイアウェーハを2枚貼り合わせた後、250℃で24時間の熱処理を行った。
試験例1では、サファイアウェーハはシリコンウェーハから剥がれており、シリコンウェーハが破損していた。一方、試験例2では、サファイアウェーハはシリコンウェーハに強固に貼り合わされていた。この結果から、サファイアウェーハとシリコンウェーハを貼り合わせる前に表面活性化処理を施すことによって、接合強度を高めることができることが示された。
酸化膜を50nm成長させ、水素イオンをドーズ量7.0×1016atoms/cm2、加速電圧50KeVのエネルギーで注入した、面取り加工を行わなかった6インチのシリコンウェーハ上に、2インチのサファイアウェーハを3枚貼り合わせた。250℃で24時間の熱処理を行った後、イオン注入界面より楔を挿入して機械的剥離を行った。
得られた複合ウェーハにおいて、シリコン薄膜はサファイアウェーハ上に転写されていることが確認できた。この結果から、シリコンウェーハへの面取り加工の欠如は、転写されるシリコン薄膜に影響を与えないことが示された。
酸化膜を50nm成長させ、水素イオンをドーズ量7.0×1016atoms/cm2、加速電圧50KeVのエネルギーで注入した、面取り加工を行わなかった4インチのシリコンウェーハ上に、2インチのサファイアウェーハを2枚貼り合わせた。250℃で24時間の熱処理を行った後、サファイアウェーハ側から強力な可視光を照射することによって、イオン注入界面からシリコン薄膜を剥離転写させた。可視光の光源は、RTA、グリーンレーザー光、及びフラッシュランプ光を用いた。
全ての光源において、シリコン薄膜はサファイアウェーハ上に問題なく転写されたことが確認できた。この結果から、シリコンウェーハへの面取り加工の欠如は、転写されるシリコン薄膜に影響を与えないことが示された。
酸化膜をCVD法によって50nm成膜させ、水素イオンをドーズ量9.8×1016atoms/cm2、加速電圧70KeVのエネルギーで注入した、面取り加工を行わなかった4インチの炭化ケイ素ウェーハ上に、2インチのサファイアウェーハを3枚貼り合わせた。250℃で24時間の熱処理を行った後、イオン注入界面より楔を挿入して機械的剥離を行った。
得られた複合ウェーハにおいて、シリコン薄膜はサファイアウェーハ上に転写されていることが確認できた。この結果から、シリコンウェーハへの面取り加工の欠如は、転写されるシリコン薄膜に影響を与えないことが示された。
11s、12s 表面
13 ドナーウェーハ
13s 表面
13B 薄膜
13b 貼り合わされていない薄膜部分
14 水素イオン注入層
15 貼り合わせウェーハ
16、17 複合ウェーハ
21 ハンドルウェーハ
22 ドナーウェーハ
Claims (10)
- 少なくとも2枚のハンドルウェーハの直径の合計と同じか大きい直径を有するドナーウェーハの表面から水素イオンを注入して内部に水素イオン注入層を形成させた該ドナーウェーハの該表面と、前記少なくとも2枚のハンドルウェーハの表面とを貼り合わせて、貼り合わせウェーハを得る工程と、
前記貼り合わせウェーハに、温度が200~400℃の熱処理を施す工程と、
前記熱処理後、前記水素イオン注入層に沿って前記ハンドルウェーハ上の薄膜を剥離し、該ハンドルウェーハ上に該薄膜が転写された複合ウェーハを得る剥離転写工程と、
を少なくとも含む複合ウェーハの製造方法。 - 前記ドナーウェーハの直径が6~12インチであり、前記少なくとも2枚のハンドルウェーハのそれぞれの直径が2~6インチである請求項1に記載の複合ウェーハの製造方法。
- 前記ドナーウェーハの前記表面と前記ハンドルウェーハの前記表面のうちいずれか一方又は両方の表面に表面活性化処理を施す請求項1又は2に記載の複合ウェーハの製造方法。
- 前記ドナーウェーハ及び前記ハンドルウェーハが、それぞれシリコンウェーハ、酸化膜付きシリコンウェーハ、ガラス、石英、サファイア、炭化ケイ素又は窒化ガリウムのいずれかである請求項1~3のいずれかに記載の複合ウェーハの製造方法。
- 前記ドナーウェーハが、シリコンウェーハ又は酸化膜付きシリコンウェーハであり、前記ハンドルウェーハが、ガラス、石英又はサファイアである請求項4に記載の複合ウェーハの製造方法。
- 前記ドナーウェーハ又は前記ハンドルウェーハのうち少なくとも一方が透明ウェーハであり、前記剥離転写工程が、前記透明ウェーハ側から可視光を照射することを含む請求項1~5のいずれかに記載の複合ウェーハの製造方法。
- 前記可視光の光源が、RTA、レーザー又はフラッシュランプ光である請求項6に記載の複合ウェーハの製造方法。
- 前記ハンドルウェーハがガラス、石英又はサファイアであり、前記剥離転写工程が、前記ハンドルウェーハ側から可視光を照射することを含む請求項1~7のいずれかに記載の複合ウェーハの製造方法。
- 前記ハンドルウェーハがガラス、石英又はサファイアであり、前記剥離転写工程が、前記水素イオン注入層に機械的衝撃を与えることを含む請求項1~7のいずれかに記載の複合ウェーハの製造方法。
- 前記ハンドルウェーハがガラス、石英又はサファイアであり、前記剥離転写工程が、前記水素イオン注入層に予めへき開用部材を接触させ、前記ハンドルウェーハ側から可視光を照射すると同時に機械的衝撃を与えることを含む請求項1~7のいずれかに記載の複合ウェーハの製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/343,515 US9312166B2 (en) | 2011-09-15 | 2012-09-14 | Method for manufacturing composite wafers |
KR1020147004547A KR101952982B1 (ko) | 2011-09-15 | 2012-09-14 | 복합 웨이퍼의 제조 방법 |
EP12832334.2A EP2757574B1 (en) | 2011-09-15 | 2012-09-14 | Method for manufacturing composite wafer |
CN201280045025.2A CN103828021B (zh) | 2011-09-15 | 2012-09-14 | 制造复合晶片的方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011-201790 | 2011-09-15 | ||
JP2011201790A JP5417399B2 (ja) | 2011-09-15 | 2011-09-15 | 複合ウェーハの製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2013039200A1 true WO2013039200A1 (ja) | 2013-03-21 |
Family
ID=47883416
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2012/073629 WO2013039200A1 (ja) | 2011-09-15 | 2012-09-14 | 複合ウェーハの製造方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US9312166B2 (ja) |
EP (1) | EP2757574B1 (ja) |
JP (1) | JP5417399B2 (ja) |
KR (1) | KR101952982B1 (ja) |
CN (1) | CN103828021B (ja) |
TW (1) | TWI567780B (ja) |
WO (1) | WO2013039200A1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103696022A (zh) * | 2013-12-27 | 2014-04-02 | 贵州蓝科睿思技术研发中心 | 一种离子注入分离蓝宝石的方法 |
CN111910155A (zh) * | 2020-06-30 | 2020-11-10 | 北京航空航天大学合肥创新研究院 | 一种薄膜材料的改性方法及改性薄膜材料 |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10049947B2 (en) * | 2014-07-08 | 2018-08-14 | Massachusetts Institute Of Technology | Method of manufacturing a substrate |
EP3311422A4 (en) | 2015-06-19 | 2019-06-12 | Qmat, Inc. | PROCESS FOR LAYER AND SEPARATION TRANSFER |
FR3041364B1 (fr) * | 2015-09-18 | 2017-10-06 | Soitec Silicon On Insulator | Procede de transfert de paves monocristallins |
CN106992140A (zh) * | 2016-01-20 | 2017-07-28 | 沈阳硅基科技有限公司 | 一种采用激光裂片技术制备soi硅片的方法 |
KR20200005310A (ko) * | 2018-07-06 | 2020-01-15 | 고려대학교 산학협력단 | 하이브리드 불순물 활성화 방법 |
US11450734B2 (en) | 2019-06-17 | 2022-09-20 | Fuji Electric Co., Ltd. | Semiconductor device and fabrication method for semiconductor device |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000036583A (ja) * | 1998-05-15 | 2000-02-02 | Canon Inc | 半導体基板、半導体薄膜の作製方法および多層構造体 |
JP2000294754A (ja) * | 1999-04-07 | 2000-10-20 | Denso Corp | 半導体基板及び半導体基板の製造方法並びに半導体基板製造装置 |
JP2009044136A (ja) * | 2007-07-13 | 2009-02-26 | Semiconductor Energy Lab Co Ltd | 半導体基板の作製方法 |
JP4531694B2 (ja) | 2002-07-17 | 2010-08-25 | エス.オー.アイ.テック、シリコン、オン、インシュレター、テクノロジーズ | 支持体に転移する材料から成る有用な層の面積を拡大する方法 |
JP2010272853A (ja) * | 2009-04-24 | 2010-12-02 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5349207A (en) * | 1993-02-22 | 1994-09-20 | Texas Instruments Incorporated | Silicon carbide wafer bonded to a silicon wafer |
US6054370A (en) * | 1998-06-30 | 2000-04-25 | Intel Corporation | Method of delaminating a pre-fabricated transistor layer from a substrate for placement on another wafer |
JP3822043B2 (ja) * | 2000-09-25 | 2006-09-13 | 太陽誘電株式会社 | チップ部品組立体の製造方法 |
FR2858875B1 (fr) * | 2003-08-12 | 2006-02-10 | Soitec Silicon On Insulator | Procede de realisation de couches minces de materiau semi-conducteur a partir d'une plaquette donneuse |
US7674687B2 (en) * | 2005-07-27 | 2010-03-09 | Silicon Genesis Corporation | Method and structure for fabricating multiple tiled regions onto a plate using a controlled cleaving process |
US8993410B2 (en) * | 2006-09-08 | 2015-03-31 | Silicon Genesis Corporation | Substrate cleaving under controlled stress conditions |
JP5460984B2 (ja) * | 2007-08-17 | 2014-04-02 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
JP5506172B2 (ja) * | 2007-10-10 | 2014-05-28 | 株式会社半導体エネルギー研究所 | 半導体基板の作製方法 |
US8093136B2 (en) | 2007-12-28 | 2012-01-10 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate |
US20090166654A1 (en) * | 2007-12-31 | 2009-07-02 | Zhiyin Gan | Light-emitting diode with increased light efficiency |
KR20090106822A (ko) * | 2008-04-07 | 2009-10-12 | 삼성전자주식회사 | 웨이퍼 본딩 방법 및 그 방법에 의해 본딩된 웨이퍼 구조체 |
EP2157602A1 (en) * | 2008-08-20 | 2010-02-24 | Max-Planck-Gesellschaft zur Förderung der Wissenschaften e.V. | A method of manufacturing a plurality of fabrication wafers |
JP5389627B2 (ja) * | 2008-12-11 | 2014-01-15 | 信越化学工業株式会社 | ワイドバンドギャップ半導体を積層した複合基板の製造方法 |
US9023729B2 (en) * | 2011-12-23 | 2015-05-05 | Athenaeum, Llc | Epitaxy level packaging |
-
2011
- 2011-09-15 JP JP2011201790A patent/JP5417399B2/ja active Active
-
2012
- 2012-09-14 TW TW101133776A patent/TWI567780B/zh active
- 2012-09-14 CN CN201280045025.2A patent/CN103828021B/zh active Active
- 2012-09-14 KR KR1020147004547A patent/KR101952982B1/ko active IP Right Grant
- 2012-09-14 EP EP12832334.2A patent/EP2757574B1/en active Active
- 2012-09-14 US US14/343,515 patent/US9312166B2/en active Active
- 2012-09-14 WO PCT/JP2012/073629 patent/WO2013039200A1/ja active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000036583A (ja) * | 1998-05-15 | 2000-02-02 | Canon Inc | 半導体基板、半導体薄膜の作製方法および多層構造体 |
JP2000294754A (ja) * | 1999-04-07 | 2000-10-20 | Denso Corp | 半導体基板及び半導体基板の製造方法並びに半導体基板製造装置 |
JP4531694B2 (ja) | 2002-07-17 | 2010-08-25 | エス.オー.アイ.テック、シリコン、オン、インシュレター、テクノロジーズ | 支持体に転移する材料から成る有用な層の面積を拡大する方法 |
JP2009044136A (ja) * | 2007-07-13 | 2009-02-26 | Semiconductor Energy Lab Co Ltd | 半導体基板の作製方法 |
JP2010272853A (ja) * | 2009-04-24 | 2010-12-02 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法 |
Non-Patent Citations (1)
Title |
---|
See also references of EP2757574A4 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103696022A (zh) * | 2013-12-27 | 2014-04-02 | 贵州蓝科睿思技术研发中心 | 一种离子注入分离蓝宝石的方法 |
CN103696022B (zh) * | 2013-12-27 | 2016-04-13 | 贵州蓝科睿思技术研发中心 | 一种离子注入分离蓝宝石的方法 |
CN111910155A (zh) * | 2020-06-30 | 2020-11-10 | 北京航空航天大学合肥创新研究院 | 一种薄膜材料的改性方法及改性薄膜材料 |
CN111910155B (zh) * | 2020-06-30 | 2022-05-31 | 北京航空航天大学合肥创新研究院 | 一种薄膜材料的改性方法及改性薄膜材料 |
Also Published As
Publication number | Publication date |
---|---|
EP2757574B1 (en) | 2016-03-02 |
US9312166B2 (en) | 2016-04-12 |
TW201327627A (zh) | 2013-07-01 |
JP2013065589A (ja) | 2013-04-11 |
US20140308800A1 (en) | 2014-10-16 |
JP5417399B2 (ja) | 2014-02-12 |
KR101952982B1 (ko) | 2019-02-27 |
EP2757574A4 (en) | 2015-03-11 |
EP2757574A1 (en) | 2014-07-23 |
TWI567780B (zh) | 2017-01-21 |
CN103828021A (zh) | 2014-05-28 |
KR20140060292A (ko) | 2014-05-19 |
CN103828021B (zh) | 2016-05-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5417399B2 (ja) | 複合ウェーハの製造方法 | |
KR101575917B1 (ko) | 실리콘 박막 전사 절연성 웨이퍼의 제조 방법 | |
JP5415129B2 (ja) | 貼り合わせ基板の製造方法 | |
WO2010128666A1 (ja) | 貼り合わせウェーハの製造方法 | |
KR101335713B1 (ko) | 접합 기판의 제조방법 및 접합 기판 | |
JP5926527B2 (ja) | 透明soiウェーハの製造方法 | |
JP2008153411A (ja) | Soi基板の製造方法 | |
JP2006210898A (ja) | Soiウエーハの製造方法及びsoiウェーハ | |
JP2010186992A (ja) | 高温貼り合わせ法による貼り合わせウェーハの製造方法 | |
JP5465830B2 (ja) | 貼り合わせ基板の製造方法 | |
WO2007074551A1 (ja) | Soiウェーハの製造方法及びsoiウェーハ | |
KR20070084075A (ko) | 반도체 웨이퍼의 제조방법 | |
JP2010278340A (ja) | 貼り合わせウェーハの製造方法 | |
KR20090042139A (ko) | 반도체 기판의 제조 방법 | |
JP2006202989A (ja) | Soiウエーハの製造方法及びsoiウェーハ | |
JP2009253184A (ja) | 貼り合わせ基板の製造方法 | |
WO2010137683A1 (ja) | Soi基板の製造方法 | |
JP2008263010A (ja) | Soi基板の製造方法 | |
WO2010147081A1 (ja) | Ge膜付きSOI基板の製造方法及びGe膜付きSOI基板 | |
KR20090107919A (ko) | 접합 기판의 제조 방법 | |
JP6117134B2 (ja) | 複合基板の製造方法 | |
KR20090043109A (ko) | 이온 주입에 의한 ion-cut기술 및 웨이퍼 접합기술을 이용한 실리콘 웨이퍼 상의 단결정 GaAs박막제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 12832334 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 20147004547 Country of ref document: KR Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2012832334 Country of ref document: EP |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
WWE | Wipo information: entry into national phase |
Ref document number: 14343515 Country of ref document: US |