WO2013039099A1 - 半導体装置の製造方法およびその製造方法を用いて製造した半導体装置 - Google Patents
半導体装置の製造方法およびその製造方法を用いて製造した半導体装置 Download PDFInfo
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Abstract
Description
図9において、放熱ベース51上に半田52を載置し、その上に導電パターン付絶縁基板69を載置する。この導電パターン付絶縁基板69はセラミックなどの絶縁基板54の裏面に裏面導電膜53が形成され表面には導電パターン55が形成されている。続いて、この導電パターン付絶縁基板69の導電パターン55上に半田56を載置し、その上にIGBTチップ57aの図示しないコレクタ電極を下に、FWDチップ57bの図示しないカソード電極を下にして載置する。続いて、IGBTチップ57aの図示しないエミッタ電極とFWDチップ57bの図示しないアノード電極にそれぞれ半田58を載置する。続いて、半田58上にエミッタ下側端子60を載置する。また、導電パターン付絶縁基板69の導電パターン55上に半田59を載置し、半田59上にコレクタ下側端子61を載置する。続いて、この状態で加熱し、各半田52,56,58,59を溶融させた後、冷却・再凝固させて、各部材を半田52,56,58,59を介して固着し一体とする。ここでは、溶融前、溶融中、固化後の半田について同一の符号を付した。
図10の工程において、上下端子60,62間に隙間を生じた場合には図13に示すように荷重73を掛けてこの隙間Pを無くして上下端子60,62を密着させる。
また、十分な接合強度を確保するために複数点の溶接を実施するとモジュールの製造コストが増加する。
また、請求の範囲第9項に記載の発明によれば、第1項~第8項のいずれか一項に記載の半導体装置の製造方法を用いて製造された半導体装置であって、レーザ溶接部近傍の上側端子と下側端子の間に隙間が存在する半導体装置とする。
これにより溶接点数(溶接箇所数)を削減することができ、製造コストを低減することができる。
<実施例1>
図1~図4は、この発明の第1実施例の半導体装置の製造方法を工程順に示した要部製造工程断面図である。ここでは半導体装置としてパワー半導体モジュールを例に挙げた。
図5は、上下端子間の隙間と接合強度の関係を示す図である。この図は実験で得られたデータである。
また、部品の寸法公差および組立公差によって上下端子間に隙間Lが生じた場合でも、この隙間Lが、20μm以上で400μm以下であれば、接合強度を高めることができる。そのため部品の寸法公差および組立公差を大きくできて、組立性が向上し、生産性が上がるため製造コストを低減することができる。上下端子間の隙間Lの下限を50μmとする場合についても、100μmとする場合についても、もとの部品の寸法公差や組立公差をさらに大きくとることができる。
しかし本発明では、図3や図4に見られるように、レーザ溶接する溶接部16の上側端子12と下側端子10との間や、レーザ溶接する溶接部16の上側端子13と下側端子11との間は、閉じられた空間ではなく開放された空間になっていてレーザの熱で溶接部付近の気体が熱せられても上側端子と下側端子との間から気体が逃げて気体圧力による部材の変形が生ずることもない。また、溶融部内のボイド発生が起こりにくい。
また、上側端子12と下側端子10の間の隙間Lを20μm以上で400μm以下に確保できれば、上下端子12は必ずしも下側端子10に対して平行に配置されなくてもよい。このように、上側端子12と下側端子10の間の隙間Lを20μm以上で400μm以下に確保できればよいため、組立公差に余裕が出てきて、従来の10μmの隙間Mが要求される場合に比べて組立性が向上する。
<実施例2>
図8は、この発明の第2実施例の半導体装置の要部断面図である。この図はレーザ溶接を2箇所で行った後の上下端子10,12の断面図である。この半導体装置は実施例1の製造方法を用いて製造される。溶接部16近傍の上下端子間の隙間Kは350μm以下である。溶接前の上下端子間の隙間Lが50μm~80μm以下の場合に溶接後の上下端子間の隙間Kは0μmとなり隙間Kは形成されない。
2,6,8,9 半田
3 裏面導電膜
4 絶縁基板
5 導電パターン
7a IGBTチップ
7b FWDチップ
10 エミッタ下側端子(下側端子)
10a,12a バリ部
11 コレクタ下側端子(下側端子)
12 エミッタ上側端子(上側端子)
13 コレクタ上側端子(上側端子)
14 樹脂ケース
15 接着剤
16 溶接部
17 レーザ光
18 封止材
19 導電パターン付絶縁基板
21 段差部
22 隙間形成部品
L 隙間(レーザ溶接前、レーザ溶接中)
K 隙間(レーザ溶接後)
Claims (10)
- 半導体装置の内部配線部材である上側端子と下側端子の接合にレーザ溶接を用いる半導体装置の製造方法において、下側端子に上側端子をレーザ溶接で固着する際に、前記下側端子の上面と前記上側端子の下面の間の隙間を20μm以上で、400μm以下とすることを特徴とする半導体装置の製造方法。
- 前記上側端子の裏面に段差部を設け、該上側端子の段差部が形成されない裏面と前記下側端子の上面を密着させて、前記段差部で隙間を設け、前記上側端子の段差部直上の表面にレーザ光を照射して上側端子と下側端子をレーザ溶接する半導体装置の製造方法であって、前記段差部で形成される隙間を20μm以上で、400μm以下とすることを特徴とする請求の範囲第1項に記載の半導体装置の製造方法。
- 前記下側端子の上面に段差部を設け、該下側端子の段差部が形成されない上面と前記上側端子の裏面を密着させて、前記段差部で隙間を設け、該段差部の直上の上側端子の表面にレーザ光を照射して上側端子と下側端子をレーザ溶接する半導体装置の製造方法であって、前記段差部で形成される隙間を20μm以上で、400μm以下とすることを特徴とする請求の範囲第1項に記載の半導体装置の製造方法。
- 前記上側端子の裏面外周部にバリ部を設け、該上側端子の裏面のバリ部の先端部と前記下側端子の上面を密着させて隙間を設け、該隙間上の上側端子の表面にレーザ光を照射して上側端子と下側端子をレーザ溶接する半導体装置の製造方法であって、前記バリ部で形成される隙間を20μm以上で、400μm以下とすることを特徴とする請求の範囲第1項に記載の半導体装置の製造方法。
- 前記下側端子の上面外周部にバリ部を設け、該下側端子の上面のバリ部の先端部と前記上側端子の裏面を密着させて隙間を設け、該隙間上の上側端子の表面にレーザ光を照射して上側端子と下側端子をレーザ溶接する半導体装置の製造方法であって、前記バリ部で形成される隙間を20μm以上で、400μm以下とすることを特徴とする請求の範囲第1項に記載の半導体装置の製造方法。
- 導電パターン付絶縁基板と、該導電パターン付絶縁基板上に固着する半導体チップと、該半導体チップもしくは前記導電パターン付絶縁基板上に固着する下側端子と、該下側端子にレーザ溶接される上側端子とを有する半導体装置の製造方法において、前記下側端子もしくは導電パターン付絶縁基板上に隙間確保部材を配置し、該隙間確保部材上に上側端子を配置し、前記レーザ溶接される箇所の前記上下端子間の隙間を20μm以上で、400μm以下とすることを特徴とする半導体装置の製造方法。
- 前記隙間確保部材を隙間形成部品とし、該隙間形成部品を前記下側端子上に固着し、該隙間形成部品で上側端子を固定し、上下端子間の隙間を20μm以上で、400μm以下とすることを特徴とする請求の範囲第6項に記載の半導体装置の製造方法。
- 前記隙間確保部材が隙間を形成するためのスペーサであることを特徴とする請求の範囲第6項に記載の半導体装置の製造方法。
- 前記請求の範囲第1項~第8項のいずれか一項に記載の半導体装置の製造方法を用いて製造された半導体装置であって、レーザ溶接部近傍の上側端子と下側端子の間に隙間が存在することを特徴とする半導体装置。
- 前記隙間が350μm以下であることを特徴とする請求の範囲第9項に記載の半導体装置。
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