WO2013021477A1 - Procédé de fabrication de substrats de circuit - Google Patents

Procédé de fabrication de substrats de circuit Download PDF

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Publication number
WO2013021477A1
WO2013021477A1 PCT/JP2011/068243 JP2011068243W WO2013021477A1 WO 2013021477 A1 WO2013021477 A1 WO 2013021477A1 JP 2011068243 W JP2011068243 W JP 2011068243W WO 2013021477 A1 WO2013021477 A1 WO 2013021477A1
Authority
WO
WIPO (PCT)
Prior art keywords
metal foil
main
hole
prepreg
forming
Prior art date
Application number
PCT/JP2011/068243
Other languages
English (en)
Japanese (ja)
Inventor
秀吉 瀧井
典明 種子
高木　剛
Original Assignee
株式会社メイコー
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社メイコー filed Critical 株式会社メイコー
Priority to PCT/JP2011/068243 priority Critical patent/WO2013021477A1/fr
Priority to TW101126558A priority patent/TW201320849A/zh
Publication of WO2013021477A1 publication Critical patent/WO2013021477A1/fr

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
    • H05K1/0206—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0263—High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board
    • H05K1/0265—High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board characterized by the lay-out of or details of the printed conductors, e.g. reinforced conductors, redundant conductors, conductors having different cross-sections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/094—Array of pads or lands differing from one another, e.g. in size, pitch, thickness; Using different connections on the pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/063—Lamination of preperforated insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1572—Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/421—Blind plated via connections

Definitions

  • the present invention relates to a circuit board manufacturing method, and more particularly to a circuit board manufacturing method having a heat dissipation path for heat dissipation.
  • High heat generation type circuit boards such as circuit boards on which electrical or electronic components with a large amount of heat are mounted and circuit boards for large currents where large currents flow through the circuit, have a heat dissipation path that dissipates the generated heat.
  • This type of heat dissipation path generally includes a thermal via, which covers the through hole penetrating from one surface of the circuit board to the other surface and the inner wall surface of the through hole and the both surfaces of the circuit board. And a metal material connected to the wiring pattern.
  • a circuit board including such a thermal via for example, even if the component mounted on one surface of the circuit board generates heat, the heat is transmitted to the other surface of the circuit board through the thermal via. The heat is dissipated.
  • the through hole is filled with a metal paste to further improve the heat dissipation efficiency.
  • a technique of filling the through hole provided in the circuit board with the metal paste for example, see Patent Document 1 is used.
  • the method of filling the through hole of the circuit board of Patent Document 1 with the metal paste is as follows. First, through holes are provided in a circuit board having wiring patterns on both sides. Thereafter, a metal paste containing a required metal powder is prepared, and this metal paste is pushed into the through hole with a roll or a piston. At this time, by applying ultrasonic vibration to the circuit board at the same time, the metal paste can easily flow and the metal paste can easily enter the through hole. In this way, the metal paste is filled into the through hole.
  • the metal paste may not be completely filled in the through holes, and the desired heat dissipation efficiency may not be obtained with certainty.
  • An object of the present invention is to provide a manufacturing method that enables rapid manufacture of a circuit board having a heat dissipation function without requiring a separate manufacturing process for securing only a heat dissipation path.
  • an insulating substrate, a first wiring pattern formed on one surface of the insulating substrate, a second wiring pattern formed on the other surface, and the first and first wiring patterns are provided in the insulating substrate.
  • a circuit board manufacturing method comprising a heat radiation path made of a metal column that thermally connects two wiring patterns, wherein first and second supporting substrates are prepared, and the first supporting substrate is provided with the first supporting substrate.
  • the first and second support substrates are arranged, and the columnar body Forming the insulating substrate sandwiched between the first metal foil and the second metal foil and having the columnar body embedded therein while the first bump and the second bump are abutted with each other to form And laminating the both sides of the insulating substrate with the first and second metal foils interposed therebetween to form a laminate, and peeling the first and second carrier substrates from the laminate. And a pattern forming step of forming the first and second metal foils on the first and second wiring patterns after exposing the first and second metal foils, respectively.
  • a circuit board manufacturing method is provided.
  • the laminating step is a plate-like main prepreg having one main through-hole into which the first and second bumps are to be inserted, and prepares a main prepreg containing uncured insulating resin,
  • the first and second support substrates on both sides of the main prepreg
  • the first and second bumps are integrated to form the columnar body, and the main prepreg It is preferable to form the insulating substrate in which the columnar body is embedded by flowing the insulating resin.
  • the bump forming step is a thick conductor for providing a thick wiring pattern thicker than the first wiring pattern by a formation method similar to the formation method of the first bump on the first metal foil.
  • the laminating step includes a main prepreg having a part of the main through hole and a remaining part of forming the main through hole in cooperation with the part of the main through hole.
  • Sub-prepregs each having a main through-hole and a sub-through-hole into which the thick conductor is to be inserted, further comprising a sub-prepreg containing uncured insulating resin, for pressing the first and second supporting substrates Prior to disposing the first and second supporting substrates to sandwich the sub-prepreg and the main prepreg between the first metal foil and the second metal foil, It is preferable to insert the thick conductor sub through hole.
  • the first and second bumps are brought into contact with each other through the main through hole of the prepreg to form a metal columnar body, thereby thermally radiating the first wiring pattern and the second wiring pattern.
  • a route is secured. Since this heat dissipation path is not formed by a manufacturing process separately provided in the manufacturing process of the circuit board, rapid manufacturing of the entire circuit board can be realized.
  • a heat radiation path having a desired diameter can be easily formed without being limited by the hole diameter, as compared with filling the through hole or the like with a metal paste. Further, compared with the case where the through hole is filled with a metal paste, the work efficiency due to the number of holes does not decrease.
  • the wiring pattern in the portion where the thick conductor exists can be partially thickened, and a large current can flow in this portion.
  • the heat dissipation path can be easily secured even in the large current substrate.
  • the stacking process can be easily and quickly performed.
  • first and second carrier substrates 14 and 36 are prepared, and the first metal foil 8 on which the first wiring pattern 6 is to be formed is formed on the first carrier substrate 14, while the second carrier substrate is formed.
  • a second metal foil 38 on which the second wiring pattern 62 is to be formed is formed on 36 (preparation step).
  • a first carrier substrate 14 is prepared.
  • the first carrier substrate 14 is a thin plate made of, for example, stainless steel.
  • a first metal foil 8 is formed on the first carrier substrate 14.
  • the first metal foil 8 is made of, for example, a copper plating film obtained by electrolytic plating.
  • the copper-clad steel plate 16 which consists of a stainless steel plate with one surface covered with copper foil is obtained.
  • a surface in contact with the first carrier substrate 14 is a first surface 18, and a surface opposite to the first surface 18 is a second surface 20.
  • metal first and second bumps 10 and 30 having substantially half the height of the columnar body 4 are formed on the first and second metal foils 8 and 38 by plating (bump forming step), respectively.
  • metallic first bumps 10 are formed on the first metal foil 8 to be formed on the first wiring pattern 6 of the circuit board 2.
  • the second surface 20 of the first metal foil 8 of the copper-clad steel plate 16 is covered with a plating resist 22 made of a dry film having a predetermined thickness.
  • the plating resist 22 is provided with a bump formation hole 24 that reaches the second surface 20 of the first metal foil 8 at a predetermined position.
  • the bump formation hole 24 is a hole used for forming the first bump 10 to be a part of the heat dissipation path, and one opening end 23 is closed by the first metal foil 8, and the other The opening end 25 of the plating resist 22 is open to the exposed surface 34 opposite to the contact surface 35 of the plating resist 22 with the first metal foil 8.
  • the plating resist 22 is formed on the mask layer 26 that exposes the first metal foil 8 in the bump forming hole 24 and covers the other portion of the first metal foil 8 (FIG. 1D). )).
  • the bump formation hole 24 is formed at a site to be a heat dissipation path in the future by a known photoetching method, laser processing method, or the like. At least one bump forming hole 24 (four in FIG. 1D) is formed. At this time, the diameter of the bump formation hole 24 can be arbitrarily set according to the diameter of the heat dissipation path.
  • the first metal foil 8 is formed at a predetermined position on the second surface 20 of the first metal foil 8 by removing the mask layer 26 (FIG. 1F). In this way, the first metal foil 8 having the first bump 10 is obtained.
  • the first metal foil 8 is supported on a stainless steel plate as the first supporting substrate 14.
  • the second bump 30 is formed on the second metal foil 38 in parallel with or after the formation of the first bump 10.
  • the procedure for forming the second bump is shown in FIGS. 1G to 1L and is basically the same as the procedure for forming the first bump. That is, a mask layer 44 obtained by processing a plating resist 42 is formed on a copper-clad steel plate 40 in which a copper foil (second metal foil 38) is formed on a stainless steel plate (second support substrate 36), and bumps of the mask layer 44 are formed. Copper plating is performed on the portion of the formation hole 46 to form a copper pillar, and the second bump 30 is obtained. However, when the mask layer 44 is formed, the bump formation hole 46 is provided at a position facing the first bump 10.
  • first and second supporting substrates 14 and 36 are arranged so that the first metal foil 8 and the second metal foil 38 face each other, and the first bump 10 and the second bump are formed to form the columnar body 4. 30, and an insulating substrate 58 sandwiched between the first metal foil 8 and the second metal foil 38 and having the columnar body 4 embedded therein.
  • a laminated body 60 is formed in which the carrier substrates 14 and 36 are overlaid via the second metal foils 8 and 38 (lamination process).
  • first and second metal foils 8 and 38 carried on the first and second carrying substrates 14 and 36 are first formed into the first bump 10 and the second bump.
  • the second surfaces 20 and 50 having the bumps 30 are opposed to each other with the main prepreg 52 interposed therebetween.
  • the main prepreg 52 has, for example, a plate shape in which a glass fiber is impregnated with an uncured thermosetting resin.
  • the main prepreg 52 has a main through hole 54 as shown in FIG.
  • the main through hole 54 is provided at a predetermined position where the first bump 10 can be inserted from one side and the second bump 30 can be inserted from the other side. Yes.
  • the alignment of the first and second metal foils 8 and 38 supported on the first and second support substrates 14 and 36 and the main prepreg 52 is performed using, for example, a pin lamination method.
  • the first and second bumps 10 and 30 are placed on the main prepreg 50. While being inserted into the main through hole 54, the first and second carrier substrates 14 and 36 are pressed toward each other and the whole is heated.
  • the first bump 10 and the second bump 30 have the top portions 28 and 56 abutted against each other and thermocompression bonded, and the columnar body 4 connecting the first metal foil 8 and the second metal foil 38 to each other.
  • the columnar body 4 is used as a heat dissipation path in the circuit board 2.
  • the first and second bumps 10 and 30 are integrated by collapsing and deforming the top portions 28 and 56, so that the columnar body 4 having high heat radiation efficiency is obtained. be able to.
  • this columnar body 4 is the same also about conduction
  • the uncured thermosetting resin of the main prepreg 52 is pressed and flows, spread around the columnar body 4, and the like between the through hole 54 and the columnar body 4. Meet. Thereafter, such a thermosetting resin is cured by being heated. As a result, the main prepreg 52 is formed on the insulating substrate 58 in which the columnar body 4 is embedded.
  • first and second metal foils 8 and 38 are formed on the first and second wiring patterns 6 and 62, respectively (pattern forming step).
  • the first and second support substrates 14 and 36 are peeled off from the first metal foil 8 and the second metal foil 38, respectively, and the first metal foil 8 and the first metal foil 8 The first surfaces 18 and 48 of the two metal foils 38 are exposed.
  • wiring patterns 6 and 38 are formed on the first metal foil 8 and the second metal foil 38 by using a normal etching method. Specifically, an etching resist is applied to the portions of the first metal foil 8 and the second metal foil 38 that are to be left as wiring, and unnecessary portions are removed by etching, thereby forming wiring patterns 6 and 62 having a predetermined shape. (FIG. 2 (c)). Then, in the obtained wiring patterns 6 and 62, only the portions that require soldering are exposed, and the solder resist layer 64 is formed so that the solder does not adhere to the portions that do not require soldering.
  • the insulating substrate 58, the first and second wiring patterns 6, 62 having a predetermined shape formed on the front and back surfaces of the insulating substrate 58, and the first and second wiring patterns 6 built in the insulating substrate 58 are provided.
  • 62 is obtained as a circuit board 2 provided with a copper columnar body 4 as a heat radiation path (FIG. 2D).
  • the circuit board 2 provided with the heat dissipation path obtained in this way is then mounted with electronic components or processed according to the board shape to be used.
  • the first metal foil 8 and the second metal foil 38 are opposed to each other with the main prepreg 52 interposed therebetween.
  • the first and second bumps 10 and 30 of the first and second metal foils 8 and 38 are abutted and integrated with each other through the main through hole 54 of the main prepreg 52, the first wiring pattern 6 and the second wiring
  • the columnar body 4 connecting the pattern 62 is secured as a heat dissipation path. Since this heat dissipation path is not formed by a manufacturing process separately provided in the manufacturing process of the circuit board 2, the entire circuit board can be quickly manufactured.
  • a heat dissipation path having a desired diameter can be easily formed without being limited by the hole diameter, as compared with the conventional method of filling the through hole with a metal paste.
  • the bumps 10 and 30 to be the columnar bodies 4 are formed by plating, even if the number of heat dissipation paths is increased, a large number of bumps can be formed by plating at the same time, and a reduction in work efficiency is suppressed.
  • the columnar body 4 can be used not only for the purpose of heat dissipation but also as a means for achieving conduction between the wiring patterns on both sides.
  • a thick conductor 72 for providing a thick wiring pattern thicker than the first wiring pattern 6 is further formed in the bump forming process by the same formation method as that of the first bump 10.
  • a thick conductor forming hole 74 for the thick conductor 72 is further formed in a predetermined portion where the thick conductor 72 is to be formed in the plating resist layer 22 shown in FIG. ))
  • Plating is performed on the thick conductor formation hole 74 for the thick conductor 72 simultaneously with the bump formation hole 24 for the first bump 10, and the thick conductor 72 is formed in the same manner as the first bump 10.
  • the thick conductor 72 is provided along the wiring through which a large current flows in the first wiring pattern 6 formed on the surface of the circuit board 70. That is, the thick conductor 72 is formed on a portion of the first metal foil 8 that should be a wiring pattern through which a large current flows. As a result, in the first wiring pattern 6, a portion where the thick conductor 72 exists is locally thick, and the portion becomes a thick wiring pattern, so that a large current can flow.
  • the first metal foil 8 in which the thick conductor 72 is formed in addition to the first bump 10 is obtained (FIG. 3F). Since the thick conductor 72 is different from the first bump 10, the second bump 30 is not provided on the second metal foil 38 at a position facing the thick conductor 72.
  • a main prepreg 52 provided with a partial main through hole 55 that forms a part of the main through hole 54 at a position corresponding to each of the first and second bumps 10 and 30 is prepared.
  • a sub-prepreg provided with a sub through hole 78 into which the thick conductor 72 is to be inserted at a position corresponding to the remaining main through hole 57 and the thick conductor 72 that form the main through hole 54 in cooperation with the main through hole 55. 76 is prepared. These two prepregs 52 and 76 are disposed between the first and second metal foils 8 and 38.
  • the sub-prepreg 76 is arranged on the metal foil side on which the thick conductor 72 is formed, that is, on the first metal foil 8 side in this embodiment (FIG. 3 (m)).
  • the first and second support substrates 14 and 36 are pressed in a direction approaching each other, and the whole is heated.
  • the thick conductor 72 is embedded in the insulating substrate 58 (FIG. 4A).
  • the first and second carrier boards 14 and 36 are peeled off (FIG. 4B), and the first and second wiring patterns 6 and 62 are formed (FIG. 4C).
  • a solder resist layer 64 is formed (FIG. 4D).
  • the circuit board 70 for large current is manufactured.
  • the circuit board 70 since the thickness of the first metal foil 8 (copper foil) on the surface is not different from the conventional one, even if a thick thick conductor 72 is formed in the insulating substrate 58 for a large current, it is fine. A simple wiring pattern can be formed. Further, by using the sub prepreg 76 in which the sub through holes 78 are formed at positions corresponding to the thick conductors 72, the laminating process can be performed easily and quickly.
  • the circuit board 70 has the same structure, operation, and effects as those of the circuit board 2.
  • Circuit board 4 Columnar body (heat dissipation path) 6 1st wiring pattern 8 1st metal foil 10 1st bump 14 1st support substrate 24 bump formation hole 26 mask layer 28 top 30 2nd bump 36 2nd support substrate 38 2nd metal foil 44 mask layer 46 bump formation hole 52 Main prepreg 54 Main through hole 62 Second wiring pattern 70 Circuit board 72 Thick conductor 74 Thick conductor forming hole 78 Sub through hole

Abstract

L'invention concerne un procédé de fabrication de substrats de circuit, comportant : une étape de préparation consistant à former une première feuille métallique (8) sur un premier substrat porteur (14) et à former une deuxième feuille métallique (38) sur un deuxième substrat porteur (36) ; une étape de formation de bosses consistant à former respectivement des première et deuxième bosses métalliques (21, 38) sur les première et deuxième feuilles métalliques par plaquage ; une étape de stratification consistant à placer les premières bosses (21) et les deuxièmes bosses (38) face à face pour former des corps colonnaires (4), à former un substrat (58) d'isolation pris en sandwich entre la première feuille métallique et la deuxième feuille métallique et dans lequel les corps colonnaires (4) sont encastrés, et à former un corps stratifié (60) caractérisé en ce que les substrats porteurs sont en chevauchement respectif via les première et deuxième feuilles métalliques de part et d'autre du substrat d'isolation ; et une étape de formation de tracés consistant à détacher les premier et deuxième substrats porteurs (14, 36) du corps stratifié (60), à découvrir les première et deuxième feuilles métalliques (8, 38) et à façonner respectivement les première et deuxième feuilles métalliques pour donner des premier et deuxième tracés (6, 62) de câblage.
PCT/JP2011/068243 2011-08-10 2011-08-10 Procédé de fabrication de substrats de circuit WO2013021477A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/JP2011/068243 WO2013021477A1 (fr) 2011-08-10 2011-08-10 Procédé de fabrication de substrats de circuit
TW101126558A TW201320849A (zh) 2011-08-10 2012-07-24 電路基板之製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2011/068243 WO2013021477A1 (fr) 2011-08-10 2011-08-10 Procédé de fabrication de substrats de circuit

Publications (1)

Publication Number Publication Date
WO2013021477A1 true WO2013021477A1 (fr) 2013-02-14

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ID=47668028

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Application Number Title Priority Date Filing Date
PCT/JP2011/068243 WO2013021477A1 (fr) 2011-08-10 2011-08-10 Procédé de fabrication de substrats de circuit

Country Status (2)

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TW (1) TW201320849A (fr)
WO (1) WO2013021477A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107205313A (zh) * 2016-03-16 2017-09-26 景硕科技股份有限公司 易于测试的多层电路板

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107251667B (zh) 2014-11-28 2019-10-18 英特尔公司 多层印刷布线板的制造方法
CN107466168B (zh) * 2016-06-02 2019-09-20 鹏鼎控股(深圳)股份有限公司 具细线路的电路板及其制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58164290A (ja) * 1982-03-24 1983-09-29 日本電信電話株式会社 マイクロピン付配線基板の製法
JP2001177249A (ja) * 1999-12-16 2001-06-29 Hitachi Ltd 電極構造とその製造方法およびそれを用いた電子回路基板
JP2004281667A (ja) * 2003-03-14 2004-10-07 Yamaichi Electronics Co Ltd 多層配線板の製造方法
JP2010258081A (ja) * 2009-04-22 2010-11-11 Meiko:Kk プリント基板の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58164290A (ja) * 1982-03-24 1983-09-29 日本電信電話株式会社 マイクロピン付配線基板の製法
JP2001177249A (ja) * 1999-12-16 2001-06-29 Hitachi Ltd 電極構造とその製造方法およびそれを用いた電子回路基板
JP2004281667A (ja) * 2003-03-14 2004-10-07 Yamaichi Electronics Co Ltd 多層配線板の製造方法
JP2010258081A (ja) * 2009-04-22 2010-11-11 Meiko:Kk プリント基板の製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107205313A (zh) * 2016-03-16 2017-09-26 景硕科技股份有限公司 易于测试的多层电路板
CN107205313B (zh) * 2016-03-16 2020-01-03 景硕科技股份有限公司 易于测试的多层电路板

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