WO2013011848A1 - Dispositif de mémoire à semi-conducteur - Google Patents

Dispositif de mémoire à semi-conducteur Download PDF

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Publication number
WO2013011848A1
WO2013011848A1 PCT/JP2012/067302 JP2012067302W WO2013011848A1 WO 2013011848 A1 WO2013011848 A1 WO 2013011848A1 JP 2012067302 W JP2012067302 W JP 2012067302W WO 2013011848 A1 WO2013011848 A1 WO 2013011848A1
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Prior art keywords
data
address
selection
signal
external clock
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PCT/JP2012/067302
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English (en)
Japanese (ja)
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佐藤　正幸
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太陽誘電株式会社
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders

Definitions

  • the present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capable of switching between synchronous and asynchronous in a memory cell.
  • synchronous SRAM Static Random Access Memory
  • asynchronous SRAM asynchronous SRAM
  • asynchronous SRAM does not require consideration of clock control, and is not synchronized with the clock signal. Therefore, compared with synchronous SRAM, it can be accessed without considering clock sharing and the like, and data access is easy. It is used as a main storage device for devices such as control devices and measurement systems. However, since the word line can always be accessed from the outside, the reliability is inferior to that of the synchronous SRAM. *
  • a waiting time called latency occurs between the time when a CPU (Central Processing Unit) makes an access request to the memory and when data is sent to the CPU or when writing is completed, and the processing speed of the CPU decreases. It becomes a factor.
  • memory access requests have high locality in the short term, and reading and writing are often performed sequentially in consecutive areas. Using this feature, consecutive addresses are allocated alternately across multiple memory banks, and an access request is issued to the next address during the delay time for accessing certain data, thereby effectively using the time.
  • the technology is called “memory interleaving”. By increasing the number of memory cell blocks (also referred to as “memory banks”) that can be accessed in parallel from the CPU, the latency can be lowered. *
  • Patent Document 1 discloses an interleave type memory that can operate two memory banks each constituting a cell array block as a synchronous SRAM or an asynchronous SRAM.
  • data to be stored is distributed according to the least significant bit (A0) of the address according to “EVEN” or “ODD”.
  • the disclosed interleaved memory uses an ATD (address transition detection) circuit to recognize access by an external address, and a read signal and an address latch enable (ALE) signal indicating "synchronous" or "asynchronous” It recognizes whether the mode requested by the CPU to the memory is asynchronous mode data reading by random access or data reading in synchronous mode by burst access.
  • ATD address transition detection
  • ALE address latch enable
  • the internal address counter uses the ATD signal and the address to be subjected to burst access to generate a sequential internal address by the increment operation, thereby enabling reading of data for the burst access in the synchronous mode.
  • the disclosed interleaved memory enables data reading in either a synchronous mode or an asynchronous mode for a memory bank, and cannot perform synchronous or asynchronous allocation for each data. Therefore, when only certain data is read synchronously or asynchronously, the entire memory bank has to be synchronous or asynchronous.
  • An object of the semiconductor memory according to the embodiment of the present invention is to enable synchronous or asynchronous data reading for each data.
  • a plurality of memory cells each storing data, and an address signal that identifies the memory cell, and 1 of word lines connected to a part of the plurality of memory cells based on the decoded address
  • An address decoder that outputs a word line selection signal for selecting one, a selection unit that holds selection data and selects an external clock supplied from the outside based on the selection data, and the external clock is selected
  • the plurality of memory cells selected based on the word line selection signal without being synchronized with the external clock in synchronization with the selected external clock or when the external clock is not selected.
  • a semiconductor memory device comprising: a data reading unit that reads data from a part of the semiconductor memory device.
  • An address change detection unit that detects a change in an address signal and a clock generation circuit that generates an internal clock are further provided, and the address decoder detects the change in address when the address change detection unit detects an address change.
  • the selection unit outputs a selection signal, the selection unit selects the internal clock based on the selection data, and the data reading unit synchronizes with the internal clock when the external clock is not selected,
  • the semiconductor memory device according to (1), wherein data is read from a part of the plurality of memory cells selected based on the word line selection signal.
  • the address decoder includes: an X address decoder that outputs the word line selection signal; a Y address decoder that decodes the address signal and selects a bit line from which the data is read based on the decoded address;
  • the semiconductor memory device according to (2) comprising: (4) The selection data is held in some memory cells of the memory cell array, and the selection unit selects an external clock supplied from the outside based on the selection data held in the memory cell.
  • the semiconductor memory device according to any one of (1) to (3).
  • An address decoder that outputs a word line selection signal for selecting a signal, a selection unit that holds selection data and selects an external clock supplied from the outside based on the selection data, and the external clock is selected The external clock is synchronized with the selected external clock or when the external clock is not selected.
  • the semiconductor device characterized by without synchronization, and a data reading unit for reading the data for some of the plurality of memory cells selected on the basis of said word line selection signal.
  • An address change detection unit that detects a transition of an address signal and a clock generation circuit that generates an internal clock are further provided.
  • the address decoder selects the word line when the address change detection unit detects an address change.
  • the selection unit selects the internal clock based on the selection data, and the data reading unit synchronizes with the internal clock when the external clock is not selected.
  • the semiconductor device according to (5) wherein data is read from a part of the plurality of memory cells selected based on a word line selection signal.
  • the address decoder includes: an X address decoder that outputs the word line selection signal; a Y address decoder that decodes the address signal and selects a bit line from which the data is read based on the decoded address;
  • the semiconductor device according to (5) or (6).
  • the selection data is held in some memory cells of the memory cell array, and the selection unit selects an external clock supplied from the outside based on the selection data held in the memory cell.
  • the selection data is set to be synchronized with an internal clock when the logic unit operates as a combinational circuit or wiring logic, and is synchronized with an external clock when the logic unit operates as a sequential circuit.
  • the semiconductor device according to (8).
  • the semiconductor memory device can perform synchronous or asynchronous data reading for each data. Since specific data in the SRAM does not make the entire memory cell synchronous or asynchronous, the reliability of the synchronous SRAM and the high speed of the asynchronous SRAM can be provided at the same time.
  • FIG. 1 is a diagram illustrating a first example of a semiconductor memory device according to the present embodiment.
  • FIG. 2 is a detailed example of the memory element.
  • FIG. 3 is a detailed example of the address decoder.
  • FIG. 4 is a diagram illustrating a second example of the semiconductor memory device according to the present embodiment.
  • FIG. 5 is a diagram illustrating a detailed example of the precharge circuit.
  • FIG. 6A is a detailed example of an ATD circuit.
  • FIG. 6B is a time chart of signals flowing through the ATD circuit.
  • FIG. 7 is a diagram illustrating a third example of the semiconductor memory device according to the present embodiment. These are figures which show an example of MPLD which used the semiconductor memory device as MLUT.
  • FIG. 9A is a diagram illustrating an example of an MPLD.
  • FIG. 9B is a diagram illustrating an example of an MPLD memory operation.
  • FIG. 9C is a diagram illustrating an example of the logical operation of the MLUT.
  • FIG. 10 is a diagram illustrating an example of an MLUT.
  • FIG. 11 is a diagram illustrating an example of an MLUT that operates as a logical element.
  • FIG. 12 is a diagram illustrating an example of an MLUT that operates as a logic circuit.
  • FIG. 13 is a diagram showing a truth table of the logic circuit shown in FIG.
  • FIG. 14 is a diagram illustrating an example of an MLUT that operates as a connection element.
  • FIG. 15 is a diagram showing a truth table of the connection elements shown in FIG. FIG.
  • FIG. 16 is a diagram illustrating an example of a connection element realized by an MLUT having four AD pairs.
  • FIG. 17 is a diagram illustrating an example in which one MLUT operates as a logical element and a connection element.
  • FIG. 18 shows a truth table of the logic elements and connection elements shown in FIG.
  • FIG. 19 is a diagram illustrating an example of logical operations and connection elements realized by an MLUT having an AD pair.
  • FIG. 1 is a diagram illustrating a first example of a semiconductor memory device.
  • a semiconductor memory device 100 shown in FIG. 1 includes a memory cell array 110 including memory cells each storing data, an address decoder 120, a selection unit 130 for selecting an external clock supplied from the outside, and selection of an external clock.
  • the data input / output unit 140 is configured to read data from or write data to the memory cell array 110 in accordance with the presence or absence of data.
  • the memory cell array has m ⁇ 2 m memory elements, and the m ⁇ 2 n memory elements are arranged at a connection portion between 2 n word lines and m bit lines.
  • FIG. 2 is a detailed example of the memory element.
  • the storage element 40 shown in FIG. 2 includes pMOS transistors 161 and 162 and nMOS transistors 163, 164, 165, and 166.
  • the source of the pMOS transistor 161 and the source of the pMOS transistor 162 are connected to VDD (power supply voltage terminal).
  • the drain of the nMOS transistor 163 and the drain of the nMOS transistor 164 are connected to VSS (ground voltage terminal).
  • the drain of the nMOS transistor 165 is connected to the bit line b.
  • the gate of the nMOS transistor 165 is connected to the word line WL.
  • the drain of the nMOS transistor 166 is connected to the bit line / b.
  • the gate of the nMOS transistor 166 is connected to the word line WL.
  • the storage element 40 changes the signal level transmitted from the bit line b and the bit line / b according to the signal level “H (High)” of the word line WL to the pMOS transistors 161 and 162 and the nMOS. This is held in the transistors 163 and 164.
  • the memory element 40 causes the signal levels held in the pMOS transistors 161 and 162 and the nMOS transistors 163 and 164 to be applied to the bit line b and the bit line / b according to the signal level “H” of the word line WL. Tell. *
  • FIG. 3 is a diagram showing a detailed example of the address decoder.
  • the address decoder 120 shown in FIG. 3 includes an inverter circuit 120-1, an AND circuit 120-2, and an AND circuit 120-3. There are n inverter circuits 120-1 for every n address signal lines. There are 2 n AND circuits 120-2 and 120-3, respectively. *
  • the inverter circuit 120-1 inverts the logic of the address signal received from the n address signal lines and outputs the inverted address signal to the AND circuit 120-2.
  • the AND circuit 120-2 receives the address signal and the inverted address signal as input signals. When the signal levels of all input values are “H”, the AND circuit 120-2 outputs the signal level “H” to the second AND by the AND operation. Output to the circuit.
  • the AND circuit 120-3 receives the output of the AND circuit 120-2 and an internal clock (described later) as input signals. When the signal levels of all the input values are “H”, the signal level “H” is obtained by a logical product operation. Is output. *
  • the word line selection signal has a signal level “H”, and the word line non-selection signal has a signal level “L (Low)”.
  • the address decoder 120 is configured to output a word line selection signal having a signal level “H” to one word line out of 2 n word lines.
  • the address decoder 120 decodes an address signal received from n address signal lines, and outputs a word line selection signal as a decode signal to 2 n word lines WL.
  • the selection unit 130 is a selection circuit that transmits an external clock supplied from the outside to the data input / output unit 140 based on selection data supplied from the outside.
  • the selection unit 130 is a plurality of selection circuits provided individually for each data output line, and each selection circuit holds selection data supplied from the outside.
  • the selection data may be supplied from the memory cell array 110.
  • each selection circuit is connected to a specific memory cell (selection data memory cell) in the memory cell array 110.
  • selection data memory cell When the signal level of the selection data memory cell is “H”, the signal level of the selection data When the signal level of the memory cell for selected data is “L”, the signal level of the selected data is also “L”.
  • the selection circuit When the signal level of the selection data is “L”, the selection circuit transmits the external clock to the data input / output unit 140, and the read data Q corresponding to the selection circuit is read in synchronization with the external clock.
  • the signal level of the selection data is “H”, the selection circuit does not transmit the external clock to the data input / output unit 140, and the read data Q corresponding to the selection circuit is read asynchronously with the external clock.
  • the data input / output unit 140 When the data input / output unit 140 receives the write enable (WE) edge timing and the write data from the outside, the data input / output unit 140 transmits the signal level of the write data to the m bit lines b and / b, and writes it to the memory cell. Write data.
  • the data input / output unit 140 outputs read data by outputting the signal levels of the m bit lines b and / b to the outside.
  • the semiconductor memory device 100 can perform data reading synchronously or asynchronously for each data. Since specific data in the SRAM does not make the entire memory cell synchronous or asynchronous, the reliability of the synchronous SRAM and the accessibility of the asynchronous SRAM can be provided at the same time. *
  • FIG. 4 is a diagram illustrating a second example of the semiconductor memory device.
  • a semiconductor memory device 100A shown in FIG. 3 includes a memory cell array 110, address decoders 120A and 120B, a selection unit 130A, a bit line precharge circuit 135, and a data input / output unit 140A. *
  • the X column has 2 5 word lines
  • the Y column has 2 squares ⁇ 7 and 1 prepared for reading and writing, respectively.
  • the bit lines are formed in a grid pattern vertically and horizontally, and the memory cells are arranged at the intersections of the word lines and the bit lines. Therefore, it has 2 7 ⁇ 7 (7 + 1) memory cells, of which 7 memory cells are the memory cells for selection data described above. *
  • the address decoder 120 described in FIG. 1 includes an X address decoder 120A for the X column and a Y address decoder 120B for the Y column in FIG. 4, and the X address decoder 120A and the Y address decoder 120B include the address signal lines A0 to A0. A4 and address signal lines A5 to A6 are respectively connected. When the number of address signal lines increases, the memory cell shape can be extended in the X-axis direction by dividing into X-column and Y-column decoders as shown in FIG. *
  • the memory cell for selection data holds selection data, and signals of the selection data are set as control signals for the selection circuit as S0, S1,..., S6. *
  • the X address decoder 120A includes an ATD circuit (Address Transition Detect) 121 as an address change detection unit.
  • the ATD circuit is a circuit that is provided at an address input terminal, detects a change in an address input signal applied to the address input terminal, and outputs the changed address signal. A detailed example of the ATD circuit will be described later with reference to FIGS. *
  • the ATD circuit Since the ATD circuit outputs the changed address signal to the X address decoder 120A only when it detects a change in the address signal, the X address decoder 120A outputs a word line selection signal only when the address signal changes, When the signal does not change, the word line selection signal is not output. In this way, when there is no address change, the word line selection signal is not output, so that a write malfunction due to disturbance noise can be prevented. Further, the X address decoder 120A reduces the number of address lines for activating word lines as compared with the address decoder 120 shown in FIG. 1, so that when an address change occurs, noise is mixed into the memory cell via the word line. Can reduce the possibility of *
  • the X address decoder 120A has a clock generation circuit 122 for generating an internal clock.
  • the internal clock is also used as a flip-flop of the data input / output unit 140 and a synchronization signal of the ATD circuit 121.
  • the output variation of the word line selection signal can be suppressed in synchronization with the internal clock.
  • the high speed of the asynchronous SRAM can be achieved.
  • the internal clock may have a different period from that of the external clock, and the internal clock may have a shorter period than the external clock in order to obtain the high speed of the asynchronous SRAM that can be accessed without being synchronized with the external clock as an asynchronous SRAM. preferable.
  • the example in which the ATD circuit 121 and the clock generation circuit 122 are provided in the X address decoder 120A has been described.
  • the ATD circuit 121 and the clock generation circuit 122 may be provided separately from the X address decoder 120A.
  • the ATD circuit 121 needs to be provided in the upper stage of the X address decoder 120A in order to detect address transition.
  • the Y address decoder 120B is a plurality of selection circuits, each of which may be provided for every seven data lines. In that case, each selection circuit selects one bit pair b, / b as an output or input data line from the four bit pairs according to the address signals A5, A6. *
  • the bit line precharge circuit 135 precharges both the bit line b and the bit line / b to “1”. *
  • FIG. 5 shows a detailed example of a bit line precharge circuit for one bit line pair.
  • the bit line precharge circuit 135a for one bit line pair has two PMOSs, and the input of the bit line precharge circuit 135a is connected to the memory cell via the bit line b and the bit line / b.
  • the output of the bit line precharge circuit 135a is connected to the Y address decoder via the bit line b and the bit line / b.
  • the bit line precharge circuit 135a precharges the signal level of the bit line pair b, / b to “H” according to the internal clock.
  • Such a bit line precharge circuit 135 a for one bit line pair is provided for each bit line pair b, / b of the memory cell array 110. *
  • the PMOS When the clock is input and the signal level becomes “H”, the PMOS is turned off, so that the connection with VDD is cut off, and the bit line outputs the level based on the information of the memory cell.
  • the signal level of the clock becomes “L”
  • the PMOS When the signal level of the clock becomes “L”, the PMOS is turned on and the bit line is pulled up to the potential of VDD. In this manner, the bit line is connected to the memory cell only when the clock is input, thereby preventing a write malfunction due to disturbance noise to the memory cell.
  • the selection unit 130A is a plurality of selection circuits provided for each data output line, like the selection unit 130 shown in FIG. 1, and each of the selection circuits holds selection data. To do.
  • the selection unit 130A differs from the selection unit 130 in that when the selection circuit has a signal level “H” of the selection data, the external clock is not transmitted to the data input / output unit 140 but the internal clock is transmitted to the data input / output unit 140.
  • One bit line is added to the memory cell array 110 as D7.
  • the internal signal of the memory cell at address D7 is S0
  • the internal signal of the memory cell at address 2 is S1
  • the signals up to the internal signal S7 of the memory cell at address 7 are the internal and external clocks of the output latch clock. Select signal. *
  • the memory cell array 110 can be downsized. Further, an existing memory cell may be used for storing selection data without newly providing a memory cell for storing selection data. *
  • a register for receiving external data is required. Further, externally, write control for registers is required. If the selection data is written in the memory cell, the selection circuit can be controlled from the outside without requiring new writing control.
  • the output does not change even if the address changes, but asynchronous operation operates according to the internal clock if the address changes. In this way, if the internal clock has a shorter period than the external clock, data access is possible with higher immediacy. Therefore, as in the case of asynchronous SRAM, when high speed is required when not synchronizing with an external clock, the internal clock needs to have a shorter cycle than the external clock.
  • the data input / output unit 140 has a plurality of flip-flops (F / F) provided for each output data line (D-type flip-flop in the example shown in FIG. 3), and D at the rising edge of the C (CLOCK) terminal.
  • the input value is held as the Q output. That is, the output is changed only at the clock, and the information is held otherwise.
  • the bit line can be set to the “H” state, and a margin can be ensured when the device voltage is lowered.
  • the sense amplifier since there are 32 word lines and the signal level is less deteriorated, the sense amplifier is not shown. However, when the number of word lines increases due to an increase in addresses and memory cells, the bit line precharge is performed. A sense amplifier or a write amplifier may be provided between the circuit 135 and the Y address decoder 120B. *
  • the memory cell shown in FIG. 2 is a single-port memory cell, but may be a double-port memory cell when a high-speed memory cell that performs reading and writing simultaneously is used. *
  • the semiconductor memory device 100A since the semiconductor memory device 100A does not output a word line selection signal when there is no address change, it can prevent a write malfunction due to disturbance noise, and can provide an external clock and an internal clock for each data line. Can be switched. *
  • FIG. 6A is a diagram illustrating an example of an ATD circuit.
  • the ATD circuit 121 shown in FIG. 6A includes, as indicated by 121-1, a flip-flop (F / F), a delay circuit (DC), an AND circuit that performs a logical product operation, an XOR circuit that performs an exclusive logical sum operation, An OR circuit that performs a logical sum operation and a transmission gate (TG) are included.
  • the AND circuit, XOR circuit, and OR circuit are indicated by MIL symbols. *
  • the ATD circuit 121 detects an address change by a combination of the XOR circuit and the delay circuit.
  • FIG. 6B shows a time chart of the ATD circuit shown in FIG. 6A.
  • 6A and 6B corresponds to an address signal input from the outside
  • ai corresponds to a signal input branched from the upper stage of the inverter circuit 120-1 shown in FIG. 3, and ai with an overline is shown in FIG.
  • An output signal of the inverter circuit 120-1 shown ⁇ 1 is a feedback signal input from the TG to the flip-flop clock, and ⁇ 2 is a feedback signal input to the AND circuit. *
  • the flip-flop receives ⁇ 1 synchronized with the internal clock as a clock and holds the address signal at the rising edge of the clock.
  • the XOR circuit When the address of the previous cycle is different from the address of the current cycle, the XOR circuit outputs a signal level “H”, and the signal is output from the TG as ⁇ 2.
  • the flip-flop that receives ⁇ 2 as a clock outputs the address held in the cycle ⁇ 1.
  • the AND circuit outputs the address of ⁇ 1 cycle as the address ai when the signal level of the address of ⁇ 1 cycle output from the flip-flop in the cycle of ⁇ 2 is the same as the signal level of ⁇ 2. In this way, the ATD circuit outputs the changed address signal to the address decoder only when detecting an address change.
  • FIG. 7 is a diagram illustrating a third example of the semiconductor memory device.
  • the semiconductor memory 100B shown in FIG. 7 is the same as the semiconductor memory 100A shown in FIG. 3 in other configurations, except that the ATD circuit 121A detects changes in all address signals.
  • the ATD circuit 121A detects changes in all address signals.
  • the ATD circuit 121A detects changes in the signals A0 to A4, it outputs a word line selection signal for the memory cell array 110, and changes the signals in A5 and A6.
  • a signal is output to Y address decoder 120B.
  • the address change detected by the ATD circuit 121A is the addresses A5 and A6 shown in FIG. 7, the address is supplied to the Y address decoder 120B, and is not supplied when there is no address change. *
  • the word line is selected only by the X address and the Y address only selects the data output by the bit line, it is not directly related to noise countermeasures for the data stored in the memory cell array 110.
  • the Y address is also used by the Y address decoder 120B to select output data, a malfunction may occur in which data is output from a non-target memory cell due to an address mutated by external noise. Therefore, the malfunction of data output due to external noise can be prevented by inputting the Y address via the ATD circuit 121A.
  • MPLD Memory Based Programmable Logic Device
  • MPLD is also a reconfigurable device that uses SRAM
  • MLUT Multi Look-Up-Table
  • MLUT Multi Look-Up-Table
  • the MLUT is used as the logic as the wiring
  • the delay with the synchronous clock in the MLUT is a big problem
  • the asynchronous SRAM is used.
  • Asynchronous SRAMs output in accordance with address switching, so that they are good structures for solving the delay problem as MPLD MLUTs.
  • the bit line is driven by the memory cell, the size of the transistor tends to be large.
  • the word line is always selected, the data is rewritten due to noise at the time of reading, causing a malfunction of the MPLD.
  • future semiconductor miniaturization semiconductor process after 90 nm
  • the problem is that in the case of a synchronous SRAM, writing and reading can be performed only during clock operation, and in other states, the word line can be deselected to protect the memory cell state.
  • the bit line can be set to Hi level except during reading, so that the memory cell state can be maintained even when the voltage of the device is lowered, and the voltage is reduced by miniaturization. It can correspond to.
  • the synchronous SRAM is read / write only with the synchronous clock, and the clock stage number delay for each number of MLUT stages such as wiring cannot be seen and used.
  • MPLD in a conventional asynchronous SRAM can express wiring and combinational circuits, but cannot express sequential circuits.
  • a sequential circuit can be configured by adding F / F to the AD pair 7 of the MLUT with a limited number of MPLDs (AD pair not connected to the surrounding MPLD among the seven AD pairs).
  • the F / F is insufficient in the sequential circuit representation and the wiring MLUT must be provided between the F / Fs, the operation speed is limited.
  • the number of F / Fs used is limited because the limited AD pairs have F / Fs, and in the prior art (for example, Japanese Patent Application Laid-Open No. 2010-239325), F / Fs are limited. Since the output of F is returned to its own MLUT, when a sequential circuit is configured, a signal is returned to its own MLUT (MLUT ⁇ F / F), and the MLUT is wired by MLUT, which adversely affects mounting efficiency.
  • the AD pair of the MLUT must have a built-in F / F and a general F / F connection state such as MLUT ⁇ F / F ⁇ MLUT must be established.
  • This can be realized by using a synchronous SRAM, but it is detrimental in MLUT representation with wiring and combinational circuits.
  • the asynchronous SRAM cannot operate at a low voltage corresponding to miniaturization, synchronization corresponding to miniaturization is necessary.
  • FIG. 8 is a diagram illustrating an example of an MPLD using a semiconductor memory device as an MLUT.
  • the MPLD 20 shown in FIG. 8 has a plurality of MLUTs 30.
  • the rectangle in the MLUT 30 is an F / F provided for each data output line that can be switched by the selection signal described in the semiconductor memory device. This F / F corresponds to the F / F of the data input / output unit 140.
  • 6-way MLUT (Six MLUTs are arranged around one MLUT, and the MLUT in the center and the six MLUTs in the periphery are each connected by one AD pair.
  • six MLUTs Address lines are connected to the other six MLUT data lines arranged in the periphery, and the six MLUT data lines are connected to the other MLUT address lines of the MLUT, respectively.
  • Is capable of providing a uniform connection to the AD pair but a circuit having two CLA (carrier look-ahead) circuits such as a multiplier circuit can implement the circuit within its own MLUT.
  • the logical configuration efficiency is poor.
  • alternating arrangement (eight MLUTs are arranged around one MLUT, and four MLUTs in the periphery are connected to an AD pair, and two MLUTs are connected by two AD pairs. 1 (disclosed in FIG. 1 of 2010-239325) can have two AD pairs in adjacent MLUTs, and in this case, the alternate arrangement is advantageous.
  • the MLUT arranged in 6 directions can reduce the number of MLUTs operating as connection elements, so that the total amount of storage element blocks constituting a desired logic circuit can be reduced, so that an MLUT arranged in 6 directions is possible. It is preferable to use as much as possible.
  • the separated wiring is an AD pair wiring that connects MLUTs that are not short-distance wiring.
  • the MLUT can be saved in the long distance wiring.
  • the AD pair 7 is used and the necessary F / F is connected to the sequential circuit, the F / F has a structure that returns to its own MLUT.
  • the separated wiring and the F / F are mixed at a certain ratio. If a sequential circuit is configured in this relationship, an MLUT as a connection element is required, and the logical configuration efficiency is poor. *
  • the semiconductor memory device shown in FIG. 1, 4 or 7 is used as the MLUT.
  • the MLUT shown in FIG. 8 is an example in which the semiconductor memory device shown in FIG. 1, 4 or 7 is used as a MLUT arranged in six directions. Since the MLUT (semiconductor memory device) itself has an F / F and there is no need to use an AD pair to connect to an external F / F, the AD pair 7 can all be used for separated wiring. . *
  • the selection data can be defined by the memory cell for selection data in the memory cell array 110. Therefore, the circuit realized by the MLUT needs to be synchronized.
  • the MLUT can be divided into a circuit and a circuit that does not require synchronization, or a single MLUT can be used separately for a circuit that requires dynamic synchronization and a circuit that does not require synchronization.
  • MLUT is set for each data line so that it is synchronized for each data line as an internal clock when asynchronous is required in the combinational circuit or wiring logic, and is synchronized for each data line with an external clock when it is a sequential circuit. can do.
  • FIG. 9A is a diagram showing a detailed example of MPLD.
  • Reference numeral 20 shown in FIG. 9A denotes an MPLD as a semiconductor device.
  • the MPLD 20 includes a plurality of MLUTs 30 serving as storage element blocks and an MLUT decoder 12. As will be described later, the MPLD 20 operates as a logic unit connected to the arithmetic processing unit. *
  • the MPLD 20 includes a plurality of storage elements. Since the data constituting the truth table is stored in the memory element, the MPLD 20 performs a logic operation that operates as a logic element, a connection element, or a logic element and a connection element. *
  • the MPLD 20 further performs a memory operation.
  • the memory operation refers to writing or reading of data to / from a storage element included in the MLUT 30. Therefore, the MPLD 20 can operate as a main storage device or a cache memory.
  • FIG. 9B is a diagram illustrating an example of the MPLD memory operation.
  • the MPLD 20 uses any one of the memory operation address, MLUT address, write data WD, and read data RD indicated by the solid line in the memory operation, and the logical operation address LA indicated by the broken line and the logic operation Data LD is not used.
  • the memory operation address, the MLUT address, and the write data are output by, for example, an arithmetic processing device outside the MPLD 20, and the read data WD is output to the arithmetic processing device.
  • the MPLD 20 receives the memory operation address and the MLUT address as addresses for specifying the storage element, receives write data at the time of writing, and outputs read data LD at the time of reading.
  • the MLUT address is an address that specifies one MLUT included in the MPLD 20.
  • the MLUT address is output to the MPLD 20 via l signal lines.
  • l is the number of selected address signal lines that specify the MLUT.
  • the number of MLUTs of 2 to the power of 1 can be specified by l signal lines.
  • the MLUT decoder 12 receives the MLUT address via one signal line, decodes the MLUT address, and selects and specifies the MLUT 30 that is the target of the memory operation.
  • the memory operation address is decoded by an address decoder, which will be described later with reference to FIG. 11, via l signal lines, and a memory cell to be subjected to the memory operation is selected. *
  • the MPLD 20 receives, for example, the MLUT address, write data, and read data all via n signal lines.
  • n is the number of selected address signal lines for MLUT memory operation or logic operation, as will be described later with reference to FIG.
  • the MPLD 20 supplies the MLUT address, write data, and read data to each MLUT via n signal lines.
  • FIG. 9C is a diagram illustrating an example of the MPLD 20 logic operation.
  • the logic operation of the MPLD 20 uses a logic operation address and a logic operation data signal indicated by solid lines. *
  • the logic operation address is output from an external device and used as an input signal of a logic circuit configured by the truth table of the MLUT 30.
  • the logic operation data signal is an output signal of the logic circuit, and is output to the external device as an output signal of the logic circuit.
  • the MLUT arranged outside the MPLD 20 operates as an MLUT that receives an apparatus for external operation of the MPLD 20 and the logical operation address LA and outputs the logical operation data LD.
  • the MLUTs 30a and 30b illustrated in FIG. 9A receive the logic operation address LA from the outside of the semiconductor device 100, and output the logic operation data LD to the other MLUTs 30d around.
  • the MLUTs 30e and 30f shown in FIG. 9A receive the logical operation address LA from the other MLUTs 30c and 30d and output the logical operation data LD to the outside of the MPLD 20.
  • the address line of the logical operation address LA of the MLUT is connected to the data line of the logical operation data LD of the adjacent MLUT.
  • the MLUT 30c converts the logical operation data output from the MLUT 30a into the logical operation address.
  • the MLUT logical operation address or the logical operation data is different from the MLUT address to which each MLUT is uniquely connected, in that the MLUT logical operation address or logical operation data is obtained by input / output with the surrounding MLUT.
  • the logic realized by the logic operation of the MPLD 20 is realized by truth table data stored in the MLUT 30.
  • Some MLUTs 30 operate as logic elements as combinational circuits such as AND circuits and adders.
  • the other MLUTs operate as connection elements that connect the MLUTs 30 that realize the combinational circuit. Rewriting of truth table data for realizing the logic element and the connection element is performed by reconfiguration by the above-described memory operation. *
  • FIG. 10 is a diagram illustrating a first example of the MLUT.
  • the MLUT 30 shown in FIG. 10 includes an address switching circuit 10a, an address decoder 9, a storage element 40, and an output data switching circuit 10b.
  • the operation switching signal indicates a logical operation
  • the MLUT 30 illustrated in FIG. 10 operates to output logical operation data according to the logical operation address.
  • the operation switching signal indicates a memory operation
  • the MLUT 30 operates to accept write data or output read data according to a memory operation address.
  • the address switching circuit 10a includes n memory operation address signal lines to which a memory operation address is input, n logic operation address input signal lines to which a logic operation address signal is input, and an operation switching signal. Connect the input operation switching signal line.
  • the address switching circuit 10a operates so as to output either the memory operation address or the logic operation address to the n selected address signal lines based on the operation switching signal. As described above, the address switching circuit 10a selects the address signal line because the storage element 40 is a one-port type storage element that accepts either a read operation or a write operation. *
  • the address decoder 9 decodes the selected address signal received from the n address signal lines supplied from the address switching circuit 10a, and outputs a decode signal to 2 n word lines.
  • n ⁇ 2 n memory elements are arranged at a connection portion of 2 n word lines, n write data lines, and n output bit lines.
  • the output data switching circuit 10b When the output data switching circuit 10b receives signals from the n output bit lines, the output data switching circuit 10b outputs read data to the n read data signal lines in accordance with the input operation switching signal, or outputs the read data to the logic operation signal. Operates to output on a line.
  • FIG. 11 is a diagram illustrating an example of an MLUT that operates as a logical element.
  • the MLUT illustrated in FIG. 11 is a circuit similar to the MLUT illustrated in FIG. 10 or the semiconductor memory device illustrated in FIG. In FIG. 11, the description of the address switching circuit 10a and the output data switching circuit 10b is omitted to simplify the description.
  • the logic operation data lines D0 to D3 connect 24 memory elements 40 in series, respectively.
  • the address decoder 9 is configured to select four storage elements connected to any of the 24 word lines based on signals input to the logic operation address lines A0 to A3. These four storage elements are connected to logic operation data lines D0 to D3, respectively, and output data stored in the storage elements to logic operation data lines D0 to D3. For example, when an appropriate signal is input to the logic operation address lines A0 to A3, the four memory elements 40a, 40b, 40c, and 40d can be selected.
  • the storage element 40a is connected to the logic operation data line D0
  • the storage element 40b is connected to the logic operation data line D1
  • the storage element 40d is connected to the logic operation data line D2.
  • 40d is connected to the logic operation data line D3.
  • signals stored in the storage elements 40a to 40d are output to the logic operation data lines D0 to D3.
  • the MLUTs 30a and 30b receive the logical operation addresses from the logical operation address lines A0 to A3, and the values stored in the four storage elements 40 selected by the address decoder 9 based on the logical operation addresses are logically converted.
  • the data is output to the operation data lines D0 to D3 as logic operation data.
  • the logical operation address line A2 of the MLUT 30a is connected to the logical operation data line D0 of the adjacent MLUT 30b, and the MLUT 30a receives the logical operation data output from the MLUT 30b as the logical operation address.
  • the logical operation data line D2 of the MLUT 30a is connected to the logical operation address line A0 of the MLUT 30b, and the logical operation data output from the MLUT 30a is received as a logical operation address by the MLUT 30b.
  • the logic operation data line D2 of the MLUT 30a is one of 24 storage elements connected to the logic operation data line D2 based on signals input to the logic operation address lines A0 to A3 of the MLUT 30a. Is output to the logic operation address A0 of the MLUT 30b.
  • the logic operation data line D0 of the MLUT 30b is one of 24 storage elements connected to the logic operation data line D0 based on signals input to the logic operation address lines A0 to A3 of the MLUT 30b.
  • the signal stored in one is output to the logic operation address A2 of the MLUT 30a.
  • the MPLDs are connected by using a pair of address lines and data lines.
  • a pair of address lines and data lines used for MLUT connection such as the logic operation address line A2 and the logic operation data line D2 of the MLUT 30a, is referred to as an "AD pair". *
  • the AD pairs included in the MLUTs 30a and 30b are 4, but the number of AD pairs is not limited to 4 as will be described later. *
  • FIG. 12 is a diagram illustrating an example of an MLUT that operates as a logic circuit.
  • the logic operation address lines A 0 and A 1 are input to the 2-input NOR circuit 701
  • the logic operation address lines A 2 and A 3 are input to the 2-input NAND circuit 702.
  • the output of the 2-input NOR circuit and the output of the 2-input NAND circuit 702 are input to the 2-input NAND circuit 703, and a logic circuit is configured to output the output of the 2-input NAND circuit 703 to the logic operation data line D0. . *
  • FIG. 13 is a diagram showing a truth table of the logic circuit shown in FIG. Since the logic circuit of FIG. 12 has four inputs, all the inputs A0 to A3 are used as inputs. On the other hand, since there is only one output, only the output D0 is used as an output. “*” Is written in the columns of outputs D1 to D3 of the truth table. This indicates that any value of “0” or “1” may be used. However, when the truth table data is actually written into the MLUT for reconstruction, it is necessary to write either “0” or “1” in these fields. *
  • FIG. 14 is a diagram illustrating an example of an MLUT that operates as a connection element.
  • the MLUT as a connection element outputs a signal of the logic operation address line A0 to the logic operation data line D1, and outputs a signal of the logic operation address line A1 to the logic operation data line D2. It operates so as to output the signal of the operation address line A2 to the logic operation data line D3.
  • the MLUT as the connection element further operates to output the signal of the logic operation address line A3 to the logic operation data line D1.
  • FIG. 15 is a diagram showing a truth table of the connection elements shown in FIG.
  • the connection element shown in FIG. 14 has 4 inputs and 4 outputs. Therefore, all inputs A0-A3 and all outputs D0-D3 are used.
  • the MLUT outputs the signal of the input A0 to the output D1, outputs the signal of the input A1 to the output D2, outputs the signal of the input A2 to the output D3, and outputs the signal of the input A3. It operates as a connection element that outputs to the output D0. *
  • FIG. 16 is a diagram illustrating an example of a connection element realized by an MLUT having four AD pairs of AD0, AD1, AD2, and AD3.
  • AD0 has a logic operation address line A0 and a logic operation data line D0.
  • AD1 has a logic operation address line A1 and a logic operation data line D1.
  • AD2 has a logic operation address line A2 and a logic operation data line D2.
  • AD3 has a logic operation address line A3 and a logic operation data line D3.
  • a one-dot chain line indicates a signal flow in which a signal input to the logic operation address line A0 of the AD pair 0 is output to the logic operation data line D1 of the AD pair 1.
  • a two-dot chain line indicates a signal flow in which a signal input to the logic operation address line A1 of the second AD pair 1 is output to the logic operation data line D2 of the AD pair 2.
  • a broken line indicates a flow of a signal that is input to the logic operation address line A2 of the AD pair 2 and output to the logic operation data line D3 of the AD pair 3.
  • a solid line indicates a flow of a signal that is input to the logical operation address line A3 of the AD pair 3 and is output to the logical operation data line D0 of the AD pair 0.
  • the MLUT 30 has four AD pairs, but the number of AD pairs is not particularly limited to four. *
  • FIG. 17 is a diagram illustrating an example in which one MLUT operates as a logic element and a connection element.
  • the logic operation address lines A0 and A1 are input to the 2-input NOR circuit 171
  • the output of the 2-input NOR circuit 171 and the logic operation address line A2 are input to the 2-input NAND circuit 172.
  • a logic circuit is configured to output the output of the 2-input NAND circuit 172 to the logic operation data line D0.
  • a connection element for outputting the signal of the logic operation address line A3 to the logic operation data line D2 is formed. *
  • FIG. 18 shows a truth table of the logic elements and connection elements shown in FIG.
  • the logic operation of FIG. 17 uses three inputs D0 to D3 and uses one output D0 as an output.
  • the connection element in FIG. 18 is a connection element that outputs the signal of the input A3 to the output D2. *
  • FIG. 19 is a diagram illustrating an example of logical operations and connection elements realized by an MLUT having four AD pairs of AD0, AD1, AD2, and AD3.
  • AD0 has a logic operation address line A0 and a logic operation data line D0.
  • AD1 has a logic operation address line A1 and a logic operation data line D1.
  • AD2 has a logic operation address line A2 and a logic operation data line D2.
  • AD3 has a logic operation address line A3 and a logic operation data line D3.
  • the MLUT 30 realizes two operations, ie, a logic operation with three inputs and one output and a connection element with one input and one output, with one MLUT 30.
  • the logic operation uses the logic operation address line A0 of AD pair 0, the logic operation address line A1 of AD pair 1, and the logic operation address line A2 of AD pair 2 as inputs. Then, the address line of the logic operation data line D0 of AD pair 0 is used as an output. Further, the connection element outputs a signal input to the logic operation address line A3 of the AD pair 3 to the logic operation data line D2 of the AD pair 2 as indicated by a broken line.

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  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
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Abstract

[Problème] L'invention a pour objet de permettre, dans un dispositif de mémoire à semi-conducteur, d'effectuer une lecture de données synchrone ou asynchrone pour chaque élément de données. [Solution] Un dispositif de mémoire à semi-conducteur est décrit qui comprend : une pluralité de cellules de mémoire stockant chacune des données ; un décodeur d'adresse qui décode des signaux d'adresse qui spécifient les cellules de mémoire, et délivre un signal de sélection de ligne de mot qui est basé sur les adresses décodées et est utilisé pour sélectionner l'une des lignes de mot connectées à une partie de la pluralité de cellules de mémoire ; une unité de sélection qui conserve des données de sélection, et sélectionne une horloge externe qui est fournie depuis l'extérieur, sur la base des données de sélection ; et une unité de lecture de données qui lit des données dans une partie de la pluralité de cellules de mémoire sélectionnée sur la base du signal de sélection de ligne de mot, ladite unité de lecture de données effectuant une lecture d'une manière synchrone avec l'horloge externe quand l'horloge externe est sélectionnée, ou d'une manière asynchrone avec l'horloge externe quand l'horloge externe n'est pas sélectionnée.
PCT/JP2012/067302 2011-07-15 2012-07-06 Dispositif de mémoire à semi-conducteur WO2013011848A1 (fr)

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WO2013153850A1 (fr) * 2012-04-11 2013-10-17 太陽誘電株式会社 Dispositif à semi-conducteur reconfigurable
GB2512641A (en) * 2013-04-05 2014-10-08 Ibm SRAM array comprising multiple cell cores
US9384823B2 (en) 2014-09-19 2016-07-05 International Business Machines Corporation SRAM array comprising multiple cell cores

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JP5962533B2 (ja) 2013-02-13 2016-08-03 ソニー株式会社 固体撮像素子、駆動方法、および撮像装置
TWI618060B (zh) * 2013-04-02 2018-03-11 太陽誘電股份有限公司 Semiconductor device

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WO2013153850A1 (fr) * 2012-04-11 2013-10-17 太陽誘電株式会社 Dispositif à semi-conducteur reconfigurable
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GB2512641A (en) * 2013-04-05 2014-10-08 Ibm SRAM array comprising multiple cell cores
US9384823B2 (en) 2014-09-19 2016-07-05 International Business Machines Corporation SRAM array comprising multiple cell cores

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