WO2013010828A1 - Method for growing iii-v epitaxial layers - Google Patents

Method for growing iii-v epitaxial layers Download PDF

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Publication number
WO2013010828A1
WO2013010828A1 PCT/EP2012/063317 EP2012063317W WO2013010828A1 WO 2013010828 A1 WO2013010828 A1 WO 2013010828A1 EP 2012063317 W EP2012063317 W EP 2012063317W WO 2013010828 A1 WO2013010828 A1 WO 2013010828A1
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WO
WIPO (PCT)
Prior art keywords
substrate
layer
μιη
local electrical
electrical isolations
Prior art date
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Ceased
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PCT/EP2012/063317
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English (en)
French (fr)
Inventor
Joff Derluyn
Stefan Degroote
Marianne Germain
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EpiGan NV
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EpiGan NV
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Publication date
Application filed by EpiGan NV filed Critical EpiGan NV
Priority to JP2014520601A priority Critical patent/JP6120841B2/ja
Priority to EP12740090.1A priority patent/EP2735030B1/en
Priority to US14/232,933 priority patent/US9230803B2/en
Priority to KR1020147003437A priority patent/KR101674274B1/ko
Priority to CN201280035896.6A priority patent/CN103765592B/zh
Publication of WO2013010828A1 publication Critical patent/WO2013010828A1/en
Anticipated expiration legal-status Critical
Priority to US14/965,550 priority patent/US9748331B2/en
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H10D30/4755—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/824—Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/27—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3414—Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3414—Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
    • H10P14/3416—Nitrides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/64—Wet etching of semiconductor materials
    • H10P50/642—Chemical etching
    • H10P50/646—Chemical etching of Group III-V materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/06—Planarisation of inorganic insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0125—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN

Definitions

  • isolation is done by deep trench etching (6a) through the Ill-nitride layers and into the Si substrate.
  • isolation is done by impurity implantation (in combination with trench etching or not).
  • isolation is done by trench etching followed by a shallow implantation by plasma treatment.
  • the direction of the growth front on which the epitaxial layers grow is changed by tuning growth conditions, allowing the isolation patterns to be overgrown.
  • These processes are well known by the person skilled in the art and are referred to as epitaxial lateral overgrowth (ELOG).
  • ELOG epitaxial lateral overgrowth
  • the change of growth direction changes the way stress is built up in the growing layer and opens a new parameter space when depositing Ill-nitrides on foreign substrates.
  • stress engineering requires AlGaN interlayers to be inserted between A1N and GaN, but in an example this is no longer required.

Landscapes

  • Junction Field-Effect Transistors (AREA)
PCT/EP2012/063317 2011-07-18 2012-07-06 Method for growing iii-v epitaxial layers Ceased WO2013010828A1 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2014520601A JP6120841B2 (ja) 2011-07-18 2012-07-06 Ｉｉｉ−ｖエピタキシャル層を成長させるための方法
EP12740090.1A EP2735030B1 (en) 2011-07-18 2012-07-06 III-V epitaxial layers and method of growing thereof
US14/232,933 US9230803B2 (en) 2011-07-18 2012-07-06 Method for growing III-V epitaxial layers
KR1020147003437A KR101674274B1 (ko) 2011-07-18 2012-07-06 Iii-v 에피택셜층들을 성장시키는 방법
CN201280035896.6A CN103765592B (zh) 2011-07-18 2012-07-06 用于生长iii‑v外延层的方法
US14/965,550 US9748331B2 (en) 2011-07-18 2015-12-10 Method for growing III-V epitaxial layers

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB1112327.0A GB201112327D0 (en) 2011-07-18 2011-07-18 Method for growing III-V epitaxial layers
GB1112327.0 2011-07-18

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US14/232,933 A-371-Of-International US9230803B2 (en) 2011-07-18 2012-07-06 Method for growing III-V epitaxial layers
US14/965,550 Continuation US9748331B2 (en) 2011-07-18 2015-12-10 Method for growing III-V epitaxial layers

Publications (1)

Publication Number Publication Date
WO2013010828A1 true WO2013010828A1 (en) 2013-01-24

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PCT/EP2012/063317 Ceased WO2013010828A1 (en) 2011-07-18 2012-07-06 Method for growing iii-v epitaxial layers

Country Status (7)

Country Link
US (2) US9230803B2 (https=)
EP (1) EP2735030B1 (https=)
JP (1) JP6120841B2 (https=)
KR (1) KR101674274B1 (https=)
CN (1) CN103765592B (https=)
GB (1) GB201112327D0 (https=)
WO (1) WO2013010828A1 (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2662896A3 (de) * 2012-05-07 2014-09-10 Forschungsverbund Berlin e.V. Halbleiterschichtenstruktur
US9831333B2 (en) 2013-02-07 2017-11-28 Enkris Semiconductor, Inc. High-voltage nitride device and manufacturing method thereof
US9871162B2 (en) 2014-04-25 2018-01-16 Samsung Electronics Co., Ltd. Method of growing nitride single crystal and method of manufacturing nitride semiconductor device

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI493617B (zh) * 2013-10-07 2015-07-21 Nat Univ Tsing Hua 部分隔離矽基板之三族氮化物半導體裝置之製作方法
US9761439B2 (en) * 2014-12-12 2017-09-12 Cree, Inc. PECVD protective layers for semiconductor devices
CN107615447B (zh) * 2015-05-29 2021-01-19 美国亚德诺半导体公司 具有陷阱富集区域的氮化镓设备
US9484412B1 (en) 2015-09-23 2016-11-01 International Business Machines Corporation Strained silicon—germanium integrated circuit with inversion capacitance enhancement and method to fabricate same
GB2547661A (en) * 2016-02-24 2017-08-30 Jiang Quanzhong Layered vertical field effect transistor and methods of fabrication
US10074721B2 (en) * 2016-09-22 2018-09-11 Infineon Technologies Ag Method of fabricating a semiconductor wafer that includes producing a planarised surface having both a mesa surface and an insulating layer surface
US10134603B2 (en) 2016-09-22 2018-11-20 Infineon Technologies Ag Method of planarising a surface
US10734303B2 (en) * 2017-11-06 2020-08-04 QROMIS, Inc. Power and RF devices implemented using an engineered substrate structure
CA3101187A1 (en) * 2018-05-29 2019-12-05 Iqe Plc Optoelectronic devices formed over a buffer
US10741666B2 (en) * 2018-11-19 2020-08-11 Vanguard International Semiconductor Corporation High electron mobility transistor and method for forming the same
US10666353B1 (en) * 2018-11-20 2020-05-26 Juniper Networks, Inc. Normal incidence photodetector with self-test functionality
CN111463273A (zh) * 2020-03-25 2020-07-28 西北工业大学 一种基于氮化镓异质结外延的长关型hemt器件及其制备方法
WO2021257965A1 (en) * 2020-06-19 2021-12-23 Macom Technology Solutions Holdings, Inc. Suppression of parasitic acoustic waves in integrated circuit devices
CN113130644B (zh) * 2020-12-18 2023-03-24 英诺赛科(苏州)科技有限公司 半导体器件以及制造半导体器件的方法
US20220199817A1 (en) 2020-12-18 2022-06-23 Innoscience (Suzhou) Technology Co., Ltd. Semiconductor device and method for manufacturing the same
CN113224193B (zh) * 2021-04-12 2022-06-14 华南理工大学 结合嵌入电极与钝化层结构的InGaN/GaN多量子阱蓝光探测器及其制备方法与应用
WO2022217539A1 (zh) * 2021-04-15 2022-10-20 苏州晶湛半导体有限公司 半导体结构及其制作方法
WO2024113095A1 (en) * 2022-11-28 2024-06-06 Innoscience (suzhou) Semiconductor Co., Ltd. Nitride-based semiconductor device and method for manufacturing the same
CN116230653B (zh) * 2023-03-31 2025-10-28 上海华虹宏力半导体制造有限公司 深沟槽隔离结构及其制造方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0272384A1 (de) * 1986-12-24 1988-06-29 Licentia Patent-Verwaltungs-GmbH Monolithisch integrierter Photoempfänger
US20050017236A1 (en) * 1999-03-30 2005-01-27 Hitachi, Ltd. Semiconductor device and semiconductor substrate
US20050110054A1 (en) * 2003-11-24 2005-05-26 Triquint Semiconductor, Inc. Monolithic integrated enhancement mode and depletion mode field effect transistors and method of making the same
US7247889B2 (en) 2004-12-03 2007-07-24 Nitronex Corporation III-nitride material structures including silicon substrates
US20080048196A1 (en) 2005-03-07 2008-02-28 Technische Universitat Berlin Component and Process for Manufacturing the Same
CN101719465A (zh) 2009-11-27 2010-06-02 晶能光电（江西）有限公司 硅衬底GaN基半导体材料的制造方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5077231A (en) 1991-03-15 1991-12-31 Texas Instruments Incorporated Method to integrate HBTs and FETs
US5243207A (en) * 1991-03-15 1993-09-07 Texas Instruments Incorporated Method to integrate HBTs and FETs
JP2891204B2 (ja) * 1996-09-27 1999-05-17 日本電気株式会社 半導体装置の製造方法
US6620665B1 (en) 1998-09-14 2003-09-16 Matsushita Electric Industrial Co., Ltd. Method for fabricating semiconductor device
JP2000196029A (ja) * 1998-12-28 2000-07-14 Sony Corp 半導体装置とその製造方法
JP2002170877A (ja) * 2000-12-01 2002-06-14 Sharp Corp 半導体装置の製造方法
US6756633B2 (en) * 2001-12-27 2004-06-29 Silicon Storage Technology, Inc. Semiconductor memory array of floating gate memory cells with horizontally oriented floating gate edges
AU2003202499A1 (en) 2002-01-09 2003-07-30 Matsushita Electric Industrial Co., Ltd. Semiconductor device and its production method
JP2003332676A (ja) * 2002-05-08 2003-11-21 Mitsubishi Electric Corp 半導体光装置
WO2007108055A1 (ja) * 2006-03-16 2007-09-27 Fujitsu Limited 化合物半導体装置及びその製造方法
US7955960B2 (en) 2007-03-22 2011-06-07 Hynix Semiconductor Inc. Nonvolatile memory device and method of fabricating the same
KR100966989B1 (ko) * 2007-03-22 2010-06-30 주식회사 하이닉스반도체 플래시 메모리 소자의 제조 방법
JP5767811B2 (ja) * 2007-09-12 2015-08-19 トランスフォーム インコーポレイテッドＴｒａｎｓｐｈｏｒｍ Ｉｎｃ． Ｉｉｉ族窒化物双方向スイッチ
JP2010016089A (ja) * 2008-07-02 2010-01-21 Nec Electronics Corp 電界効果トランジスタ、その製造方法、及び半導体装置
US20100155831A1 (en) * 2008-12-20 2010-06-24 Power Integrations, Inc. Deep trench insulated gate bipolar transistor
JP2011082216A (ja) * 2009-10-02 2011-04-21 Fujitsu Ltd 化合物半導体装置及びその製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0272384A1 (de) * 1986-12-24 1988-06-29 Licentia Patent-Verwaltungs-GmbH Monolithisch integrierter Photoempfänger
US20050017236A1 (en) * 1999-03-30 2005-01-27 Hitachi, Ltd. Semiconductor device and semiconductor substrate
US20050110054A1 (en) * 2003-11-24 2005-05-26 Triquint Semiconductor, Inc. Monolithic integrated enhancement mode and depletion mode field effect transistors and method of making the same
US7247889B2 (en) 2004-12-03 2007-07-24 Nitronex Corporation III-nitride material structures including silicon substrates
US20080048196A1 (en) 2005-03-07 2008-02-28 Technische Universitat Berlin Component and Process for Manufacturing the Same
CN101719465A (zh) 2009-11-27 2010-06-02 晶能光电（江西）有限公司 硅衬底GaN基半导体材料的制造方法

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
SRIVASTAVA ET AL.: "Record Breakdown Voltage (2200 V) of GaN DHFETs on Si With 2-pm Buffer Thickness by Local Substrate Removal", EDL 32-1, 2011
UMEDA ET AL.: "Blocking-Voltage Boosting Technology for GaN Transistors by Widening Depletion Layer in Si Substrates", IEEE ELECTRON DEVICES MEETING, SAN FRANCISCO, CA, 2010, pages 20.5.1 - 20.5.4, XP031885013, DOI: doi:10.1109/IEDM.2010.5703400

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2662896A3 (de) * 2012-05-07 2014-09-10 Forschungsverbund Berlin e.V. Halbleiterschichtenstruktur
US9831333B2 (en) 2013-02-07 2017-11-28 Enkris Semiconductor, Inc. High-voltage nitride device and manufacturing method thereof
US9871162B2 (en) 2014-04-25 2018-01-16 Samsung Electronics Co., Ltd. Method of growing nitride single crystal and method of manufacturing nitride semiconductor device

Also Published As

Publication number Publication date
KR20140063593A (ko) 2014-05-27
US20160099309A1 (en) 2016-04-07
CN103765592A (zh) 2014-04-30
US9230803B2 (en) 2016-01-05
US9748331B2 (en) 2017-08-29
KR101674274B1 (ko) 2016-11-08
JP6120841B2 (ja) 2017-04-26
EP2735030A1 (en) 2014-05-28
EP2735030B1 (en) 2017-03-15
US20140167114A1 (en) 2014-06-19
CN103765592B (zh) 2017-09-19
JP2014521229A (ja) 2014-08-25
GB201112327D0 (en) 2011-08-31

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