WO2012155535A1 - 氮化镓基薄膜芯片的生产制造方法 - Google Patents

氮化镓基薄膜芯片的生产制造方法 Download PDF

Info

Publication number
WO2012155535A1
WO2012155535A1 PCT/CN2012/000664 CN2012000664W WO2012155535A1 WO 2012155535 A1 WO2012155535 A1 WO 2012155535A1 CN 2012000664 W CN2012000664 W CN 2012000664W WO 2012155535 A1 WO2012155535 A1 WO 2012155535A1
Authority
WO
WIPO (PCT)
Prior art keywords
gan
substrate
thin film
layer
chip according
Prior art date
Application number
PCT/CN2012/000664
Other languages
English (en)
French (fr)
Inventor
赵汉民
朱浩
熊传兵
曲晓东
Original Assignee
晶能光电（江西）有限公司
易美芯光（北京）科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN201110132402.3A external-priority patent/CN102790137B/zh
Priority claimed from CN201110132454.0A external-priority patent/CN102790139B/zh
Priority claimed from CN201110132423.5A external-priority patent/CN102790138B/zh
Application filed by 晶能光电（江西）有限公司, 易美芯光（北京）科技有限公司 filed Critical 晶能光电（江西）有限公司
Priority to EP12786729.9A priority Critical patent/EP2711991A4/en
Priority to JP2014510643A priority patent/JP5792375B2/ja
Publication of WO2012155535A1 publication Critical patent/WO2012155535A1/zh
Priority to US14/083,487 priority patent/US9224597B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/0242—Crystalline insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6835—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/405—Reflective materials

Definitions

  • the present invention relates to a process for preparing a semiconductor light emitting device. More specifically, the present invention relates to a method of preparing a GaN-based thin film chip by a laser lift-off process. .
  • the sapphire substrate is the main substrate for epitaxial growth of gallium nitride-based LEDs, and its conductivity and heat dissipation are relatively poor. Due to poor conductivity, the light-emitting device has a lateral structure that causes current blockage and heat generation. The poor thermal conductivity limits the power of the light emitting device. After the sapphire substrate is removed by laser stripping technology, the LED is made into a vertical structure, which can effectively solve the problem of heat dissipation and light emission. The low yield is the bottleneck for the industrialization of sapphire substrate technology by laser stripping.
  • the gallium nitride film is easily broken during the sapphire stripping process due to the stress generated by the difference in thermal expansion coefficients between the sapphire, the gallium nitride film, and the supporting substrate.
  • a common practice is to find a conductive, thermally conductive support substrate that matches the coefficient of thermal expansion and the corresponding bonding technique.
  • the high energy impact of the decomposition gas of the gallium nitride film during the laser stripping process causes the pulling force of the sapphire stripping on the gallium nitride film, which may cause damage and cracking of the gallium nitride film. .
  • the conventional method is to directly bond the epitaxial layer on the sapphire to the conductive and thermally conductive substrate, and sapphire is peeled off to form a device structure, but the chip yield thus obtained is low.
  • This method fails to solve the stress effect during laser stripping, which causes cracking of a large number of gallium nitride thin film chips. Summary of the invention
  • the first technical problem to be solved by the present invention is to provide a method for preparing a GaN-based thin film chip for solving the problem of cracking of an epitaxial film which occurs when laser-peeling a sapphire substrate.
  • the present invention provides a method for fabricating a GaN-based thin film chip, comprising the steps of: sequentially growing an n-type GaN layer, an active layer, and a p-type GaN layer on a sapphire substrate to form a semiconductor multilayer. Structure; thinning and polishing the sapphire substrate; coating the first adhesive on the semiconductor multilayer structure, curing with the first temporary substrate; laser stripping the sapphire substrate, applying the second adhesive on the peeling surface, and curing to a second temporary substrate; removing the first temporary substrate and the first adhesive; bonding the semiconductor multilayer structure to the permanent supporting substrate by eutectic bonding; removing the second temporary substrate and the second adhesive.
  • the semiconductor multilayer structure is further vapor-deposited with a conductive reflective composite metal layer and subjected to alloy treatment at an alloy temperature of 400 to 600 °C.
  • the sapphire is thinned and polished to 100 to 150 ⁇ m.
  • the unit device is separated.
  • the first glue is a high-temperature epoxy resin modified glue, which has a Shore hardness of 80-100D after curing, a temperature resistance range of -25-300 ° C, and a bending strength of 80- -120MPa, compressive strength 200 ⁇ 300MPa.
  • the first adhesive has a thickness of 10-100 ⁇ m, a curing temperature of 80-160 ° C, and a curing time of 30-120 minutes.
  • the second adhesive is a modified heterocyclic resin, and has a temperature resistance range of -55 to +42 (TC, tensile strength of 60 to 100 MPa, and tensile strength of 105 to 200 MPa.
  • the second adhesive has a thickness of 5 to 30 ⁇ m, a curing temperature of 120 to 180 ⁇ , and a curing time of 10 to 60 minutes.
  • the material of the first and second temporary substrates is any one of silicon, sapphire, glass or ceramic materials.
  • the permanent support substrate is a silicon substrate.
  • the bonding method employs Au-Sn bonding at a temperature of 200 to 400 °C.
  • the epitaxial layer is transferred a plurality of times by using a glue, especially the sapphire epitaxial layer is bonded to the first temporary substrate by gel before laser stripping, since the adhesive has appropriate strength and hardness, the sapphire substrate is peeled off.
  • the GaN decomposition energy is uneven, the tearing strength of the sapphire film on the gallium nitride film can be effectively reduced, thereby reducing damage to the gallium nitride film, and the process can be greatly improved.
  • the yield of the obtained GaN-based thin film chip since the epitaxial layer is transferred a plurality of times by using a glue, especially the sapphire epitaxial layer is bonded to the first temporary substrate by gel before laser stripping, since the adhesive has appropriate strength and hardness, the sapphire substrate is peeled off.
  • the GaN decomposition energy is uneven, the tearing strength of the sapphire film on the gallium nitride film can be effectively reduced, thereby reducing damage to the gallium nitrid
  • a second technical problem to be solved by the present invention is to provide a chip production method for solving the problem of cracking of an epitaxial film when a sapphire substrate is peeled off.
  • the present invention provides a method for producing a GaN-based thin film chip, comprising: growing a GaN layer, an active layer, and a P-type GaN layer on a sapphire substrate to form an epitaxial layer; etching the epitaxial layer: on the epitaxial layer Gluing, adhering the first temporary substrate and curing; laser stripping the sapphire substrate; bonding the peeled surface to the second temporary substrate; removing the first temporary substrate and the adhesive layer to expose the epitaxial layer; and supporting the substrate permanently Bonding; etching the second substrate.
  • the epitaxial wafer is thinned to 200-400 microns prior to etching.
  • the etching has a depth of at least 1 micrometer.
  • the protective layer is first evaporated on the P-type GaN layer, and the protective layer material is Ti,
  • the protective layer has a thickness of 100-1000 nm.
  • the laser lift-off method is progressive scanning or single-grain peeling, preferably single-grain peeling.
  • the protective layer may be first evaporated, and the protective layer material is made of Ti, Ni, Al, Pt, Pd, Au, Cr, Ag, Si0 2
  • the protective layer material is made of Ti, Ni, Al, Pt, Pd, Au, Cr, Ag, Si0 2
  • Ti0 2 , IT0, A1 2 0 3 , and MgF 2 is made of Ti, Ni, Al, Pt, Pd, Au, Cr, Ag, Si0 2
  • Ti0 2 , IT0, A1 2 0 3 , and MgF 2 with a thickness of 1 nm
  • the bonding with the second temporary substrate is one or more of Au-Au, Au-In, In-In, Ag-Sn, In-Sn, preferably Au- In bonding.
  • the first or second temporary substrate or the permanent supporting substrate may be one or more of Si, ceramic, W, Cu, Mo, GaAs, graphite, using wet etching or mechanical
  • the first and second temporary substrates are removed by a grinding method.
  • the substrate is removed by wet etching, and the etching solution may be sulfuric acid, hydrochloric acid, nitric acid, hydrofluoric acid, acetic acid, potassium hydroxide, hydrogen peroxide, ammonia water, One or more of bromine water, oxalic acid, potassium permanganate, potassium iodide, iodine, ammonium iodide.
  • the etching solution may be sulfuric acid, hydrochloric acid, nitric acid, hydrofluoric acid, acetic acid, potassium hydroxide, hydrogen peroxide, ammonia water, One or more of bromine water, oxalic acid, potassium permanganate, potassium iodide, iodine, ammonium iodide.
  • the reflective material comprises one or more of Ti, Ni, Al, Pt, Pd, Au, Cr, Ag, Si0 2 , Ti0 2 , IT0, ⁇ 1 ⁇ , MgF 2 , preferably Ag, Al, Si0 2 , the reflective layer has a thickness of 50-400 nm.
  • a protective layer on the reflective material including Ti, Ni, Al, Pt, Pd, Au, Cr, Ag, Si0 2 , Ti0 2 , IT0, A1 2 0:, MgF 2
  • a protective layer thickness of from 1 nm to 1000 nm.
  • the bonding manner with the permanent supporting substrate includes one or more of Au-Au, Au-In, In-In, Ag-In, Ag-Sn, and In-Sn.
  • An Au-Sn bonding mode is preferred.
  • a third technical problem to be solved by the present invention is to provide a method of manufacturing a gallium nitride chip which can solve the problem of cracking of an epitaxial film caused by peeling off a sapphire substrate.
  • the present invention provides a method for fabricating a sapphire-peeled thin film GaN chip, comprising the steps of: etching an epitaxial layer on a sapphire substrate;
  • the second substrate and the resin are removed, and the second substrate can also be removed before the laser peeling.
  • the etching is performed by ICP or RIE dry etching, wherein the etching has a depth of at least 1 ⁇ m, preferably 5-7 ⁇ m.
  • the reflective layer material includes one or more of Ti, Ni, Al, Pt, Pd, Au, Cr, Ag, Si0 2 , Ti0 2 , IT0, ⁇ 1 ⁇ , and MgF 2 .
  • Ag, Al, SiO 2 , and the reflective layer material have a thickness of 500 to 4000 angstroms.
  • the protective layer material is made of Ti, Ni, Al, Pt, Pd, Au, Cr, Ag, Si0 2 , Ti0 2 , IT0, ⁇ 1 ⁇ , M g
  • F 2 preferably IT0, Ni, Au, Cr, Pt
  • the protective layer material has a thickness of 1000-10000 ⁇ .
  • the bonding to the permanent substrate includes one of Au-Au, Au-In, In-In, Ag-In, Ag-Sn, and In-Sn, preferably an Au-Sn bond. Hehe.
  • the adhesive is an epoxy resin or an acrylic resin
  • the curing method is heat curing or UV curing
  • the hardness after curing is shore D 10-95, preferably shore D 50-90.
  • the laser lift-off method is progressive scanning, and the laser wavelength is 355 nm.
  • the laser lift-off method is single-crystal peeling, and the laser wavelength is 248 nm or 192 nm.
  • the second substrate is a temporary substrate
  • the temporary substrate and the permanent supporting substrate may be at least one of Si, ceramic, W, Cu, Mo, GaAs, graphite, glass, sapphire, organic materials.
  • One or more of the temporary substrates are removed by wet etching, mechanical grinding or layer-by-layer peeling.
  • the temporary substrate is Si
  • the temporary substrate is removed by wet etching, and the wet etching corrosion solution may be sulfuric acid, hydrochloric acid, nitric acid, hydrofluoric acid, acetic acid, potassium hydroxide.
  • the wet etching corrosion solution may be sulfuric acid, hydrochloric acid, nitric acid, hydrofluoric acid, acetic acid, potassium hydroxide.
  • the bonding material Since the substrate is bonded by the permanent support first, and then the permanently bonded substrate is combined with the temporary substrate by a suitable bonding material, the bonding material has a certain hardness and strength, so that In the subsequent laser lift-off, a reduction in the tearing phenomenon of the GaN layer occurs, and the yield of the GaN thin film chip is improved.
  • Figure la is a schematic illustration of the fabrication of a multilayer semiconductor structure and a composite metal layer on a sapphire substrate in accordance with the present invention.
  • Figure lb is a structural view of the sapphire substrate after thinning and polishing.
  • Figure lc is a structural view of the first temporary substrate bonded.
  • Figure Id is a structural diagram of the sapphire substrate removed.
  • Figure le is a structural view of a second temporary substrate bonded.
  • Figure If is a structural diagram for removing the first temporary substrate.
  • Figure lg is a structural view of a bonded permanent support substrate.
  • Figure lh is a structural view of the second temporary substrate removed.
  • Figure 11a is an epitaxial layer grown on a sapphire substrate.
  • Figure l ib is a grinding and thinning of the sapphire substrate.
  • Figure 11c is an etch of the epitaxial layer to form a recess in the substrate.
  • the lid is a protective layer formed on the epitaxial layer.
  • Figure l is the first temporary substrate bonded.
  • Figure Uf is an epitaxial wafer after laser stripping of a sapphire substrate.
  • Figure 11g is a structural diagram of a bonding second temporary substrate.
  • Figure l lh is a structural diagram of removing the first temporary substrate.
  • Figure lli is a structural diagram of a bonding permanent support substrate.
  • Figure l lj is a structural diagram for removing the second temporary substrate.
  • Figure Ilk is a chip structure diagram after splitting.
  • 21a-21h are processes for preparing a GaN-based thin film chip by the method of the present invention.
  • the present invention includes the following steps: growing an n-type GaN layer, an active layer, and a P-type GaN layer on the sapphire substrate 100 to form an epitaxial layer 110.
  • the epitaxial layer 110 is a GaN-based epitaxial film, which is a multilayer semiconductor structure, and is evaporated.
  • the conductive reflective composite metal layer 120 is as shown in FIG. 1; the sapphire substrate is thinned and polished, as shown in FIG.
  • the conductive reflective composite metal layer 120 is coated with the first adhesive 130, and then cured with the first temporary substrate 140, As shown in Figure lc; the sapphire is laser stripped, the sapphire substrate 100 is detached, as shown in Figure Id; the second adhesive 150 is applied to the surface after peeling, and cured to the second temporary substrate 160, as shown in Fig. 1; In the case of the 160 and the second glue 150, the first temporary substrate 140 and the first adhesive 130 are removed, as shown in FIG.; after the first temporary substrate and the first adhesive are removed, the surface is clear. After washing, the eutectic bonding 170 is performed to form a permanent supporting substrate 180, as shown in FIG. 1g ; the second temporary substrate 160 and the second strand are removed, such as LH ; other processes for chip fabrication are completed.
  • An n-type GaN layer, an active layer, and a p-type GaN layer are sequentially grown in a MOCVD on a sapphire substrate, and Ag is used as a reflective metal film by electron beam evaporation, and then a Cr/Pt/Au multilayer metal film is vapor-deposited at 500 ⁇ . Alloy treatment.
  • the sapphire substrate was thinned and polished to a thickness of 120 microns. The sapphire substrate was cut to obtain a separate unit device.
  • the glue is a high-temperature epoxy resin modified glue, which has a Shore hardness of 80-100D after curing, a temperature range of -25-300 ⁇ , a bending strength of 80-120 MPa, and a compressive strength. 200 ⁇ 300MPa. The thickness was 25 ⁇ m, and it was cured at 100 ° C for 60 minutes together with the first temporary substrate silicon substrate. Laser peeling through the sapphire substrate surface, using a 248 nm excimer laser with a power of 500 mW, and applying another glue on the peeled surface.
  • the adhesive is a modified heterocyclic resin with a temperature range of -55 - + 420 ° C, tensile strength 60-100 MPa, tensile strength 105-200 MPa.
  • the second temporary silicon substrate was bonded and cured at a temperature of 150 ° C for 30 minutes.
  • the first temporary silicon substrate is etched by hydrofluoric acid plus hydrogen peroxide plus nitric acid (5:2:2), and the high temperature epoxy resin is modified by using toluene at 100 ° C. gum.
  • Au-Sn bonding is then applied to the permanently supported silicon substrate at a temperature of 300 ⁇ :.
  • the permanently supported silicon substrate was protected with wax, the second temporary silicon substrate was etched with hydrofluoric acid plus hydrogen peroxide plus nitric acid (5:2:2), and the modified heterocyclic resin was etched away with sulfuric acid sulfate. Then, the surface of the obtained n-type GaN layer was cleaned to fabricate an N electrode.
  • An n-type GaN layer, a light-emitting layer, and a p-type GaN layer are sequentially grown on the sapphire substrate, and Ag is used as a reflective metal film and a multilayer metal film Cr/Pt/Au by electron beam evaporation, and is treated with a 500 ⁇ alloy.
  • the sapphire substrate is thinned and polished to a sapphire thickness of 150 microns.
  • the sapphire substrate was cut, and the sapphire unit was glued to a high-temperature epoxy resin modified paste having a thickness of 20 ⁇ m, and bonded to a silicon substrate, and cured at 12 CTC for 40 minutes.
  • the stripped sapphire unit was coated with another gel, a modified heterocyclic resin, and cured at 120 ° C for 60 minutes.
  • the silicon substrate is first etched with hydrofluoric acid and hydrogen peroxide (5:2:2), and the high temperature epoxy resin modified rubber is etched at 120 degrees with acetamide, and the second surface rubber is protected with wax.
  • Au-In is bonded to the silicon substrate at a temperature of 230 ⁇ ; the P-side silicon substrate is protected with wax, and the silicon substrate is first etched with hydrofluoric acid and hydrogen peroxide (5:2:2), and then N is etched.
  • the modified heterocyclic resin was etched away with sulfuric acid sulfate. For the N-side cleaning and passivation treatment, an N electrode was fabricated.
  • a buffer layer, an n-type GaN layer, a light-emitting layer, p-type GaN or the like was sequentially grown by MOCVD on a sapphire substrate, and AgPt was vapor-deposited as a reflective composite layer, and treated at 50 CTC alloy.
  • the obtained epitaxial wafer was waxed and polished to have a sapphire thickness of 400 ⁇ m.
  • the sapphire substrate was cut and the sapphire unit was glued.
  • the glue was a high temperature epoxy resin modified adhesive with a thickness of 60 microns. It was bonded to the sapphire substrate and cured at 120 Torr for 60 minutes. Laser stripping through the sapphire surface, using a 248 nm excimer laser with a power of 550 mW.
  • the stripped sapphire unit is coated with another modified heterocyclic resin, bonded to a silicon substrate, and subjected to 120 ° C. Cured for 60 minutes.
  • the sapphire substrate was etched with acetamide at 120 Torr to remove the sapphire substrate, while the second surface was protected with wax.
  • Au-Sn is bonded to the silicon substrate at a temperature of 310 ° C; the P-side silicon substrate is protected with wax, and the N-side silicon substrate is first etched by hydrofluoric acid plus hydrogen peroxide plus nitric acid (5:2:2).
  • the N-face modified heterocyclic resin was etched away with sulfuric acid sulfate.
  • the N electrode was fabricated by cleaning and passivating the N surface.
  • a buffer layer, n-type GaN, a light-emitting layer, and a p-type GaN layer were sequentially grown by MOCVD on a sapphire substrate, and Ag was vapor-deposited as a reflective composite layer, and treated in a 500'C alloy.
  • the obtained epitaxial wafer was waxed and polished to have a sapphire thickness of 400 ⁇ m.
  • the sapphire substrate was cut, and the sapphire unit was coated with a high-temperature epoxy resin modified glue having a thickness of 40 ⁇ m, and bonded to a silicon substrate, and cured at 110 ° C for 70 minutes.
  • Figure l la-l lk is a process for preparing a GaN-based thin film chip by the method of the present invention.
  • an n-GaN layer, an active layer, and a P-GaN layer are first grown on the sapphire substrate 11-100 by an MOCVD apparatus to form an epitaxial layer 11-110.
  • the epitaxial wafer obtained by epitaxial growth is mechanically ground and thinned, for example, to 380 ⁇ m, as shown in FIG.
  • Use 1CP or Other etched epitaxial layers may or may not be etched through the epitaxial layer, such as an etch depth of 5.5 microns, as shown in FIG.
  • the protective layer 11-120 is evaporated on the P-type GaN layer, and the protective layer is composed of a Ti layer and an A1 layer having a thickness of 3000 ⁇ and 3000 ⁇ , respectively.
  • the protective layer is also not necessary, as shown in FIG. Applying a glue on the protective layer, the adhesive is epoxy resin 11-130, the epoxy resin is a modified epoxy resin, the temperature is above 150 ,, and the first temporary substrate 11-140 is adhered,
  • the substrate may be a silicon substrate, or may be ceramic, W, Cu, Mo, GaAs, graphite, etc., and the first temporary substrate and the glue are cured at 80 Torr for 30 minutes, as shown in FIG.
  • the laser-peeled sapphire substrate is exposed to expose the n-type GaN layer of the epitaxial layer 11-110, as shown in FIG.
  • the protective layer of the TiAu layer 11-150 is evaporated on the n-type GaN layer by electron beam evaporation, and the layer includes a 5000 ⁇ Ti layer and a 5000 ⁇ Au layer, and then bonded at 250 ° C with Au-In bonding.
  • 11-160 is bonded to the second temporary silicon substrate 11-170, as shown in FIG.
  • the second temporary silicon substrate is protected by applying a layer of wax or the like to the surface, and then etching the first temporary silicon substrate 11-140, the epoxy resin 11-130 and the protective layer by using nitric acid, hydrofluoric acid and sulfuric acid.
  • the p-type GaN layer of the epitaxial layer 11-110 is exposed, as shown in FIG.
  • An Ag layer of 1000 angstroms was evaporated on the p-type GaN layer as the reflective material 11-180, and the alloy was 420 ⁇ for 10 minutes. It is noted that the reflective material may also be performed after the initial epitaxial material growth.
  • the Pt layer 11-190 was evaporated by electron beam evaporation to a thickness of 1000 ⁇ , and then bonded to the permanently supported silicon substrate 11-210 by means of Au-Au bonding 11-200 at a temperature of 350 V, as shown in Fig. 11i.
  • the silicon substrate and the Auln layer are sequentially etched by using nitric acid, hydrofluoric acid and ammonium iodide solution, and the n-type GaN layer is obtained again, as shown in FIG.
  • the n-type GaN layer is roughened in a KOH solution, and the electron beam is evaporated to form an A1 electrode, and the chip manufacturing process is completed to obtain a chip, as shown in FIG.
  • 21a-21h are processes for preparing a GaN-based thin film chip by the method of the present invention.
  • an n-type GaN layer, an active layer, and a p-type GaN layer are grown on the sapphire substrate 100 by a MOCVD apparatus to form epitaxial layers 21-110, as shown in Fig. 21a.
  • the epitaxial layer was etched to a depth of 5.5 ⁇ m to etch the epitaxial layer as shown in Fig. 21b.
  • Evaporating the composite reflective layer material 21-120 by electron beam respectively evaporating the Ni layer and the Ag layer to a thickness of 20 angstroms and 1000 angstroms respectively, and alloying at 420 ° C for 10 minutes, and then evaporating the Pt layer and the Au layer by electron beam, respectively.
  • the silicon substrate (permanent support substrate) 21-140 is Au-Sn bonded to the composite reflective material 21-130 at a temperature of 360 ⁇ as shown in Fig. 21d.
  • the other side of the silicon substrate is coated with a glue 21-150, and cured with a temporary silicon substrate (i.e., second substrate) 21-160, as shown in Fig. 21e.
  • Laser peeling is performed to peel off the sapphire substrate 21-100, as shown in Fig. 21f. It is noted that the second substrate can also be removed before laser stripping.
  • the temporary silicon substrate and the adhesive layer were etched with nitric acid, sulfuric acid, hydrogen peroxide, and hydrofluoric acid, as shown in Fig. 21g.
  • the epitaxial surface is roughened by a conventional process, electron beam is evaporated, and an aluminum electrode is prepared to obtain a chip, as shown in Fig. 21h.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Led Devices (AREA)
  • Semiconductor Lasers (AREA)

Description

氮化镓基薄膜芯片的生产制造方法 技术领域
本发明涉及半导体发光器件的制备工艺。更具体而言，本发明涉及采用激光剥离工艺制备 GaN基薄膜 芯片的方法。。
背景技术
蓝宝石衬底作为氮化镓基 LED外延生长的主要衬底， 其导电性和散热性都比较差。 由于导电性差， 发光器件要采用横向结构， 导致电流堵塞和发热。 而较差的导热性能限制了发光器件的功率。 采用激光剥 离技术将蓝宝石衬底去除后， 将发光二极管做成垂直结构， 可以有效解决散热和出光问题。 成品率低是利 用激光剥离蓝宝石衬底技术产业化的瓶颈。 由于蓝宝石、 氮化镓薄膜和支撑衬底三者热膨胀系数的差异产 生的应力， 使氮化镓薄膜在蓝宝石剥离过程中容易破裂。 普通的做法是寻找热膨胀系数相匹配的导电、 导 热性好的支撑衬底以及相应的键合技术。 但由于键合界面不平整和存在很小的空隙， 在激光剥离过程中氮 化镓薄膜分解气体的高能冲击造成蓝宝石剥离对氮化镓膜的拉扯力， 会导致氮化镓薄膜的损伤和破裂。 传 统方法是将蓝宝石上的外延层直接键合到导电导热衬底上， 将蓝宝石剥离后做成器件结构， 但是这样得到 的芯片合格率很低。 该方法没能解决激光剥离过程中的应力作用， 会导致大量氮化镓薄膜芯片发生开裂。 发明内容
本发明要解决的第一个技术问题是提供一种 GaN基薄膜芯片的制备方法，用于解决在激光剥离蓝宝石 衬底时发生的外延薄膜破裂的问题。
为解决上述第一个技术问题， 本发明提出一种 GaN基薄膜芯片的制备方法，包括以下步骤： 在蓝宝石 衬底上依次生长 n型 GaN层、 活性层、 p型 GaN层， 形成半导体多层结构； 对蓝宝石衬底进行减薄和抛 光处理； 半导体多层结构上涂第一胶， 与第一临时基板进行固化； 将蓝宝石衬底进行激光剥离， 在剥离面 涂第二胶， 并固化到第二临时基板； 将第一临时基板和第一胶去掉； 采用共晶键合方式将所述半导体多层 结构与永久支撑基板结合； 去掉第二临时基板和第二胶。
作为本发明的优选方案，其中所述半导体多层结构上还蒸镀有导电反射复合金属层，并进行合金处理， 合金温度为 400-600°C。
作为本发明的优选方案， 其中所述蓝宝石减薄抛光到 100-150微米。
作为本发明的优选方案， 其中对所述半导体多层结构进行周期性切割处理， 分离单元器件。
作为本发明的优选方案，其中所述第一胶为一种高温环氧树脂改性胶，其固化后邵氏硬度在 80— 100D, 耐温度范围 -25— 300°C， 拉弯强度 80--120MPa， 压縮强度 200~300MPa。
作为本发明的优选方案， 其中所述第一胶厚度为 10-100微米， 固化温度 80-160'C， 固化时间 30-120 分钟。
作为本发明的优选方案， 其中所述第二胶为改性杂环树脂， 耐温范围 -55— +42(TC， 拉伸强度 60 -lOOMPa, 拉弯强度 105-200 MPa。
作为本发明的优选方案， 其中所述第二胶的厚度为 5-30微米， 固化温度 120— 180Ό , 固化时间 10— 60分钟。
作为本发明的优选方案， 其中所述第一和第二临时基板的材质为硅、 蓝宝石、 玻璃或陶瓷材质中的任 一种。
作为本发明的优选方案， 其中所述永久支撑基板为硅基板。
作为本发明的优选方案， 其中所述键合方式采用 Au-Sn键合， 温度为 200-400°C。
上述第一个技术方案的有益效果如下：
本发明由于采用胶将外延层进行多次转移， 尤其是在激光剥离前将蓝宝石外延层用胶粘结在第一临时基板 上， 由于该胶具有适当的强度和硬度， 在进行蓝宝石衬底剥离的时候， 可以有效降低氮化镓分解能量不均 匀导致整面蓝宝石对氮化镓薄膜的撕扯强度， 从而降低对氮化镓薄膜的损伤， 可以大大提高通过这种工艺 得到的 GaN基薄膜芯片的良率。
本发明要解决的第二个技术问题是提供一种芯片生产方法， 其用于解决在剥离蓝宝石衬底时外延薄膜 破裂的问题。
为了解决该问题，本发明提出一种 GaN基薄膜芯片的生产方法，包括在蓝宝石衬底上生长型 GaN层、 活性层、 P型 GaN层， 形成外延层； 刻蚀外延层： 在外延层上涂胶， 黏附第一临时基板并固化； 对蓝宝石 衬底进行激光剥离； 将剥离后的表面与第二临时基板键合； 除掉第一临时基板和胶层， 露出外延层； 与永 久支撑基板进行键合； 腐蚀第二基板。
作为本发明的优选方案， 其中在刻蚀以前将外延片减薄到 200-400微米。
作为本发明的优选方案， 其中所述刻蚀的深度为至少 1微米。
作为本发明的优选方案， 其中在涂覆所述胶前， 在 P型 GaN层上先蒸发保护层， 保护层材料由 Ti、
Ni、 Al、 Pt、 Pd、 Au、 Cr、 Ag、 Si02、 Ti02、 IT0、 Α1Λ、 MgF2其中的一种或几种组成， 优选 IT0、 Ti、 Ni、
Al、 Au、 Si02， 保护层厚度为 100-1000纳米。
作为本发明的优选方案， 其中激光剥离方式为逐行扫描或者单晶粒剥离， 优选为单晶粒剥离。
作为本发明的优选方案， 其中在 N型 GaN层与临时基板键合前， 还可以先蒸鍍保护层， 保护层材料 由 Ti、 Ni、 Al、 Pt、 Pd、 Au、 Cr、 Ag、 Si02、 Ti02、 IT0、 A1203、 MgF2中的一种或几种组成， 厚度为 1纳米
-1000纳米。
作为本发明的优选方案， 其中所述与第二临时基板的键合为 Au-Au， Au-In, In- In, Ag-Sn, In- Sn中 的一种或几种， 优选为 Au-In键合。
作为本发明的优选方案， 其中所述第一、 第二临时基板或者永久支撑基板可以为 Si、 陶瓷、 W、 Cu、 Mo、 GaAs、 石墨中的一种或者几种， 采用湿法腐蚀或者机械研磨的方法去除所述第一、 第二临时基板。
作为本发明的进一步优选方案， 其中所述临时基板为 Si， 采用湿法腐蚀的方法去除衬底， 腐蚀液可以 是硫酸、 盐酸、 硝酸、 氢氟酸、 乙酸、 氢氧化钾、 双氧水、 氨水、 溴水、 草酸、 高锰酸钾、 碘化钾、 碘、 碘化铵中的一种或几种。
作为本发明的优选方案， 其中所述反射材料包括 Ti、 Ni、 Al、 Pt、 Pd、 Au、 Cr、 Ag、 Si02、 Ti02、 IT0、 Α1Λ、 MgF2其中的一种或几种， 优选 Ag、 Al、 Si02, 反射层厚度为 50- 400纳米。
作为本发明的优选方案， 其中在反射材料上还有一保护层， 包括 Ti、 Ni、 Al、 Pt、 Pd、 Au、 Cr、 Ag、 Si02、 Ti02、 IT0、 A120:,、 MgF2其中的一种或几种，优选 Ti、 Ni、 Al、 Cr、 Pt、 Au, 保护层厚度为 1纳米- 1000 纳米。
作为本发明的优选方案，其中所述与永久支撑基板的键合方式包括 Au-Au、 Au-In, In-In、 Ag-In、 Ag-Sn, In-Sn中的一种或几种， 优选 Au-Sn键合方式。
上述第二个技术方案的有益效果如下： 由于采用了多次转移， 并且在第二次转移过程中， 采取了键合 的方式固定第二临时基板，可以使得第一次临时基板和相应的胶可以很顺利的腐蚀掉，使得工艺带来方便， 提高了生产的良率。
本发明要解决的第三个技术问题是提供一种氮化镓芯片的制造方法， 该方法能解决在剥离蓝宝石衬底 过程中导致的外延薄膜破裂的问题。
为解决上述问题， 本发明提出一种基于蓝宝石剥离的薄膜 GaN芯片的制造方法， 其包括以下步骤： 刻蚀蓝宝石衬底上的外延层；
在刻蚀的外延层上制备反射层材料， 并进行合金；
与永久支撑基板键合；
在永久支撑基板的另一侧采用树脂与第二基板进行固化；
激光剥离蓝宝石衬底；
剥离后去除第二基板和树脂， 第二基板也可在激光剥离前去掉。
作为本发明的优选方案， 所述刻蚀采用 ICP或 RIE干法刻蚀， 其中所述刻蚀的深度为至少 1微米， 优 选为 5-7微米。
作为本发明的优选方案， 其中所述反射层材料包括 Ti、 Ni、 Al、 Pt、 Pd、 Au、 Cr、 Ag、 Si02、 Ti02、 IT0、 Α1Λ、 MgF2其中的一种或多种， 优选 Ag、 Al、 Si02， 反射层材料厚度为 500- 4000埃。 作为本发明的优选方案， 其中在反射层材料外面还有保护层， 保护层材料由 Ti、 Ni、 Al、 Pt、 Pd、 Au、 Cr、 Ag、 Si02、 Ti02、 IT0、 Α1Λ、 MgF2其中的一种或多种组成, 优选 IT0、 Ni、、 Au、、 Cr、 Pt, 保护层 材料厚度为 1000-10000埃。
作为本发明的优选方案， 其中所述与永久基板的键合包括 Au-Au、 Au-In、 In-In、 Ag-In、 Ag-Sn、 In-Sn 中的一种， 优选 Au-Sn键合。
作为本发明的优选方案， 其中胶为环氧树脂胶或者丙烯酸树脂胶， 其固化方式为热固化或者 UV固化， 其固化后硬度为 shore D 10-95, 优选为 shore D 50-90。
作为本发明的优选方案， 其中激光剥离方式为逐行扫描， 激光波长为 355nm。
作为本发明的优选方案， 其中激光剥离方式为单晶粒剥离， 激光波长为 248nm或 192nm。
作为本发明的优选方案， 其中所述第二基板为临时基板， 该临时基板、 永久支持基板至少一种可以为 Si、 陶瓷、 W、 Cu、 Mo、 GaAs、 石墨、 玻璃、 蓝宝石、 有机材料中的一种或者多种， 采用湿法腐蚀、 机 械研磨或逐层剥离的方法去除临时基板。
作为本发明的进一步优选方案， 其中所述临时基板为 Si， 采用湿法腐蚀的方法去除该临时基板， 湿法 腐蚀的腐蚀液可以是硫酸、 盐酸、 硝酸、 氢氟酸、 乙酸、 氢氧化钾、 双氧水、 氨水、 溴水、 草酸、 高猛酸 钾、 碘化钾、 碘、 碘化铵中的一种或几种。
上述第三个技术方案的有益效果： 由于采用先进行永久支持基板键合， 而后永久键合的基板又通过合 适的粘结材料与临时基板结合， 粘接材料具有一定的硬度和强度， 使得在随后的激光剥离中， 出现对于 GaN层的撕扯现象的减少， 使 GaN薄膜芯片的合格率提高。
附图说明
图 la是本发明在蓝宝石衬底上制备多层半导体结构和复合金属层的示意图。
图 lb是对蓝宝石衬底进行减薄和抛光处理后的结构图。
图 lc是粘合第一临时基板的结构图。
图 Id是去除蓝宝石衬底的结构图。
图 le是粘合第二临时基板的结构图。
图 If是去除第一临时基板的结构图。
图 lg是键合永久支撑基板的结构图。
图 lh是去除第二临时基板的结构图。
图 11a是在蓝宝石衬底上生长外延层。
图 l ib是对蓝宝石衬底进行研磨减薄。
图 11c是对外延层进行刻蚀， 在衬底上形成凹槽。
图 lid是在外延层上形成保护层。
图 l ie是粘接第一临时基板。
图 Uf是激光剥离蓝宝石衬底后的外延片。
图 llg是邦定第二临时基板的结构图。
图 l lh是去除第一临时基板的结构图。
图 lli是邦定永久支撑基板的结构图。
图 l lj是去除第二临时基板的结构图。
图 Ilk是经过裂片后的芯片结构图。
图 21a-21h为用本发明的方法制备 GaN基薄膜芯片的工艺过程。
具体实施方式
下面结合附图和实施例对本发明进一步说明。
本发明包括以下步骤： 在蓝宝石衬底 100上用 MOCVD生长 n型 GaN层、 活性层、 P型 GaN层， 形 成外延层 110， 外延层 110为 GaN基外延薄膜， 为多层半导体结构， 蒸镀导电反射复合金属层 120， 如图 la; 对于蓝宝石衬底进行减薄和抛光处理， 如图 lb; 将导电反射复合金属层 120进行涂第一胶 130， 然后 与第一临时基板 140进行固化， 如图 lc; 将蓝宝石进行激光剥离， 蓝宝石衬底 100脱落， 如图 Id; 在剥 离后的表面涂第二胶 150， 并固化到笫二临时基板 160， 如图 le; 在保护第二临时基板 160和第二胶 150 的情况下， 将第一临时基板 140和第一胶 130去掉， 如图 If; 在去掉第一临时基板和第一胶后的表面经清 洗后， 进行共晶键合 170， 形成永久支撑基板 180， 如图 lg; 去掉第二临时基板 160和第二股， 如田 lh; 完成芯片制作的其他工艺。
具体实施例 1
在蓝宝石衬底上在 MOCVD中依次生长 n型 GaN层、 活性层、 p型 GaN层， 采用电子束蒸发蒸镀 Ag 作为反射金属膜， 然后蒸镀 Cr/Pt/Au多层金属膜，在 500Ό合金处理。对蓝宝石衬底进行减薄和抛光处理， 使蓝宝石衬底厚度为 120微米。 切割蓝宝石衬底， 得到分离的单元器件。 在多层金属膜上进行涂胶， 胶为 一种高温环氧树脂改性胶，其固化后邵氏硬度在 80— 100D,耐温度范围 -25— 300Ό，拉弯强度 80— 120MPa， 压缩强度 200~300MPa。 厚度为 25微米， 与第一临时基板硅基板粘结一起， 在 100°C温度下进行固化 60 分钟。 透过蓝宝石衬底面进行激光剥离， 采用 248纳米准分子激光， 功率 500mW， 在剥离后的面上再涂 另外一种胶， 该胶为改性杂环树脂， 其耐温范围为 -55— +420°C， 拉伸强度 60— lOOMPa, 拉弯强度 105— 200 MPa。 与第二临时硅基板进行粘结， 并在 150°C温度下进行固化 30分钟。 将第二临时硅基板用蜡进行 保护后， 用氢氟酸加双氧水加硝酸（5: 2： 2)腐蚀第一临时硅基板， 采用甲苯在 100'C下进行腐蚀该高温 环氧树脂改性胶。 然后进行 Au-Sn键合到永久支撑硅基板， 温度为 300Ϊ：。 将永久支撑硅基板用蜡进行保 护， 用氢氟酸加双氧水加硝酸 （5: 2： 2)腐蚀第二临时硅基板， 并用硫酸双氧水腐蚀掉改性杂环树脂胶。 然后对于得到的 n型 GaN层表面进行清洗， 制造 N电极。
具体实施例 2
蓝宝石衬底上依次生长 n型 GaN层、 发光层、 p型 GaN层， 采用电子束蒸发蒸镀 Ag作为反射金属 膜和多层金属膜 Cr/Pt/Au， 在 500Ό合金处理。 对蓝宝石衬底进行减薄和抛光处理， 使蓝宝石厚度为 150 微米。 切割蓝宝石衬底， 将蓝宝石单元进行涂胶， 胶为高温环氧树脂改性胶， 厚度为 20微米， 与硅基板 粘结一起， 在 12CTC下进行固化 40分钟。透过蓝宝石面进行激光剥离， 采用 193nm准分子激光， 功率 480 毫瓦， 剥离后的蓝宝石单元再涂敷另外一种胶——改性杂环树脂， 并在 120'C下进行固化 60分钟。先用氢 氟酸加双氧水加硝酸 （5: 2： 2) 腐蚀硅基板， 再采用乙酰胺在 120度进行腐蚀高温环氧树脂改性胶， 同 时将第二面胶用蜡进行保护。 然后进行 Au-In键合到硅基板上， 温度为 230Ό ; 将 P面的硅基板用蜡进行 保护， 先用氢氟酸加双氧水加硝酸 （5: 2： 2)腐蚀硅基板， 然后将 N面的改性杂环树脂用硫酸双氧水腐 蚀掉。 对于 N面进行清洗和钝化处理， 制作 N电极。
具体实施例 3
在蓝宝石衬底上用 MOCVD依次生长缓冲层， n型 GaN层， 发光层， p型 GaN等， 并蒸镀 AgPt作为 反射复合层， 在 50CTC合金处理。 将得到的外延片上蜡， 进行抛光处理， 使蓝宝石厚度为 400微米。 切割 蓝宝石衬底， 将蓝宝石单元进行涂胶， 胶为高温环氧树脂改性胶， 厚度为 60微米， 与蓝宝石基板粘结一 起，在 120Ό下进行固化 60分钟。透过蓝宝石面进行激光剥离，采用 248纳米准分子激光，功率 550毫瓦， 剥离后的蓝宝石单元再涂敷另外一种改性杂环树脂， 与硅基板粘结， 并在 120'C下进行固化 60分钟。采用 乙酰胺在 120Ό进行腐蚀高温环氧树脂改性胶， 使蓝宝石衬底脱离， 同时将第二面胶用蜡进行保护。 然后 进行 Au-Sn键合到硅基板上， 温度为 310'C ; 将 P面的硅基板用蜡进行保护， 先用氢氟酸加双氧水加硝酸 ( 5： 2： 2 )腐蚀 N面硅基板， 然后将 N面的改性杂环树脂用硫酸双氧水腐蚀掉。 在对 N面进行清洗和钝 化处理， 制作 N电极。
具体实施例 4
在蓝宝石衬底上用 MOCVD依次生长缓冲层， n型 GaN, 发光层， p型 GaN层， 并蒸镀 Ag作为反射 复合层， 在 500'C合金处理。 将得到的外延片上蜡， 进行抛光处理， 使蓝宝石厚度为 400微米。 切割蓝宝 石衬底， 将蓝宝石单元进行涂胶， 胶为高温环氧树脂改性胶， 厚度为 40微米， 与硅基板粘结一起， 在 110 °C温度下进行固化 70分钟。 透过蓝宝石面进行激光剥离， 采用 193纳米准分子激光， 功率 500mw， 剥离 后的蓝宝石单元再涂敷另外一种胶——改性杂环树脂，与蓝宝石基板粘结，并在 150Ό下进行固化 30分钟。 先用氢氟酸加双氧水加硝酸 （5: 2： 2 ) 腐蚀硅基板， 采用甲苯在 100°C下进行腐蚀高温环氧树脂改性胶。 清洗后进行 Au-Sn键合到硅基板，温度为 310'C，然后将 N面的改性杂环树脂用乙酰胺在 120°C进行腐蚀， 蓝宝石基板脱离。 对于 N面进行清洗和钝化处理， 制作 N电极。
图 l la-l lk为用本发明的方法制备 GaN基薄膜芯片的工艺过程。
如图 lla， 首先用 MOCVD设备在蓝宝石衬底 11-100上生长 n-GaN层、 活性层、 P-GaN层， 形成外 延层 11-110。 将外延生长得到的外延片进行机械研磨减薄， 比如减薄到 380微米， 如图 l lb。 采用 1CP或 其它万法刻蚀外延层， 可以将外延层刻穿， 也可以不将外延层刻穿， 如刻蚀深度为 5.5微米， 如图 l lc。 然后在 P型 GaN层上蒸发保护层 11-120, 保护层由 Ti层和 A1层组成， 厚度分别 3000埃和 3000埃， 应 该注意的是， 该保护层也不是必须的， 如图 l ld。 在保护层上方涂覆上粘胶， 粘胶为环氧树脂 11-130， 该 环氧树脂为一种改性环氧树脂， 耐温 150Ό以上， 并黏附上第一临时基板 11-140， 该基板可以为硅基板， 也可以为陶瓷、 W、 Cu、 Mo、 GaAs、石墨等， 在 80Ό下将第一临时基板与胶进行固化 30分钟， 如图 l l e。 然后进行激光剥离蓝宝石衬底， 露出外延层 11-110的 n型 GaN层， 如图 l lf。用电子束蒸发的方式在 n型 GaN层上蒸发 TiAu层 11-150的保护层， 该层包括 5000埃的 Ti层和 5000埃的 Au层， 然后在 250°C下釆 用 Au-In键合 11-160与第二临时硅基板 11-170进行键合， 如图 l lg。将第二临时硅基板进行保护， 可以在 表面涂上一层蜡等方法， 然后依次釆用硝酸、 氢氟酸和硫酸腐蚀第一临时硅基板 11-140、 环氧树脂 11-130 和保护层 11-120后， 露出了外延层 11-110的 p型 GaN层， 如图 l lh。 在 p型 GaN层上蒸发 1000埃的 Ag 层作为反射材料 11-180, 在 420Ό合金 10分钟， 值得注意的是， 此处反射材料也可以在最初外延材料生长 后进行。 用电子束蒸发的方式蒸发 Pt层 11-190, 厚度为 1000埃， 然后采用 Au-Au键合 11-200方式与永 久支撑硅基板 11-210进行键合， 温度为 350V , 如图 l l i。 在对于永久支撑硅基板进行保护后， 依次采用 硝酸、 氢氟酸和碘化铵溶液腐蚀硅基板和 Auln层， 重新得到 n型 GaN层， 如图 l lj。 在 KOH溶液中粗化 n型 GaN层， 电子束蒸发形成 A1电极， 完成芯片的制造过程， 得到芯片， 如图 l lk。
图 21 a-21h为用本发明的方法制备 GaN基薄膜芯片的工艺过程。
首先用 MOCVD设备在蓝宝石衬底 100上生长 n型 GaN层、活性层、 p型 GaN层，形成外延层 21-110， 如图 21a。 将外延层进行刻蚀， 刻蚀深度为 5.5微米， 将外延层刻开， 如图 21b。 用电子束蒸发复合反射层 材料 21-120， 分别蒸发 Ni层和 Ag层， 厚度分别为 20埃和 1000埃， 在 420°C合金 10分钟， 再用电子束 蒸发 Pt层和 Au层， 厚度分别为 5000埃和 5000埃， 如图 21c。 将硅基板 （永久支持基板） 21 -140与复合 反射材料进行 Au-Sn键合 21-130， 温度为 360Ό , 如图 21d。 将硅基板的另一面涂上粘胶 21-150， 与临时 硅基板（即第二基板） 21-160进行固化， 如图 21e。 进行激光剥离， 剥离掉蓝宝石衬底 21-100， 如图 21 f， 值得注意的是， 也可以在激光剥离前先去掉第二基板。 剥离后用硝酸、 硫酸、 双氧水、 和氢氟酸腐蚀临时 硅基板和胶层， 如图 21g。 用常规工艺对于外延表面进行粗化， 电子束蒸发并制备铝电极， 得到芯片， 如 图 21h。

Claims

1、 一 W UaN ¾溥朕' &斤的制 ¾ "万) ¾，
a. 在蓝宝石衬底上依次生长 n型 GaN层、 活性层、 p型 GaN层， 形成半导体多层结构； b. 对蓝宝石衬底进行减薄和抛光处理；
c 在半导体多层结构上涂第一胶， 与第一临时基板进行固化；
d. 将蓝宝石衬底进行激光剥离， 在剥离面涂第二胶， 并与第二临时基板固化；
e. 将第一临时基板和第一胶去掉；
f. 采用共晶键合方式将所述半导体多层结构与永久支撑基板结合；
g. 去掉第二临时基板和第二胶。
2、 根据权利要求 1所述的 GaN基薄膜芯片的制备方法， 其特征在于： 所述半导体多层结构上还蒸镀有导 电反射复合金属层， 并进行合金处理， 合金温度为 400-600°C。
3、根据权利要求 1所述的 GaN基薄膜芯片的制备方法，其特征在于：所述蓝宝石衬底减薄抛光到 100-150 微米。
4、 根据权利要求 1所述的 GaN基薄膜芯片的制备方法， 其特征在于： 对所述半导体多层结构进行周期性 切割处理， 分离单元器件。
5、 根据权利要求 1所述的 GaN基薄膜芯片的制备方法， 其特征在于： 所述第一胶为一种高温环氧树脂改 性胶， 其固化后邵氏硬度在 80— 100D, 耐温度范围 -25— 300 °C， 拉弯强度 80— 120MPa， 压缩强度 200~ 300MPa。
6、 根据权利要求 1所述的 GaN基薄膜芯片的制备方法， 其特征在于： 第一胶厚度为 10-100微米， 固化温 度 80-160 °C , 固化时间 30-120分钟。
7、 根据权利要求 1所述的 GaN基薄膜芯片的制备方法， 其特征在于： 所述第二胶为改性杂环树脂， 其耐 温范围为 -55— +420°C , 拉伸强度 60— 100MPa， 拉弯强度 105— 200 MPa。
8、根据权利要求 1所述的 GaN基薄膜芯片的制备方法， 其特征在于： 所述第二胶的厚度为 5-30微米， 固 化温度 120— 180°C， 固化时间 10— 60分钟。
9、 根据权利要求 1所述的 GaN基薄膜芯片的制备方法， 其特征在于： 所述第一和第二临时基板的材质为 硅、 蓝宝石、 玻璃或陶瓷材质的任一种。
10、 根据权利要求 1所述的 GaN基薄膜芯片的制备方法， 其特征在于： 所述永久支撑基板为硅基板。
11、 根据权利要求 1所述的 GaN基薄膜芯片的制备方法， 其特征在于： 所述共晶键合方式为 Au-Sn键合， 温度为 200-400° ( 。
12、 一种 GaN基薄膜芯片的生产方法， 包括：
在蓝宝石衬底上生长 n型 GaN层、 活性层、 p型 GaN层， 形成外延层；
刻蚀外延层， 并将外延层用胶粘合第一临时基板并固化；
对蓝宝石衬底进行激光剥离；
将剥离后的表面与第二临时基板键合；
腐蚀第一临时基板和胶层， 露出外延层；
蒸发反射材料， 并进行合金， 蒸发保护层材料；
与永久支撑基板进行键合；
腐蚀第二临时基板。
13、 根据权利要求 11所述的一种 GaN基薄膜芯片的生产方法， 其特征在于在刻蚀前将整个外延片减薄达 到 200-400微米。
14、 根据权力要求 11所述的一种 GaN基薄膜芯片的生产方法， 其特征在于刻蚀深度为至少 1微米。
15、根据权力要求 11所述的一种 GaN基薄膜芯片的生产方法，其特征在于在涂覆所述胶前在 P型 GaN层 上先蒸发一层保护层， 保护层材料为 Ti、 Ni、 Al、 Pt、 Pd、 Au、 Cr、 Ag、 Si02、 Ti02、 IT0、 Α1Λ、 MgF2 中的一种或多种， 保护层厚度为 100-1000纳米。
16、 根据权力要求 11所述的一种 GaN基薄膜芯片的生产方法， 其特征在于激光剥离方式为逐行扫描或者 单晶粒剥离。
17、根据权力要求 11所述的一种 GaN基薄膜芯片的生产方法， 其特征在于在 n型 GaN层与第二临时基板 键合前， 先蒸发保护层， 该保护层主要材料包括 Ti、 Ni、 Al、 Pt、 Pd、 Au、 Cr、 Ag、 Si02、 Ti02、 IT0、 Α1 、 MgF2其中的一种或多种， 其厚度是 1纳米- 1000纳米。
18、 根据权力要求 11所述的一种 GaN基薄膜芯片的生产方法， 其特征在于所述与第二临时基板的键合包 括 Au-Au、 Au-In、 In-In、 Ag-In、 Ag-Sn、 In-Sn中的一种或多种。
19、 根据权力要求 11所述的一种 GaN基薄膜芯片的生产方法， 其特征在于第一临时基板、 第二临时基板 和永久支撑基板为 Si、 陶瓷、 W、 Cu、 Mo、 GaAs、 石墨材质中的一种或者多种。
20、 根据权力要求 11所述的一种 GaN基薄膜芯片的生产方法， 其特征在于所述第一临时基板、 第二临时 基板为硅基板， 硅基板通过湿法腐蚀方式去除， 湿法腐蚀的腐蚀液是硫酸、 盐酸、 硝酸、 氢氟酸、 乙酸、 氢氧化钾、 双氧水、 氨水、 溴水、 草酸、 高锰酸钾、 碘化钾、 碘、 碘化铵中的一种或多种。
21、根据权力要求 11所述的一种 GaN基薄膜芯片的生产方法， 其特征在于反射材料包括 Ti、 Ni、 Al、 Pt、 Pd> Au、 Cr、 Ag、 Si02、 Ti02、 IT0、 A1203、 MgF2其中的一种或多种， 其厚度是 50- 400纳米。
22、 根据权力要求 11所述的一种 GaN基薄膜芯片的生产方法， 其特征在于所述保护层材料包括 Ti、 Ni、 Al、 Pt、 Pd、 Au、 Cr、 Ag、 Si02、 Ti02、 IT0、 Α1 、 MgF2其中的一种或几种， 厚度为 1纳米- 1000纳米。
23、 根据权力要求 11所述的一种 GaN基薄膜芯片的生产方法， 其特征在于所述与永久支撑基板的键合包 括 Au-Au、 Au-In、 In-In、 Ag-Sn、 In-Sn中的一种或多种。
24、 一种 GaN基薄膜芯片的生产方法， 包括：
在蓝宝石衬底上生长 n型 GaN层、 活性层、 p型 GaN层， 形成外延层；
蒸发反射材料， 并进行合金， 蒸发保护层材料；
刻蚀外延反射层， 将外延反射层用胶粘合第一临时基板并固化；
对蓝宝石衬底进行激光剥离；
将剥离后的表面与第二临时基板键合；
腐蚀第一临时基板和胶层， 露出外延反射层；
与永久支撑基板进行键合；
腐蚀第二临时基板。
25、 一种基于蓝宝石剥离的薄膜 GaN芯片的制造方法， 其特征在于包括以下步骤：
刻蚀蓝宝石衬底上的外延层；
在刻蚀的外延层上制备反射层材料， 并进行合金；
与永久支撑基板键合；
在永久支撑基板的另一侧采用树脂与第二基板进行固化；
激光剥离蓝宝石衬底；
剥离后去除第二基板和树脂。
26、根据权利要求 25所述的基于蓝宝石剥离的薄膜 GaN芯片的制造方法，其特征在于：所述刻蚀采用 ICP 或 RIE干法刻蚀， 刻蚀厚度为至少为 1微米
27、 根据权利要求 25所述的基于蓝宝石剥离的薄膜 GaN芯片的制造方法， 其特征在于： 所述反射层材料 包括 Ti、 Ni、 Al、 Pt、 Pd、 Au、 Cr、 Ag、 Si02、 Ti02、 ITO、 A1203、 MgF2中的一种或多种。
28、 根据权利要求 27所述的基于蓝宝石剥离的薄膜 GaN芯片的制造方法， 其特征在于： 所述反射层材料 厚度是 500-4000埃。
29、 根据权利要求 25所述的基于蓝宝石剥离的薄膜 GaN芯片的制造方法， 其特征在于： 在所述反射层材 料外面还有保护层，保护层材料包括 Ti、 Ni、 Al、 Pt、 Pd、 Au、 Cr、 Ag、 Si02、 Ti〇2、 ITO、 A1203、 MgF2 其中的一种或多种。
30、 根据权利要求 29所述的基于蓝宝石剥离的薄膜 GaN芯片的制造方法， 其特征在于： 在所述反射层材 料外面还有保护层， 保护层材料其厚度是 1000-10000埃。
31、 根据权利要求 25 所述的基于蓝宝石剥离的薄膜 GaN芯片的制造方法， 其特征在于： 所述键合采用 Au-Au、 Au-In、 In-In、 Ag-In、 Ag-Sn或 In-Sn中的一种。
32、 根据权利要求 25所述的基于蓝宝石剥离的薄膜 GaN芯片的制造方法， 其特征在于： 所述树脂可以是 环氧类树脂或者丙烯酸类树脂， 固化方式为热固化或者 UV固化， 其固化后硬度为 shore D10-95。
33、 根据权利要求 25所述的基于蓝宝石剥离的薄膜 GaN芯片的制造方法， 其特征在于： 所述树脂可以是 环氧类树脂或者丙烯酸类树脂， 固化方式为热固化或者 UV固化， 其固化后硬度为 shOre D50-90。
34、 根据权利要求 25所述的基于蓝宝石剥离的薄膜 GaN芯片的制造方法， 其特征在于： 所述剥离采用逐 行扫面， 激光波长为 355nm。
35、 根据权利要求 25所述的基于蓝宝石剥离的薄膜 GaN芯片的制造方法， 其特征在于： 所述剥离采用单 晶粒剥离， 激光波长为 248nm或 192 nm。
36、 根据权利要求 25所述的基于蓝宝石剥离的薄膜 GaN芯片的制造方法， 其特征在于： 所述第二基板采 用 Si、 陶瓷、 W、 Cu、 Mo、 GaAs、 石墨、 玻璃、 蓝宝石、 有机材料等中的一种或者多种， 采用湿法腐蚀、 机械研磨或者逐层剥离的方法去除该第二基板。
PCT/CN2012/000664 2011-05-19 2012-05-15 氮化镓基薄膜芯片的生产制造方法 WO2012155535A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP12786729.9A EP2711991A4 (en) 2011-05-19 2012-05-15 METHOD FOR PRODUCING A FILM CHIP ON GALLIUM NITRIDE BASE
JP2014510643A JP5792375B2 (ja) 2011-05-19 2012-05-15 窒化ガリウムベースフィルムチップの生産方法および製造方法
US14/083,487 US9224597B2 (en) 2011-05-19 2013-11-19 Method for manufacturing gallium nitride-based film chip

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
CN201110132402.3A CN102790137B (zh) 2011-05-19 2011-05-19 GaN基薄膜芯片的制备方法
CN201110132454.0A CN102790139B (zh) 2011-05-19 基于蓝宝石剥离的薄膜GaN芯片的制造方法
CN201110132454.0 2011-05-19
CN201110132423.5 2011-05-19
CN201110132402.3 2011-05-19
CN201110132423.5A CN102790138B (zh) 2011-05-19 2011-05-19 一种GaN基薄膜芯片的生产方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US14/083,487 Continuation US9224597B2 (en) 2011-05-19 2013-11-19 Method for manufacturing gallium nitride-based film chip

Publications (1)

Publication Number Publication Date
WO2012155535A1 true WO2012155535A1 (zh) 2012-11-22

Family

ID=47176188

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2012/000664 WO2012155535A1 (zh) 2011-05-19 2012-05-15 氮化镓基薄膜芯片的生产制造方法

Country Status (4)

Country Link
US (1) US9224597B2 (zh)
EP (1) EP2711991A4 (zh)
JP (1) JP5792375B2 (zh)
WO (1) WO2012155535A1 (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014094363A1 (zh) * 2012-12-21 2014-06-26 晶能光电（常州）有限公司 一种GaN基白光倒装芯片的制备方法
WO2015063034A1 (de) * 2013-10-28 2015-05-07 Osram Opto Semiconductors Gmbh Optoelektronisches bauelement und verfahren zu seiner herstellung
CN108461586A (zh) * 2018-03-31 2018-08-28 华南理工大学 一种基于NiO纳米点反射镜的垂直结构LED芯片及其制备方法
US20220028907A1 (en) * 2020-07-24 2022-01-27 University Of Southern California Composite substrate for fabricating iii-v photodetector arrays
CN115881862A (zh) * 2023-02-16 2023-03-31 江西兆驰半导体有限公司 一种mini LED芯片减薄方法及mini LED

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE212014000274U1 (de) * 2014-09-19 2017-04-20 Apple Inc. Ausgeglichenes magnetisches Array
TWI581460B (zh) * 2015-09-04 2017-05-01 錼創科技股份有限公司 發光元件及其製作方法
US9595616B1 (en) * 2015-12-02 2017-03-14 Sandia Corporation Vertical III-nitride thin-film power diode
CN105762263A (zh) * 2016-04-01 2016-07-13 陕西新光源科技有限责任公司 一种led芯片用键合衬底的制备方法
DE102016124646A1 (de) 2016-12-16 2018-06-21 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung eines Halbleiterbauelements
CN107369746B (zh) * 2017-08-30 2023-05-23 华南理工大学 一种化学腐蚀剥离衬底的微尺寸谐振腔led芯片及其制备方法
KR102424347B1 (ko) 2018-11-06 2022-07-22 삼성전자주식회사 반도체 칩의 접착 방법
KR102315911B1 (ko) * 2020-01-08 2021-10-22 웨이브로드 주식회사 반도체 발광소자 및 이를 제조하는 방법
CN110943149A (zh) * 2019-12-20 2020-03-31 佛山市国星半导体技术有限公司 一种抗水解红光led芯片及其制作方法
CN112967990B (zh) * 2020-11-23 2023-02-24 重庆康佳光电技术研究院有限公司 芯片处理方法、led芯片及显示装置
TWM645474U (zh) * 2021-09-29 2023-09-01 日商信越半導體股份有限公司 接合體、接合型晶圓、剝離系統及製造系統

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101465401A (zh) * 2008-07-11 2009-06-24 厦门市三安光电科技有限公司 基于平面键合及暂时性基底转移技术的薄膜GaN LED制备方法
EP2302705A2 (en) * 2008-06-02 2011-03-30 Korea University Industrial & Academic Collaboration Foundation Supporting substrate for fabrication of semiconductor light emitting device and semiconductor light emitting device using the same

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3667125B2 (ja) * 1998-12-07 2005-07-06 日亜化学工業株式会社 光半導体装置とその製造方法
US6562648B1 (en) * 2000-08-23 2003-05-13 Xerox Corporation Structure and method for separation and transfer of semiconductor thin films onto dissimilar substrate materials
US8294172B2 (en) * 2002-04-09 2012-10-23 Lg Electronics Inc. Method of fabricating vertical devices using a metal support film
WO2005018008A1 (ja) * 2003-08-19 2005-02-24 Nichia Corporation 半導体素子
JP5021151B2 (ja) * 2003-11-19 2012-09-05 株式会社カネカ 半導体のパッケージ用硬化性樹脂組成物および半導体
JP4843235B2 (ja) * 2004-03-18 2011-12-21 昭和電工株式会社 Ｉｉｉ族窒化物半導体発光素子の製造方法
DE102005009066A1 (de) * 2005-02-28 2006-09-07 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung eines optischen und eines strahlungsemittierenden Bauelementes und optisches sowie strahlungsemittierendes Bauelement
US7829909B2 (en) * 2005-11-15 2010-11-09 Verticle, Inc. Light emitting diodes and fabrication methods thereof
JP2007220865A (ja) * 2006-02-16 2007-08-30 Sumitomo Chemical Co Ltd ３族窒化物半導体発光素子およびその製造方法
JP2007221051A (ja) * 2006-02-20 2007-08-30 Sanyo Electric Co Ltd 窒化物系半導体素子の製造方法
KR100755658B1 (ko) * 2006-03-09 2007-09-04 삼성전기주식회사 발광다이오드 패키지
KR100725610B1 (ko) * 2006-04-18 2007-06-08 포항공과대학교 산학협력단 오믹 전극 형성 방법 및 반도체 발광 소자
JP5072070B2 (ja) * 2007-03-08 2012-11-14 日東電工株式会社 光半導体素子封止用エポキシ樹脂組成物およびそれを用いた光半導体装置
JP2009099675A (ja) * 2007-10-15 2009-05-07 Showa Denko Kk 発光ダイオードの製造方法及び発光ダイオード、並びにランプ
JP2009246334A (ja) * 2008-03-12 2009-10-22 Hitachi Chem Co Ltd 光反射用熱硬化性樹脂組成物、光半導体素子搭載用基板及びその製造方法、並びに光半導体装置
JP2010168525A (ja) * 2008-12-24 2010-08-05 Hitachi Chem Co Ltd 透明フィルム、この透明フィルムを用いた積層フィルム、無機粒子挟持フィルム、及び、ディスプレイ用パネル
JP5253260B2 (ja) * 2009-03-26 2013-07-31 旭化成ケミカルズ株式会社 Ｌｅｄ用蛍光樹脂組成物、それを用いた封止材及び蓄光材料
US8460794B2 (en) * 2009-07-10 2013-06-11 Seagate Technology Llc Self-aligned wafer bonding
US8203153B2 (en) * 2010-01-15 2012-06-19 Koninklijke Philips Electronics N.V. III-V light emitting device including a light extracting structure
JP5592248B2 (ja) * 2010-12-27 2014-09-17 シャープ株式会社 窒化物半導体発光素子

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2302705A2 (en) * 2008-06-02 2011-03-30 Korea University Industrial & Academic Collaboration Foundation Supporting substrate for fabrication of semiconductor light emitting device and semiconductor light emitting device using the same
CN101465401A (zh) * 2008-07-11 2009-06-24 厦门市三安光电科技有限公司 基于平面键合及暂时性基底转移技术的薄膜GaN LED制备方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2711991A4 *

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014094363A1 (zh) * 2012-12-21 2014-06-26 晶能光电（常州）有限公司 一种GaN基白光倒装芯片的制备方法
WO2015063034A1 (de) * 2013-10-28 2015-05-07 Osram Opto Semiconductors Gmbh Optoelektronisches bauelement und verfahren zu seiner herstellung
US9847467B2 (en) 2013-10-28 2017-12-19 Osram Opto Semiconductors Gmbh Optoelectronic component and method for the production thereof
CN108461586A (zh) * 2018-03-31 2018-08-28 华南理工大学 一种基于NiO纳米点反射镜的垂直结构LED芯片及其制备方法
CN108461586B (zh) * 2018-03-31 2023-06-20 华南理工大学 一种基于NiO纳米点反射镜的垂直结构LED芯片及其制备方法
US20220028907A1 (en) * 2020-07-24 2022-01-27 University Of Southern California Composite substrate for fabricating iii-v photodetector arrays
CN115881862A (zh) * 2023-02-16 2023-03-31 江西兆驰半导体有限公司 一种mini LED芯片减薄方法及mini LED

Also Published As

Publication number Publication date
US20140147987A1 (en) 2014-05-29
EP2711991A4 (en) 2015-05-20
JP2014517518A (ja) 2014-07-17
EP2711991A1 (en) 2014-03-26
US9224597B2 (en) 2015-12-29
JP5792375B2 (ja) 2015-10-14

Similar Documents

Publication Publication Date Title
WO2012155535A1 (zh) 氮化镓基薄膜芯片的生产制造方法
CN102790138B (zh) 一种GaN基薄膜芯片的生产方法
CN102790137B (zh) GaN基薄膜芯片的制备方法
US6562648B1 (en) Structure and method for separation and transfer of semiconductor thin films onto dissimilar substrate materials
US6607931B2 (en) Method of producing an optically transparent substrate and method of producing a light-emitting semiconductor chip
KR101254539B1 (ko) 수직 구조 반도체 장치
CN102496667B (zh) GaN基薄膜芯片的制造方法
TW201248696A (en) Mnufacturing method for gan semiconductor device
US9356188B2 (en) Tensile separation of a semiconducting stack
KR20100008123A (ko) 이중 히트 씽크층으로 구성된 지지대를 갖춘 고성능수직구조의 반도체 발광소자
KR20110042249A (ko) 수직 구조 화합물 반도체 디바이스의 제조 방법
KR20140097364A (ko) GaN성장용 복합기판의 제조방법
CN108878596B (zh) 一种边缘无损的垂直结构led芯片衬底的转移方法
WO2013017040A1 (zh) 一种通过湿法剥离GaN基外延层和蓝宝石衬底来制备垂直结构发光二极管的方法
CN103943741A (zh) 一种基于激光剥离的半导体发光器件的制备方法
US20150048301A1 (en) Engineered substrates having mechanically weak structures and associated systems and methods
JP5603812B2 (ja) 半導体素子の製造方法
CN103489979A (zh) 一种半导体发光器件的制备方法
JP5281536B2 (ja) 半導体発光装置の製造方法
CN102790139B (zh) 基于蓝宝石剥离的薄膜GaN芯片的制造方法
WO2022249675A1 (ja) 化合物半導体接合基板の製造方法、及び化合物半導体接合基板
CN102790139A (zh) 基于蓝宝石剥离的薄膜GaN芯片的制造方法
TW202322419A (zh) 垂直式發光二極體及其製造方法
TW202316494A (zh) 暫時接合晶圓及其製造方法
CN117691016A (zh) 发光器件及用于制备发光器件的方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12786729

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2014510643

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 2012786729

Country of ref document: EP