KR102424347B1 - 반도체 칩의 접착 방법 - Google Patents

반도체 칩의 접착 방법 Download PDF

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KR102424347B1
KR102424347B1 KR1020180135345A KR20180135345A KR102424347B1 KR 102424347 B1 KR102424347 B1 KR 102424347B1 KR 1020180135345 A KR1020180135345 A KR 1020180135345A KR 20180135345 A KR20180135345 A KR 20180135345A KR 102424347 B1 KR102424347 B1 KR 102424347B1
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South Korea
Prior art keywords
semiconductor chip
substrate
bonding
irradiation process
adhesive
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KR1020180135345A
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English (en)
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KR20200052136A (ko
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김영석
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삼성전자주식회사
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Priority to KR1020180135345A priority Critical patent/KR102424347B1/ko
Priority to US16/427,162 priority patent/US10825795B2/en
Priority to CN201910806622.6A priority patent/CN111146100A/zh
Publication of KR20200052136A publication Critical patent/KR20200052136A/ko
Application granted granted Critical
Publication of KR102424347B1 publication Critical patent/KR102424347B1/ko

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Abstract

반도체 칩의 접착 방법은 접착막을 반도체 칩의 표면에 형성하고, 상기 접착막이 기판의 상면에 접촉하도록 상기 반도체 칩을 상기 기판 상에 실장하고, 그리고 상기 반도체 칩이 실장된 상기 기판에 대하여 열압착 공정 및 자외선 조사 공정을 동시에 수행하여 상기 반도체 칩을 상기 기판에 접착시키는 것을 포함할 수 있다.

Description

반도체 칩의 접착 방법{ADHESION METHOD OF SEMICONDUCTOR CHIPS}
본 발명은 반도체 칩의 접착 방법에 관한 것이다. 보다 상세하게 본 발명은 접착 소재를 이용한 반도체 칩의 접착 방법에 관한 것이다.
반도체 패키지의 제조 공정에 있어서, 반도체 칩과 기판의 접착을 위해서 접착 소재가 사용될 수 있다. 상기 접착 소재는 열경화성 수지를 포함하는 비전도성 페이스트(non-conductive paste; NCP) 또는 비전도성 필름(non-conductive film; NCF) 형태일 수 있다.
상기 접착 소재는 열압착 공정(thermo compression process)에 의해 경화되어 경화막(cured layer)이 형성될 수 있는데, 상기 경화막이 상기 반도체 칩을 전면적으로 커버하지 못하거나 혹은 상기 반도체 칩으로부터 돌출되는 경우, 상기 반도체 패키지의 신뢰성이 저하될 수 있다.
본 발명의 과제는 반도체 패키지의 신뢰성을 향상시킬 수 있는 반도체 칩의 접착 방법을 제공하는 데 있다.
상술한 본 발명의 과제를 달성하기 위한 예시적인 실시예들에 따른 반도체 칩의 접착 방법에 있어서, 상기 반도체 칩의 접착 방법은 접착막을 반도체 칩의 표면에 형성하고, 상기 접착막이 기판의 상면에 접촉하도록 상기 반도체 칩을 상기 기판 상에 실장하고, 그리고 상기 반도체 칩이 실장된 상기 기판에 대하여 열압착 공정 및 자외선 조사 공정을 동시에 수행하여 상기 반도체 칩을 상기 기판에 접착시키는 것을 포함할 수 있다.
상술한 본 발명의 과제를 달성하기 위한 예시적인 실시예들에 따른 반도체 칩의 접착 방법에 있어서, 상기 반도체 칩의 접착 방법은 반도체 칩 표면에 연결 구조물을 형성하고, 상기 반도체 칩 상에 상기 연결 구조물을 커버하는 접착막을 형성하고, 상기 접착막이 기판의 상면에 접촉하도록 상기 반도체 칩을 상기 기판 상에 실장하고, 그리고 상기 반도체 칩이 실장된 상기 기판에 대하여 열압착 공정 및 자외선 조사 공정을 동시에 수행하여 상기 반도체 칩을 상기 기판에 접착시키는 것을 포함할 수 있다.
상술한 본 발명의 과제를 달성하기 위한 예시적인 실시예들에 따른 반도체 칩의 접착 방법에 있어서, 상기 반도체 칩의 접착 방법은 기판 패드를 포함하는 기판 상에 접착 페이스트를 도포하고, 반도체 칩을상기 접착 페이스트가 도포된 상기 기판 상에 실장하고, 상기 반도체 칩이 실장된 상기 기판에 대하여 열압착 공정 및 자외선 조사 공정을 동시에 수행하여 상기 반도체 칩을 상기 기판에 접착시키는 것을 포함할 수 있다.
예시적인 실시예들에 따른 반도체 칩의 접착 방법은 열경화성 수지 및 광경화성 수지를 포함하는 접착 소재를 이용한 열압착 공정 및 자외선 조사 공정을 반도체 칩이 실장된 기판에 대해 동시에 수행하여, 상기 반도체 칩을 상기 기판에 접착할 수 있다. 이때, 반도체 칩의 꼭지점 부분들을 모두 채우기 위하여 높은 온도 및/또는 높은 압력 조건에서 열압착 공정이 수행될 수 있는데, 상기 꼭지점 부분들을 제외한 반도체 칩 변들을 초과하여 형성되는 접착 소재 부분들이 자외선 조사 공정에 의해 광경화될 수 있다.
이에 따라, 접착 소재가 경화되어 형성되는 경화막이 반도체 칩의 꼭지점 부분들을 모두 채우도록 형성되어 보이드가 형성되지 않을 수 있고, 상기 꼭지점 부분들을 제외한 반도체 칩의 변들을 초과하지 않도록 형성되어 접착 소재의 오버플로우가 방지될 수 있으며, 이에 따라 반도체 패키지의 신뢰성이 향상될 수 있다.
다만, 본 발명의 효과는 상기 언급한 효과에 한정되는 것이 아니며, 본 발명의 사상 및 영역으로부터 벗어나지 않는 범위에서 다양하게 확장될 수 있을 것이다.
도 1 내지 도 11은 예시적인 실시예들에 따른 반도체 칩의 접착 방법의 단계들을 설명하기 위한 평면도들, 단면도들 및 사시도이다.
도 12 내지 도 18은 예시적인 실시예들에 따른 반도체 칩의 접착 방법의 단계들을 설명하기 위한 평면도들 및 단면도들이다.
이하, 첨부한 도면들을 참조하여 본 발명의 실시예들을 상세히 설명하고자 한다.
도 1 내지 도 11은 예시적인 실시예들에 따른 반도체 칩의 접착 방법의 단계들을 설명하기 위한 평면도들, 단면도들 및 사시도이다. 구체적으로 도 1, 7-8 및 10-11은 평면도들이고, 도 2, 4-6 및 9는 대응하는 각 평면도들의 A-A'선을 따라 절단한 단면도들이며, 도 3은 도 2의 X 영역을 확대한 사시도이다.
도 1 내지 도 3을 참조하면, 칩 패드(110)를 포함하는 반도체 칩(100) 상에 순차적으로 적층된 제1 도전성 범프(120) 및 제2 도전성 범프(130)를 포함하는 도전성 범프 구조물(140)을 형성할 수 있다.
구체적으로, 반도체 칩(100)의 칩 패드(110) 상에 시드층(도시되지 않음)을 형성한 후, 상기 시드층 상에 도금 공정을 수행하여 제1 및 제2 도전성 범프막들을 형성하고 이를 패터닝함으로써, 순차적으로 적층된 제1 및 제2 도전성 범프들(120, 130)을 형성할 수 있다. 칩 패드(110) 및 도전성 범프(140)은 함께 연결 구조물을 형성할 수 있다.
일 실시예에 있어서, 반도체 칩(100)은 트랜지스터, 콘택 플러그, 배선, 및 커패시터 등의 반도체 소자를 포함할 수 있다.
도 1에서 반도체 칩(100)은 상면에서 보았을 때 정사각형 또는 직사각형 형상을 가지는 것으로 도시되고 있지만, 본 발명의 개념은 반드시 이에 한정되지 않으며, 반도체 칩(100)은 상면에서 보았을 때 삼각형, 오각형 등의 다각형 형상을 가질 수도 있다.
칩 패드(110)는 반도체 칩(100) 상면에 평행한 제1 방향을 따라 복수 개로 형성될 수 있으며, 반도체 칩(100) 상면에 평행하고 상기 제1 방향과 교차하는 제2 방향으로 각각 연장될 수 있다. 예시적인 실시예들에 있어서, 상기 제1 및 제2 방향들은 서로 직교할 수 있다.
도전성 범프 구조물(140)은 칩 패드(110) 상에서 상기 제2 방향을 따라 복수 개로 형성될 수 있다. 이에 따라, 도전성 범프 구조물(140)은 칩 패드(110)와 서로 전기적으로 연결될 수 있다.
예시적인 실시예들에 있어서, 도전성 범프 구조물(140)의 상기 제2 방향으로의 측벽은 반도체 칩(100) 상면에 대해 수직하지 않고 경사진 기울기를 가질 수 있으며, 이에 따라 제2 도전성 범프(130)의 상면은 제1 도전성 범프(120)의 저면보다 상기 제2 방향으로의 폭이 더 클 수 있다. 즉, 상기 제1 방향에서 보았을 때, 도전성 범프 구조물(140)은 사다리꼴 형상을 가질 수 있다. 하지만, 본 발명의 개념은 반드시 이에 한정되지 않으며, 제2 도전성 범프(130)의 상면은 상기 제1 도전성 범프(120)의 저면보다 상기 제2 방향으로의 폭이 더 작을 수도 있다. 즉, 상기 제1 방향에서 보았을 때, 도전성 범프 구조물(140)은 전체적으로 사다리꼴 형상이 반전된 형상을 가질 수도 있다.
이와는 달리, 도전성 범프 구조물(140)의 상기 제2 방향으로의 측벽은 반도체 칩(100) 상면에 대해 수직인 기울기를 가질 수도 있으며, 이에 따라 제2 도전성 범프(130)의 상면의 상기 제2 방향으로의 폭이 제1 도전성 범프(120)의 저면의 상기 제2 방향으로의 폭과 서로 같을 수도 있다. 즉, 상기 제1 방향에서 보았을 때, 도전성 범프 구조물(140)은 직사각형 형상을 가질 수도 있다.
한편, 도 3에서 제1 및 제2 도전성 범프들(120, 130)이 상기 제1 방향으로의 서로 동일한 폭을 갖는 것으로 도시되고 있지만, 본 발명의 개념은 반드시 이에 한정되지 않을 수 있다. 즉, 제2 도전성 범프(130)의 상기 제1 방향으로의 폭은 상부에서 하부로 갈수록 증가할 수 있고, 상기 제1 도전성 범프(120)의 상기 제1 방향으로의 폭은 하부에서 상부로 갈수록 증가할 수 있으며, 이에 따라 도전성 범프 구조물(140)은 상기 제2 방향에서 보았을 때, 타원형 형상을 가질 수도 있다.
예시적인 실시예들에있어서, 칩 패드(110)는 폴리실리콘을 포함할 수 있고, 제1 도전성 범프(120)는 구리(Cu), 니켈(Ni) 등의 제1 도전성 물질을 포함할 수 있으며, 제2 도전성 범프(130)는 주석(Sn), 주석/은(Sn/Ag), 주석(Sn/Cu), 주석/인듐(Sn/In) 등의 제2 도전성 물질을 포함할 수 있다. 그러나, 상기 제1 및 제2 도전성 물질들은 이에 제한되지 않음을 이해할 수 있을 것이다.
도 4를 참조하면, 반도체 칩(100) 상면에 칩 패드(110) 및 도전성 범프(140)를 포함하는 상기 연결 구조물을 커버하는 접착막(150)을 형성할 수 있다. 이때, 접착막(150)의 상면의 높이는 제2 도전성 범프(130)의 상면의 높이보다 클 수 있다.
예시적인 실시예들에 있어서, 접착막(150)은 화학 기상 증착(Chemical Vapor Deposition: CVD) 공정, 원자층 증착(Atomic Layer Deposition: ALD) 공정 등을 통해 형성될 수 있다.
예시적인 실시예들에 있어서, 접착막(150)은 바인딩 수지, 열경화성 수지 및 광경화성 수지를 포함할 수 있다. 상기 바인딩 수지는 예를 들어, 아크릴계 수지 또는 페녹시계 수지를 포함할 수 있다. 상기 열경화성 수지는 예를 들어, 에폭시계 수지, 아크릴계 수지 및 실리콘계 수지로 이루어진 그룹에서 선택된 적어도 하나와 열경화제의 반응을 통하여 형성될 수 있고, 상기 열경화제는 예를 들어, 열경화제는 아민계 경화제, 산무수물계 경화제, 폴리올계 경화제, 아진계 경화제, 페놀계 경화제 등을 포함할 수 있다. 상기 광경화성 수지는 예를 들어, 탄소 이중결합을 가지는 아크릴계 수지와 광경화 개시제의 반응을 통하여 형성될 수 있고, 상기 탄소 이중결합을 가지는 아크릴계 수지는 예를 들어, 2-하이드록시에틸 아크릴레이트(HEA), 2-하이드록시에틸 메타크릴레이트(HEMA), 2,3-에폭시프로필 메타크릴레이트(EPMA), 아크릴산(AA), 메타크릴산(MAA) 등을 포함할 수 있으며, 상기 광경화 개시제는 예를 들어, 이소데실 아크릴레이트(IDA), 2-페녹시에틸 아크릴레이트(PEA), 헥산디올 디아크릴레이트(HDDA), 트리프로필렌글리콜 디아크릴레이트(TrPGDA), 트리메틸올프로판 트리아크릴레이트(TMPTA), 트리메틸올프로판 에톡시트리아크릴레이트(TMPEOTA) 등을 포함할 수 있다.
일 실시예에 있어서, 접착막(150)은 무기 필러, 유기 필러 및/또는 금속 필러를 더 포함할 수 있다. 상기 무기 필러는 예를 들어, 이산화규소(SiO2), 산화알루미늄(Al2O3), 이산화티타늄(TiO2), 질화알루미늄(AlN), 질화규소(Si3N4), 붕화질소(BN) 등을 포함할 수 있고, 상기 유기 필러는 예를 들어, 분자량 100,000 이상의 Epoxy기를 함유하는 acryl 공중합체를 포함할 수 있으며, 상기 금속 필러는 예를 들어, 알루미늄(Al), 니켈(Ni), 은(Ag) 등의 금속을 포함할 수 있다. 상기 무기 필러, 상기 유기 필러 및 상기 금속 필러는 접착막(150)의 열팽창 계수를 낮추는 역할을 할 수 있고, 이후에 수행되는 열압착 공정이 안정적으로 수행되도록 컨트롤 가능하게 할 수 있으며, 이에 따라 반도체 패키지의 신뢰성이 증가할 수 있다.
도 5를 참조하면, 접착막(150)이 형성된 반도체 칩(100)을 180도 뒤집을 수 있다.
이에 따라, 반도체 칩(100) 상면에 형성된 상기 연결 구조물을 커버하는 접착막(150)이 아래로 향할 수 있다.
도 6을 참조하면, 반도체 칩(100)을 기판 패드(210)를 포함하는 기판(200) 상에 실장할 수 있다.
즉, 상기 연결 구조물을 커버하는 접착막(150)이 형성된 반도체 칩(100)의 상면이 기판(200) 상면에 대향하도록 반도체 칩(100)을 기판(200) 상에 실장할 수 있으며, 상기 연결 구조물에 포함된 제2 도전성 범프(130)와 기판(200)의 기판 패드(210)는 서로 얼라인될 수 있다.
일 실시예에 있어서, 기판(200)은 예를 들어, 인쇄회로기판(printed circuit board; PCB)일 수 있으며, 상기 인쇄회로기판은 내부에 비아와 다양한 회로들을 갖는 다층 회로 보드일 수 있다. 이와는 달리, 기판(200)은 예를 들어, 실리콘 칩(Si chip) 또는 실리콘 웨이퍼(Si wafer) 일 수도 있다.
한편, 기판(200)은 하부 금형(10) 상에 위치할 수 있고, 반도체 칩(100)의 상부에는 상부 금형(20)이 위치할 수 있으며, 하부 및 상부 금형들(10, 20) 사이의 공간에는 자외선 조사 장치(30)가 위치할 수 있다. 하부 금형(10)은 기판(200)이 상하 방향으로 움직이지 않도록 고정시키는 역할을 할 수 있고, 상부 금형(20)은 이후에 수행되는 열압착 공정(thermo compression process)이 수행될 때, 반도체 칩(100)을 기판(200)의 상면에 수직한 방향을 따라 아래 방향으로 압축시키는 역할을 할 수 있다. 상기 자외선 조사 장치는 이후에 수행되는 자외선 조사 공정(ultra violet rays irradiation process)이 수행될 때, 접착막(150)에 대하여 자외선을 조사하는 역할을 할 수 있다.
도 4 내지 도 6에서는 접착막(150)이 반도체 칩(100) 상에 형성된 상기 연결 구조물을 커버하도록 형성된 것이 도시되지만, 본 발명의 개념은 반드시 이에 한정되지는 않는다. 즉, 접착막(150)은 별도로 제작될 수도 있으며, 이에 따라 반도체 칩(100) 상의 상기 연결 구조물을 커버하지 않을 수 있다. 이 경우, 반도체 칩(100)이 기판(200) 상에 실장될 때, 반도체 칩(100)과 기판(200) 사이의 공간, 즉 상기 연결 구조물과 기판 패드(210) 사이의 공간에 제공될 수도 있다.
도 7 내지 도 10을 참조하면, 반도체 칩(100) 및 기판(200)에 대하여 열압착 공정 및 자외선 조사 공정을 동시에 수행할 수 있다.
이에 따라, 반도체 칩(100)과 기판(200) 사이의 공간에 위치하는 접착막(150)이 열압착되어 반도체 칩(100)의 상기 연결 구조물이 기판(200) 상의 기판 패드(210)에 접촉하여 전기적으로 연결될 수 있으며, 상기 열압착 공정 및 상기 자외선 조사 공정에 의해 접착막(150)이 경화되어 제1 경화막(160)이 형성될 수 있다.
상기 열압착 공정은 상부 금형(20)을 아래 방향으로 움직여 반도체 칩(100)을 하부 금형(10) 상에 놓여진 기판(200) 상으로 압착시킨 후, 하부 및 상부 금형들(10, 20) 사이 공간의 온도를 증가시킴으로써 수행될 수 있고, 도 7에 도시된 바와 같이, 반도체 칩(100)이 갖는 다각형 형상의 꼭지점 부분들을 포함한 모든 변들에 대응하는 접착막(150) 부분에 대하여 수행될 수 있다.
상기 자외선 조사 공정은 자외선 조사 장치(30)에서 발생한 자외선을 상기 열압착 공정에 의해 압착된 접착막(150)에 대하여 상기 기판(200) 상면으로부터 0˚ 내지 90˚ 각도로 조사함으로써 수행될 수 있고, 도 8에 도시된 바와 같이, 반도체 칩(100)이 갖는 다각형의 꼭지점 부분들을 제외한 모든 변들, 또는 상기 모든 변들 중 적어도 일부에 대응하는 접착막(150) 부분에 대응하여 수행될 수 있다. 일 실시예에 있어서, 상기 자외선 조사 공정은 상기 제1 및 제2 방향들을 따라 수행될 수 있다.
이에 따라, 상기 열압착 공정에 의해 접착막(150)이 반도체 칩(100)의 꼭지점들보다 이의 변들에 대응하는 공간을 먼저 채우도록 경화되더라도, 상기 자외선 조사 공정에 의해 접착막(150)이 반도체 칩(100)의 꼭지점들을 제외한 변들로부터 외부로 돌출되는 부분이 최소화되도록 경화될 수 있다. 즉, 접착막(150)은 열경화성 수지 및 광경화성 수지를 모두 포함하므로, 상기 열압착 공정에 의해 제1 경화막(160)은 반도체 칩(100)의 꼭지점들에 대응하는 공간을 대부분 채울 수 있고, 상기 자외선 조사 공정에 의해 제1 경화막(160)은 반도체 칩(100)의 꼭지점들을 제외한 변들에 대응하는 공간으로부터 외부로 돌출되는 것이 최소화되도록 할 수 있다.
예시적인 실시예들에 있어서, 제1 경화막(160) 저면의 최대 폭과 반도체 칩(100) 저면의 최대 폭의 차이는 500㎛ 미만일 수 있다. 즉, 상기 제1 방향으로의 제1 경화막(160)의 저면 폭과 상기 제1 방향으로의 반도체 칩(100)의 저면 폭의 차이가 500㎛ 미만일 수 있고, 상기 제2 방향으로의 제1 경화막(160)의 저면 폭과 상기 제2 방향으로의 상기 반도체 칩(100)의 저면 폭의 차이도 500㎛ 미만일 수 있다.
예시적인 실시예들에 있어서, 상기 열압착 공정은 350℃ 이하의 온도 및 100N 이하의 압력 조건에서 수행될 수 있고, 상기 자외선 조사 공정은 자외선 광량(light quantity) 5,000mJ/cm2 이하의 조건에서 수행될 수 있다.
한편, 도 9에서 접착막(150)이 경화되어 형성되는 제1 경화막(160)의 측벽이 기판(200) 상면에 대해 일정한 기울기를 갖는 것이 도시되어 있지만, 본 발명의 개념은 반드시 이에 한정되지 않는다. 즉, 제1 경화막(160)의 측벽은 기판(200) 상면에 대해 일정하지 않은 기울기를 가질 수도 있으며, 예를 들어, 제1 경화막(160)은 기판(200) 상면에 대해 점차 증가하는 기울기를 갖는 측벽을 갖거나, 혹은 기판(200) 상면에 대해 점차 감소하는 기울기를 갖는 측벽을 가질 수도 있다.
한편 도 11을 참조하면, 제1 경화막(160)은 기판(200) 상의 반도체 칩(100)에 대응하는 모든 공간을 채울 수도 있으며, 다만 반도체 칩(100)으로부터 외부로 돌출되는 부분의 면적은 작을 수 있다.
전술한 바와 같이, 반도체 칩(100)과 기판(200) 사이에 형성되는 접착막(150)에 대하여 열압착 공정 및 자외선 조사 공정을 수행할 때, 상기 열압착 공정은 반도체 칩(100)이 갖는 다각형상의 꼭지점을 포함하여 모든 변들에 대응하는 접착막(150) 부분에 대해 수행되는 반면, 상기 자외선 조사 공정은 반도체 칩(100)이 갖는 다각형상의 꼭지점을 제외한 변들에 대응하는 접착막(150) 부분에 대해서만 수행될 수 있다.
이에 따라, 접착막(150)이 경화되어 형성되는 제1 경화막(160)은 반도체 칩(100)이 갖는 다각형상의 꼭지점 부분에 대응하는 공간을 대부분 채우면서도 상기 다각형상의 변들에 대응하는 공간으로부터 외부로 돌출되는 것이 최소화될 수 있다. 그 결과, 반도체 칩(100)이 기판(200)에 잘 접착되면서도, 접착막(150)의 오버플로우에 의해 제1 경화막(160)이 반도체 칩(100) 외부로 돌출되어 상기 반도체 패키지의 신뢰성이 저하되는 것을 방지할 수 있다.
도 12 내지 도 18은 예시적인 실시예들에 따른 반도체 칩의 접착 방법의 단계들을 설명하기 위한 평면도들 및 단면도들이다. 구체적으로, 도 14-15 및 17-18은 평면도들이고, 도 12-13 및 16은 대응하는 각 평면도들의 A-A'선을 따라 절단한 단면도들이다.
상기 반도체 칩의 접착 방법은 도 1 내지 도 11을 참조로 설명한 공정들과 실질적으로 동일하거나 유사한 공정들을 포함하므로, 동일한 구성 요소에는 동일한 참조 부호를 부여하고, 이들에 대한 자세한 설명은 생략한다.
도 12를 참조하면, 기판 패드(210)를 포함하는 기판(200) 상에 기판 패드(210)를 커버하도록 열경화성 수지 및 광경화성 수지를 포함하는 접착 페이스트(170)를 도포할 수 있다.
이때, 접착 페이스트(170)는 전술한 접착막(150)의 성분과 실질적으로 동일한 성분을 포함할 수 있으나 필름 형태가 아닌 액상 형태를 가질 수 있다.
도 13을 참조하면, 접착 페이스트(170)가 도포된 기판(200)을 하부 금형(10) 상에 위치시키고, 접착 페이스트(170) 상에 반도체 칩(100)을 실장하고, 반도체 칩(100) 상에 상부 금형(20)을 위치시키고, 기판(200)과 반도체 칩(100) 사이에 도포된 접착 페이스트(170)의 측부에 자외선 조사 장치(30)를 위치시킬 수 있다.
이때, 접착 페이스트(170)에 의해 커버되는 반도체 칩(100)의 연결 구조물에 포함된 칩 패드(110), 및 제1 및 제2 도전성 범퍼들(120, 130)과 기판(200)의 기판 패드(210)는 서로 얼라인 될 수 있다.
도 14 내지 도 17을 참조하면, 반도체 칩(100) 및 기판(200)에 대하여 열압착 공정 및 자외선 조사 공정을 동시에 수행할 수 있다.
이에 따라, 반도체 칩(100)과 기판(200) 사이의 공간에 위치하는 접착 페이스트(170)가 열압착되어 반도체 칩(100)의 상기 연결 구조물이 기판(200) 상의 기판 패드(210)에 접촉하여 전기적으로 연결될 수 있으며, 상기 열압착 공정 및 상기 자외선 조사 공정에 의해 접착 페이스트(170)가 경화되어 제2 경화막(180)이 형성될 수 있다.
상기 열압착 공정은 상부 금형(20)을 아래 방향으로 움직여 반도체 칩(100)을 하부 금형(10)상에 놓여진 기판(200) 상에 압착시킨 후, 하부 및 상부 금형들(10, 20) 사이 공간의 온도를 증가시킴으로써 수행될 수 있고, 도 14에 도시된 바와 같이, 반도체 칩(100)이 갖는 반도체 칩(100)이 갖는 다각형상의 꼭지점 부분들을 포함한 모든 변들에 대응하는 접착 페이스트(170) 부분에 수행될 수 있다.
상기 자외선 조사 공정은 자외선 조사 장치(30)에서 발생한 자외선을 상기 열압착 공정에 의해 압착된 접착 페이스트(170)에 대하여 기판(200) 상면으로부터 0˚ 내지 90˚ 각도로 조사함으로써 수행될 수 있고, 도 15에 도시된 바와 같이, 반도체 칩(100)이 갖는 다각형상의 꼭지점 부분들을 제외한 모든 변들, 또는 상기 모든 변들 중 적어도 일부에 대응하는 접착 페이스트(150) 부분에 대하여 수행될 수 있다.
이때, 제2 경화막(180)의 성분은 제1 경화막(160)의 성분과 실질적으로 동일할 수 있다.
한편, 도 16에서 접착 페이스트(170)가 경화되어 형성되는 제2 경화막(180)의 측벽이 기판(200) 상면에 대해 일정한 기울기를 갖는 것이 도시되어 있지만, 본 발명의 개념은 반드시 이에 한정되지 않는다. 즉, 제2 경화막(180)의 측벽은 기판(200) 상면에 대해 일정하지 않는 기울기를 가질 수도 있으며, 예를 들어, 제2 경화막(180)은 기판(200) 상면에 대해 점차 증가하는 기울기를 갖는 측벽을 갖거나, 혹은 기판(200) 상면에 대해 점차 감소하는 기울기를 갖는 측벽을 가질 수도 있다.
한편, 도 18을 참조하면, 제2 경화막(180)은 기판(200) 상의 반도체 칩(100)에 대응하는 모든 공간을 채울 수도 있으며, 다만 반도체 칩(100)으로부터 외부로 돌출되는 부분의 면적은 작을 수 있다.
전술한 반도체 칩의 접착 방법은 로직 소자나 메모리 소자와 같은 반도체 소자를 포함하는 반도체 칩을 접착하는 데 사용될 수 있다. 상기 반도체 칩의 접착 방법은, 예를 들어 중앙처리장치(CPU, MPU), 애플리케이션 프로세서(AP) 등과 같은 로직 소자, 예를 들어 에스램(SRAM) 장치, 디램(DRAM) 장치 등과 같은 휘발성 메모리 장치, 및 예를 들어 플래시 메모리 장치, 피램(PRAM) 장치, 엠램(MRAM) 장치, 알램(RRAM) 장치 등과 같은 불휘발성 메모리 장치를 포함하는 반도체 칩의 접착 방법에 사용될 수 있다.
이상에서는 본 발명의 실시예들을 참조하여 설명하였지만, 해당 기술 분야의 숙련된 당업자는 하기의 특허 청구의 범위에 기재된 본 발명의 사상 및 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.
10: 하부 금형 20: 상부 금형
30: 자외선 조사 장치 100: 반도체 칩
110: 칩 패드 120, 130: 제1 및 제2 도전성 범프들
140: 도전성 범프 구조물 150: 접착막
160: 제1 경화막 170: 접착 페이스트
180: 제2 경화막 200: 기판
210: 기판 패드

Claims (20)

  1. 접착막을 반도체 칩의 표면에 형성하고;
    상기 접착막이 기판의 상면에 접촉하도록 상기 반도체 칩을 상기 기판 상에 실장하고; 그리고
    상기 반도체 칩이 실장된 상기 기판에 대하여 열압착 공정 및 자외선 조사 공정을 동시에 수행하여 상기 반도체 칩을 상기 기판에 접착시키는 것을 포함하며,
    상기 반도체 칩은 상면에서 보았을 때 다각형 형상을 가지며,
    상기 자외선 조사 공정은 상기 접착막에 대하여 상기 반도체 칩이 갖는 다각형의 꼭지점 부분들을 제외한 변들 중 적어도 하나의 변을 향해 수행되는 반도체 칩의 접착 방법.
  2. 삭제
  3. 제1항에 있어서, 상기 자외선 조사 공정은 상기 접착막에 대하여 상기 반도체 칩이 갖는 상기 다각형의 모든 변들을 향해 수행되는 반도체 칩의 접착 방법.
  4. 제1항에 있어서, 상기 자외선 조사 공정은 자외선 광량(light quantity) 5,000mJ/cm2 이하의 조건에서 수행되는 반도체 칩의 접착 방법.
  5. 제1항에 있어서, 상기 열압착 공정 및 상기 자외선 조사 공정을 수행함으로써 상기 접착막이 경화되어 경화막이 형성되는 반도체 칩의 접착 방법.
  6. 제5항에 있어서, 상기 경화막의 저면 폭과 상기 반도체 칩 저면 폭의 차이는 500㎛ 미만인 반도체 칩의 접착 방법.
  7. 제1항에 있어서, 상기 열압착 공정은 350℃ 이하의 온도 및 100N 이하의 압력 조건에서 수행되는 반도체 칩의 접착 방법.
  8. 제1항에 있어서, 상기 접착막은 열경화성 수지 및 광경화성 수지를 포함하는 반도체 칩의 접착 방법.
  9. 제8항에 있어서, 상기 열경화성 수지는 에폭시계 수지, 아크릴계 수지 및 실리콘계 수지로 이루어진 그룹에서 선택된 적어도 하나와 열경화제의 반응을 통하여 형성되는 반도체 칩의 접착 방법.
  10. 제9항에 있어서, 열경화제는 아민계 경화제, 산무수물계 경화제, 폴리올계 경화제, 아진계 경화제 및 페놀계 경화제로 이루어진 그룹에서 선택된 적어도 하나를 포함하는 반도체 칩의 접착 방법.
  11. 제8항에 있어서, 상기 광경화성 수지는 탄소 이중결합을 가지는 아크릴계 수지와 광경화 개시제의 반응을 통하여 형성되는 반도체 칩의 접착 방법.
  12. 제11항에 있어서, 상기 탄소 이중결합을 가지는 아크릴계 수지는 2-하이드록시에틸 아크릴레이트(HEA), 2-하이드록시에틸 메타크릴레이트(HEMA), 2,3-에폭시프로필 메타크릴레이트(EPMA), 아크릴산(AA) 및 메타크릴산(MAA)으로 이루어진 그룹에서 선택된 적어도 하나를 포함하는 반도체 칩의 접착 방법.
  13. 제11항에 있어서, 상기 광경화 개시제는 이소데실 아크릴레이트(IDA), 2-페녹시에틸 아크릴레이트(PEA), 헥산디올 디아크릴레이트(HDDA), 트리프로필렌글리콜 디아크릴레이트(TrPGDA), 트리메틸올프로판 트리아크릴레이트(TMPTA) 및 트리메틸올프로판 에톡시트리아크릴레이트(TMPEOTA)로 이루어진 그룹에서 선택된 적어도 하나를 포함하는 반도체 칩의 접착 방법.
  14. 제8항에 있어서, 상기 접착막은 무기 필러, 유기 필러 및 금속 필러로 이루어진 그룹에서 선택된 적어도 하나를 더 포함하는 반도체 칩의 접착 방법.
  15. 제14항에 있어서, 상기 무기 필러는 이산화규소(SiO2), 산화알루미늄(Al2O3), 이산화티타늄(TiO2), 질화알루미늄(AlN), 질화규소(Si3N4) 및 붕화질소(BN)로 이루어진 그룹에서 선택된 적어도 하나를 포함하고, 상기 유기 필러는 분자량 100,000 이상의 Epoxy기를 함유하는 acryl 공중합체를 포함하며, 상기 금속 필러는 알루미늄(Al), 니켈(Ni) 및 은(Ag)으로 이루어진 그룹에서 선택된 적어도 하나을 포함하는 반도체 칩의 접착 방법.
  16. 제1항에 있어서, 상기 기판은 인쇄회로기판(PCB), 실리콘 칩(Si chip) 또는 실리콘 웨이퍼(Si wafer)인 반도체 칩의 접착 방법.
  17. 반도체 칩 표면에 연결 구조물을 형성하고;
    상기 반도체 칩 상에 상기 연결 구조물을 커버하는 접착막을 형성하고;
    상기 접착막이 기판의 상면에 접촉하도록 상기 반도체 칩을 상기 기판 상에 실장하고; 그리고
    상기 반도체 칩이 실장된 상기 기판에 대하여 열압착 공정 및 자외선 조사 공정을 동시에 수행하여 상기 반도체 칩을 상기 기판에 접착시키는 것을 포함하며,
    상기 반도체 칩은 상면에서 보았을 때 다각형 형상을 가지며,
    상기 자외선 조사 공정은 상기 접착막에 대하여 상기 반도체 칩이 갖는 다각형의 꼭지점 부분들을 제외한 변들 중 적어도 하나의 변을 향해 수행되는 반도체 칩의 접착 방법.
  18. 제17항에 있어서, 상기 연결 구조물은 상기 반도체 칩 표면에 순차적으로 적층된 칩 패드, 제1 도전성 범프 및 제2 도전성 범프를 포함하고, 상기 기판은 기판 패드를 포함하는 반도체 칩의 접착 방법.
  19. 제18항에 있어서, 상기 반도체 칩이 상기 기판에 접착될 때, 상기 접착막이 열압착되어 상기 연결 구조물이 상기 기판 패드에 접촉하는 반도체 칩의 접착 방법.
  20. 기판 패드를 포함하는 기판 상에 접착 페이스트를 도포하고;
    반도체 칩을 상기 접착 페이스트가 도포된 상기 기판 상에 실장하고; 그리고
    상기 반도체 칩이 실장된 상기 기판에 대하여 열압착 공정 및 자외선 조사 공정을 동시에 수행하여 상기 반도체 칩을 상기 기판에 접착시키는 것을 포함하며,
    상기 반도체 칩은 상면에서 보았을 때 다각형 형상을 가지며,
    상기 자외선 조사 공정은 상기 접착 페이스트에 대하여 상기 반도체 칩이 갖는 다각형의 꼭지점 부분들을 제외한 변들 중 적어도 하나의 변을 향해 수행되는 반도체 칩의 접착 방법.

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20240070996A (ko) 2022-11-15 2024-05-22 동국대학교 산학협력단 심리 검사용 이미지 데이터를 이용한 성격 유형 예측 장치 및 방법
KR20240084307A (ko) 2022-12-06 2024-06-13 동국대학교 산학협력단 그림검사용 앱 프로그램을 심리 검사용 이미지 데이터를 이용한 성격 유형 예측 장치 및 방법

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010018986A1 (en) * 2000-02-21 2001-09-06 Akira Nagai Resin compound, and adhesive film, metal-clad adhesive film, circuit board, and assembly structure, using the resin compound
US20140353540A1 (en) * 2013-05-31 2014-12-04 Sunray Scientific, Llc Anisotropic Conductive Adhesive with Reduced Migration
US20170355906A1 (en) * 2014-12-18 2017-12-14 Dic Corporation Liquid crystal composition and liquid crystal display element using same

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4954197A (en) 1989-03-30 1990-09-04 Xerox Corporation Process for assembling smaller arrays together to form a longer array
US5783465A (en) * 1997-04-03 1998-07-21 Lucent Technologies Inc. Compliant bump technology
JPH1187413A (ja) 1997-09-08 1999-03-30 Fujitsu Ltd 半導体ベアチップ実装方法
JP2001308145A (ja) 2000-04-25 2001-11-02 Fujitsu Ltd 半導体チップの実装方法
US6873059B2 (en) * 2001-11-13 2005-03-29 Texas Instruments Incorporated Semiconductor package with metal foil attachment film
TWI252066B (en) * 2002-02-28 2006-03-21 Hitachi Chemical Co Ltd Method for connecting electrodes, surface-treated wiring board and adhesive film used in the method, and electrodes-connected structure
US7204574B2 (en) 2004-06-30 2007-04-17 Lexmark International, Inc. Polyimide thickfilm flow feature photoresist and method of applying same
WO2006063338A1 (en) 2004-12-08 2006-06-15 Mark Knapp Molded gasket and method of making
WO2007100849A2 (en) 2006-02-27 2007-09-07 Microcontinuum, Inc. Formation of pattern replicating tools
JP4902229B2 (ja) 2006-03-07 2012-03-21 ソニーケミカル＆インフォメーションデバイス株式会社 実装方法
US8499810B2 (en) 2009-08-27 2013-08-06 Transfer Devices Inc. Molecular transfer lithography apparatus and method for transferring patterned materials to a substrate
US20110207253A1 (en) 2010-02-23 2011-08-25 Yueh-Hsun Yang Flip-chip led module fabrication method
JP5792375B2 (ja) 2011-05-19 2015-10-14 晶能光電（江西）有限公司Ｌａｔｔｉｃｅ Ｐｏｗｅｒ（Ｊｉａｎｇｘｉ）Ｃｏｒｐｏｒａｔｉｏｎ 窒化ガリウムベースフィルムチップの生産方法および製造方法
KR102047225B1 (ko) 2012-11-30 2019-11-22 엘지디스플레이 주식회사 Ncp 타입 접착수단 및 이를 구비한 표시장치
KR102090456B1 (ko) * 2012-11-30 2020-03-18 엘지디스플레이 주식회사 비 전도성 타입 접착수단과 이를 구비한 표시장치
JP2015072410A (ja) 2013-10-04 2015-04-16 富士フイルム株式会社 コレステリック液晶層を含む熱圧着貼合用フィルムおよびその応用

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010018986A1 (en) * 2000-02-21 2001-09-06 Akira Nagai Resin compound, and adhesive film, metal-clad adhesive film, circuit board, and assembly structure, using the resin compound
US20140353540A1 (en) * 2013-05-31 2014-12-04 Sunray Scientific, Llc Anisotropic Conductive Adhesive with Reduced Migration
US20170355906A1 (en) * 2014-12-18 2017-12-14 Dic Corporation Liquid crystal composition and liquid crystal display element using same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20240070996A (ko) 2022-11-15 2024-05-22 동국대학교 산학협력단 심리 검사용 이미지 데이터를 이용한 성격 유형 예측 장치 및 방법
KR20240084307A (ko) 2022-12-06 2024-06-13 동국대학교 산학협력단 그림검사용 앱 프로그램을 심리 검사용 이미지 데이터를 이용한 성격 유형 예측 장치 및 방법

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