WO2012153534A1 - 堆積物除去方法 - Google Patents
堆積物除去方法 Download PDFInfo
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- WO2012153534A1 WO2012153534A1 PCT/JP2012/003070 JP2012003070W WO2012153534A1 WO 2012153534 A1 WO2012153534 A1 WO 2012153534A1 JP 2012003070 W JP2012003070 W JP 2012003070W WO 2012153534 A1 WO2012153534 A1 WO 2012153534A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B05—SPRAYING OR ATOMISING IN GENERAL; APPLYING FLUENT MATERIALS TO SURFACES, IN GENERAL
- B05D—PROCESSES FOR APPLYING FLUENT MATERIALS TO SURFACES, IN GENERAL
- B05D3/00—Pretreatment of surfaces to which liquids or other fluent materials are to be applied; After-treatment of applied coatings, e.g. intermediate treating of an applied coating preparatory to subsequent applications of liquids or other fluent materials
- B05D3/14—Pretreatment of surfaces to which liquids or other fluent materials are to be applied; After-treatment of applied coatings, e.g. intermediate treating of an applied coating preparatory to subsequent applications of liquids or other fluent materials by electrical means
- B05D3/141—Plasma treatment
- B05D3/145—After-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
Definitions
- the present invention relates to a deposit removal method.
- a desired pattern is formed on a substrate such as a semiconductor wafer by performing a film forming process or an etching process.
- a deposit of silicon oxide for example, SiO 2 or SiOBr
- Such deposit removal has been performed by, for example, processing using a single HF gas.
- the present invention has been made in response to the above-described conventional circumstances, and can efficiently remove deposits regardless of the length of time of standing after the etching process, and can reduce the dioxide in the structure in the pattern. It is an object of the present invention to provide a deposit removal method capable of suppressing damage to silicon.
- One aspect of the deposit removal method of the present invention is a deposit removal method for removing deposits deposited on the surface of a pattern formed by etching on a substrate, the oxygen being exposed to oxygen plasma while heating the substrate.
- the substrate is exposed to a mixed gas atmosphere of hydrogen fluoride gas and alcohol gas in a treatment chamber, and the partial pressure of the alcohol gas is set to a first partial pressure.
- a cycle processing step of repeating a plurality of cycles, a first period and a second period in which the inside of the processing chamber is evacuated and the partial pressure of the alcohol gas is a second partial pressure lower than the first partial pressure, It is characterized by comprising.
- the deposit which can remove a deposit efficiently irrespective of the length of the standing time after an etching process, and can suppress the damage with respect to the silicon dioxide of the structure in a pattern. Can be provided.
- FIG. 1 is a longitudinal sectional view schematically showing a configuration example of a plasma processing apparatus 100 used in an oxygen plasma processing step in a deposit removing method according to an embodiment of the present invention.
- the plasma processing apparatus 100 includes a processing chamber 101 that can be hermetically closed.
- a stage 102 for mounting a semiconductor wafer (substrate) W is provided in the processing chamber 101.
- the stage 102 includes a temperature control mechanism (not shown) so that the temperature of the semiconductor wafer W placed on the stage 102 can be maintained at a predetermined temperature.
- the processing chamber 101 is made of, for example, quartz or the like, and a quartz window 103 is formed on the ceiling.
- An RF coil 104 connected to a high frequency power source (not shown) is provided outside the window 103.
- a gas introduction part 105 for introducing a predetermined processing gas containing oxygen gas (for example, O 2 gas single gas) into the processing chamber 101 is provided in the portion of the window 103.
- the plasma P of the processing gas introduced from the gas introduction unit 105 is generated by the action of the high frequency supplied to the RF coil 104.
- a gas diffusion plate 106 for shielding the plasma and dispersing the gas is provided below the window 103, and the semiconductor on the stage 102 is in a state where radicals in the plasma are dispersed through the gas diffusion plate 106.
- the wafer W is supplied.
- the substrate and the plasma may be brought into direct contact with each other.
- the remote plasma processing that is, the substrate and the plasma are not brought into contact with each other.
- the radicals extracted from the plasma generated at the separated sites may be allowed to act on the substrate.
- an exhaust pipe 107 is provided at the bottom of the processing chamber 101.
- the exhaust pipe 107 is connected to a vacuum pump (not shown) or the like, and can exhaust the processing chamber 101 to a predetermined pressure.
- FIG. 2 is a longitudinal sectional view schematically showing a configuration example of the gas processing apparatus 200 used in the cycle processing step in the deposit removal method of the embodiment of the present invention.
- the gas processing apparatus 200 includes a processing chamber 201 that can be hermetically closed.
- a stage 202 for placing a semiconductor wafer (substrate) W is provided in the processing chamber 201.
- the stage 202 includes a temperature control mechanism (not shown) so that the temperature of the semiconductor wafer W placed on the stage 202 can be maintained at a predetermined temperature.
- a gas introducing unit 203 for introducing a predetermined processing gas (a mixed gas of HF gas and methanol gas in the present embodiment) into the processing chamber 201 is provided on the upper portion of the processing chamber 201. Further, a gas diffusion plate 206 in which a large number of through holes 205 are formed is provided below the opening 204 where the gas introduction unit 203 opens into the processing chamber 201, and the through holes 205 of the gas diffusion plate 206 are provided. Thus, the processing gas is supplied to the surface of the semiconductor wafer W in a uniformly dispersed state.
- a predetermined processing gas a mixed gas of HF gas and methanol gas in the present embodiment
- an exhaust pipe 207 is provided at the bottom of the processing chamber 201.
- This exhaust pipe 207 is connected to a vacuum pump or the like (not shown) so that the inside of the processing chamber 201 can be exhausted to a predetermined pressure.
- the deposit removal process is performed as follows using the plasma processing apparatus 100 and the gas processing apparatus 200 having the above-described configuration.
- an etching process is performed in the previous process (step 301), and a semiconductor wafer on which a predetermined pattern is formed has a deposit (so-called deposit) accompanying the etching process on the side wall portion of the pattern. Accumulates. For example, when a SIT (Shallow Trench Isolation) process is performed, a deposit of silicon oxide (for example, SiO 2 or SiOBr) is deposited on the side wall portion of the pattern. Therefore, the deposit deposited on the side wall portion of the pattern is removed by the deposit removing process in the present embodiment.
- SIT Silicon Trench Isolation
- the etching process (step 301) is performed, for example, as a two-step etching process shown below.
- an oxygen plasma process in the deposit removal process is performed (step 302).
- This oxygen plasma processing can be performed by the plasma processing apparatus 100 shown in FIG.
- the deposit removing process may be performed immediately after the etching process, or may be performed after a certain period of time (q-time) (for example, several hours to several days).
- the oxygen plasma processing step in the plasma processing apparatus 100 is performed as follows, for example. That is, in the oxygen plasma processing step, the semiconductor wafer W is placed on the stage 102 set in advance at a predetermined temperature and is adsorbed by an electrostatic chuck or the like (not shown) so that the semiconductor wafer W is heated to the predetermined temperature. It becomes. In this state, a predetermined processing gas containing oxygen gas is introduced from the gas introduction unit 105, and exhaust is performed from the exhaust pipe 107, so that the processing chamber 101 has a processing gas atmosphere at a predetermined pressure. Then, when RF power is applied to the RF coil 104, inductively coupled plasma of oxygen gas is generated. The ions in the plasma are shielded by the gas diffusion plate 106 and supplied to the semiconductor wafer W on the stage 102 in a state where oxygen radicals having no charge are dispersed, and oxygen plasma treatment is performed by the action of oxygen radicals.
- This oxygen plasma treatment is performed in order to make the pattern and the moisture absorption state of the deposit constant (dehydrate) regardless of the length of time (q-time) after the etching treatment.
- silicon oxide for example, SiO 2 Ng SiOBr
- SiO 2 layer such as the gate oxide film which is the pattern structure from being damaged due to excessive reaction.
- a gas containing oxygen as a processing gas for example, a single gas of oxygen gas or a mixed gas of oxygen gas and nitrogen gas is used, and the heating temperature (stage temperature) of the semiconductor wafer W is, for example, 200 ° C. to 300 ° C. It is set to about °C.
- the pressure is, for example, about 66.5 Pa (0.5 Torr) to 266 Pa (2 Torr).
- a cycle treatment in the deposit removal treatment is performed (steps 303 to 305). This cycle process can be performed by the gas processing apparatus 200 shown in FIG.
- the cycle process in the gas processing apparatus 200 is performed as follows.
- the semiconductor wafer W is maintained at the predetermined temperature by placing the semiconductor wafer W on the stage 202 set at a predetermined temperature in advance.
- a predetermined processing gas HF gas + methanol gas in the present embodiment
- exhaust is performed from the exhaust pipe 207, so that the processing chamber 201 has a processing gas atmosphere at a predetermined pressure. Is done.
- the second period (step 304) in which the second partial pressure is lower than the partial pressure of 1 is repeated a plurality of cycles (step 305).
- the following method can be used.
- the processing chamber is maintained at a predetermined pressure by an automatic pressure controller (APC) while supplying a mixed gas at a predetermined flow rate
- the set pressure of the automatic pressure controller is reduced or For example, a method in which the pressure is lowered by fully drawing with a vacuum pump as fully open.
- the first period and the second period are set using the latter method.
- the temperature of the semiconductor wafer W is preferably a low temperature of, for example, several tens of degrees (for example, 30 ° C.) or less.
- the pressure in the first period is preferably, for example, about 665 Pa (5 Torr) to 1330 Pa (10 Torr), and the processing gas is a mixed gas of HF gas + alcohol gas (CH 3 OH gas in this embodiment).
- the first period is set to a partial pressure of methanol gas from which deposits can be removed by the action of the mixed gas. Further, in the second period, the partial pressure of methanol gas is reduced, and a substance (such as H 2 O) generated by the reaction between the deposit and the mixed gas during the first period without removing the deposit is removed. A period for exhausting and discharging to the outside of the processing chamber 201 is used. The first period and the second period are about 5 to 20 seconds, and this cycle is repeated a plurality of times.
- step 306 the deposit removal process ends (step 306).
- the pattern and the moisture absorption state of the deposit are made constant by the oxygen plasma treatment regardless of the standing time (q-time) after the etching treatment.
- the oxygen plasma treatment When the oxygen plasma treatment is performed, it is difficult to remove the deposits by the treatment with the HF single gas. For this reason, in the cycle processing in the present embodiment, a mixed gas of HF gas + alcohol gas (methanol gas in the present embodiment) is used. In this case, the amount of H 2 O generated by the reaction becomes excessive, and the gate oxide film or the like that is the pattern structure may be damaged, or deposition (redeposition) may occur due to the reverse reaction. For this reason, the amount of H 2 O is reduced by repeatedly performing the first period in which the deposit is removed by the cycle process and the second period in which the reaction product is exhausted without removing the deposit. Prevent excess.
- a mixed gas of HF gas + alcohol gas methanol gas in the present embodiment
- silicon oxide for example, SiO 2 or SiOBr
- SiO 2 or SiOBr silicon oxide deposited on the side wall of the pattern
- the reaction proceeds excessively due to the catalytic action of H 2 O. It is possible to prevent the SiO 2 layer such as the gate oxide film from being damaged.
- a deposit removal process was performed on a semiconductor wafer that was left for one month after a pattern was formed by etching.
- oxygen plasma treatment was performed under the following treatment conditions. Pressure: 133 Pa (1 Torr)
- Etching gas: O 2 1980 sccm
- the pressure setting in the above-described cycle processing is maintained for 10 seconds while the APC pressure is set to 931 Pa (7 Torr), and in the second period, the processing gas is supplied.
- the state where the APC is fully opened is maintained for 10 seconds, and the actual pressure fluctuation in the processing chamber 201 is as shown in the graph of FIG. That is, even if the APC pressure is set to 931 Pa (7 Torr) after the APC is fully open, it takes about 4 to 5 seconds until the actual pressure reaches 931 Pa (7 Torr).
- the APC pressure setting is fully opened from 931 Pa (7 Torr), the pressure becomes constant at about 173 Pa (1.3 Torr) in a relatively short time.
- the pressure that is the partial pressure of the methanol gas that enables deposit removal (deposition separation) is about 665 Pa (5 Torr). Accordingly, it is preferable that the time of a half cycle in the cycle processing in this case is about 5 to 20 seconds. Note that the first period and the second period are not necessarily the same, and may be different.
- FIGS. 6 (a) to 6 (c) Electron micrographs of this comparative example are shown in FIGS. 6 (a) to 6 (c). Comparing the electron micrograph of the example of FIG. 5 with the electron micrograph of the comparative example of FIG. 6, in the example of FIG. 5, the deposit on the pattern sidewall is removed and the gate oxide film portion is clearly visible as a white line. However, in the comparative example of FIG. 6, the deposit on the pattern sidewall is not removed, so that the gate oxide film portion is not seen as a white line.
- FIGS. 7A to 7C show an electron micrograph of the pattern (left side in the figure) and an oxygen map (right side in the figure) by EELS (Electron Energy-Loss Spectroscopy).
- FIG. 7B shows a pattern after removing the deposit in the above-described embodiment. As shown in these electron micrographs, in the example, the deposit on the side wall portion of the pattern is removed without almost completely remaining, and the gate oxide film that is the structure of the pattern is scraped and damaged. Is suppressed from occurring.
- FIG. 7C shows a case where deposits are removed by changing the conditions in the treatment with HF single gas. In this case, it can be seen that the gate oxide film, which is the structure of the pattern, is cut and damaged.
- the deposits of the sample were removed at pressures of 665 Pa (5 Torr), 1330 Pa (10 Torr), and 1995 Pa (15 Torr). As a result, it was confirmed that the peel strength of the deposit increased by increasing the pressure.
- the gas treatment was continuously performed without performing the cycle treatment, so that the gate oxide film, which is the structure of the pattern, was shaved and damage occurred.
- the sample deposit was removed at temperatures of 10 ° C., 30 ° C., and 50 ° C. As a result, it was confirmed that the peel strength of the deposits was increased by lowering the temperature.
- the gas treatment was continuously performed without performing the cycle treatment, so that the gate oxide film, which is the structure of the pattern, was shaved and damage occurred.
- the present invention can be used in the field of manufacturing semiconductor devices. Therefore, it has industrial applicability.
Abstract
Description
(ステップ1)
圧力:6.65Pa(50mTorr)
高周波電力(周波数の高い高周波)/(周波数の低い高周波):400/1500W
エッチングガス:HBr/NF3/O2=400/75/5sccm
ステージ温度: 110℃
時間:5秒
(ステップ2)
圧力:6.65Pa(50mTorr)
高周波電力(周波数の高い高周波)/(周波数の低い高周波):400/1400W
エッチングガス:HBr/NF3/O2=350/32/19sccm
ステージ温度: 110℃
時間:20秒
圧力:133Pa(1Torr)
高周波電力:1000W
エッチングガス:O2=1980sccm
ステージ温度: 250℃
時間:120秒
圧力:(931Pa(7Torr)10秒⇔173Pa(1.3Torr)10秒)×6サイクル
HF/CH3OH=2800/44sccm
ステージ温度:10℃
Claims (6)
- 基板上にエッチングによって形成されたパターンの表面に堆積した堆積物を除去する堆積物除去方法であって、
前記基板を加熱しながら酸素プラズマに晒す酸素プラズマ処理工程と、
前記酸素プラズマ処理工程の後、前記基板を、処理チャンバー内でフッ化水素ガスとアルコールガスの混合ガスの雰囲気に晒し、かつ、前記アルコールガスの分圧を第1の分圧とする第1の期間と、処理チャンバー内を排気し前記アルコールガスの分圧を第1の分圧より低い第2の分圧とする第2の期間とを、複数サイクル繰り返すサイクル処理工程と、
を具備したことを特徴とする堆積物除去方法。 - 請求項1記載の堆積物除去方法であって、
前記第1の分圧が、前記混合ガスの作用によって前記堆積物を除去可能な分圧である
ことを特徴とする堆積物除去方法。 - 請求項1又は2記載の堆積物除去方法であって、
前記第1の期間及び前記第2の期間が、5秒乃至20秒の期間である
ことを特徴とする堆積物除去方法。 - 請求項1~3いずれか1項記載の堆積物除去方法であって、
前記堆積物が、シリコン酸化物を含む
ことを特徴とする堆積物除去方法。 - 請求項は1~4いずれか1項記載の堆積物除去方法であって、
前記パターンが、構造物として二酸化ケイ素を含む
ことを特徴とする堆積物除去方法。 - 請求項1~5いずれか1項記載の堆積物除去方法であって、
前記アルコールガスが、メタノールガスである
ことを特徴とする堆積物除去方法。
Priority Applications (2)
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US14/116,952 US9126229B2 (en) | 2011-05-11 | 2012-05-10 | Deposit removal method |
KR1020137030325A KR101895095B1 (ko) | 2011-05-11 | 2012-05-10 | 퇴적물 제거 방법 |
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JP2011106464A JP5823160B2 (ja) | 2011-05-11 | 2011-05-11 | 堆積物除去方法 |
JP2011-106464 | 2011-05-11 |
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WO2012153534A1 true WO2012153534A1 (ja) | 2012-11-15 |
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PCT/JP2012/003070 WO2012153534A1 (ja) | 2011-05-11 | 2012-05-10 | 堆積物除去方法 |
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US (1) | US9126229B2 (ja) |
JP (1) | JP5823160B2 (ja) |
KR (1) | KR101895095B1 (ja) |
TW (1) | TWI555086B (ja) |
WO (1) | WO2012153534A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2819150A3 (en) * | 2012-04-18 | 2015-03-18 | Tokyo Electron Limited | Deposit removing method and gas processing apparatus |
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JP5859262B2 (ja) * | 2011-09-29 | 2016-02-10 | 東京エレクトロン株式会社 | 堆積物除去方法 |
JP6082391B2 (ja) * | 2012-05-23 | 2017-02-15 | 東京エレクトロン株式会社 | 基板処理装置及び基板処理方法 |
JP6499001B2 (ja) | 2015-04-20 | 2019-04-10 | 東京エレクトロン株式会社 | 多孔質膜をエッチングする方法 |
US9865471B2 (en) * | 2015-04-30 | 2018-01-09 | Tokyo Electron Limited | Etching method and etching apparatus |
JP6516603B2 (ja) * | 2015-04-30 | 2019-05-22 | 東京エレクトロン株式会社 | エッチング方法及びエッチング装置 |
US11694911B2 (en) * | 2016-12-20 | 2023-07-04 | Lam Research Corporation | Systems and methods for metastable activated radical selective strip and etch using dual plenum showerhead |
US10224212B2 (en) * | 2017-01-27 | 2019-03-05 | Lam Research Corporation | Isotropic etching of film with atomic layer control |
KR20210011493A (ko) * | 2018-06-13 | 2021-02-01 | 램 리써치 코포레이션 | 고 종횡비 구조체들의 효율적인 세정 및 에칭 |
TW202236406A (zh) * | 2021-01-26 | 2022-09-16 | 日商東京威力科創股份有限公司 | 基板處理方法、零件處理方法及基板處理裝置 |
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TWI555086B (zh) | 2016-10-21 |
US20140083979A1 (en) | 2014-03-27 |
JP2012238711A (ja) | 2012-12-06 |
JP5823160B2 (ja) | 2015-11-25 |
TW201308428A (zh) | 2013-02-16 |
KR20140024386A (ko) | 2014-02-28 |
KR101895095B1 (ko) | 2018-09-04 |
US9126229B2 (en) | 2015-09-08 |
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