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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/66007—Multistep manufacturing processes
  • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
  • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
  • H01L29/6609—Diodes
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  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/70—Bipolar devices
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  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• • H—ELECTRICITY
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  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/761—PN junctions
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  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/66007—Multistep manufacturing processes
  • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
  • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
  • H01L29/6609—Diodes
  • H01L29/66136—PN junction diodes
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  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/70—Bipolar devices
  • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
  • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
  • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
  • H01L29/7395—Vertical transistors, e.g. vertical IGBT
• • H—ELECTRICITY
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/70—Bipolar devices
  • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
  • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
  • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
  • H01L29/7395—Vertical transistors, e.g. vertical IGBT
  • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/70—Bipolar devices
  • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
  • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
  • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
  • H01L29/7395—Vertical transistors, e.g. vertical IGBT
  • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
  • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
  • H01L29/861—Diodes

Definitions

• Bipolar punch-through semiconductor device and method for manufacturing such a semiconductor device
• the invention relates to the field of power electronics and more particularly to a method for manufacturing a bipolar punch-through semiconductor device according to claim 1 and to a bipolar punch-through semiconductor device according to the claim 10.
• EP 1 017 093 A1 a method for manufacturing an IGBT having a first main side 13 (emitter side) and a second main side 14 (collector side) is described.
• an n doped layer is created by diffusion.
• a p-base layer 4 On the emitter side 13, a p-base layer 4, n source regions 5 and a gate electrode 6 are then created.
• the wafer needs to have a thickness of at least around 400 ⁇ in order to efficiently reduce the danger of breaks during the manufacturing process.
• an emitter electrode 82 is applied.
• the thickness of the wafer is now reduced on the collector side 14 such that a tail section of the diffused n doped layer remains as a buffer layer 3.
• a p collector layer 75 and a collector electrode 92 are applied.
• an IGBT is created which has a lowly doped buffer layer 3.
• Such devices are, therefore, called soft punch-through devices.
• long diffusion times up to several days are needed to diffuse the dopants deep enough into the wafer. Even with such long times the diffusion is limited to a depth of around 150 ⁇ so that low voltage devices, in which thin drift layers are required, cannot be manufactured by this method because of the requirement of working on wafers of at least 400 ⁇ thickness.
• Such a prior art method is used for devices with blocking voltages up to around 2000 V, because such devices are relatively thin. It would be difficult if such devices were manufactured directly on a thin wafer, because working directly on thin wafers requires rather complex processes if the wafer is thin in low voltage IGBTs for forming the frontside layers including the emitter MOS cells and termination and the backside layers including the anode and buffer regions.
• EP 0 889 509 A2 describes a wafer - to - wafer bonding method for the creation of a lifetime-control layer.
• One wafer, which forms a drift layer in the finalized device is bonded to another wafer, which forms a buffer layer.
• a bonding layer with recombination centers is created in between a bonding layer with recombination centers.
• the recombination centers are created either by not aligning the crystalline axes of both wafers or by evaporating a heavy metal dopant onto one of the wafer surface before bonding and applying a heating step afterwards.
• This object is achieved by a method for manufacturing a bipolar punch-through semiconductor device according to claim 1 and by a bipolar punch-through semiconductor device according to claim 10.
• a bipolar punch-through semiconductor device which comprises depending on the semiconductor type at least a two-layer structure with layers of a first and a second conductivity type, which second conductivity type is different from the first conductivity type, wherein one of the layers is a drift layer of the first conductivity type.
• the manufacturing method can be advantageously used for large wafers , e.g. 6 or even 8 inch wafers, and for the creation of low voltage devices, because due to the usage of a thick high-doped wafer and bonding it to a thin low-doped wafer, the wafer laminate thickness can be chosen independently of the required layer thicknesses.
• the inventive method it is possible to create the layers on the third side (front side) on a thick wafer even if the required drift layer in the finalized semiconductor device is very thin. As the diffusion is started from a plane inside the wafer laminate much shorter diffusion times are required and even thin drift layers as used in low voltage devices can be manufactured.
• the process and design can be easily adapted to larger wafer diameter processing.
• deep diffused buffer layers are difficult to create for larger wafers, because buffer formation during the process requires thin wafer handling at very early stages, hence the need for wafer carrier process solutions.
• this invention better handling is possible since the process requires only thin wafer handling at the backend stage compared to other buffer designs and processes and even controllable processes even for large wafers.
• at least 400 ⁇ wafer thickness is required for processing and for 8 inch wafers even higher thickness of at least 500 ⁇ are required.
• the inventive buffer design can exemplarily be made as a double diffused buffer layer, by which a better control of the process steps are achievable compared to a prior art single buffer design. Though during the manufacturing part of the wafer is removed within the rising part of the doping concentration, the effect of variation in the cut depth is less concisely with the inventive method, because due to the double profile, the cut is done in a less steep part of the doping concentration curve.
• the buffer layer shows a region of rising doping concentration and towards the second main side a region of constant doping concentration.
• the new buffer design provides a similar final thickness to the prior art soft punch-through designs while eliminating many process issues related to prior art buffer formation processes. For example, a much better control of the depth, in which the high- doped layer is thinned in order to create the buffer layer, is achieved, because the thinning is done in this exemplary embodiment in a non profiled part of the high- doped layer, i.e. in a part of constant doping concentration.
• inventive devices provide in terms of device performance better design control and processes with lower leakage currents, improved short circuit capability and softer turn-off behavior.
• FIG 1 shows a cross sectional view on a prior art IGBT with planar gate
• FIG 2 shows a doping profile of the prior art IGBT according to FIG 1 ;
• FIG 3 shows cross sectional views on inventive IGBT with planar gate
• FIG 4 shows a doping profile of the inventive IGBT according to FIG 3;
• FIG 5 shows the doping profiles of the inventive IGBTs according to FIG 4 in more detail
• FIG 6 to 10 show manufacturing steps for manufacturing an inventive
• FIG 10 shows a cross sectional view on an inventive diode
• FIG 1 1 shows cross sectional views on inventive inventive diode
• FIG 12 shows cross sectional views on inventive trench IGBTs.
• a bipolar punch-through semiconductor device as shown in the FIGs 3, 1 1 to 12 comprises a first main side 13 and a second main side 14, which is arranged opposite of the first main side 13.
• a first electrical contact 8 is arranged on the first main side 13, and a second electrical contact 9 is arranged on the second main side 14.
• the device has at least a two-layer structure with layers of a first and a second conductivity type, which second conductivity type is different from the first conductivity type.
• One of the layers is a low-doped drift layer 2 of a first conductivity type, i.e. in the figures of n type.
• the inventive device as shown in FIG 3a) to c) is an insulated gate bipolar transistor (IGBT) 1 , in which the first electrical contact 8 is formed as an emitter electrode 82 and the second electrical contact 9 is formed as a collector electrode 92.
• IGBT insulated gate bipolar transistor
• a p type layer in form of a base layer 4 is arranged on the first main side 13 (emitter side). At least one n type source region 5 is arranged on the first main side 13 and is surrounded by the base layer 4. The at least one source region 5 has a higher doping concentration than the drift layer 2.
• a first electrically insulating layer 62 is arranged on the first main side 13 on top of the drift layer 2, the base layer 4 and the source region 5. It at least partially covers the source region 5, the base layer 4 and the drift layer 2.
• An electrically conductive gate electrode 6 is arranged on the first main side 13 electrically insulated from the at least one base layer 4, the source regions 5 and the drift layer 2 by an electrically insulating layer 62, which is typically made of silicon dioxide.
• the gate electrode 6 is embedded in the electrically insulating layer 62 and covered by another second insulating layer 64, preferably of the same material as the first insulating layer 62.
• the choice of the doping concentration and thickness of the drift layer 2 depends on the blocking capability requirements.
• the low-doped drift layer 2 is the main region for supporting the blocking voltage on the main PN junction side (emitter for IGBT, anode for diode) while the higher doped buffer layer is near the second main side 14 (collector side for IGBT or cathode side in case of a diode) and has e.g. a thickness of 30 to 190 ⁇ .
• Examplary thickness of a drift layer for a 600 V device is 30 to 70 m, 80 to 120 ⁇ for a 1200 V device and 150 to 190 ⁇ for a 1700 V device.
• the doping concentration for a lower voltage device is typically higher than for a higher voltage device, e.g. around 1 .5 * 10 14 cm “3 for a 600 V device down to 5 * 10 13 cm “3 for a 1700 V device.
• the concrete values for a device may vary depending on its application.
• the first electrically insulating region 62 is arranged on top of the emitter side. In between the first and second electrically insulating layers 62, 64, the gate electrode 6 is embedded, typically it is completely embedded.
• the gate electrode 6 is typically made of a heavily doped polysilicon or a metal like aluminum.
• the at least one source region 5, the gate electrode 6 and the electrically insulating layers 62, 64 are formed in such a way that an opening is created above the base layer 4. The opening is surrounded by the at least one source region 5, the gate electrode 6 and the electrically insulating layers 62, 64.
• the first electrical contact 8 is arranged on the first main side 13 covering the opening so that it is in direct electrical contact to the base layer 4 and the source regions 5.
• This first electrical contact 8 typically also covers the electrically insulating layers 62, 64, but is separated and thus electrically insulated from the gate electrode 6 by the second electrically insulating layer 64.
• the inventive IGBT 1 may comprise a gate electrode formed as trench gate electrode 6' as shown in FIG 1 1 a) to c).
• the trench gate electrode 6' is arranged in the same plane as the base layer 4 and adjacent to the source regions 5, separated from each other by a first insulating layer 62, which also separates the gate electrode 6 from the drift layer 2.
• a second insulating layer 64 is arranged on top of the gate electrode formed as a trench gate electrode 9', thus insulating the trench gate electrode 6' from the first electrical contact 8.
• FIG 12 an inventive bipolar punch-through semiconductor device in form of a bipolar diode 100 is shown.
• the diode 100 comprises a drift layer 2 of a first conductivity type, i.e. of n type, with a first main side 13 and a second main side 14 opposite the first main side 13.
• a p doped layer in form of an anode layer 7 is arranged on the first main side 13.
• a first electrical contact 8 as an anode electrode 84, typically in form of a metal layer is arranged on top of the anode layer 7, i.e. on that side of the layer 7, which lies opposite the drift layer 2.
• an inventive (n) doped buffer layer 3 is arranged.
• This buffer layer 3 in any case has a higher doping concentration than the drift layer 2.
• a second electrical contact 9 as a cathode electrode 94 is arranged on top of buffer layer 3, i.e. on that side of the buffer layer 3, which lies opposite the drift layer 2.
• the IGBTs, as shown in the Fig.s 3b) and 1 1 b) and the diode as shown in FIG. 12b) comprise a buffer layer 3, which has a higher doping concentration than the drift layer 2.
• the buffer layer is arranged on the drift layer 2 towards the second main side 14.
• the buffer layer 3 comprises towards the second main side 14 a high-doped region 38, which is constantly high-doped, and between the high- doped region 38 and the drift layer 2 an inter-space layer 31 , which is a diffused layer and which has a doping concentration, which decreases steadily from the doping concentration of the high-doped region to the low doping concentration of the drift layer.
• an inter-space layer 31 which is a diffused layer and which has a doping concentration, which decreases steadily from the doping concentration of the high-doped region to the low doping concentration of the drift layer.
• the doping concentration decreases typically by a Gaussian function from the value of the high-doping concentration of theoriginal first wafer at the second main side 14 towards the low-doping concentration of the original second wafer.
• this shall be also covered by the invention.
• FIGs 3a) and 1 1 a) IGBTs and a diode (FIG 12a)) are shown, in which the buffer layer 3 consists of the inter-space layer 31 or a part of the inter-space layer 31 .
• the constantly high-doped part of the first wafer has been removed from the wafer laminate.
• the removal is done within the second wafer 20 and within the inter-space layer 31 such that the bonding layer 37 is not part of the finalized device (shown in FIG 3a) and 12a)). Therefore, also defects, which might arise during the bonding process will not become part of the finalized device and therefore, the electrical properties can be improved.
• the bonding layer 37 can be part of the buffer layer 3.
• the doping concentration of the interspace-layer 31 decreases continuously and thus decreases steadily to the low doping concentration of the drift layer.
• the inventive bipolar punch-through semiconductor device can also be a reverse conducting IGBT with alternating p doped collector layer and n+ doped additional layers in a plane parallel to the second main side 14.
• any inventive bipolar punch-through semiconductor device can for example be used in a converter.
• For manufacturing an inventive bipolar punch-through semiconductor device the following steps are performed:
• the first wafer 10 has a doping concentration of 5 * 10 14 to 5 * 10 16 cm "3 .
• the second wafer has a doping concentration of 3 * 10 13 cm “3 to 2 * 10 14 cm “3 .
• a wafer laminate having a wafer laminate thickness between the third side 21 and the second side 12 is created by bonding the first wafer 10 on its first side 1 1 and the second wafer 20 on its fourth side 22 together, thus creating a bonding layer 37 at the first and fourth side 1 1 , 22 between the first and second wafer 10, 20 (FIG 7).
• a diffusion step is performed, by which a diffused inter-space layer 31 is created, which comprises first sided parts of the first wafer 10 and fourth sided parts of the second wafer 20 (FIG 8). These parts are arranged adjacent to each other.
• the inter-space layer 31 has a doping concentration, which is higher than the doping concentration of the original second wafer (second wafer as provided in step (b)) and lower than the doping concentration of the original first wafer (first wafer as provided in step (a)), wherein that part of the second wafer having unamended doping concentration in the finalized device forms a drift layer 2.
• the bonding layer 37 which is arranged at the original border between the first and second wafer 10, 20 is shown as a dotted line.
• the p doped layer can also be diffused into the drift layer 2 such that the p doped layer is arranged on the first main side 13 and wherein the drift layer 2 is arranged below the p doped layer.
• the first and second wafer 10, 20, which are provided for step (a) and (b), respectively, are exemplarily n type wafers, which are uniformly high-doped or low- doped, which shall mean that the wafers have a constant doping concentration.
• the first wafer thickness shall be the thickness of the wafer between the first and second side 15, 17 in step (a).
• a first wafer 10 may be provided, which has on the first side 1 1 a high- doped layer and which is bonded to a substrate, which substrate is completely removed in a later manufacturing step (f).
• the first wafer 10 may additionally comprise on its first side 1 1 an implanted layer, which has been implanted with second particles of the first conductivity type, which particles have a different diffusion velocity than the first particles.
• the second wafer 20 may comprise on its fourth side 22 an implanted layer with said second particles or both wafers 10, 20 may comprise implanted layers on their first, respectively fourth side 1 1 , 22.
• the layer(s) has/have been implanted before step (a) and (b), respectively.
• the diffused inter-space layer 31 created in step (d) comprises a first inter-space region 33 and a second inter-space region 35.
• the first inter-space region 33 comprises the faster diffusing particles and extends to a first region depth 34 measured from the second side 12, which is the maximum diffusion depth of the faster diffusing particles from the second side 12.
• the second interspace region 35 comprises the slower diffusing particles and extends to a second region depth 36 measured from the second side 12, ), which is the maximum diffusion depth of the slower diffusing particles from the second side 12, wherein the second region depth is smaller than the first region depth 34 (FIG 5 c)).
• FIG 3c), 1 1 c) and 12c) show the resulting devices with such an inventive double- diffused buffer layer 3.
• the second inter-space region 35 also comprises faster diffusing particles.
• the faster diffusing particles are exemplarily sulphur and the slower diffusing particles are phosphorous or arsenic. In another exemplary embodiment, the faster diffusing particles are phosphorous and the slower diffusing particles are arsenic.
• the wafer laminate may undergo thinning (like etching or grinding) and / or polishing steps at the third side 21 , i.e. within the second wafer 20. This may be useful if it is desired to work with a thicker second wafer 20 at the bonding step (c) in order to avoid cracks or breaks during manufacturing.
• second wafer 20 may be formed as disclosed above for the first wafer 10 as a wafer with a low-doped layer on the fourth side 22 and a substrate, to which the low-doped layer is bonded.
• the substrate is completely removed in the finalized device by the thinning step disclosed above.
• the term low-doped second wafer 20 shall be understood the whole application as a wafer which has at least on its fourth side a low-doped layer, i.e. it shall cover a homogeneously low-doped second wafer 20 as well as a composite of a low-doped layer with a substrate.
• step (d) the diffusion is exemplarily performed at a temperature of at least 1200 °C and during a time period of at least 180 min. Particles from the high-doped first wafer 10 diffuse into the low-doped second wafer 20 so that an inter-space layer 31 is created, which comprises such part from the high-doped first wafer 10, from which particles have been diffused and such part of the low-doped second wafer 20, into which the particles from the high-doped first wafer 10 have been diffused to.
• the drift layer 2 is such part of the second wafer with unamended low doping concentration of the wafer in the finalized device, whereas the buffer layer 3 comprises such regions towards the second side 12, which are n type and which have higher doping concentration than the drift layer 2.
• step (e) in case of a diode 12, a p doped anode layer 7 is created.
• the first electrical contact 8 formed as an anode electrode 84 may be created at this step, typically be deposition of metal on the third and second side 21 , 12.
• the anode electrode 84 may be created together with the cathode electrode 94 after the thinning of step (f).
• step (e) in case of an IGBT 1 , exemplarily the p base layer 4, the source region 5 are created on the third side 21 , and on the second side 12 the p collector layer 75 is created. Afterwards the planar gate electrode 6 or trench gate electrode 6' is created on the third side 21 together with its insulation layers 62, 64.
• the first electrical contact 8 formed as emitter electrode 82 may be made on the third side 21 at this step (e). Alternatively, the emitter electrode 82 may be created together with the collector electrode 92 after the thinning of step (f).
• the wafer laminate may be reduced in its thickness within the first wafer 10 such that a buffer layer 3 is created, which comprises the inter-space layer 31 and a remaining part of the first wafer, which part forms a high-doped region 38 (cut 3 in FIG 4) (shown examplary in FIG 3b) for a planar gate IGBT, FIG 1 1 b) for a trench gate IGBT and FIG 12b) for a diode).
• the thickness is reduced by removing a part of the wafer over the whole plane of the wafer on the second side 12 and parallel to the second side 12.
• the wafer may be cut within the second wafer 20 and within the inter-space layer 31 such that the thickness is reduced within the rising part of the doping concentration profile (cut 1 in FIG 4).
• the removal may be performed at the border between the inter-space layer 31 and the constantly high-doped part of the first wafer (cut 2 in FIG 4).
• Fig. 4 shows the doping concentration within the wafer for a uniform n type wafer (uniform doping concentration) in different manufacturing steps.
• the dashed line shows the doping concentration of the high-doped first wafer 10 and low doped second wafer 20 after bonding (step (c)).
• the continuous line shows the wafer after diffusion (step (d)) and the dotted line shows the wafer after the p type layer has been created on the first main side (step (e)).
• Fig. 5 shows in more detail the doping concentration of the n doped buffer layer 3.
• Fig. 5 a) shows the doping concentration for a wafer laminate being cut along the cut 1 of Fig. 4.
• Fig. 5 b) shows the doping concentration for cut 3 of Fig. 4 and
• Fig. 5 c) shows the doping concentration for a double diffused buffer layer.
• An exemplary thickness of the buffer layer (3) is (20 - 70) ⁇ and for the interspace layer 31 (10 - 50) ⁇ .
• the buffer layer exemplarily has a thickness of (10 to 40) ⁇ , exemplarily of (20 to 40) ⁇ .
• the conductivity types are switched, i.e. all layers of the first conductivity type are p type (e.g. the drift layer 2, the source region 5) and all layers of the second conductivity type are n type (e.g. base layer 4, the collector layer 75).

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