WO2012137914A1 - 炭化珪素縦型電界効果トランジスタ - Google Patents
炭化珪素縦型電界効果トランジスタ Download PDFInfo
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- WO2012137914A1 WO2012137914A1 PCT/JP2012/059489 JP2012059489W WO2012137914A1 WO 2012137914 A1 WO2012137914 A1 WO 2012137914A1 JP 2012059489 W JP2012059489 W JP 2012059489W WO 2012137914 A1 WO2012137914 A1 WO 2012137914A1
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- silicon carbide
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- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 196
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 195
- 230000005669 field effect Effects 0.000 title claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 45
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 6
- 229910052710 silicon Inorganic materials 0.000 claims 6
- 239000010703 silicon Substances 0.000 claims 6
- 238000003763 carbonization Methods 0.000 claims 5
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 9
- 230000005684 electric field Effects 0.000 abstract description 9
- 238000010586 diagram Methods 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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Definitions
- the present invention relates to a silicon carbide vertical field effect transistor.
- a silicon carbide vertical field effect transistor such as a vertical MOSFET (MOS field effect transistor) is conventionally used in a semiconductor device as a switching device formed on a silicon carbide substrate. Yes.
- a silicon carbide vertical MOSFET will be described as an example of the silicon carbide vertical field effect transistor, but it goes without saying that the present invention is not limited to this.
- FIG. 6 shows a cross-sectional structure of an N-channel MOSFET which is one of conventional silicon carbide (hereinafter abbreviated as “SiC”) field effect transistors.
- N-type SiC layer 2 is formed on the surface of N-type SiC substrate 1
- a plurality of P-type regions 3 are formed on the surface of N-type SiC layer 2
- N-type source region 4 and P-type region 3 are formed on the surface of P-type region 3.
- a P-type contact region 5 is formed, and a source electrode 8 is formed on the surfaces of the N-type source region 4 and the P-type contact region 5.
- a gate electrode 7 is formed on the surface of the P-type region 3 between the N-type source 5 and the N-type SiC layer via a gate insulating film 6.
- a drain electrode 9 is formed on the back side.
- FIG. 7 is a cross-sectional structure diagram of another N-channel MOSFET formed using a P-type SiC layer on the surface.
- N-type SiC layer 2 is formed on the surface of N-type SiC substrate 1, and a plurality of P-type regions 10 are formed on the surface of N-type SiC layer 2. Further, a P-type SiC layer 11 is formed on the surface. Further, an N-type region 12 is formed in the P-type SiC layer 11 on the N-type SiC layer 2 where the P-type region 10 is not formed, and the N-type source region 4 and the P-type are formed on the surface of the P-type silicon carbide layer 11.
- a contact region 5 is formed, and a source electrode 8 is formed on the surfaces of the N-type source region 4 and the P-type contact region 5.
- a gate electrode 7 is formed on the surface of the P-type region 3 between the N-type source 5 and the N-type silicon carbide layer via a gate insulating film 6.
- a drain electrode 9 is formed on the back side.
- the present invention realizes a silicon carbide vertical field effect transistor capable of improving the breakdown resistance of a gate insulating film without applying a large electric field to the gate insulating film when a high voltage is applied to the drain electrode. This is the issue.
- a silicon carbide vertical field effect transistor having an electrode a high concentration is provided under the second conductivity type region. Silicon carbide vertical field effect transistor and forming a second conductive type region.
- first conductivity type silicon carbide substrate a low-concentration first conductivity type silicon carbide layer formed on the surface of the first conductivity type silicon carbide substrate, and selectively on the surface of the first conductivity type silicon carbide layer;
- the formed second conductivity type region, the first conductivity type silicon carbide layer and the second conductivity type silicon carbide layer formed on the surface of the second conductivity type region, and the first conductivity type silicon carbide layer A first conductivity type region selectively formed on the conductivity type silicon carbide layer, a first conductivity type source region formed in the second conductivity type silicon carbide layer, and a second conductivity type silicon carbide layer;
- a high concentration second conductivity type region formed between the first conductivity type source regions and a source electrode electrically connected to the high concentration second conductivity type region and the first conductivity type source region are adjacent to each other.
- the first conductive type A silicon carbide vertical field effect transistor characterized by forming a high-concentration second conductivity type region under a second conductivity type region formed in a silicon carbide layer.
- a second conductivity type region; a source electrode electrically connected to the high-concentration second conductivity type region and the first conductivity type source region; and a first conductivity type source region formed in the adjacent second conductivity type region A gate insulating film formed on the second conductive type region and the first conductive silicon carbide layer, a gate electrode formed on the gate insulating film, and a drain on the back surface side of the first conductive silicon carbide substrate.
- a part of the second conductivity type region is shallow Silicon carbide vertical field effect transistor, characterized in that it is formed.
- the formed second conductivity type region, the first conductivity type silicon carbide layer and the second conductivity type silicon carbide layer formed on the surface of the second conductivity type region, and the first conductivity type silicon carbide layer A first conductivity type region selectively formed on the conductivity type silicon carbide layer, a first conductivity type source region formed in the second conductivity type silicon carbide layer, and a second conductivity type silicon carbide layer; A high concentration second conductivity type region formed between the first conductivity type source regions and a source electrode electrically connected to the high concentration second conductivity type region and the first conductivity type source region are adjacent to each other.
- the first conductive type A silicon carbide vertical field effect transistor characterized in that a part of the second conductivity type region formed in the silicon carbide layer is shallow.
- the formed second conductivity type region, the first conductivity type silicon carbide layer and the second conductivity type silicon carbide layer formed on the surface of the second conductivity type region, and the first conductivity type silicon carbide layer A first conductivity type region selectively formed on the conductivity type silicon carbide layer, a first conductivity type source region formed in the second conductivity type silicon carbide layer, and a second conductivity type silicon carbide layer; A high concentration second conductivity type region formed between the first conductivity type source regions and a source electrode electrically connected to the high concentration second conductivity type region and the first conductivity type source region are adjacent to each other.
- the first conductive A silicon carbide vertical field effect transistor characterized in that the second conductivity type region formed in the silicon carbide layer is formed even under the first conductivity type region formed in the second conductivity type layer.
- the present invention when a high voltage is applied to the drain electrode, a large electric field is applied to the gate insulating film by causing avalanche to occur under a high concentration P region or in a region formed in a thin layer.
- a large electric field is applied to the gate insulating film by causing avalanche to occur under a high concentration P region or in a region formed in a thin layer.
- the silicon carbide vertical field effect transistor according to the present invention will be described in detail with reference to Examples 1 to 5.
- the present invention is not limited to the following first to fifth embodiments, and various design changes can be made without departing from the spirit of the present invention.
- FIG. 1 shows a cross-sectional structure of a MOSFET in the first embodiment of the present invention.
- the first conductivity type is N-type and the second conductivity type is P-type.
- an N-type SiC layer 2 is formed on the surface of an N-type SiC substrate 1, and a plurality of P-type regions 3 are formed on the surface of the N-type SiC layer 2.
- N-type source region 4 and a P-type contact region 5 are formed on the surface of the P-type region 3. Further, source electrodes 8 are formed on the surfaces of the N-type source region 4 and the P-type contact region 5.
- a high concentration P-type region 21 is formed under the P-type region 3. Further, on the surface of the P-type region 3 and the N-type SiC layer 2 sandwiched between the N-type source region 4 on the surface of the P-type region 3 and the N-type source region 4 on the surface of the P-type region 3 different from the P-type region 3.
- a gate electrode 7 is formed through a gate insulating film 6, and a drain electrode 9 is formed on the back surface side.
- the MOSFET in the structure of the first embodiment can be turned on by applying a voltage higher than the threshold voltage to the gate electrode and forming an inversion layer on the surface of the P-type region as in the conventional MOSFET.
- avalanche occurs at the PN junction portion between the high-concentration N-type SiC layer 2 in which a high voltage is applied to the drain electrode and the P-type region 21, thereby causing a large gate oxide film.
- An electric field is not applied, and the dielectric breakdown resistance of the gate insulating film when a high voltage is applied to the drain electrode can be improved, and the reliability of the gate insulating film can be improved.
- FIG. 2 shows a cross-sectional view of the MOSFET in the second embodiment of the present invention.
- N-type SiC layer 2 is formed on the surface of N-type carbide SiC substrate 1, and a plurality of P-type regions 3 are formed on the surface of N-type SiC layer 2. Further, a P-type SiC layer 11 is formed on the surface.
- An N-type region 12 is formed in the P-type SiC layer 11 so as to reach the N-type SiC layer 2.
- An N-type source region 4 and a P-type contact region 5 are formed on the surface of the P-type SiC layer 11. Further, source electrodes 8 are formed on the surfaces of the N-type source region 4 and the P-type contact region 5.
- a high concentration P-type region 21 is formed under the P-type region 3. Further, on the surface of the P-type region 3 and the N-type SiC layer 2 sandwiched between the N-type source region 4 on the surface of the P-type region 3 and the N-type source region 4 on the surface of the P-type region 3 different from the P-type region 3.
- a gate electrode 7 is formed through a gate insulating film 6, and a drain electrode 9 is formed on the back surface side. Also in the MOSFET formed in this way, avalanche occurs at the PN junction portion between the high-concentration N-type SiC layer 2 in which a high voltage is applied to the drain electrode and the P-type region 21, and a large electric field is generated in the gate oxide film.
- the breakdown resistance and reliability of the gate insulating film exhibit the same characteristics as in the first embodiment.
- FIG. 3 shows a cross-sectional view of a MOSFET according to Embodiment 3 of the present invention.
- the difference from the first embodiment is that a thin P-type region 22 is formed in a part of the P-type region 3 without forming the high-concentration P-type region 21. It is.
- avalanche occurs at the PN junction portion between the high-concentration N-type SiC layer 2 in which a high voltage is applied to the drain electrode and the thin P-type region 22, and a large gate oxide film is formed. No electric field is applied, and the dielectric breakdown resistance and reliability of the gate insulating film exhibit the same characteristics as in the first embodiment.
- FIG. 4 shows a cross-sectional view of a MOSFET according to the fourth embodiment of the present invention.
- the difference from the second embodiment is that a thin P-type region 22 is formed in a part of the P-type region 3 without forming the high-concentration P-type region 21. It is.
- avalanche occurs at the PN junction portion between the high-concentration N-type SiC layer 2 in which a high voltage is applied to the drain electrode and the thin P-type region 22, and a large gate oxide film is formed. No electric field is applied, and the dielectric breakdown resistance and reliability of the gate insulating film exhibit the same characteristics as in the first embodiment.
- FIG. 5 shows a cross-sectional view of a MOSFET in the fifth embodiment of the present invention.
- the basic structure is the same as that of the second embodiment.
- the difference from the second embodiment is that the P-type region 3 projects below the N-type region 12 without forming the high-concentration P-type region 21. It is a point that is formed.
- avalanche occurs at the PN junction portion of the high-concentration N-type SiC layer 2 in which a high voltage is applied to the drain electrode and the portion of the P-type region 3 that protrudes under the N-type region 12.
- a large electric field is not applied to the gate oxide film, and the dielectric breakdown resistance and reliability of the gate insulating film exhibit the same characteristics as in the first embodiment.
Abstract
Description
N型SiC基板1の表面にN型SiC層2が形成され、そのN型SiC層2の表面に複数のP型領域3が形成され、P型領域3の表面にはN型ソース領域4とP型コンタクト領域5が形成され、更にN型ソース領域4とP型コンタクト領域5との表面にソース電極8が形成されている。またN型ソース5の間のP型領域3とN型SiC層の表面にゲート絶縁膜6を介してゲート電極7が形成されている。また裏面側にはドレイン電極9が形成されている。
一方、ゲート電極7にゲート閾値以上の電圧を印可するとゲート電極7直下のP型領域3又はP型SiC層11の表面には反転層が形成されることにより電流が流れるため、ゲート電極7に印加する電圧によってMOSFETのスイッチング動作を行うことができる。
課題を解決するための手段
(1)第1導電型の炭化珪素基板と該第1導電型炭化珪素基板表面に形成された低濃度の第1導電型炭化珪素層と、該第1導電型炭化珪素層表面に選択的に形成された第2導電型領域と、該第2導領域内に形成された第1導電型ソース領域と、第2導電型領域内の第1導電型ソース領域の間に形成された高濃度の第2導電型領域と、該高濃度の第2導電型領域及び第1導電型ソース領域に電気的に接続するソース電極と、隣接する第2導電型領域に形成された第1導電型ソース領域から第2導電型領域及び第1導電型炭化珪素層の上に形成されたゲート絶縁膜と、該ゲート絶縁膜上に形成されたゲート電極と、第1導電型炭化珪素基板の裏面側にドレイン電極を備えた炭化珪素縦型電界効果トランジスタにおいて、第2導電型領域と第1導電型炭化珪素層との間にアバランシェ発生手段を設けたことを特徴とする炭化珪素縦型電界効果トランジスタ。
(2)第1導電型の炭化珪素基板と該第1導電型炭化珪素基板表面に形成された低濃度の第1導電型炭化珪素層と、該第1導電型炭化珪素層表面に選択的に形成された第2導電型領域と、該第2導領域内に形成された第1導電型ソース領域と、第2導電型領域内の第1導電型ソース領域の間に形成された高濃度の第2導電型領域と、該高濃度の第2導電型領域及び第1導電型ソース領域に電気的に接続するソース電極と、隣接する第2導電型領域に形成された第1導電型ソース領域から第2導電型領域及び第1導電型炭化珪素層の上に形成されたゲート絶縁膜と、該ゲート絶縁膜上に形成されたゲート電極と、第1導電型炭化珪素基板の裏面側にドレイン電極を備えた炭化珪素縦型電界効果トランジスタにおいて、第2導電型領域下に高濃度の第2導電型領域を形成することを特徴とする炭化珪素縦型電界効果トランジスタ。
(3)第1導電型の炭化珪素基板と該第1導電型炭化珪素基板表面に形成された低濃度の第1導電型炭化珪素層と、該第1導電型炭化珪素層表面に選択的に形成された第2導電型領域と、該第1導電型炭化珪素層及び第2導電型領域の表面に形成された第2導電型炭化珪素層と、該第2導電型炭化珪素層の第1導電型炭化珪素層上に選択的に形成された第1導電型領域と、第2導電型炭化珪素層内に形成された第1導電型ソース領域と、該第2導電型炭化珪素層内の第1導電型ソース領域の間に形成された高濃度の第2導電型領域と、該高濃度の第2導電型領域及び第1導電型ソース領域に電気的に接続するソース電極と、隣接する第2導電型炭化珪素層に形成された第1導電型ソース領域から第2導電型炭化珪素層及び第1導電型領域の上に形成されたゲート絶縁膜と、該ゲート絶縁膜上に形成されたゲート電極と、第1導電型炭化珪素基板の裏面側にドレイン電極を備えた炭化珪素縦型電界効果トランジスタにおいて、第1導電型炭化珪素層内に形成された第2導電型領域下に高濃度の第2導電型領域を形成することを特徴とする炭化珪素縦型電界効果トランジスタ。
(4)第1導電型の炭化珪素基板と該第1導電型炭化珪素基板表面に形成された低濃度の第1導電型炭化珪素層と、該第1導電型炭化珪素層表面に選択的に形成された第2導電型領域と、該第2導領域内に形成された第1導電型ソース領域と、第2導電型領域内の第1導電型ソース領域の間に形成された高濃度の第2導電型領域と、該高濃度の第2導電型領域及び第1導電型ソース領域に電気的に接続するソース電極と、隣接する第2導電型領域に形成された第1導電型ソース領域から第2導電型領域及び第1導電型炭化珪素層の上に形成されたゲート絶縁膜と、該ゲート絶縁膜上に形成されたゲート電極と、第1導電型炭化珪素基板の裏面側にドレイン電極を備えた炭化珪素縦型電界効果トランジスタにおいて、第2導電型領域の一部が浅く形成されていることを特徴とする炭化珪素縦型電界効果トランジスタ。
(5)第1導電型の炭化珪素基板と該第1導電型炭化珪素基板表面に形成された低濃度の第1導電型炭化珪素層と、該第1導電型炭化珪素層表面に選択的に形成された第2導電型領域と、該第1導電型炭化珪素層及び第2導電型領域の表面に形成された第2導電型炭化珪素層と、該第2導電型炭化珪素層の第1導電型炭化珪素層上に選択的に形成された第1導電型領域と、第2導電型炭化珪素層内に形成された第1導電型ソース領域と、該第2導電型炭化珪素層内の第1導電型ソース領域の間に形成された高濃度の第2導電型領域と、該高濃度の第2導電型領域及び第1導電型ソース領域に電気的に接続するソース電極と、隣接する第2導電型炭化珪素層に形成された第1導電型ソース領域から第2導電型炭化珪素層及び第1導電型領域の上に形成されたゲート絶縁膜と、該ゲート絶縁膜上に形成されたゲート電極と、第1導電型炭化珪素基板の裏面側にドレイン電極を備えた炭化珪素縦型電界効果トランジスタにおいて、第1導電型炭化珪素層に形成された第2導電型領域の一部が浅くなっていることを特徴とする炭化珪素縦型電界効果トランジスタ。
(6)第1導電型の炭化珪素基板と該第1導電型炭化珪素基板表面に形成された低濃度の第1導電型炭化珪素層と、該第1導電型炭化珪素層表面に選択的に形成された第2導電型領域と、該第1導電型炭化珪素層及び第2導電型領域の表面に形成された第2導電型炭化珪素層と、該第2導電型炭化珪素層の第1導電型炭化珪素層上に選択的に形成された第1導電型領域と、第2導電型炭化珪素層内に形成された第1導電型ソース領域と、該第2導電型炭化珪素層内の第1導電型ソース領域の間に形成された高濃度の第2導電型領域と、該高濃度の第2導電型領域及び第1導電型ソース領域に電気的に接続するソース電極と、隣接する第2導電型炭化珪素層に形成された第1導電型ソース領域から第2導電型炭化珪素層及び第1導電型領域の上に形成されたゲート絶縁膜と、該ゲート絶縁膜上に形成されたゲート電極と、第1導電型炭化珪素基板の裏面側にドレイン電極を備えた炭化珪素縦型電界効果トランジスタにおいて、該第1導電型炭化珪素層に形成された第2導電型領域が、第2導電型層に形成された第1導電型領域下にまで形成されていることを特徴とする炭化珪素縦型電界効果トランジスタ。
なお本発明は次の実施例1~5に限定されるものではなく、本発明の趣旨を逸脱することがなければ、種々の設計変更を行うことが可能である。
図1では、N型SiC基板1の表面にN型SiC層2が形成され、そのN型SiC層2の表面にP型領域3が複数形成されている。
また、P型領域3下には高濃度のP型領域21が形成されている。さらにP型領域3表面のN型ソース領域4と該P型領域3とは別のP型領域3表面のN型ソース領域4に挟まれたP型領域3とN型SiC層2の表面にはゲート絶縁膜6を介してゲート電極7が形成され、裏面側にドレイン電極9が形成されている。
このように形成されたMOSFETにおいて、ドレイン電極に高電圧が印加された高濃度のN型SiC層2とP型領域21のPN接合部分でアバランシェを起こすようになり、これによりゲート酸化膜に大きな電界が掛かることがなくなり、ドレイン電極に高電圧印加された場合のゲート絶縁膜の絶縁破壊耐量を向上させることができると共にゲート絶縁膜の信頼性を向上させることができる。
N型炭化SiC基板1の表面にN型SiC層2が形成され、そのN型SiC層2の表面にP型領域3が複数形成されている。更にその表面にはP型SiC層11が形成されている。P型SiC層11にはN型SiC層2にまで達するようにN型領域12が形成されている。
また、P型SiC層11の表面にはN型ソース領域4とP型コンタクト領域5が形成されている。さらにN型ソース領域4とP型コンタクト領域5との表面にソース電極8が形成されている。
このように形成されたMOSFETにおいても、ドレイン電極に高電圧が印加された高濃度のN型SiC層2とP型領域21のPN接合部分でアバランシェを起こすようになり、ゲート酸化膜に大きな電界が掛かることがなくなり、ゲート絶縁膜の絶縁破壊耐量及び信頼性は実施例1と同様の特性を示す。
基本的な構造は実施例1と同様であるが、実施例1と異なる点は高濃度のP型領域21を形成せずにP型領域3の一部を薄いP型領域22を形成する点である。
このように形成されたMOSFETにおいても、ドレイン電極に高電圧が印加された高濃度のN型SiC層2と薄いP型領域22のPN接合部分でアバランシェを起こすようになり、ゲート酸化膜に大きな電界が掛かることがなくなりゲート絶縁膜の絶縁破壊耐量及び信頼性は実施例1と同様の特性を示す。
基本的な構造は実施例2と同様であるが、実施例2と異なる点は高濃度のP型領域21を形成せずにP型領域3の一部を薄いP型領域22を形成する点である。
このように形成されたMOSFETにおいても、ドレイン電極に高電圧が印加された高濃度のN型SiC層2と薄いP型領域22のPN接合部分でアバランシェを起こすようになり、ゲート酸化膜に大きな電界が掛かることがなくなりゲート絶縁膜の絶縁破壊耐量及び信頼性は実施例1と同様の特性を示す。
基本的な構造は実施例2と同様であるが、実施例2と異なる点は、高濃度のP型領域21を形成せずにP型領域3がN型領域12の下まで張り出すように形成している点である。
このように形成されたMOSFETにおいても、ドレイン電極に高電圧が印加された高濃度のN型SiC層2とN型領域12下まで張り出した部分のP型領域3のPN接合部分でアバランシェを起こすようになり、ゲート酸化膜に大きな電界が掛かることがなくなりゲート絶縁膜の絶縁破壊耐量及び信頼性は実施例1と同様の特性を示す。
2 N型炭化珪素層
3 P型領域
4 Nソース領域
5 Pコンタクト領域
6 ゲート絶縁膜
7 ゲート電極
8 ソース電極
9 ドレイン電極
10 P型ベース領域
11 P型炭化珪素層
12 N型領域
21 高濃度P型領域
22 薄層P型領域
Claims (6)
- 第1導電型の炭化珪素基板と該第1導電型炭化珪素基板表面に形成された低濃度の第1導電型炭化珪素層と、該第1導電型炭化珪素層表面に選択的に形成された第2導電型領域と、該第2導領域内に形成された第1導電型ソース領域と、第2導電型領域内の第1導電型ソース領域の間に形成された高濃度の第2導電型領域と、該高濃度の第2導電型領域及び第1導電型ソース領域に電気的に接続するソース電極と、隣接する第2導電型領域に形成された第1導電型ソース領域から第2導電型領域及び第1導電型炭化珪素層の上に形成されたゲート絶縁膜と、該ゲート絶縁膜上に形成されたゲート電極と、第1導電型炭化珪素基板の裏面側にドレイン電極を備えた炭化珪素縦型電界効果トランジスタにおいて、第2導電型領域と第1導電型炭化珪素層との間にアバランシェ発生手段を設けたことを特徴とする炭化珪素縦型電界効果トランジスタ。
- 第1導電型の炭化珪素基板と該第1導電型炭化珪素基板表面に形成された低濃度の第1導電型炭化珪素層と、該第1導電型炭化珪素層表面に選択的に形成された第2導電型領域と、該第2導領域内に形成された第1導電型ソース領域と、第2導電型領域内の第1導電型ソース領域の間に形成された高濃度の第2導電型領域と、該高濃度の第2導電型領域及び第1導電型ソース領域に電気的に接続するソース電極と、隣接する第2導電型領域に形成された第1導電型ソース領域から第2導電型領域及び第1導電型炭化珪素層の上に形成されたゲート絶縁膜と、該ゲート絶縁膜上に形成されたゲート電極と、第1導電型炭化珪素基板の裏面側にドレイン電極を備えた炭化珪素縦型電界効果トランジスタにおいて、第2導電型領域下に高濃度の第2導電型領域を形成することを特徴とする炭化珪素縦型電界効果トランジスタ。
- 第1導電型の炭化珪素基板と該第1導電型炭化珪素基板表面に形成された低濃度の第1導電型炭化珪素層と、該第1導電型炭化珪素層表面に選択的に形成された第2導電型領域と、該第1導電型炭化珪素層及び第2導電型領域の表面に形成された第2導電型炭化珪素層と、該第2導電型炭化珪素層の第1導電型炭化珪素層上に選択的に形成された第1導電型領域と、第2導電型炭化珪素層内に形成された第1導電型ソース領域と、該第2導電型炭化珪素層内の第1導電型ソース領域の間に形成された高濃度の第2導電型領域と、該高濃度の第2導電型領域及び第1導電型ソース領域に電気的に接続するソース電極と、隣接する第2導電型炭化珪素層に形成された第1導電型ソース領域から第2導電型炭化珪素層及び第1導電型領域の上に形成されたゲート絶縁膜と、該ゲート絶縁膜上に形成されたゲート電極と、第1導電型炭化珪素基板の裏面側にドレイン電極を備えた炭化珪素縦型電界効果トランジスタにおいて、第1導電型炭化珪素層内に形成された第2導電型領域下に高濃度の第2導電型領域を形成することを特徴とする炭化珪素縦型電界効果トランジスタ。
- 第1導電型の炭化珪素基板と該第1導電型炭化珪素基板表面に形成された低濃度の第1導電型炭化珪素層と、該第1導電型炭化珪素層表面に選択的に形成された第2導電型領域と、該第2導領域内に形成された第1導電型ソース領域と、第2導電型領域内の第1導電型ソース領域の間に形成された高濃度の第2導電型領域と、該高濃度の第2導電型領域及び第1導電型ソース領域に電気的に接続するソース電極と、隣接する第2導電型領域に形成された第1導電型ソース領域から第2導電型領域及び第1導電型炭化珪素層の上に形成されたゲート絶縁膜と、該ゲート絶縁膜上に形成されたゲート電極と、第1導電型炭化珪素基板の裏面側にドレイン電極を備えた炭化珪素縦型電界効果トランジスタにおいて、第2導電型領域の一部が浅く形成されていることを特徴とする炭化珪素縦型電界効果トランジスタ。
- 第1導電型の炭化珪素基板と該第1導電型炭化珪素基板表面に形成された低濃度の第1導電型炭化珪素層と、該第1導電型炭化珪素層表面に選択的に形成された第2導電型領域と、該第1導電型炭化珪素層及び第2導電型領域の表面に形成された第2導電型炭化珪素層と、該第2導電型炭化珪素層の第1導電型炭化珪素層上に選択的に形成された第1導電型領域と、第2導電型炭化珪素層内に形成された第1導電型ソース領域と、該第2導電型炭化珪素層内の第1導電型ソース領域の間に形成された高濃度の第2導電型領域と、該高濃度の第2導電型領域及び第1導電型ソース領域に電気的に接続するソース電極と、隣接する第2導電型炭化珪素層に形成された第1導電型ソース領域から第2導電型炭化珪素層及び第1導電型領域の上に形成されたゲート絶縁膜と、該ゲート絶縁膜上に形成されたゲート電極と、第1導電型炭化珪素基板の裏面側にドレイン電極を備えた炭化珪素縦型電界効果トランジスタにおいて、第1導電型炭化珪素層に形成された第2導電型領域の一部が浅くなっていることを特徴とする炭化珪素縦型電界効果トランジスタ。
- 第1導電型の炭化珪素基板と該第1導電型炭化珪素基板表面に形成された低濃度の第1導電型炭化珪素層と、該第1導電型炭化珪素層表面に選択的に形成された第2導電型領域と、該第1導電型炭化珪素層及び第2導電型領域の表面に形成された第2導電型炭化珪素層と、該第2導電型炭化珪素層の第1導電型炭化珪素層上に選択的に形成された第1導電型領域と、第2導電型炭化珪素層内に形成された第1導電型ソース領域と、該第2導電型炭化珪素層内の第1導電型ソース領域の間に形成された高濃度の第2導電型領域と、該高濃度の第2導電型領域及び第1導電型ソース領域に電気的に接続するソース電極と、隣接する第2導電型炭化珪素層に形成された第1導電型ソース領域から第2導電型炭化珪素層及び第1導電型領域の上に形成されたゲート絶縁膜と、該ゲート絶縁膜上に形成されたゲート電極と、第1導電型炭化珪素基板の裏面側にドレイン電極を備えた炭化珪素縦型電界効果トランジスタにおいて、該第1導電型炭化珪素層に形成された第2導電型領域が、第2導電型層に形成された第1導電型領域下にまで形成されていることを特徴とする炭化珪素縦型電界効果トランジスタ。
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