WO2012127861A1 - 不揮発性記憶装置の製造方法 - Google Patents
不揮発性記憶装置の製造方法 Download PDFInfo
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- WO2012127861A1 WO2012127861A1 PCT/JP2012/001947 JP2012001947W WO2012127861A1 WO 2012127861 A1 WO2012127861 A1 WO 2012127861A1 JP 2012001947 W JP2012001947 W JP 2012001947W WO 2012127861 A1 WO2012127861 A1 WO 2012127861A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
- H10B63/22—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes of the metal-insulator-metal type
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Shaping switching materials
- H10N70/066—Shaping switching materials by filling of openings, e.g. damascene method
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
Definitions
- the present invention relates to a method for manufacturing a resistance change type nonvolatile memory device using a resistance change element that changes its resistance value by application of a voltage pulse and can hold the resistance value in a nonvolatile manner.
- the resistance change element is an element that has a property that the resistance value reversibly changes by an electrical signal, and that can store information corresponding to the resistance value in a nonvolatile manner.
- Patent Document 1 discloses a nonvolatile memory device having a configuration in which a resistance change film is used as a memory unit and a diode element is used as a switching element.
- An object of the present invention is to provide a method for manufacturing a variable resistance nonvolatile memory device that has good consistency with a dual damascene process suitable for forming a fine copper wiring, and is capable of high capacity and high integration. .
- a method for manufacturing a nonvolatile semiconductor memory device is a method for manufacturing a resistance variable nonvolatile memory device, which includes a plurality of stripe-shaped first methods on a substrate.
- Forming a first wiring, forming a first interlayer insulating layer on the plurality of first wirings, and penetrating the first interlayer insulating layer and connected to the first wiring A step of forming a plurality of memory cell holes; a step of embedding at least one electrode of a resistance change element and a resistance change layer in the memory cell hole; and a second interlayer insulating layer on the first interlayer insulating layer.
- the contact hole and the resistance change Forming the wiring groove connected to the child, covering the wiring groove and not covering the bottom surface of the contact hole, the first interlayer insulating layer, the second interlayer insulating layer, and the Forming a current control layer of the bidirectional diode element on the variable resistance layer; and a lower layer serving as an upper electrode of the bidirectional diode element and an upper layer composed of a wiring material in the contact hole and the wiring groove.
- variable resistance nonvolatile memory device that has good consistency with a dual damascene process suitable for forming a fine copper wiring, and that is capable of high capacity and high integration.
- FIG. 1A is a plan view showing a variable resistance nonvolatile memory device according to the first embodiment of the present invention.
- FIG. 1B is a cross-sectional view showing a variable resistance nonvolatile memory device according to the first embodiment of the present invention.
- FIG. 2 is a cross-sectional view showing the main steps of the method of manufacturing the variable resistance nonvolatile memory device according to the first embodiment of the present invention.
- FIG. 3 is a cross-sectional view showing the main steps of the method of manufacturing the variable resistance nonvolatile memory device according to the first embodiment of the present invention.
- FIG. 4 is a cross-sectional view showing the main steps of the method of manufacturing the variable resistance nonvolatile memory device according to the first embodiment of the present invention.
- FIG. 5A is a cross-sectional view illustrating in detail the positional relationship between the opening of the contact hole and the wiring groove of the variable resistance nonvolatile memory device according to the first embodiment of the present invention.
- FIG. 5B is an enlarged cross-sectional view (a view in which an X portion in FIG. 5A is enlarged) of a part of the variable resistance nonvolatile memory device according to the first embodiment of the present invention.
- FIG. 6A is a plan view for explaining the flying direction of material molecules in the step of forming the current control layer of the diode element in the method of manufacturing the variable resistance nonvolatile memory device according to the first embodiment of the present invention.
- FIG. 6B is a cross-sectional view illustrating the direction in which material molecules fly in the process of forming a current control layer of the diode element in the method of manufacturing the variable resistance nonvolatile memory device according to the first embodiment of the present invention.
- FIG. 7 is a cross-sectional view illustrating a sputtering method in the process of forming the current control layer of the diode element in the method of manufacturing the variable resistance nonvolatile memory device according to the first embodiment of the present invention.
- FIG. 8 is a cross-sectional view illustrating the shape of the current control layer after sputtering in the step of forming the current control layer of the diode element in the method of manufacturing the variable resistance nonvolatile memory device according to the first embodiment of the invention. .
- FIG. 1 is a cross-sectional view illustrating the direction in which material molecules fly in the process of forming a current control layer of the diode element in the method of manufacturing the variable resistance nonvolatile memory device according to the first embodiment of the
- FIG. 9A is a plan view illustrating the configuration of the contact hole opening and the wiring groove of the variable resistance nonvolatile memory device according to the first embodiment of the invention.
- FIG. 9B is a cross-sectional view showing a modification of the variable resistance nonvolatile memory device according to the first embodiment of the present invention.
- FIG. 10A is a plan view for explaining a modification example of the flying direction of the material molecules in the step of forming the current control layer of the diode element in the method of manufacturing the variable resistance nonvolatile memory device according to the first embodiment of the present invention. .
- FIG. 10A is a plan view for explaining a modification example of the flying direction of the material molecules in the step of forming the current control layer of the diode element in the method of manufacturing the variable resistance nonvolatile memory device according to the first embodiment of the present invention. .
- FIG. 10B is a cross-sectional view illustrating a variation of the flying direction of the material molecules in the process of forming the current control layer of the diode element in the variable resistance nonvolatile memory device manufacturing method according to the first embodiment of the present invention.
- FIG. 11A is a cross-sectional view showing a variable resistance nonvolatile memory device according to a second embodiment of the present invention.
- FIG. 11B is a cross-sectional view showing a variable resistance nonvolatile memory device according to the second embodiment of the present invention.
- FIG. 12 is a plan view showing a variable resistance nonvolatile memory device according to the second embodiment of the present invention.
- FIG. 13A is a cross-sectional view showing the main steps in the method of manufacturing the variable resistance nonvolatile memory device according to the second embodiment of the present invention.
- FIG. 13B is a cross-sectional view showing the main steps in the method of manufacturing the variable resistance nonvolatile memory device according to the second embodiment of the present invention.
- FIG. 14 is a cross-sectional view showing the main steps of the method of manufacturing the variable resistance nonvolatile memory device according to the second embodiment of the present invention.
- FIG. 15 is a cross-sectional view showing the main steps of the method of manufacturing the variable resistance nonvolatile memory device according to the second embodiment of the present invention.
- FIG. 16 shows the relationship between the sputtering angle and the film formation state of the current control layer in the process of forming the current control layer of the diode element in the method of manufacturing the variable resistance nonvolatile memory device according to the second embodiment of the present invention. It is sectional drawing shown.
- FIG. 17 shows the relationship between the sputtering angle and the film formation state of the current control layer in the process of forming the current control layer of the diode element in the method of manufacturing the variable resistance nonvolatile memory device according to the second embodiment of the invention. It is sectional drawing which shows a modification.
- FIG. 18 is a cross-sectional view showing a modification of the main steps of the method of manufacturing the variable resistance nonvolatile memory device according to the second embodiment of the present invention.
- FIG. 19A is a cross-sectional view showing a variable resistance nonvolatile memory device according to an embodiment of the present invention.
- FIG. 19B is a cross-sectional view showing the variable resistance nonvolatile memory device according to the embodiment of the present invention.
- FIG. 20 is a plan view showing a variable resistance nonvolatile memory device according to an embodiment of the present invention.
- FIG. 21 is a cross-sectional view showing the main steps of the method of manufacturing the variable resistance nonvolatile memory device according to the embodiment of the present invention.
- FIG. 22 is a cross-sectional view showing the main steps of the method of manufacturing the variable resistance nonvolatile memory device according to the embodiment of the present invention.
- FIG. 23 is a cross-sectional view showing the main steps of the method of manufacturing the variable resistance nonvolatile memory device according to the embodiment of the present invention.
- FIG. 24A is a cross-sectional view showing a modification of the variable resistance nonvolatile memory device according to the embodiment of the present invention.
- FIG. 24B is a cross-sectional view showing a modification of the variable resistance nonvolatile memory device according to the embodiment of the present invention.
- FIG. 24C is a cross-sectional view showing a modification of the main process of the method of manufacturing the variable resistance nonvolatile memory device according to the embodiment of the present invention.
- FIG. 25A is a cross-sectional view showing a variable resistance nonvolatile memory device of a prior example.
- FIG. 25B is a cross-sectional view showing a variable resistance nonvolatile memory device of a prior example.
- FIG. 26 is a plan view showing a resistance variable nonvolatile memory device of a prior example.
- FIG. 27 is a cross-sectional view showing the main steps of the manufacturing method of the resistance variable nonvolatile memory device of the prior example.
- FIG. 28 is a cross-sectional view showing the main steps of the manufacturing method of the resistance variable nonvolatile memory device of the preceding example.
- FIG. 25A and 25B are cross-sectional views illustrating a configuration example of the variable resistance nonvolatile memory device 40 in Patent Document 1
- FIG. 26 is a plan view illustrating a configuration example of the variable resistance nonvolatile memory device. is there. 26 corresponds to FIG. 25A, and the cross-sectional view of the alternate long and short dash line indicated by 1B in FIG. 26 is viewed in the direction of the arrow. The cross-sectional view corresponds to FIG. 25B.
- a memory cell hole 103 is formed at the position.
- the variable resistance nonvolatile memory device 40 in Patent Document 1 covers a substrate 100 on which a first electrode 101 is formed and covers the first electrode 101 on the substrate 100.
- An interlayer insulating layer 102 composed of a silicon oxide film formed in this manner, and a memory cell hole 103 formed through the interlayer insulating layer 102 and electrically connected to the first electrode 101;
- a first variable resistance layer 104a is formed on the bottom and side walls of the memory cell hole 103 in contact with the first electrode 101, and a second variable resistance layer 104b is formed above and inside the first variable resistance layer 104a. ing.
- a recess is provided above the memory cell hole 103 on the surface of the interlayer insulating layer 102, and the second electrode is formed so as to cover the surfaces of the first resistance change layer 104a and the second resistance change layer 104b in the recess. 105 is embedded. Further, an interlayer insulating layer 112 between wirings made of a silicon oxide film is formed on the interlayer insulating layer 102, and the second insulating film is formed on the bottom and side walls of the wiring trench formed in the interlayer insulating layer 112 between the wirings.
- the current control layer 111 is formed so as to cover the surface of the electrode 105, and the third electrode 109 is formed so as to cover at least the surface of the current control layer 111 on the second electrode 105. .
- a lead wiring 128 made of copper is formed using the third electrode 109 as an adhesion layer.
- the lead wiring 128 is formed integrally with the wiring and the contact plug, and is formed above the memory cell hole 103.
- the variable resistance element includes a first electrode 101, a first variable resistance layer 104a, a second variable resistance layer 104b, and a second electrode 105, and the diode element includes a second electrode 105 and a current control layer 111. , And a third electrode 109.
- variable resistance nonvolatile memory device 40 When the above-described variable resistance nonvolatile memory device 40 is viewed in plan, as shown in FIG. 26, a lower wiring layer composed of the first electrode 101, a third electrode 109, a current control layer 111, The upper wiring layers composed of the lead wires 128 have stripe shapes and are orthogonal to each other. A resistance change element and a diode element are formed at the intersection via the memory cell hole 103. Further, the first electrode 101 is connected to the lead-out wiring 128 through the contact hole 106 to constitute a cross point memory array.
- variable resistance nonvolatile memory device capable of high capacity and high integration can be realized without providing a switching element such as a transistor.
- tantalum nitride is used as the second electrode 105 and the third electrode 109, and a nitrogen-deficient silicon nitride film is used as the current control layer 111. Since the work function of tantalum nitride is 4.76 eV, which is sufficiently higher than the electron affinity of silicon, 3.78 eV, a Schottky barrier is formed at the interface between the second electrode 105 and the third electrode 109 and the current control layer 111.
- a bidirectional MSM (Metal-Semiconductor-Metal) diode element can be realized.
- the second electrode 105 made of tantalum nitride has a lower standard electrode potential than the first electrode 101 and is an electrode that hardly causes a resistance change of the resistance change element. The resistance change selectively occurs in the vicinity of the interface between the first electrode 101 and the first resistance change layer 104a.
- the second electrode 105 made of tantalum nitride is characterized by good adhesion to the lead wiring 128 made of copper.
- FIGS. 28 (a) to 28 (c) are cross-sectional views showing a method of manufacturing the main part of the resistance variable nonvolatile memory device 40 in Patent Document 1. FIG. The manufacturing method is demonstrated using these.
- a first electrode (an electrode that also serves as a wiring) 101 is formed on a substrate 100, and then an interlayer insulating layer 102 is formed on the first electrode 101. Thereafter, a memory cell hole 103 reaching the first electrode 101 is formed in the interlayer insulating layer 102. After the first variable resistance layer 104a and the second variable resistance layer 104b having a lower oxygen content than the first variable resistance layer 104a are formed in the memory cell hole 103 so as to be embedded in the memory cell hole. Then, the first variable resistance layer 104a and the second variable resistance layer 104b above the memory cell hole 103 are removed.
- a second electrode 105 made of tantalum nitride is formed only in the memory cell hole 103.
- an interlayer insulating layer 112 composed of a silicon oxide film or the like is formed on the interlayer insulating layer 102, and a wiring groove 108a for embedding a later lead wiring 128 or the like is formed.
- the interlayer insulating layer 102 is patterned with a desired mask. At this time, the upper surface of the second electrode 105 is exposed at the bottom of the wiring groove 108a.
- a current control layer composed of a nitrogen-deficient silicon nitride film or the like on the entire surface including the interlayer insulating layer 102 and the wiring groove 108a where the second electrode 105 is exposed. 111 is formed.
- an opening that is, a contact hole 106 that penetrates the interlayer insulating layer 102 and the current control layer 111 formed in the wiring groove 108a and is connected to the first electrode 101 is formed.
- the entire surface is made of tantalum nitride or the like so as to cover the surface of the current control layer 111 on the wiring trench 108a and the interlayer insulating layer 112 and the inner surface of the contact hole 106.
- a third electrode 109 is formed.
- the lead-out wiring 128 made entirely of copper or the like so as to cover the surfaces of the wiring groove 108a, the interlayer insulating layer 112, and the third electrode 109 on the contact hole 106. Form.
- the current control layer 111 is provided under the conventional wiring structure in order to connect the material in the memory cell hole 103 constituting the cross-point memory and the MSM diode element. Need to form. Therefore, it is necessary to form the wiring trench 108a before the contact hole 106, and the conventional dual damascene process cannot be applied. Therefore, first, as shown in FIG. 28B, the wiring groove 108a is formed, the current control layer 111 is formed in the wiring groove 108a, and then the contact hole 106 is formed on the wafer surface having a large step in the wiring groove 108a. Is opened (FIG. 28D).
- the current control layer 111 on the opening of the contact hole 106 can be completely removed simultaneously with the formation of the opening of the contact hole 106. Therefore, a part of the surface of the first electrode 101 is exposed at the bottom of the contact hole 106, and good ohmic characteristics are provided between the third electrode 109 and the first electrode 101 formed in the contact hole 106. A bond with is formed.
- the wiring groove 108a is formed in the place where the contact hole 106 is formed. Therefore, the place where the contact hole 106 is formed. Is lower than the surface of the interlayer insulating layer 102 by the height of the wiring trench 108a.
- resist coating by spin coating as the width of a groove having a step increases, the thickness of the resist applied on the groove tends to decrease, and the resist is applied locally on the wafer surface in accordance with the pattern of the wiring groove 108a. The resist film thickness varies.
- the variation in the resist film thickness causes the variation in the exposure dimension in lithography, which causes variations in the size of the opening of the contact hole 106. For this reason, it is difficult to accurately form the contact hole 106 having a fine dimension within the wafer surface. Therefore, the process procedure of the preceding example is effective when the design rule is large and the dimensional variation of the opening of the contact hole 106 can be tolerated, but there is a problem that the application becomes difficult as the size is reduced.
- the contact hole 106 is first opened on the planarized wafer surface, so that there is almost no influence of the focus margin in the lithography process of the contact hole 106. Further, in the subsequent lithography process for forming the wiring trench 108a, the opening area of the contact hole 106 is small, so that the local variation of the resist film thickness is much larger than that in the case of forming the opening of the contact hole 106 of the previous example. The influence on the focus margin can be reduced to such an extent that it does not cause a problem in processing.
- a method for manufacturing a nonvolatile semiconductor memory device is a method for manufacturing a resistance change type nonvolatile memory device, which includes a plurality of stripe-shaped devices on a substrate. Forming a first wiring; forming a first interlayer insulating layer on the plurality of first wirings; and penetrating the first interlayer insulating layer and connected to the first wiring.
- the contact hole and the resistor A step of forming the wiring groove to be connected to the activating element; and the first interlayer insulating layer, the second interlayer insulating layer, covering the wiring groove and not covering the bottom surface of the contact hole; Forming a current control layer of the bidirectional diode element on the variable resistance layer; and a lower layer serving as an upper electrode of the bidirectional diode element and an upper layer composed of a wiring material in the contact hole and the wiring groove.
- Forming a second wiring configured to form the bidirectional diode element connected to the variable resistance element and a contact plug of the contact hole.
- the current control is performed by sputtering in which a film-forming material comes from a direction parallel to the arrangement direction of the plurality of memory cell holes and oblique to the surface of the substrate.
- a layer may be deposited.
- the wiring groove is formed.
- the focus margin is ensured, and the contact hole having a fine dimension is formed in the wafer surface.
- the current control layer of the bidirectional diode element is formed in the wiring groove so as to cover the opening of the memory cell hole, but is selectively formed so as not to be formed in the bottom surface portion of the contact hole.
- the first wiring and the contact hole are in contact with each other through the barrier film having good adhesion, not the current control layer of the bidirectional diode element.
- the contact resistance between the first wiring and the contact plug can be kept low, and at the same time, a bidirectional diode element can be formed in the wiring groove on the memory cell hole. Therefore, a variable resistance nonvolatile memory device capable of high capacity and high integration by miniaturization can be provided.
- the current control layer of the bidirectional diode element can be selectively formed, an etching process for separately removing the current control layer of the bidirectional diode element can be omitted, and the number of manufacturing steps can be reduced. Become. As a result, a variable resistance nonvolatile memory device can be provided at low cost.
- the size of the contact hole opening in the alignment direction is a
- the memory cell hole closest to one end of the wiring groove opening from one end of the wiring groove opening in the alignment direction is The distance from the opening to one end of the opening of the wiring groove is e
- the height of the contact hole is c
- the height of the wiring groove is d
- a and e are the alignment direction.
- the contact holes and the memory cell holes arranged in parallel and the wiring grooves including the openings thereof are values measured in the same cross section in the same direction, and ⁇ and ⁇ are used by using the a, the c, the d and the e.
- the direction in which the film forming material flies has an angle of ⁇ with respect to the surface of the substrate, and is parallel to the direction of the cross section in which a and e are measured, and the ⁇ , ⁇ , and The ⁇ may satisfy the condition of ⁇ ⁇ ⁇ .
- the contact hole is located between the memory cell hole closest to one end of the wiring groove opening in the arrangement direction and the one end of the wiring groove opening, and the contact hole opening
- the distance from the end far from one end of the wiring groove opening to one end of the wiring groove opening is b, and the contact hole and the memory cell hole are arranged such that a and b are arranged in the arrangement direction.
- the wiring trench and the contact hole may be formed so as to satisfy a condition of ⁇ > ⁇ .
- the direction in which the film-forming material flies has an angle of ⁇ with respect to the surface of the substrate, and is parallel to the cross-sectional direction in which the a, the b, and the e are measured, and the The direction from one end of the opening of the wiring trench toward the contact hole may be such that ⁇ , ⁇ , and ⁇ satisfy the condition of ⁇ ⁇ ⁇ .
- the step of forming the current control layer includes a bidirectional diode element on the first interlayer insulating layer, the second interlayer insulating layer, and the resistance change layer so as to cover the contact hole and the wiring groove.
- the second wiring may be formed in the wiring groove on the upper side.
- the wiring groove is formed.
- the focus margin is ensured, and the contact hole having a fine dimension is formed on the wafer surface.
- the one in the contact hole can be selectively removed while protecting the one in the wiring groove. Accordingly, the first wiring and the contact plug in the contact hole are in contact with each other through the barrier film having good adhesion, not the current control layer of the bidirectional diode. As a result, the contact resistance between the first wiring and the contact plug can be kept low, and at the same time, a bidirectional diode can be formed in the wiring groove. Therefore, a variable resistance nonvolatile memory device capable of high capacity and high integration by miniaturization can be provided.
- FIG. 1A and FIG. 1B are plan views showing a configuration example of a variable resistance nonvolatile memory device according to the first embodiment of the present invention.
- FIG. 1B is a cross-sectional view showing a configuration example of the variable resistance nonvolatile memory device according to this embodiment. Note that a cross-sectional view of the cross-section taken along the alternate long and short dash line indicated by 1A in FIG. 1A in the direction of the arrow corresponds to FIG. 1B.
- this nonvolatile memory device (cross point memory) is almost the same as FIG. 25A and FIG. 25B showing the cross-sectional views of the previous example and FIG. 26 showing the plan view.
- members having substantially the same functions as the members used are represented by the same symbols.
- the difference between the preceding example and this embodiment is that the first electrode 101 of the preceding example is provided as the first electrode 101c on the first wiring 101a in this embodiment.
- the second electrode 105 is provided as a lower electrode of the MSM diode element separately from the second variable resistance layer 104b.
- the second variable resistance layer 104b includes the MSM diode element. This is a structure in which the lower electrode is also used.
- liner films 115 and 116 are provided for protecting wiring by preventing copper oxidation and the like.
- a first wiring 101a composed of a plurality of cross-point array wirings formed in a stripe shape in parallel with each other and wirings used to connect the wirings to peripheral circuits
- a plurality of cross-point array wirings formed in a stripe shape in parallel with each other and second wirings (drawing wirings) 108 formed from wirings used to connect the wirings to peripheral circuits are formed.
- a memory cell hole 103 is formed at a position where the cross point array wiring of the first wiring 101a and the cross point array wiring of the second wiring 108 intersect.
- a plurality of wiring grooves 108a are formed, and the extending directions of the plurality of wiring grooves 108a are unified in the same direction.
- FIGS. 2A to 2C, FIGS. 3A to 3C, and FIGS. 4A to 4B show the main steps of the method of manufacturing the variable resistance nonvolatile memory device according to this embodiment. It is sectional drawing shown. The manufacturing method is demonstrated using these.
- FIG. 2A shows a process of forming the first wiring 101a and the interlayer insulating layers 102 and 114.
- a silicon oxide film for example, a plasma TEOS (Tetra Ethyl Ortho Silicate) film or a fluorine film is formed on a substrate 100 on which transistors, lower layer wirings, and the like are formed using a plasma CVD (Chemical Vapor Deposition) method or the like.
- An interlayer insulating layer 114 made of an FSG (Fluorinated Silicate Glass) film containing the like is formed.
- a wiring trench in which the first wiring 101a is embedded in the interlayer insulating layer 114 is formed by photolithography and dry etching.
- a barrier film 101b composed of TaN (film thickness: 5 nm to 40 nm) and Ta (film thickness: 5 nm to 40 nm) and copper as a wiring material (film thickness: 50 nm to 300 nm) are formed in the formed wiring trench. And the like are sequentially deposited using a sputtering method or the like.
- the barrier film 101b improves the adhesion between the interlayer insulating layer 114 formed of a silicon oxide film or the like and the first wiring 101a formed of copper, and the copper of the first wiring 101a is formed in the interlayer insulating layer 114. It is a film
- an interlayer insulating layer 102 as a first interlayer insulating layer is further deposited on the liner film 115 (the plurality of first wirings 101a), and if necessary, a step on the surface of the interlayer insulating layer 102 by CMP. Relax.
- FIG. 2B shows a process of forming a memory cell hole penetrating the interlayer insulating layer 102 and connected to the first wiring 101a.
- an opening that penetrates the interlayer insulating layer 102 and the liner film 115 and is connected to the first wiring 101a, that is, a memory cell hole 103 is formed.
- a first electrode 101c made of a noble metal or the like is selectively formed only on copper, which is the first wiring 101a at the bottom of the memory cell hole 103, by electroless plating or the like.
- Pt, Ir, Pd, etc. are grown from 2 nm to 30 nm, and here Pt is grown by about 5 nm.
- a plating underlayer containing Ni or the like may be grown between copper and a noble metal.
- the electroless plating can be controlled more easily than in the case where the base of the first electrode 101c is copper.
- a tantalum target is sputtered in an argon and oxygen gas atmosphere, so-called reactive sputtering, on the first electrode 101c at the bottom of the memory cell hole 103, on the side wall of the memory cell hole 103, and on the surface of the interlayer insulating layer 102
- the first variable resistance layer 104a made of tantalum oxide or the like is formed. In reactive sputtering, if the oxygen flow rate during film formation is increased, the oxygen content of the formed film can be increased.
- the first variable resistance layer 104a having an oxygen content of about 71 atm% was formed under the conditions of argon 34 sccm, oxygen 24 sccm, and power 1.6 kW. Subsequently, oxygen is contained in the memory cell hole 103 having the first variable resistance layer 104a formed on the surface thereof, that is, on the first variable resistance layer 104a in the memory cell hole 103 from the first variable resistance layer 104a.
- the tantalum oxide of the second variable resistance layer 104b having a low rate is formed. This formation is performed by reactive sputtering in the same manner as the formation of the first variable resistance layer 104a.
- the second variable resistance layer 104b having an oxygen content of about 60 atm% was formed under the conditions of argon 34 sccm, oxygen 20.5 sccm, and power 1.6 kW.
- a tantalum oxide film is formed by sputtering until the inside of the memory cell hole 103 is completely filled, and then unnecessary tantalum oxide on the surface of the interlayer insulating layer 102 is formed by CMP.
- the first variable resistance layer 104 a and the second variable resistance layer 104 b are formed only in the memory cell hole 103. As a result, at least one electrode of the variable resistance element and the variable resistance layer 104 are embedded in the memory cell hole 103.
- an oxygen-deficient transition metal oxide preferably an oxygen-deficient tantalum oxide
- An oxygen-deficient transition metal oxide is an oxide having a lower oxygen content (atomic ratio: ratio of the number of oxygen atoms to the total number of atoms) than an oxide having a stoichiometric composition.
- an oxide having a stoichiometric composition is an insulator or has a very high resistance value.
- the transition metal is Ta
- the stoichiometric oxide composition is Ta 2 O 5 and the ratio of the number of Ta and O atoms (O / Ta) is 2.5.
- the oxygen-deficient tantalum oxide the atomic ratio of Ta and O is larger than 0 and smaller than 2.5.
- the oxygen-deficient transition metal oxide is preferably an oxygen-deficient tantalum oxide.
- the resistance change layer 104 includes a second tantalum oxide layer having a composition represented by TaO x (where 0 ⁇ x ⁇ 2.5) as the second resistance change layer 104b,
- the first variable resistance layer 104a has at least a stacked structure in which a first tantalum oxide layer having a composition represented by TaO y (where x ⁇ y) is stacked. It goes without saying that other layers such as a third tantalum-containing layer and other transition metal oxide layers can be appropriately disposed.
- TaO x preferably satisfies 0.8 ⁇ x ⁇ 1.9
- TaO y preferably satisfies 2.1 ⁇ y.
- the thickness of the first tantalum oxide layer is preferably 1 nm or more and 8 nm or less. That is, the resistance change layer 104 preferably has a stacked structure in which a second tantalum oxide layer having a low oxygen content and a first tantalum oxide layer having a high oxygen content are stacked. In other words, the resistance change layer 104 includes the second tantalum oxide layer 104b having a high oxygen deficiency as the second resistance change layer 104b and the first oxygen deficiency as the first resistance change layer 104a.
- the degree of oxygen deficiency refers to the proportion of oxygen that is deficient with respect to the amount of oxygen constituting the oxide of the stoichiometric composition in the transition metal oxide.
- the transition metal is tantalum (Ta)
- the stoichiometric oxide composition is Ta 2 O 5 and can be expressed as TaO 2.5. Therefore, the oxygen deficiency of TaO 2.5 is 0%.
- the oxygen content of Ta 2 O 5 is the ratio of oxygen to the total number of atoms (O / (Ta + O)), which is 71.4 atm%. Therefore, the oxygen-deficient tantalum oxide has an oxygen content greater than 0 and less than 71.4 atm%.
- a transition metal other than tantalum may be used as the metal constituting the resistance change layer 104.
- the transition metal tantalum (Ta), titanium (Ti), hafnium (Hf), zirconium (Zr), niobium (Nb), tungsten (W), or the like can be used. Since transition metals can take a plurality of oxidation states, different resistance states can be realized by oxidation-reduction reactions.
- the composition of the second hafnium oxide layer as the second variable resistance layer 104b is HfO x
- x is 0.9 or more and 1.6 or less
- the first When the composition of the first hafnium oxide layer as the first resistance change layer 104a is HfO y and y is larger than the value of x, the first hafnium oxide layer and the second hafnium oxide It has been confirmed that the resistance value of the variable resistance layer 104 having a stacked structure of oxide layers can be stably changed at high speed.
- the thickness of the first hafnium oxide layer is preferably 3 nm or more and 4 nm or less.
- the thickness of the first zirconium oxide layer is preferably 1 nm or more and 5 nm or less.
- a hafnium oxide is formed on the first electrode 101c by a so-called reactive sputtering method in which an Hf target is used and sputtering is performed in argon gas and oxygen gas.
- the first hafnium oxide layer is formed by exposing the surface of the hafnium oxide layer to plasma of argon gas and oxygen gas.
- the second hafnium oxide layer is formed again on the first hafnium oxide layer by the reactive sputtering method described above.
- the oxygen content of the first hafnium oxide layer can be easily adjusted by changing the flow rate ratio of oxygen gas to argon gas during reactive sputtering, as in the case of the tantalum oxide layer described above.
- the substrate temperature can be set to room temperature without any particular heating.
- the film thickness of the first hafnium oxide layer can be easily adjusted by the hafnium oxide film thickness formed by reactive sputtering and the exposure time to the plasma of argon gas and oxygen gas.
- a first zirconium oxide layer is formed by exposing the surface of the zirconium oxide layer to a plasma of argon gas and oxygen gas.
- the second zirconium oxide layer is formed again on the first zirconium oxide layer by the reactive sputtering method described above.
- the oxygen content of the first zirconium oxide layer can be easily adjusted by changing the flow ratio of oxygen gas to argon gas during reactive sputtering.
- the substrate temperature can be set to room temperature without any particular heating.
- the film thickness of the first zirconium oxide layer can be easily adjusted by the zirconium oxide film thickness formed by reactive sputtering and the exposure time to the plasma of argon gas and oxygen gas.
- variable resistance layer 104 has a stacked structure of a first transition metal oxide layer as the first variable resistance layer 104a and a second transition metal oxide layer as the second variable resistance layer 104b
- Different transition metals may be used for the first transition metal constituting the first transition metal oxide layer and the second transition metal constituting the second transition metal oxide layer.
- the first transition metal oxide layer has a lower oxygen deficiency than the second transition metal oxide layer, that is, has a higher resistance.
- a voltage applied between the first electrode 101c and the other electrode constituting the resistance change element is more voltage applied to the first transition metal oxide layer. Can be distributed to facilitate the redox reaction that occurs in the first transition metal oxide layer.
- the standard electrode potential of the first transition metal is preferably lower than the standard electrode potential of the second transition metal. This is because the resistance change phenomenon is considered to occur due to an oxidation-reduction reaction that occurs in a small filament (conductive path) formed in the first transition metal oxide layer having a high resistance, and the resistance value changes. .
- the resistance change phenomenon is considered to occur due to an oxidation-reduction reaction that occurs in a small filament (conductive path) formed in the first transition metal oxide layer having a high resistance, and the resistance value changes.
- oxygen-deficient tantalum oxide for the second transition metal oxide layer and titanium oxide (TiO 2 ) for the first transition metal oxide layer stable resistance change operation can be obtained. It is done.
- the standard electrode potential represents a characteristic that the higher the value, the less likely it is to oxidize.
- the resistance change phenomenon in the resistance change layer 104 having the laminated structure of each material described above is caused by an oxidation-reduction reaction occurring in a minute filament formed in the first transition metal oxide layer having a high resistance.
- the value changes and is thought to occur. That is, when a positive voltage is applied to the electrode on the first transition metal oxide layer side with respect to the electrode on the other side, oxygen ions in the resistance change layer 104 are changed to the first transition metal oxide layer side. It is considered that the resistance of the microfilament is increased due to the occurrence of an oxidation reaction in the microfilament formed in the first transition metal oxide layer.
- the electrodes connected to the first transition metal oxide layer having a smaller oxygen deficiency are, for example, platinum (Pt), iridium (Ir), etc., the transition metal constituting the first transition metal oxide layer, and the other It is made of a material having a higher standard electrode potential than that of the material constituting the electrode on the side. With such a configuration, a redox reaction occurs selectively in the first transition metal oxide layer in the vicinity of the interface between the electrode and the first transition metal oxide layer, and a stable resistance change phenomenon occurs. can get.
- a resistance change layer (the first resistance change layer 104a and the second resistance change layer 104b) is formed, and the inside of the memory cell hole 103 is formed.
- a variable resistance layer is deposited on the entire wafer surface. Thereafter, an unnecessary variable resistance layer outside the memory cell hole 103 is removed by CMP to complete patterning of the variable resistance layer. Therefore, since the etching process is not required for forming the resistance change layer, the resistance change layer is formed by avoiding the etching in which the reaction with the etching gas, the oxygen reduction damage, and the damage due to the charge are concerned in principle. Can be formed.
- an interlayer insulating layer 112 is further deposited on the entire planarized wafer, and then an opening for electrical connection with the first wiring 101a, that is, a contact hole 106 is formed. Then, the interlayer insulating layers 102 and 112 are patterned with a desired photomask. In the patterning, the first wiring 101a is not exposed, and the etching is stopped when the liner film 115 is exposed. Then, the surface of the first wiring 101a can be prevented from being oxidized or corroded.
- FIG. 3A shows a process of forming a wiring groove 108a penetrating the interlayer insulating layer 112 and connected to the contact hole 106 and the resistance change element.
- a desired photomask for forming a wiring trench 108a in which the second wiring (leading wiring) 108 and the like are embedded is formed on the interlayer insulating layer 112, and the interlayer insulation is formed using this photomask.
- Layer 112 is patterned. Note that a resist may be embedded in the contact hole 106 before the wiring trench 108a is formed.
- the liner film 115 at the bottom of the contact hole 106 can be surely protected and the first wiring 101a can be prevented from being exposed.
- the liner film 115 at the bottom of the contact hole 106 is opened.
- the wiring trench 108a exposes the first variable resistance layer 104a and the second variable resistance layer 104b (also used as the lower electrode of the MSM diode element) above the memory cell hole 103. It is formed.
- the end of the opening of the wiring groove 108a (the opening formed on the side surface in the interlayer insulating layer 112 constituting the wiring groove 108a) and the opening of the contact hole 106 (interlayer of the contact hole 106).
- the positional relationship with the opening 106a on the surface of the insulating layer 102 is important in the process of forming a current control layer of the MSM diode element described later.
- FIG. 5A and 5B are diagrams for explaining in detail the positional relationship between the end of the opening of the wiring groove 108a and the opening 106a of the contact hole 106.
- FIG. FIG. 5A is a cross-sectional view of the variable resistance nonvolatile memory device according to the present embodiment
- FIG. 5B is a cross-sectional view in which a part of the nonvolatile memory device is enlarged (the X portion in FIG. 5A is enlarged). .
- the contact hole 106 is formed on the memory cell hole 103 closest to the end of one side of the opening of the wiring groove 108a (the side close to the contact hole 106) and one side of the opening of the wiring groove 108a in the arrangement direction of the memory cell holes 103. Located between the ends.
- the size (opening diameter) of the opening 106a of the contact hole 106 in a direction parallel to the main surface of the substrate 100 and parallel to the alignment direction is a.
- one side of the opening 106a of the contact hole 106 on the right side in FIG. 5B, that is, one side of the opening of the wiring groove 108a in the direction parallel to the main surface of the substrate 100 and parallel to the alignment direction (see FIG. In 5B, the distance from the end (opening edge) far from the end on the left side of the drawing to the end on one side of the opening of the wiring groove 108a is b.
- the height of the contact hole 106 that is, the height from the exposed surface of the first wiring 101a to the surface of the interlayer insulating layer 102 is defined as c.
- the height of the wiring groove 108a that is, the height from the surface of the interlayer insulating layer 102 to the surface of the interlayer insulating layer 112 is defined as d.
- the opening of the memory cell hole 103 closest to the end of one side of the wiring groove 108a from the end of one side of the opening of the wiring groove 108a in the direction parallel to the main surface of the substrate 100 and parallel to the arrangement direction ( One end side of the opening of the wiring groove 108a (the opening on the surface of the uppermost interlayer insulating layer 102 of the memory cell hole 103) (left side as viewed in FIG. 5B), that is, a contact in which the memory cell hole 103 is not provided.
- e be the distance to the end (opening edge) on the hole 106 side.
- the end on one side of the opening 106a that determines the opening diameter a is the end of the opening 106a far from the end on one side of the opening of the wiring groove 108a (on the right side in FIG. 5B). Further, the other end of the opening 106a that determines the opening diameter a is the end of the opening 106a that is close to the one end of the wiring groove 108a (on the left side in FIG. 5B).
- a distance in a direction parallel to the main surface of the substrate 100 at these two ends and parallel to the alignment direction is defined as a.
- a, b, and e are values measured in the same cross section in the same direction with respect to the contact holes 106 and all the memory cell holes 103 arranged in the arrangement direction and the wiring grooves 108a including the openings.
- ⁇ tan ⁇ 1 (c / a)
- All contact holes 106, all memory cell holes 103, and wiring trenches 108 a for making ohmic contact with the first wiring 101 a are memory cells in a later step.
- the hole 103 is formed so as to satisfy the conditions of ⁇ > ⁇ and ⁇ > ⁇ so that the opening of the hole 103 is covered with the current control layer 111 and the bottom surface of the contact hole 106 is not covered with the current control layer 111.
- the contact hole 106 is first formed on the flat interlayer insulating layer 112 by photolithography, so that the focus margin is increased and the contact hole 106 is formed. Fine and uniform dimensional control can be performed. On the other hand, in the above-described prior example, the focus margin is reduced by 100 nm or more and 300 nm or less corresponding to the depth of the wiring groove. Further, the upper portion of the memory cell hole 103 can be opened while preventing the first wiring 101a at the bottom of the contact hole 106 from being exposed to the end.
- the current control layer 111 as a current control layer of the MSM diode element which is a current control element will be described.
- a nitrogen-deficient type is used as a material for the current control layer 111 on the entire surface including the side surface of the contact hole 106 and the inner surface of the wiring groove 108a where the first variable resistance layer 104a and the second variable resistance layer 104b are exposed.
- a silicon nitride film (SiN x film) is deposited.
- the nitrogen-deficient silicon nitride film was formed by so-called reactive sputtering, in which a silicon target was sputtered in an argon and nitrogen gas atmosphere.
- the nitrogen content is 25 atm% or more and 40 atm% or less.
- FIGS. 6A and 6B are views for explaining the positional relationship between the material molecule flying direction during sputtering and the end of the wiring groove 108a and the contact hole opening 106a.
- 6A is a plan view parallel to the surface (wafer surface) of the variable resistance nonvolatile memory device according to the present embodiment
- FIG. 6B is parallel to the BB ′ direction of FIG. FIG.
- the flying direction of the material molecules at the time of sputtering is as shown in FIG. A direction (in a direction parallel to the extending direction of the second wiring 108) in a parallel direction and a direction from the end of the wiring groove 108a closer to the contact hole 106 to the end of the wiring groove 108a farther in the arrangement direction ( In FIG. 6A, it is the direction from the left side to the right side).
- a, b, c, d, and e in FIG. 5B are values in a cross section that is parallel to the B-B ′ direction in FIG. 6A and perpendicular to the main surface of the substrate 100.
- the flying direction of the material molecules during sputtering when viewed from a direction parallel to the surface of the substrate 100 (when the cross section of the substrate 100 is viewed from the side) is as shown in FIG. 6B.
- a direction having an angle ⁇ , and a, b, and e are parallel to the measured cross-sectional direction.
- the material molecules are deposited in a state where the substrate 100 is inclined by ⁇ in the vertical direction along the BB ′ direction with respect to the direction of the material molecules flying at the time of sputtering.
- Such a forming method can be realized.
- the current control layer 111 of the MSM diode element is not formed in those regions. Conversely, the current control layer 111 of the MSM diode element is formed in other regions.
- the end of one side of the wiring groove 108a that determines the distance e in FIG. 5B is positioned in front of the flying direction of the material molecules at the time of sputtering. It becomes the end of the wiring groove 108a to be used. Furthermore, the end on one side of the opening of the memory cell hole 103 closest to the one end is the other end that determines the distance e.
- the material molecules at the time of sputtering cannot reach the entire bottom surface of the contact hole 106 because the interlayer insulating layer 102 is shaded.
- ⁇ ⁇ ⁇ a memory cell hole 103 that does not reach the material molecules at the time of sputtering is generated. That is, by satisfying the condition that ⁇ , ⁇ , and ⁇ satisfy ⁇ ⁇ ⁇ , all the openings are exposed without forming the current control layer 111 of the MSM diode element on the bottom surface of the contact hole 106.
- the current control layer 111 of the MSM diode element is formed on the bottom surface of the wiring groove 108a including the upper portion of the memory cell hole 103, that is, in a region other than the shadowed region when viewed from the direction of material molecule flight during sputtering of the wiring groove 108a. It becomes possible to do.
- the material molecule flying direction of the contact hole 106 does not form the current control layer 111 of the MSM diode element on the bottom surface of the contact hole 106.
- the bottom of the wiring groove 108a including the upper part of all the memory cell holes 103 where the openings are exposed that is, a region that becomes a shadow when viewed from the direction in which the material molecules fly during sputtering. It becomes possible to form the current control layer 111 of the MSM diode element in a region other than (FIG. 8, FIG. 3B).
- FIG. 3C and FIGS. 4A to 4B show a process of forming the second wiring 108 and the barrier film 109a.
- the barrier film 109a and the wiring are formed on the entire surface including the first wiring 101a exposed at the bottom of the contact hole 106 and the current control layer 111 on the inner surface of the wiring groove 108a and the surface of the interlayer insulating layer 112.
- the material copper is sequentially deposited using a sputtering method or the like.
- the barrier film 109a improves the adhesion between the interlayer insulating layer 102 formed of a silicon oxide film or the like and the second wiring 108 formed of copper, and the copper of the second wiring 108 is formed in the interlayer insulating layer 102. It is a film
- Planarization is performed (FIG. 4A).
- the barrier film 109a other than in the wiring trench 108a and the current control layer 111 therebelow are also removed at the same time, thereby preventing leakage current between the second wirings 108 in different wiring trenches 108a.
- a SiN film is deposited to a thickness of about 30 nm to 200 nm on the flat surfaces of the interlayer insulating layer 112 and the second wiring 108 by using, for example, a plasma CVD method, and the liner that covers the copper that is the second wiring 108 is covered.
- a film 116 is formed (FIG. 4B).
- the second wiring 108 and the barrier film 109a formed in the contact hole 106 serve as contact plugs.
- the barrier film 109a serving as the upper electrode of the MSM diode element and the second wiring 108 made of the wiring material are formed in the contact hole 106 and the wiring groove 108a.
- the second wiring 108 used for the wiring connecting the contact hole 106 and the memory cell hole 103 in the cross point array and the wiring connecting the memory cell hole 103 is described.
- the second wiring 108 in the same layer as the second wiring 108 is also used as a wiring for forming a peripheral circuit for driving the cross point array.
- the current control layer 111 of the MSM diode element is formed on the bottom surface of the contact hole 106 of the peripheral circuit. It can be prevented from being formed.
- the second resistance change layer 104b is a tantalum oxide exhibiting conductivity, it can also be used as the metal of the lower electrode of the MSM diode element.
- the current control layer 111 of the MSM diode element can be used as the upper electrode of the resistance change element including the first electrode 101c and the resistance change layer 104, and has a structure in which the intermediate electrode is omitted (resistance change layer A structure in which the resistance change element and the current control element are configured by four layers of the lower electrode, the resistance change layer, the current control layer, and the upper electrode.
- an intermediate electrode may be separately formed between the resistance change layer 104 and the current control layer 111.
- the intermediate electrode is preferably arranged separately between the resistance change elements from the viewpoint of preventing crosstalk with adjacent memory cells.
- the upper surfaces of the first variable resistance layer 104a and the second variable resistance layer 104b embedded in the memory cell hole 103 are formed on the substrate 100 side by using an etch back method, CMP overpolishing, or the like.
- the recess region is formed in the upper portion of the memory cell hole 103 and an intermediate electrode material (for example, TaN) is formed, and the excess intermediate electrode material is polished and removed by CMP to form the upper portion of the memory cell hole 103.
- the intermediate electrode 160 can be formed so as to remain only in the recess region.
- the nonvolatile memory device is, for example, a multi-layer cross-point array in which a second-layer memory cell hole 103 is formed above the second wiring 108 and a third wiring is formed thereon. Also good. In this case, since the extending direction of the third wiring is substantially perpendicular to the extending direction of the second wiring 108, the second-layer contact hole 106 formed between the second wiring 108 and the third wiring.
- the direction of the cross section for determining a, b, c, and d for the memory cell hole 103 and the wiring groove 108a and the flying direction of the material molecules when sputtering the current control layer of the MSM diode element are the extending direction of the third wiring Accordingly, the direction is substantially perpendicular to the extending direction of the second wiring.
- the cross-sectional direction determining a, b, c, and d for the third-layer contact hole 106, the memory cell hole 103, and the wiring groove 108a and the current control of the MSM diode element The flying direction of the material molecules when the layer is sputtered is substantially perpendicular to the extending direction of the third wiring.
- the direction in which the material molecules fly during sputtering is as shown in FIG. 6A and FIG. 6B on the side far from the end of the wiring groove 108a near the contact hole 106 in the direction in which the contact holes 106 are arranged. It is assumed that the direction is toward the end of the wiring groove 108a (in FIG. 6A, the direction is from the left side toward the right side in FIG. 6A). However, if the condition of ⁇ ⁇ ⁇ is satisfied, the flying direction of the material molecules at the time of sputtering is opposite to the flying direction of FIG. 6A, that is, the arrangement direction of the contact holes 106, as shown in FIGS. 10A and 10B. In FIG.
- the direction from the end of the wiring groove 108a far from the contact hole 106 to the end of the wiring groove 108a closer to the contact hole 106 may be used. In this case, it is not always necessary to satisfy the condition of ⁇ > ⁇ .
- the current control layer 111 of the MSM diode element is not formed on the bottom surface of the contact hole 106, and the opening of the memory cell hole 103 is covered with the wiring groove 108a.
- the current control layer 111 of the MSM diode element can be formed. Therefore, it is possible to form an MSM diode element in the wiring groove 108 a over the memory cell hole 103 while keeping the contact resistance between the first wiring 101 a and the contact plug low. As a result, a variable resistance nonvolatile memory device capable of high capacity and high integration by miniaturization can be provided.
- a bidirectional diode is selectively formed on the bottom surface of the contact hole 106 without using a removal step such as etching.
- the current control layer 111 of the element can be prevented from being formed. This is a combination of a device with a planar layout of the second wiring 108 and the contact hole 106 and a film forming method that limits the flying angle of material molecules when forming the current control layer 111 of the bidirectional diode element. It is realized by.
- the contact resistance between the first wiring 101 a and the contact plug can be made ohmic and low resistance, and at the same time, a bidirectional diode can be formed in the wiring groove 108 a above the memory cell hole 103.
- a variable resistance nonvolatile memory device capable of high capacity and high integration by miniaturization can be provided.
- the wiring groove 108a is formed after the contact hole is formed first, and a focus margin is ensured in the lithography process for forming the contact hole 106 (preceding that the lithography process for the contact hole is performed on the step of the wiring groove 108a).
- the focus margin is 100 to 300 nm, which is equivalent to the depth of the wiring trench, and the contact hole 106 with fine dimensions can be formed with high precision in the wafer surface. As a result, it is possible to provide a variable resistance nonvolatile memory device having good consistency with a dual damascene process suitable for forming a fine copper wiring.
- FIG. 11A and 11B are cross-sectional views illustrating a configuration example of a variable resistance nonvolatile memory device according to the second embodiment of the present invention.
- FIG. 12 is a plan view showing a configuration example of the variable resistance nonvolatile memory device according to the embodiment. 12A corresponds to FIG. 11A, and the cross-section of the alternate long and short dash line indicated by 1B in FIG. 12 is viewed in the direction of the arrow. The cross-sectional view corresponds to FIG. 11B.
- this non-volatile memory device (cross point memory) is almost the same as FIGS. 25A and 25B showing the cross-sectional views of the preceding example and FIG. 26 showing the plan view, and in FIGS. 11A, 11B and 12, FIG. Members having substantially the same function as the members used in FIGS. 25B and 26 are denoted by the same symbols.
- the difference between the preceding example and this embodiment is that the first electrode 101 of the preceding example is provided as the first electrode 101c on the first wiring 101a in this embodiment.
- the second electrode 105 is provided as a lower electrode of the MSM diode element separately from the second variable resistance layer 104b.
- the second variable resistance layer 104b includes the MSM diode element. This is a structure in which the lower electrode is also used.
- liner films 115 and 116 are provided for protecting wiring by preventing copper oxidation and the like.
- a first wiring 101a composed of a plurality of cross point array wirings formed in a stripe shape in parallel with each other and wirings used to connect the wirings to peripheral circuits
- a plurality of cross point array wirings formed in a stripe shape in parallel with each other and a second wiring 108 composed of wirings used to connect the cross point array wirings to peripheral circuits are formed.
- a memory cell hole 103 is formed at a position where the cross point array wiring of the first wiring 101a and the cross point array wiring of the second wiring 108 intersect.
- a plurality of wiring grooves 108a are formed, and the extending directions of the plurality of wiring grooves 108a are unified in the same direction.
- FIG. 13A (a) to 13 (d), FIG. 13B (a) to (b), FIG. 14 (a) to (c), and FIG. 15 (a) to (c) are resistance variable nonvolatiles in this embodiment. It is sectional drawing which shows the main processes of the manufacturing method of a memory
- FIG. 13A (a) shows a process of forming the first wiring 101a and the interlayer insulating layers 102 and 114.
- FIG. 13A (a) shows a process of forming the first wiring 101a and the interlayer insulating layers 102 and 114.
- a silicon oxide film for example, a plasma TEOS film or an FSG film containing fluorine
- An interlayer insulating layer 114 is formed.
- a wiring trench in which the first wiring 101a is embedded in the interlayer insulating layer 114 is formed by photolithography and dry etching.
- a barrier film 101b composed of TaN (film thickness: 5 nm to 40 nm) and Ta (film thickness: 5 nm to 40 nm) and copper as a wiring material (film thickness: 50 nm to 300 nm) are formed in the formed wiring trench. And the like are sequentially deposited using a sputtering method and the like, and copper is further deposited by electrolytic plating using the deposited copper as a seed, thereby filling all the wiring grooves with copper as a wiring material.
- a first wiring 101a having a stripe shape is formed. Further, planarization is performed while removing excess copper on the surface by CMP so that the surfaces of the interlayer insulating layer 114 and the first wiring 101a are flat (flat).
- a SiN film is deposited to a thickness of about 30 nm to 200 nm by using, for example, a plasma CVD method, and a liner film 115 is formed so as to cover the copper that is the first wiring 101a.
- an interlayer insulating layer 102 as a first interlayer insulating layer is further deposited on the liner film 115 (the plurality of first wirings 101a), and if necessary, the step difference on the surface of the interlayer insulating layer 102 is reduced by CMP. .
- FIG. 13A (b) shows a process of forming the memory cell hole 103 that penetrates the interlayer insulating layer 102 and is connected to the first wiring 101a.
- an opening i.e., a memory cell hole 103
- a first electrode 101c made of a noble metal or the like is selectively formed only on copper, which is the first wiring 101a at the bottom of the memory cell hole 103, by electroless plating or the like.
- electroless plating or the like. For example, Pt, Ir, Pd, etc.
- a plating underlayer containing Ni or the like may be grown between copper and a noble metal. In that case, the electroless plating can be controlled more easily than in the case where the base of the first electrode 101c is copper.
- a tantalum target is sputtered in an argon and oxygen gas atmosphere, so-called reactive sputtering on the first electrode 101c at the bottom of the memory cell hole 103, on the sidewall of the memory cell hole 103, and on the surface of the interlayer insulating layer 102.
- a first resistance change layer 104a made of tantalum oxide or the like is formed.
- the oxygen content of the formed film can be increased.
- the first variable resistance layer 104a having an oxygen content of about 71 atm% was formed under the conditions of argon 34 sccm, oxygen 24 sccm, and power 1.6 kW.
- oxygen is contained in the memory cell hole 103 having the first variable resistance layer 104a formed on the surface thereof, that is, on the first variable resistance layer 104a in the memory cell hole 103 from the first variable resistance layer 104a.
- the tantalum oxide of the second variable resistance layer 104b having a low rate is formed.
- This formation is performed by reactive sputtering in the same manner as the formation of the first variable resistance layer 104a.
- the second variable resistance layer 104b having an oxygen content of about 60 atm% was formed under the conditions of argon 34 sccm, oxygen 20.5 sccm, and power 1.6 kW.
- a tantalum oxide film is formed by sputtering until the inside of the memory cell hole 103 is completely filled, and then unnecessary tantalum oxide on the surface of the interlayer insulating layer 102 is formed by CMP.
- the first variable resistance layer 104 a and the second variable resistance layer 104 b are formed only in the memory cell hole 103. As a result, the variable resistance element is embedded in the memory cell hole 103.
- a resistance change layer (the first resistance change layer 104a and the second resistance change layer 104b) is formed, and the inside of the memory cell hole 103 is formed.
- a variable resistance layer is deposited on the entire wafer surface. Thereafter, an unnecessary variable resistance layer outside the memory cell hole 103 is removed by CMP to complete patterning of the variable resistance layer. Therefore, since the etching process is not required for forming the resistance change layer, the resistance change layer is formed by avoiding the etching in which the reaction with the etching gas, the oxygen reduction damage, and the damage due to the charge are concerned in principle. Can be formed.
- the second resistance change layer 104b is a tantalum oxide exhibiting conductivity, it can also be used as the metal of the lower electrode of the MSM diode element.
- FIG. 13A (c) shows a step of forming the hard mask layer 120 and the photoresist layer 130 after forming the interlayer insulating layer 112 as the second interlayer insulating layer on the surface of the interlayer insulating layer 102.
- FIG. 13A (d) shows a step of forming a hard mask pattern 120 ′ for forming a wiring groove.
- FIG. 13B (a) shows a step of forming a contact hole 106 penetrating the interlayer insulating layers 102 and 112 and connected to the first wiring 101a.
- FIG. 13B (b) shows a step of filling the formed contact hole 106 with a resist material.
- an interlayer insulating layer 112 is further deposited on the entire planarized wafer, and then a hard mask layer (for example, Ti having a high etching selectivity with respect to the interlayer insulating layer 112) is formed. And a photoresist layer 130 are deposited over the entire surface.
- the film thickness of the hard mask layer 120 is set to be thin, for example, 30 nm or less so as to increase the focus margin.
- a photoresist pattern for patterning the wiring groove 108a is formed, and the hard mask layer 120 is etched using this photoresist pattern, thereby forming a hard mask 120 ′ as shown in FIG. 13A (d).
- the photoresist pattern used to form the hard mask 120 ' is removed by ashing.
- a photoresist pattern 131 is newly formed to form an opening for electrical connection with the first wiring 101a, that is, a contact hole 106.
- the interlayer insulating layers 102 and 112 are patterned. In this patterning, etching that penetrates the liner film 115 and exposes the first wiring 101a is performed.
- FIG. 13B (b) shows a process of embedding the resist 117c in the contact hole 106.
- a resist 117 c is applied in the contact hole 106 and on the surface of the interlayer insulating layer 112, and the entire surface is etched back by ashing using oxygen gas or the like to form the resist 117 c in the contact hole 106.
- the resist 117 c is embedded in the contact hole 106 so that the surface of the resist 117 c is lower than the surface of the interlayer insulating layer 112.
- FIG. 14A shows a process of forming a wiring groove 108a that penetrates the interlayer insulating layer 112 and is connected to the contact hole 106 and the resistance change element.
- the interlayer insulating layer 112 is dry-etched using the patterned hard mask 120 'to form the wiring trench 108a.
- the first wiring 101a at the bottom of the contact hole 106 is protected by the already embedded resist 117c and is not dry-etched.
- the interlayer insulating layer 112 is dry-etched above the memory cell hole 103, and the first resistance change layer 104a and the second resistance change layer 104b are exposed at the bottom of the formed wiring trench 108a.
- the resist 117c is preferably formed to protrude in a convex shape from the bottom surface of the wiring groove 108a including the contact hole 106 (the surface of the interlayer insulating layer 102 in the wiring groove 108a).
- the distance between the bottom surface of the wiring groove 108a including the contact hole 106 and the top surface of the convex resist 117c is preferably larger than the film thickness of the current control layer 111 formed later, for example, 10 nm to 20 nm.
- dry etching using a halogen-based gas such as chlorine or hydrogen bromide is performed to remove the hard mask 120 ′, whereby the hard mask 120 ′ can be completely removed while suppressing the resist receding amount. .
- the photoresist pattern 131 for forming the contact hole 106 has the interlayer insulating layer 112. And formed on the hard mask 120 '. Since the film thickness of the hard mask 120 ′ is 30 nm or less, there is almost no deterioration of the focus margin in the photolithography process for forming the photoresist pattern 131, and the photolithography process is performed on the flat interlayer insulating layer 112. The focus margin can be increased to the same extent, and fine and uniform dimension control of the contact hole 106 can be performed. Further, the wiring trench 108a opening above the memory cell hole 103 can be formed while preventing the first wiring 101a at the bottom of the contact hole 106 from being exposed by the resist 117c.
- current control layers 111 and 111a as current control layers of the MSM diode element are formed on the interlayer insulating layers 102 and 112 so as to cover the exposed surface of the resist 117c and the inner surface of the wiring groove 108a shown in FIG.
- the process to form is shown.
- current control layers 111 and 111a of a diode element composed of a nitrogen-deficient silicon nitride film are formed.
- the current control layer on the upper surface of the resist 117c formed in a convex shape with respect to the surface of the interlayer insulating layer 102 is referred to as a current control layer 111a.
- the nitrogen-deficient silicon nitride film was formed by so-called reactive sputtering, in which a silicon target was sputtered in an argon and nitrogen gas atmosphere.
- the nitrogen content is 25 atm% or more and 40 atm% or less.
- the angle 119 with respect to the flying direction of material molecules at the time of sputtering that is, the surface of the interlayer insulating layer 112 of sputtering (surface of the substrate 100). Is adjusted vertically.
- the current control layer 111a is formed on the convex side wall of the resist 117c thinner than the current control layer 111a on the convex upper surface of the resist 117c.
- the angle 119 is adjusted obliquely, and the current control layer 111 is not formed on the sidewall of the convex resist 117c.
- the current control layer 111 may be formed by sputtering in which material molecules fly from a direction oblique to the surface of the interlayer insulating layer 112 (the surface of the substrate 100). In this case, the sputtered material molecules cannot reach the side wall of the resist 117c shadowed (shadowed) by the interlayer insulating layer 112, and the region where the current control layer 111a is not formed is formed on the convex side wall of the resist 117c.
- the resist 117c in FIG. 14A when the resist 117c is formed so that the upper surface thereof is flush with the interlayer insulating layer 102 at the bottom of the wiring groove 108a, as shown in FIG.
- the surfaces of the current control layer 111 on the interlayer insulating layer 102 at the bottom of the wiring trench 108a and the current control layer 111a on the resist 117c are flat (level).
- FIG. 14C shows a step of lifting off the current control layer 111a on the resist 117c embedded in the contact hole 106 by removing the resist 117c.
- the resist 117c embedded in the contact hole 106 is removed by ashing using oxygen gas, and the current control layer 111a formed on the resist 117c together with the resist 117c is lifted off simultaneously.
- the first wiring 101a is not exposed and the liner is not exposed. Etching may be stopped when the film 115 is exposed. In this case, in the step of FIG. 14C, etching is performed so as to penetrate the liner film 115 and expose the first wiring 101a.
- the interlayer insulating layers 102 and 112 and the resistance change layer are formed so as to cover the inner surface of the wiring groove 108a and not cover the bottom surface of the contact hole 106.
- a current control layer 111 as a current control layer of the MSM diode element is formed on 104.
- FIGS. 15A to 15C show a process of forming the barrier film 109a and the second wiring 108.
- FIG. In this step, first, the barrier film 109a and the wiring are formed on the entire surface including the first wiring 101a exposed at the bottom of the contact hole 106 and the current control layer 111 on the inner surface of the wiring groove 108a and the surface of the interlayer insulating layer 112. Copper, which is the seed material of the layer, is sequentially deposited using a sputtering method or the like.
- the sputtering direction in this case is preferably performed under the condition of approximately 90 ° with respect to the surface of the substrate 100 because the material molecules need to reach the bottom surface of the contact hole 106.
- the contact hole 106 and the wiring groove 108a are entirely filled with the second wiring 108 made of copper as a wiring material (FIG. 15 ( a)).
- the surface of the interlayer insulating layer 112 and the second wiring 108 is flattened (with the same surface), while removing excess copper on the surface of the interlayer insulating layer 112 and the second wiring 108 by CMP. (FIG. 15B).
- the barrier film 109a other than in the wiring trench 108a and the current control layer 111 therebelow are also removed at the same time, thereby preventing leakage current between the second wirings 108 in different wiring trenches 108a.
- a SiN film is deposited to a thickness of about 30 nm to 200 nm on the flat surfaces of the interlayer insulating layer 112 and the second wiring 108 by using, for example, a plasma CVD method, and the liner that covers the copper that is the second wiring 108 is covered.
- a film 116 is formed (FIG. 15C).
- the second wiring 108 and the barrier film 109a formed in the contact hole 106 serve as contact plugs.
- 15A to 15C in the contact hole 106 and the wiring groove 108a, the lower layer that becomes the upper electrode of the MSM diode element and the upper layer that is made of the wiring material are formed.
- the second wiring 108 By forming the second wiring 108, the MSM diode element connected to the variable resistance element and the contact plug of the contact hole 106 are formed simultaneously.
- the current control layer 111 of the MSM diode element is formed in the wiring groove 108 a above the memory cell hole 103 without forming the current control layer 111 of the MSM diode element at the bottom of the contact hole 106. Can be formed. Therefore, it is possible to form an MSM diode element in the wiring groove 108 a above the memory cell hole 103 while keeping the contact resistance between the first wiring 101 a and the contact plug low. As a result, a variable resistance nonvolatile memory device capable of high capacity and high integration by miniaturization can be provided.
- a bidirectional diode is selectively formed on the bottom surface of the contact hole 106 without using a removal step such as etching.
- the current control layer 111 of the element can be prevented from being formed. This is realized by embedding a resist in the contact hole 106 in advance when the current control layer of the bidirectional diode element is formed.
- the contact resistance between the first wiring 101 a and the contact plug can be made ohmic and low resistance, and at the same time, a bidirectional diode can be formed in the wiring groove 108 a above the memory cell hole 103.
- a variable resistance nonvolatile memory device capable of high capacity and high integration by miniaturization can be provided.
- the wiring groove 108a is formed after the contact hole 106 is formed first, a focus margin is ensured in the lithography process for forming the contact hole 106, and the contact hole 106 having a fine dimension is formed accurately in the wafer surface. can do. As a result, it is possible to provide a variable resistance nonvolatile memory device having good consistency with a dual damascene process suitable for forming a fine copper wiring.
- FIG. 19A and FIG. 19B are cross-sectional views showing a configuration example of a variable resistance nonvolatile memory device according to an embodiment of the present invention.
- FIG. 20 is a plan view showing a configuration example of the variable resistance nonvolatile memory device according to the embodiment. Note that a cross-sectional view taken along the dashed-dotted line indicated by 1A-1A in FIG. 20 in the direction of the arrow corresponds to FIG. 19A, and a cross-sectional view indicated by the dashed-dotted line indicated by 1B-1B in FIG. A cross-sectional view seen in the direction of the arrow corresponds to FIG. 19B.
- this nonvolatile memory device (cross-point memory) is almost the same as FIGS. 25A and 25B showing the cross-sectional views of the preceding example and FIG. 26 showing the plan view, and in FIGS. 19A, 19B and 20, FIG. Members having substantially the same function as the members used in FIGS. 25B and 26 are denoted by the same symbols.
- the difference between the preceding example and this embodiment is that the first electrode 101 of the preceding example is provided as the first electrode 101c on the first wiring 101a in this embodiment.
- the second electrode 105 is provided as a lower electrode of the MSM diode element separately from the second variable resistance layer 104b.
- the second variable resistance layer 104b includes the MSM diode element. This is a structure in which the lower electrode is also used.
- liner films 115 and 116 are provided for protecting wiring by preventing copper oxidation and the like.
- a first wiring 101a composed of a plurality of cross-point array wirings formed in a stripe shape in parallel with each other and wirings used to connect the wirings to peripheral circuits
- a plurality of cross-point array wirings formed in a stripe shape in parallel with each other and second wirings (drawing wirings) 108 formed from wirings used to connect the wirings to peripheral circuits are formed.
- a memory cell hole 103 is formed at a position where the cross point array wiring of the first wiring 101a and the cross point array wiring of the second wiring 108 intersect.
- a plurality of wiring grooves 108a are formed, and the extending directions of the plurality of wiring grooves 108a are unified in the same direction.
- FIG. 21A to FIG. 21D, FIG. 22A to FIG. 22D, and FIG. 23A to FIG. 23C show the variable resistance nonvolatile memory device of this embodiment. It is sectional drawing which shows the main processes of a manufacturing method. The manufacturing method is demonstrated using these.
- FIG. 21A shows a process of forming the first wiring 101a and the interlayer insulating layers 102 and 114.
- a silicon oxide film for example, a plasma TEOS (Tetra Ethyl Ortho Silicate) film or a fluorine film is formed on a substrate 100 on which transistors, lower layer wirings, and the like are formed using a plasma CVD (Chemical Vapor Deposition) method or the like.
- An interlayer insulating layer 114 made of an FSG (Fluorinated Silicate Glass) film or the like is formed.
- a wiring groove in which the first wiring 101a is embedded in the interlayer insulating layer 114 is formed by photolithography and dry etching.
- a barrier film 101b composed of TaN (film thickness: 5 nm to 40 nm) and Ta (film thickness: 5 nm to 40 nm) and copper as a wiring material (film thickness: 50 nm to 300 nm) are formed in the formed wiring trench. And the like are sequentially deposited using a sputtering method and the like, and copper is further deposited by electrolytic plating using the deposited copper as a seed, thereby filling all the wiring grooves with copper as a wiring material.
- a first wiring 101a having a stripe shape is formed. Further, planarization is performed while removing excess copper on the surface by CMP so that the surfaces of the interlayer insulating layer 114 and the first wiring 101a become flat.
- a plasma CVD method or the like is used to deposit a SiN film of about 30 nm to 200 nm, and a liner film 115 is formed so as to cover the copper that is the first wiring 101a.
- a plasma CVD method or the like is used to deposit a SiN film of about 30 nm to 200 nm, and a liner film 115 is formed so as to cover the copper that is the first wiring 101a.
- an interlayer insulating layer 102 as a first interlayer insulating layer is further deposited on the liner film 115 (the plurality of first wirings 101a), and if necessary, a step on the surface of the interlayer insulating layer 102 by CMP. Relax.
- FIG. 21B shows a process of forming a memory cell hole 103 that penetrates the interlayer insulating layer 102 and is connected to the first wiring 101a.
- an opening i.e., a memory cell hole 103
- a first electrode 101c made of a noble metal or the like is selectively formed only on copper, which is the first wiring 101a at the bottom of the memory cell hole 103, by electroless plating or the like.
- Pt, Ir, Pd, etc. are grown from 2 to 30 nm, here Pt is grown by about 5 nm.
- a plating underlayer containing Ni or the like may be grown between copper and a noble metal.
- the electroless plating can be controlled more easily than in the case where the base of the first electrode 101c is copper.
- a tantalum target is sputtered in an argon and oxygen gas atmosphere, so-called reactive sputtering on the first electrode 101c at the bottom of the memory cell hole 103, on the side wall of the memory cell hole 103, and on the interlayer insulating layer 102.
- a first resistance change layer 104a made of tantalum oxide or the like is formed. In reactive sputtering, if the oxygen flow rate during film formation is increased, the oxygen content of the formed film can be increased.
- the first variable resistance layer 104a having an oxygen content of about 72 atm% was formed under the conditions of argon 34 sccm, oxygen 24 sccm, and power 1.6 kW. Subsequently, oxygen is contained in the memory cell hole 103 having the first variable resistance layer 104a formed on the surface thereof, that is, on the first variable resistance layer 104a in the memory cell hole 103 from the first variable resistance layer 104a.
- the tantalum oxide of the second variable resistance layer 104b having a low rate is formed. This formation is performed by reactive sputtering in the same manner as the formation of the first variable resistance layer 104a.
- the second variable resistance layer 104b having an oxygen content of about 65 atm% was formed under the conditions of argon 34 sccm, oxygen 20.5 sccm, and power 1.6 kW.
- tantalum oxide is formed by sputtering until the memory cell hole 103 is completely filled, and then unnecessary tantalum oxide on the interlayer insulating layer 102 is removed by CMP.
- the first variable resistance layer 104 a and the second variable resistance layer 104 b, that is, the variable resistance layer 104 are formed only in the memory cell hole 103.
- the variable resistance element is embedded in the memory cell hole 103.
- the resistance change phenomenon is considered to occur due to a redox reaction of a transition metal having a plurality of oxidation states.
- the oxidation-reduction reaction is generated by a voltage (or current) applied to the resistance change layer.
- a voltage or current equal to or higher than a predetermined threshold voltage or threshold current is applied to the resistance change layer, it is considered that an oxidation-reduction reaction occurs in the resistance change layer and the resistance changes.
- the resistance change layer a laminated structure of a low oxygen deficiency layer (high resistance layer) and a high oxygen deficiency layer (low resistance layer)
- the voltage applied to the resistance change layer is distributed more to the high resistance layer. It is considered that the resistance change phenomenon is stably generated in the high resistance layer. In this case, it is considered that the resistance of the entire high resistance layer does not change, but a part of the high resistance layer changes.
- composition of the first resistance change layer 104a is TaO y
- y is 2.1 or more
- composition of the second resistance change layer 104b is TaO x
- x is 0.8 or more
- x and y are within the above ranges, the resistance value of the resistance change layer 104 can be stably changed at high speed. Therefore, x and y are preferably within the above range.
- the thickness of the resistance change layer 104 is preferably 1 ⁇ m or less in order to obtain a change in resistance value. Furthermore, when the thickness of the resistance change layer 104 is 200 nm or less, the formation of the resistance change layer 104 by the patterning process can be simplified. Further, when the thickness of the resistance change layer 104 is set to 200 nm or less, the voltage value of the voltage pulse necessary for changing the resistance value of the resistance change layer 104 can be lowered. On the other hand, the thickness of the resistance change layer 104 is preferably at least 5 nm or more from the viewpoint of more surely avoiding breakdown (dielectric breakdown) during voltage pulse application.
- the thickness of the first variable resistance layer 104a is disadvantageous in that the initial resistance value is too high if it is too large, and if it is too small, there is a disadvantage that a stable resistance change cannot be obtained. 8 nm or less is preferable.
- a resistance change layer (the first resistance change layer 104a and the second resistance change layer 104b) is formed, and the inside of the memory cell hole 103 is formed.
- a variable resistance layer is deposited on the entire wafer surface. Thereafter, an unnecessary variable resistance layer outside the memory cell hole 103 is removed by CMP to complete patterning of the variable resistance layer. Therefore, since the etching process is not required for forming the resistance change layer, the resistance change layer is formed by avoiding the etching in which the reaction with the etching gas, the oxygen reduction damage, and the damage due to the charge are concerned in principle. Can be formed.
- the second resistance change layer 104b is a tantalum oxide exhibiting conductivity, it can also be used as the metal of the lower electrode of the MSM diode element.
- the interlayer insulating layers 102 and 112 are inserted through the interlayer insulating layers 102 and 112 to 1 shows a step of forming a contact hole 106 connected to one wiring 101a.
- an interlayer insulating layer 112 is further deposited on the entire planarized wafer, and then an opening for electrical connection with the first wiring 101a, that is, a contact hole 106 is formed.
- the interlayer insulating layers 102 and 112 are patterned with a desired photomask. In the patterning, the etching is stopped when the first wiring 101a is not exposed and the liner film 115 is exposed. Then, the surface of the first wiring 101a can be prevented from being oxidized or corroded.
- FIG. 21D shows a step of forming in the interlayer insulating layer 112 a wiring groove 108a penetrating the interlayer insulating layer 112 and connected to the contact hole 106 and the resistance change element.
- a desired photomask made of photoresist or the like is formed.
- the interlayer insulating layer 112 is patterned using a photomask. Note that a photoresist (hereinafter also simply referred to as a resist) may be embedded in the contact hole 106 before the wiring groove 108a is formed.
- the liner film 115 at the bottom of the contact hole 106 can be surely protected and the first wiring 101a can be prevented from being exposed.
- the liner film 115 at the bottom of the contact hole 106 is opened.
- the wiring groove 108 a is formed at the bottom of the wiring groove 108 a above the memory cell hole 103 so that the first resistance change layer 104 a and the second resistance change layer 104 b are exposed. .
- the contact hole 106 is first formed on the flat interlayer insulating layer 112 by photolithography, so that the focus margin can be increased and the contact hole 106 can be formed. Fine and uniform dimensional control can be performed. On the other hand, in the above-described prior example, the focus margin, for example, a focus margin of 100 to 300 nm becomes small. Further, while preventing the first wiring 101 a at the bottom of the contact hole 106 from being exposed to the end, the upper surface of the memory cell hole 103 in which the electrode layer and the resistance change layer constituting the resistance change element are embedded is opened. The variable resistance layer can be exposed.
- the current control layer 111 is formed of the nitrogen deficient silicon nitride film on the entire surface including the inside of the contact hole 106 and the wiring groove 108a where the first variable resistance layer 104a and the second variable resistance layer 104b are exposed.
- Layer 111 is formed.
- the nitrogen deficient silicon nitride film is formed by so-called reactive sputtering, in which a silicon target is sputtered in an argon and nitrogen gas atmosphere.
- the nitrogen-deficient silicon nitride film thus formed has a nitrogen content of 25 to 40 atm%.
- a resist is formed so as to cover the surface of the current control layer 111 in the contact hole 106 and in the wiring groove 108 a on the contact hole 106 and in the wiring groove 108 a on the resistance change layer 104.
- the process to perform is shown.
- a resist 117a is applied to the entire surface of the current control layer 111 composed of a nitrogen-deficient silicon nitride film, and then the entire surface is etched back by ashing using oxygen gas or the like.
- a resist 117a is selectively buried only in the wiring groove 108a. At this time, the resist 117a is not exposed.
- the resist 117 a in the wiring groove 108 a on the resistance change element (resistance change layer 104) is left, and the contact hole 106 and the wiring groove 108 a on the contact hole 106.
- a process of selectively removing only the resist 117a and exposing the current control layer 111 at the bottom of the contact hole 106 is shown.
- another resist 117b is deposited on the resist 117a in a state where the unphotosensitized resist 117a is buried, and photolithography using a desired photomask is further performed on these resists 117a and 117b, thereby forming a desired pattern. Resist 117a and 117b are formed.
- the pattern is such that only the current control layer 111 of the MSM diode element in the contact hole 106 is exposed while leaving the resist.
- the current control layer 111 in the contact hole 106 and on the wiring groove 108a on the contact hole is left with the current control layer 111 on the variable resistance element (resistance change layer 104) left.
- the step of selectively removing only the first wiring 101a and the step of removing the resists 117a and 117b are shown.
- dry etching is performed using the resists 117a and 117b in FIG. 22C as a mask to selectively remove only the current control layer 111 of the MSM diode element in the contact hole 106 and on the wiring groove on the contact hole.
- the surface of the first wiring 101 a is exposed in the contact hole 106.
- the resists 117a and 117b embedded in the wiring trench 108a and the like are removed by ashing, whereby the state shown in FIG.
- the resists 117a and 117b having an opening larger than the opening of the contact hole 106 are formed, whereby the current control layer 111 in the contact hole 106 is formed. Can be reliably removed.
- the steps of forming the second wiring 108 are shown in FIGS.
- the barrier film 109a and the seed are formed on the entire surface including the first wiring 101a exposed at the bottom of the contact hole 106 and the current control layer 111 on the inner surface of the wiring groove 108a and the surface of the interlayer insulating layer 112.
- Layer copper is sequentially deposited by sputtering or the like.
- the sputtering is preferably performed under the condition that the material molecules are incident substantially perpendicular to the surface of the substrate 100.
- a SiN film is deposited to a thickness of about 30 to 200 nm on the flat surfaces of the interlayer insulating layer 112 and the second wiring 108 by using, for example, a plasma CVD method, and a liner film is formed so as to cover the copper that is the second wiring 108. 116 is formed (FIG. 23C).
- the second wiring 108 and the barrier film 109a formed in the contact hole 106 and in the wiring groove 108a on the contact hole 106 serve as contact plugs.
- the lower layer is formed of the MSM diode element in the contact hole 106, the wiring groove 108a on the contact hole 106, and the wiring groove 108a on the resistance change layer 104.
- the wiring groove 108a is formed after the contact hole 106 is formed first, and a focus margin is ensured in the lithography process for forming the contact hole 106, and the contact hole 106 having a fine dimension is accurately formed within the wafer surface. Can be formed. As a result, it is possible to provide a variable resistance nonvolatile memory device having good consistency with a dual damascene process suitable for forming a fine copper wiring.
- the second resistance change layer 104b is an oxygen-deficient tantalum oxide exhibiting conductivity, it can also be used as the metal of the lower electrode of the MSM diode element.
- the current control layer 111 of the MSM diode element can also be used as the upper electrode of the resistance change element composed of the lower electrode 101C and the resistance change layer 104, and has an intermediate electrode-less structure (lower electrode of the resistance change layer, resistance A structure in which the resistance change element and the current control element are configured by four layers of the change layer, the semiconductor layer, and the upper electrode layer.
- an intermediate electrode may be formed between the resistance change layer 104 and the current control layer 111.
- the intermediate electrode is preferably arranged separately between the resistance change elements from the viewpoint of preventing crosstalk with adjacent memory cells.
- the top surfaces of the first variable resistance layer 104a and the second variable resistance layer 104b embedded in the memory cell hole 103 are etched using an etch back method, CMP overpolishing, or the like.
- an intermediate electrode material for example, TaN
- excess intermediate electrode material is polished and removed by CMP to remove the memory cell hole 103.
- the intermediate electrode 160 may be formed on the upper portion of the intermediate electrode 160 so as to remain only in the recess region.
- the manufacturing method of the non-volatile memory device of this invention was demonstrated based on embodiment, this invention is not limited to these embodiment.
- the present invention includes various modifications made by those skilled in the art without departing from the scope of the present invention.
- at least the bottom of the contact hole is filled with the filling material so that the current control layer is not formed at least at the bottom of the contact hole for forming the contact for drawing each wiring (bit line and word line) constituting the memory array to the external circuit.
- a manufacturing method including at least a step of removing the filling material after forming the current control layer.
- the MSM diode element is exemplified as the diode element, but the MIM diode element may be used as long as it is a bidirectional diode element, and is not limited to the MSM diode element.
- the stacking order of the first variable resistance layer 104a and the second variable resistance layer 104b in the stacked structure of the variable resistance elements may be arranged upside down. That is, the second variable resistance layer 104b and the first variable resistance layer 104a may be formed in this order on the first electrode 101c.
- the method for manufacturing a nonvolatile memory device may further include a step of burying a resist in the contact hole, and the step of forming the current control layer may cover the first resist and the wiring groove.
- the wiring groove is formed.
- the focus margin is ensured, and the contact hole having a fine dimension is formed in the wafer surface.
- the resist buried in the contact hole is not removed, and the current control layer of the bidirectional diode element is formed thereon, and the bidirectional diode element formed on the resist Only the current control layer can be selectively removed by lifting off at the time of resist removal. Therefore, the first wiring and the contact plug in the contact hole are in contact via a barrier film having good adhesion, not the current control layer of the bidirectional diode element. As a result, the contact resistance between the first wiring and the contact plug can be kept low, and at the same time, a bidirectional diode element can be formed in the wiring groove on the memory cell hole. Therefore, a variable resistance nonvolatile memory device capable of high capacity and high integration by miniaturization can be provided.
- the step of forming the current control layer sputtering is performed in which a film forming material comes from an oblique direction with respect to the surface of the substrate so that the current control layer is not formed on the convex sidewall of the resist.
- the current control layer may be formed.
- the sputtered film forming material can reach the side wall of the resist shadowed (shadowed) on the side wall of the interlayer insulating layer forming the wiring groove.
- a region where the current control layer is not formed can be formed on the sidewall of the resist.
- the photomask used in forming the resists 116a and 117b in FIG. 22C is the same photomask as that used when the contact hole 106 was opened, thereby realizing cost reduction. May be.
- resists 116a and 117b are formed as shown in FIG. 24C (a), and only the current control layer 111 in the contact hole 106 is selectively removed as shown in FIG. 24C (b). Therefore, the end surface of the current control layer 111 and the side surface of the contact hole 106 are flush with each other, and the opening width of the current control layer 111 above the contact hole 106 is substantially equal to the opening width of the contact hole 106.
- the present invention is useful as a method for manufacturing a large-capacity non-volatile memory device, and particularly as a method for manufacturing various digital devices such as mobile phones and a mixed memory.
- Nonvolatile memory device 100 Substrate 101, 101c First electrode 101a First wiring 101b, 109a Barrier film 102, 112, 114 Interlayer insulating layer 103 Memory cell hole 104 Resistance change layer 104a First resistance change layer 104b Second Resistance change layer 105 second electrode 106 contact hole 106a opening 108 second wiring 108a wiring groove 109 third electrode 111, 111a current control layer 115, 116 liner film 116a, 117a, 117b resist 117c resist 119 angle 120 hard Mask layer 120 'Hard mask 128 Lead-out wiring 130 Photoresist layer 131 Photoresist pattern 150 Copper 160 Intermediate electrode
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Abstract
Description
本発明者は、「背景技術」の欄において記載した、特許文献1の不揮発性記憶装置の製造方法に関し、以下の問題が生じることを見出した。
まず、図1A及び図1Bは、本発明の第1の実施形態における抵抗変化型の不揮発性記憶装置の構成例を示す平面図である。また、図1Bは、本実施形態における抵抗変化型の不揮発性記憶装置の構成例を示す断面図である。なお、図1A中の1Aで示された1点鎖線の断面を矢印方向に見た断面図が図1Bに相当する。
α=tan-1(c/a)
β=tan-1{(c+d)/b}
γ=tan-1(d/e)
図11A及び図11Bは、本発明の第2の実施形態における抵抗変化型の不揮発性記憶装置の構成例を示す断面図である。また、図12は、同実施形態における抵抗変化型の不揮発性記憶装置の構成例を示す平面図である。なお、図12中の1Aで示された1点鎖線の断面を矢印方向に見た断面図が図11Aに相当し、図12中の1Bで示された1点鎖線の断面を矢印方向に見た断面図が図11Bに相当する。
まず、図19Aおよび図19Bは、本発明の実施形態における抵抗変化型の不揮発性記憶装置の構成例を示す断面図である。また、図20は、同実施形態における抵抗変化型の不揮発性記憶装置の構成例を示す平面図である。なお、図20中の1A-1Aで示された1点鎖線の断面を矢印方向に見た断面図が図19Aに相当し、図20中の1B-1Bで示された1点鎖線の断面を矢印方向に見た断面図が図19Bに相当する。
100 基板
101、101c 第1の電極
101a 第1の配線
101b、109a バリア膜
102、112、114 層間絶縁層
103 メモリセルホール
104 抵抗変化層
104a 第1の抵抗変化層
104b 第2の抵抗変化層
105 第2の電極
106 コンタクトホール
106a 開口
108 第2の配線
108a 配線溝
109 第3の電極
111、111a 電流制御層
115、116 ライナ膜
116a、117a、117b レジスト
117c レジスト
119 角度
120 ハードマスク層
120’ ハードマスク
128 引き出し配線
130 フォトレジスト層
131 フォトレジストパターン
150 銅
160 中間電極
Claims (14)
- 抵抗変化型の不揮発性記憶装置の製造方法であって、
基板上に複数のストライプ状の第1の配線を形成する工程と、
前記複数の第1の配線上に第1の層間絶縁層を形成する工程と、
前記第1の層間絶縁層を貫通し、前記第1の配線に接続される複数のメモリセルホールを形成する工程と、
前記メモリセルホールに抵抗変化素子の少なくとも一方の電極と抵抗変化層とを埋め込む工程と、
前記第1の層間絶縁層上に第2の層間絶縁層を形成した後、前記第1の層間絶縁層及び前記第2の層間絶縁層を貫通し、前記第1の配線に接続されるコンタクトホールを形成する工程と、
前記第2の層間絶縁層を貫通し、前記コンタクトホール及び前記抵抗変化素子に接続される配線溝を形成する工程と、
前記配線溝を被覆し、かつ、前記コンタクトホールの底面を被覆しないように前記第1の層間絶縁層、前記第2の層間絶縁層及び前記抵抗変化層上に双方向ダイオード素子の電流制御層を形成する工程と、
前記コンタクトホール及び前記配線溝内に、前記双方向ダイオード素子の上部電極となる下層と、配線材料からなる上層とで構成される第2の配線を形成することにより、前記抵抗変化素子に接続される前記双方向ダイオード素子と、前記コンタクトホールのコンタクトプラグとを形成する工程とを含む
不揮発性記憶装置の製造方法。 - 前記電流制御層を形成する工程では、前記複数のメモリセルホールの並び方向に平行で、かつ、前記基板の表面に対して斜めの方向から成膜材料が飛来するスパッタリングにより前記電流制御層を成膜する
請求項1に記載の不揮発性記憶装置の製造方法。 - 前記並び方向における前記コンタクトホールの開口の大きさをaとし、前記並び方向における前記配線溝の開口の一方の端から前記配線溝の開口の一方の端に最も近い前記メモリセルホールの開口の前記配線溝の開口の一方の端側の端までの距離をeとし、前記コンタクトホールの高さをcとし、前記配線溝の高さをdとし、
前記a及び前記eを前記並び方向に並んだ前記コンタクトホール及び前記メモリセルホール並びにそれらの開口を含む前記配線溝について同一方向の同一断面において測定された値とし、
前記a、前記c、前記d及び前記eを用いて、α及びγを
α=tan-1(c/a)
γ=tan-1(d/e)
で定義したとき、
前記配線溝、前記コンタクトホール及び前記全てのメモリセルホールは、α>γの条件を満たすように形成される
請求項2に記載の不揮発性記憶装置の製造方法。 - 前記コンタクトホールは、前記並び方向において前記配線溝の開口の一方の端に最も近いメモリセルホールと前記配線溝の開口の一方の端との間に位置し、
前記コンタクトホールの開口の前記配線溝の開口の一方の端に遠い側の端から前記配線溝の開口の一方の端までの距離をbとし、
前記a及び前記bを前記並び方向に並んだ前記コンタクトホール及び前記メモリセルホール並びにそれらの開口を含む前記配線溝について同一方向の同一断面において測定された値とし、
前記b、前記c及び前記dを用いて、βを
β=tan-1{(c+d)/b}
で定義したとき、
前記配線溝及び前記コンタクトホールは、β>αの条件を満たすように形成される
請求項3に記載の不揮発性記憶装置の製造方法。 - 前記成膜材料が飛来する方向は、前記基板の表面に対してθの角度を持ち、かつ、前記a及び前記eが測定された断面の方向と平行であり、
前記θ、前記α及び前記γは、γ<θ<αの条件を満たす
請求項3に記載の不揮発性記憶装置の製造方法。 - 前記成膜材料が飛来する方向は、前記基板の表面に対してθの角度を持ち、かつ、前記a、前記b及び前記eが測定された断面の方向と平行であり、かつ、前記配線溝の開口の一方の端から前記コンタクトホールに向かう方向であり、
前記θ、前記α及び前記γは、γ<θ<βの条件を満たす
請求項4に記載の不揮発性記憶装置の製造方法。 - 前記成膜材料が飛来する方向は、前記基板の表面に対して垂直方向から見たとき、前記複数のメモリセルホールの並び方向に平行な方向である
請求項2~6のいずれか1項に記載の不揮発性記憶装置の製造方法。 - 前記配線溝は、複数形成され、
複数の前記配線溝の延伸方向は、同一方向に統一されている
請求項1~7のいずれか1項に記載の不揮発性記憶装置の製造方法。 - 前記不揮発性記憶装置の製造方法は、さらに、
前記コンタクトホール内にレジストを埋め込む工程を含み、
前記電流制御層を形成する工程は、
前記レジスト及び前記配線溝を被覆するように前記第1の層間絶縁層及び前記第2の層間絶縁層上に前記電流制御層を形成する工程と、
前記レジストを除去することで、前記レジスト上の前記電流制御層をリフトオフする工程とを含む
請求項1に記載の不揮発性記憶装置の製造方法。 - 前記電流制御層を形成する工程では、前記レジストが前記コンタクトホールの開口を含む前記配線溝の底面から凸状に突出している
請求項9に記載の不揮発性記憶装置の製造方法。 - 前記コンタクトホールの開口を含む前記配線溝の底面と凸状の前記レジストの上面との距離は、前記電流制御層の膜厚より大きい
請求項10に記載の不揮発性記憶装置の製造方法。 - 前記電流制御層を形成する工程では、凸状の前記レジストの側壁上に前記電流制御層が形成されないように、前記基板の表面に対して斜めの方向から成膜材料が飛来するスパッタリングにより前記電流制御層を成膜する
請求項10に記載の不揮発性記憶装置の製造方法。 - 前記電流制御層を形成する工程は、
前記コンタクトホールおよび前記配線溝を被覆するように前記第1の層間絶縁層、前記第2の層間絶縁層および前記抵抗変化層上に双方向ダイオード素子の電流制御層を形成する工程と、
前記抵抗変化層上の前記電流制御層を残した状態で、前記コンタクトホール内および当該コンタクトホール上の前記配線溝内の前記電流制御層を除去して前記第1の配線を露出させる工程とを含み、
前記双方向ダイオード素子と前記コンタクトホールのコンタクトプラグとを形成する工程では、前記コンタクトホール内および当該コンタクトホール上の前記配線溝内と前記抵抗変化層上の前記配線溝内とに前記第2の配線を形成する
請求項1に記載の不揮発性記憶装置の製造方法。 - 前記電流制御層を除去する工程は、
前記コンタクトホール内および当該コンタクトホール上の前記配線溝内と前記抵抗変化層上の前記配線溝内との前記電流制御層を被覆するようにレジストを形成する工程と、
前記抵抗変化層上の前記配線溝内の前記レジストを残した状態で、前記コンタクトホール内および当該コンタクトホール上の前記配線溝内の前記レジストを除去して前記コンタクトホールの底部の前記電流制御層を露出させる工程と、
前記レジストをマスクとして前記コンタクトホールの底部の露出した前記電流制御層を除去して前記第1の配線を露出させた後、前記レジストを除去する工程とを含む
請求項13に記載の不揮発性記憶装置の製造方法。
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WO2010137339A1 (ja) * | 2009-05-28 | 2010-12-02 | パナソニック株式会社 | メモリセルアレイ、不揮発性記憶装置、メモリセル、およびメモリセルアレイの製造方法 |
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- 2012-03-21 CN CN201280003672.7A patent/CN103210491B/zh not_active Expired - Fee Related
- 2012-03-21 WO PCT/JP2012/001947 patent/WO2012127861A1/ja active Application Filing
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CN103515534A (zh) * | 2013-10-10 | 2014-01-15 | 北京大学 | 一种高一致性的阻变存储器及其制备方法 |
CN103515534B (zh) * | 2013-10-10 | 2015-05-13 | 北京大学 | 一种高一致性的阻变存储器及其制备方法 |
WO2015182074A1 (ja) * | 2014-05-29 | 2015-12-03 | 日本電気株式会社 | 半導体装置およびその製造方法 |
JPWO2015182074A1 (ja) * | 2014-05-29 | 2017-04-20 | 日本電気株式会社 | 半導体装置およびその製造方法 |
US9905758B2 (en) | 2014-05-29 | 2018-02-27 | Nec Corporation | Semiconductor device and method for manufacturing same |
Also Published As
Publication number | Publication date |
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JPWO2012127861A1 (ja) | 2014-07-24 |
CN103210491B (zh) | 2015-09-09 |
CN103210491A (zh) | 2013-07-17 |
US20130224931A1 (en) | 2013-08-29 |
US8900965B2 (en) | 2014-12-02 |
JP5324724B2 (ja) | 2013-10-23 |
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