Classifications

• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K7/00—Constructional details common to different types of electric apparatus
  • H05K7/02—Arrangements of circuit components or wiring on supporting structure
  • H05K7/10—Plug-in assemblages of components, e.g. IC sockets
  • H05K7/1053—Plug-in assemblages of components, e.g. IC sockets having interior leads
  • H05K7/1061—Plug-in assemblages of components, e.g. IC sockets having interior leads co-operating by abutting
  • H05K7/1069—Plug-in assemblages of components, e.g. IC sockets having interior leads co-operating by abutting with spring contact pieces
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
  • G01R1/02—General constructional details
  • G01R1/04—Housings; Supporting members; Arrangements of terminals
  • G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
  • G01R1/0433—Sockets for IC's or transistors
  • G01R1/0483—Sockets for un-leaded IC's having matrix type contact fields, e.g. BGA or PGA devices; Sockets for unpackaged, naked chips
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
  • G01R1/02—General constructional details
  • G01R1/06—Measuring leads; Measuring probes
  • G01R1/067—Measuring probes
  • G01R1/073—Multiple probes
  • G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
  • G01R1/07364—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch
  • G01R1/07371—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch using an intermediate card or back card with apertures through which the probes pass

Definitions

• Patent reference 2 Japanese Unexamined Patent Application Publication No. 2009-85948
• the conductive contact pin described above is preferably made thick and short.
• the thickness of the conductive contact pin is necessarily limited by narrowing the pitch between the IC device terminals.
• the reliability of conductive contact pins decreases as they are used repeatedly, and thus they are generally replaced as needed due to the high cost of conductive contact pins. Therefore, conductive contact pins are required to have a certain length or longer in consideration of workability and the like when replacing the conductive contact pins. Note that the shorter the conductive contact pins are, the shorter the operating life thereof becomes.
• the use of conductive contact pins with at least a certain length is also preferable in the sense that, in some cases, it may not be possible to make the conductive contact pins compliant if the substrate or the semiconductor package is not flat.
• the impedance was decreased by directly connecting a capacitor between a power pin and a ground pin of the conductive contact pins mounted in the IC device socket or IC device socket housing.
• the volume occupied by the IC device socket increases when the capacitor is directly connected to the conductive contact pins or the IC device socket housing. In this case, there is a fear that this may interfere with the arrangement of the conductive contact pins of the IC device socket in a high density pattern.
• the present invention has a basic structure for solving the above problem. Specifically, the present invention is equipped with a structure that additionally allows stable signal transmission during IC device inspections without causing a reduction in workability when exchanging the conductive contact pins.
• semiconductor devices having a plurality of power sources and/or grounds inside a single package such as a System on Chip (SoC) or System in Package (SiP) have become known recently.
• SoC System on Chip
• SiP System in Package
• Such semiconductor devices include those in which various functions that operate at different voltages are implemented within a single package, but even when the voltage is the same, it may be necessary to accommodate the coexistence of analog and digital circuits that require independent power sources and/or grounds to operate normally. Accordingly, it is an object of the present invention to provide an IC device socket equipped with a configuration for easily allowing the setting of a plurality of types of power sources and/or grounds, without increasing the thickness of the substrate itself, in which conductive contact pins are inserted, by adopting the above basic configuration.
• An IC device socket includes a substrate and a plurality of conductive contact pins.
• the substrate includes a first surface, a second surface facing the first surface, and a plurality of through holes that each communicate with the first surface and the second surface.
• the plurality of conductive contact pins is held by the substrate in a state in which a portion of the conductive contact pins are inserted into any of the plurality of through holes.
• the substrate at least includes a base material, at least one dielectric layer, a first conductive layer, and a second conductive layer.
• the base material is composed of an insulating material and includes the first surface, the second surface, and the plurality of through holes.
• the dielectric layer is provided between the first surface and the second surface of the base material in an intersecting state with the plurality of through holes and has a permittivity higher than the base material.
• the first and second conductive layers sandwich the dielectric layer along a first direction from the first surface of the base material toward the second surface.
• At least one of the first and second conductive layers is segmented into two or more portions in a horizontal direction with an insulation region interspersed therebetween.
• the horizontal direction corresponds to a direction orthogonal to the first direction from the first surface of the substrate toward the second surface.
• a plurality of conductive layers corresponding to a segmented power source and a segmented ground may be provided when the number of power sources and grounds is high or when, in order to increase capacity, the power sources and grounds cannot be segmented in one plane.
• a structure in which a plurality of dielectric layers is laminated in the substrate according to this IC device socket includes a plurality of dielectric layers having on at least one surface thereof a conductive layer segmented with an insulation region interspersed therebetween, while another dielectric layer may use any of a structure having on at least one surface thereof a conductive layer segmented with an insulation region interspersed therebetween, a structure having conductive layers on both surfaces with insulation regions interspersed therebetween, and a structure having unsegmented conductive layers on both surfaces.
• a capacitor (hereinafter called a C component) is made up of conductive layers opposing each other, by providing conductive layers on both sides of a dielectric layer.
• the present invention allows for forming a plurality of C components on one plane by adopting a configuration in which a conductive layer provided on at least one surface of the dielectric layer is segmented with an insulation region interspersed therebetween.
• surface areas of segmented regions of the conductive layer are basically not limited as to a surface area or planar pattern (form) thereof, so long as the required minimum capacity can be assured.
• a segment pattern of the conductive layers may be different for each dielectric layer.
• the insulating material may also be a material (for example, an insulating material such as that of the base material) that is different from the dielectric layer.
• the dielectric layers themselves, along with the conductive layers, have a structure that is segmented in the horizontal direction.
• these segmented regions are defined as one dielectric layer.
• the IC device socket according to the invention of the present disclosure is formed of a substantially integrated substrate as described above made up of the base material, in which is embedded the dielectric layer and the conductive layers provided on both sides of the dielectric layer which together configure the C component.
• the distance between the conductive contact pins and the C component is extremely small, and as a result the performance of the IC device socket can be improved.
• the conductive contact pins are held by being press fit or the like into the substrate.
• the substrate functions as a support of the conductive contact pins thus removing the need for another component to support the conductive contact pins.
• This plurality of conductive contact pins includes a plurality of first conductive contact pins and a plurality of second conductive contact pins that have a connection state different from the plurality of first conductive contact pins. Specifically, portions of the plurality of first conductive contact pins are inserted in any of the plurality of through holes to make contact with conductive member (a metal film or the like provided on the inner surface of the through holes) corresponding to these portions. Portions of the plurality of second conductive contact pins are inserted in any other of the plurality of through holes but remain in a state of non-contact with the first or second conductive layers.
• This state of non-contact with the first or second conductive layer indicates that the second conductive contact pins do not make contact with the conductive member provided on the inner surface of the though holes, or that conductive member is not provided on the inner surface of the through holes accommodating the second conductive contact pins.
• the first conductive layer and the second conductive layer are electrically connected to any of the plurality of first conductive contact pins with the corresponding conductive member interspersed therebetween.
• the above plurality of first conductive contact pins of the IC device socket according to the present invention is divided into a first group (e.g., a power pin group) that is electrically connected to only the first conductive layer, and a second group (e.g., a ground pin group) that is electrically connected to only the second conductive layer.
• a first group e.g., a power pin group
• a second group e.g., a ground pin group
• the plurality of second conductive contact pins not electrically connected to either the first or second conductive layers functions as signal pins.
• the C component along with the dielectric layer, at least any one of the first and second conductive layers configure the C component are segmented into two or more segments in the horizontal direction with the insulation region interspersed therebetween.
• FIG. 1 is a perspective view of a configuration of a first embodiment of the IC device socket according to the present invention.
• FIG. 2 shows a cross-section of the IC device socket shown in FIG. 1 along the line II - II.
• FIG. 3 is a plan view of a substrate of the IC device socket shown in FIG. 1 and illustrates an example of a positional relationship of a conductive layer segmented into pin arrangements.
• FIG. 4 is an enlarged view of a portion III of the cross-section structure shown in FIG. 2.
• FIG. 5 is a plan view showing a configuration of a power layer corresponding to the IV portion of the plan view shown in FIG. 3.
• FIG. 6 is a plan view showing a configuration of a ground layer corresponding to the IV portion of the plan view shown in FIG. 3.
• FIG. 7 is a plan view showing another configuration of the power layer according to the present embodiment.
• FIG. 8 is a plan view showing a configuration of the ground layer, in addition to the power layer shown in FIG. 7, with a dielectric layer sandwiched therebetween.
• FIG. 9 is a perspective view showing a portion of the structure (C component layer), which includes the power layer (power layer segmented into two or more segments by the insulation region) having the structure shown in FIG. 7 and the ground layer (power layer segmented into two or more segments by the insulation region) shown in FIG. 8, so as to sandwich the dielectric layer, and also showing a substrate region corresponding to the portion IV shown in FIG. 3.
• FIG. 10 is a first perspective view following the example shown in FIG. 9 and shows an example of a combination of a plurality of C component layers (configured by a dielectric and conductive layers provided on both sides thereof) arranged in a laminated state inside the substrate.
• FIG. 1 1 is a second perspective view following the example shown in FIG. 9 and shows an example of a combination of a plurality of C component layers arranged in a laminated state inside the substrate.
• FIG. 12 is a perspective view that illustrates a configuration of the IC device socket when the insulation region is an air gap, as an alternative example of the configurations shown in FIGS. 9 to 1 1.
• FIG. 13 is a first plan view of a substrate of the IC device socket according to the present embodiment and illustrates another example of a positional relationship of the conductive layer divided into pin arrangements.
• FIG. 14 is a second plan view of a substrate of the IC device socket according to the present embodiment and illustrates another example of a positional relationship of the conductive layer divided into pin arrangements.
• FIG. 15 is a third plan view of a substrate of the IC device socket according to the present embodiment and illustrates another example of a positional relationship of the conductive layer divided into pin arrangements.
• FIG. 16 is a fourth plan view of a substrate of the IC device socket according to the present embodiment and illustrates another example of a positional relationship of the conductive layer divided into pin arrangements.
• FIGS. 1 to 16 Embodiments of the IC device socket according to the present invention will be described below with reference to FIGS. 1 to 16. Note that in the various figures, like reference numerals designate identical or similar elements and overlapping descriptions will be omitted.
• FIG. 1 is a perspective view of a structure of a first embodiment of the IC device socket according to the present invention.
• FIG. 2 shows a cross-section of the IC device socket shown in FIG. 1 along the line II - II.
• FIG. 3 is a plan view of a structure of a substrate 2 of the IC device socket 1 shown in FIG. 1. Note that the arrow L in FIG. 3 substantially matches the line II - II in FIG. 1.
• An IC device socket 1 includes the substrate 2, a plurality of conductive contact pins 3 that are held by pressure fitting or the like in the substrate 2, and a body 4 that supports the substrate 2.
• the body 4 includes a guide portion or guide wall 41 for arranging an IC device (not shown) to be inspected in a specific position on the substrate 2, and further includes a positioning unit (a positioning pin 42 shown in FIG. 2 in the present embodiment) for arranging the IC device socket 1 in a specific position in an inspection device (not shown) for inspecting IC devices.
• a positioning unit a positioning pin 42 shown in FIG. 2 in the present embodiment
• the body 4 may be incorporated into the IC device socket 1 as needed.
• the substrate 2 may have a positioning hole or notch to work in concert with positioning means.
• FIG. 4 is an enlarged view of a portion III of the cross-section structure shown in FIG. 2. As shown in FIG.
• the substrate 2 includes a base material 21 made up of a dielectric such as glass fiber epoxy resin or the like, and at least one (four are shown as an example in FIG. 4) of dielectric layer 22 to 25 (a first to fourth dielectric layer) embedded in the base material 21 , and a conductive layer of copper and the like is formed on the upper and lower surface sides of the dielectric layers.
• the conductive layers embedded in the base material 21 are also segmented in the horizontal direction with an insulation region 290 interspersed therebetween.
• the insulation region 290 refers to a region composed of insulating material such as the base material or a conductive material. In the example shown in FIG. 4, a portion of the base material 21 and a portion of the first to fourth dielectric layers 22 to 25 are included in the insulation region 290.
• the substrate 2 is formed by laminating the material (a portion of the base material) configuring the base material 21 , the conductive layers, and the dielectric layer. Permittivity of the dielectric layers is preferably high, in order to improve the capacity of the C components.
• the first to fourth dielectric layers 22 to 25 are preferably made up of a high dielectric having a permittivity higher than the permittivity of the base material 21.
• ECM Embedded Capacitor Material manufactured by 3M may be used as a high dielectric.
• ECM is made of dielectric material formed as a flexible sheet. This type of substrate may be manufactured using a method for manufacturing a printed circuit board.
• the material making up the substrate 2, which is the material of the base material 21 may be an insulating material and may include paper in place of glass fiber, and may include phenol resin or polyamide resin in place of epoxy resin. Silver or gold may also be used in place of copper as the material composing the conductive layers.
• the first to fourth dielectric layers 22 to 25 may each include a polymer.
• the first to fourth dielectric layers 22 to 25 preferably each include a polymer and a plurality of particles, and in particular are manufactured by mixing the resin and the particles. Desirable resins include epoxy, polyamide, polyvinylidene fluoride, cyanoethyl pullulan, benzocyclobutene,
• the particles include dielectric (or insulating) particles, and representative examples include barium titanate, barium strontium titanate, titanium oxide, lead zirconium titanate, and combinations thereof.
• each of the first to fourth dielectric layers 22 to 25 may be for example 0.5 ⁇ or greater, and 100 ⁇ or less.
• the thickness is preferably thinner, for example, a thickness of 15 ⁇ or less or 10 ⁇ or less, thus improving the electrostatic capacity of the capacitors.
• the thickness of the dielectric layers is preferably thicker, for example a thickness of 1 ⁇ or more, from the perspective of bonding strength.
• the relative permittivity of the dielectric is preferably high, for example 10 or more, or 12 or more. Although there is no particular restraint on the upper limit, the relative permittivity may be for example 30 or less, 16 or less, or 20 or less.
• One of the conductive layers formed on either side of the first to fourth dielectric layers 22 to 25 configures a power layer electrically connected to power pins of the IC device socket 1, and the other conductive layer configures a ground layer electrically connected to ground (hereinbelow referred to as GND) pins of the IC device socket 1.
• GND ground
• segmented regions 222 and 222' configuring a first power layer with the insulation region 290 interspersed therebetween are formed on an upper surface 221 of the first dielectric layer 22 closest to a surface 26 (upper surface in FIG. 2) on the IC device side of the substrate 2
• segmented regions 224 and 224' configuring a first GND layer with the insulation region 290 interspersed therebetween are formed on a lower surface 223.
• segmented regions 232 and 232' configuring a second power layer with the insulation region 290 interspersed therebetween are formed on an upper surface 231 of the second dielectric layer 23 positioned directly below the first dielectric layer 22, and segmented regions 234 and 234' configuring a second GND layer with the insulation region 290 interspersed therebetween are formed on a lower surface 233. Further, segmented regions 252 and 252' configuring a fourth power layer with the insulation region 290 interspersed therebetween are formed on an upper surface 251 of the fourth dielectric layer 25 closest to a surface 27 (lower surface in FIG.
• segmented regions 254 and 254' configuring a fourth GND layer with the insulation region 290 interspersed therebetween are formed on a lower surface 253.
• segmented regions 242 and 242' configuring a third power layer with the insulation region 290 interspersed therebetween are formed on an upper surface 241 of the third dielectric layer 24 positioned directly above the fourth dielectric layer 25, and segmented regions 244 and 244' configuring a third GND layer with the insulation region 290 interspersed therebetween are formed on a lower surface 243.
• the cross-section structure illustrated in FIG. 4 shows that the upper surface 26 of the substrate 2 matches the upper surface of the base material 21 , and the lower surface 27 of the substrate 2 matches the lower surface of the base material 21.
• Different electric potentials may be set for the segmented regions 222 and 222' of the first power layer, and different GND settings are possible for the segmented regions 224 and 224' of the first GND layer (electrical connections to different GND pins).
• Different electric potentials may be set for the segmented regions 232 and 232' of the second power layer, and separate GND settings are possible for the segmented regions 234 and 234' of the second GND layer.
• Different electric potentials may be set for the segmented regions 242 and 242' of the third power layer, and the segmented regions 244 and 244' of the third GND layer do not need to be electrically connected to shared GND pins.
• Different electric potentials may be set for the segmented regions 252 and 252' of the fourth power layer, and the segmented regions 254 and 254' of the fourth GND layer do not need to be electrically connected to shared GND pins.
• all of the first to fourth dielectric layers 22 to 25 are provided on both sides thereof with conductive layers segmented in the horizontal direction interspersed therebetween with the insulation region 290.
• a dielectric layer provided on both sides thereof with an unsegmented conductive layer may be included in the configuration in which a plurality of dielectric layers is arranged in a laminated state inside the substrate 2. For example, when an
• the unsegmented conductive layer is arranged over the full surface of the substrate 2, a C component with a surface area approximately equal to the surface area of the substrate 2 may be formed. Additionally, the surface area of the unsegmented conductive layer may be determined according to the required capacity of the C component without the need to ensure that the surface area necessarily matches the full surface of the substrate 2. Moreover, any planar shape of the conductive layer may be determined in the substrate 2 regardless of whether the conductive layer is segmented or not.
• Each of the conductive contact pins 3 penetrates the substrate 2 in a substantially vertical direction through the upper layer 26 and the lower layer 27 of the substrate 2.
• through holes 28 in which the conductive contact pins 3 can be inserted are formed in the base material 21, the dielectric layers, and the conductive layers formed on both side thereof that make up the substrate 2.
• a conductive member 281 of copper, gold, or silver and the like is formed by plating or the like on the inside surface of the through holes 28.
• Pin bodies 31 of the conductive contact pins 3 press-fitted into the through holes 28, except for those conductive contact pins 3 that are signal pins, are electrically connected to any of the conductive layers through the conductive member 281. Note that the inner surface of holes for signal pins may or may not be formed with the conductive member 281.
• the dimensions of the through holes 28 are determined so as to allow the conductive contact pins 3 to be held in the through holes without falling out due to a counterforce of springs mounted in the conductive contact pins 3 generated when arranging the IC device socket 1 on the inspecting device substrate.
• a press fit gripping force of the conductive contact pins 3 is preferably 0.1 N or greater.
• the dimensions of the through holes 28 are determined in such a way that the conductive contact pins 3 can be removed fairly easily from the through holes 28 when replacing or maintaining the conductive contact pins 3.
• the dimensions of the through holes 28 are determined in such a way that the conductive member 281 on the inner surface of the through hole 28 is not peeled off when removing the conductive contact pins 3 from the substrate 2.
• a press fit gripping force of the conductive contact pins 3 is preferably no more than 2.0 N.
• Each of the conductive contact pins 3 include the substantially cylindrical pin body 31 that is held by press fitting in the substrate 2, a first contact portion 32 that is electrically contactable, i.e., conductively connects with, the inspection device (not shown) by protruding from one end (the lower end in FIG. 4) of the pin body 31, and a second contact portion 33 that is electrically contactable, i.e., conductively connects with, the IC device (not shown) by protruding from the other end (the upper end in FIG. 4) of the pin body 31.
• conductive contact pins 3 Although various modes are applicable as conductive contact pins 3, those such as, for example, so-called spring probe types, in which both contact portions 32 and 33 can be displaced in relation to the pin body 31 by a spring and the like (not shown) in the axial direction of the pin body 31, are preferable.
• the pin bodies 31 of the conductive contact pins 3 are preferably cylindrical in shape. When the conductive contact pins 3 are shaped in this way, the conductive contact pins 3 can be easily arranged in a substantially axial direction of the through holes 28 since the outer surface of the pin bodies 31 make contact with the through holes 28 throughout a wide surface area. An electrically stable connection can be realized since the contact surface area of the conductive member 281 and the conductive contact pins 3 is increased.
• the conductive contact pins 3 are divided into a power pin group electrically connected to the power layer described above, a GND pin group connected to the GND layer, and a signal pin group not connected to any of the layers.
• a conductive contact pin 3b is connected to both the first power layer segmented region 222 and the third power layer segmented region 242
• a conductive contact pin 3i is connected to both the first power layer segmented region 222' and the third power layer segmented region 242' to both function as first power pins.
• a conductive contact pin 3c is connected to both the second power layer segmented region 232 and the fourth power layer segmented region 252, and a conductive contact pin 3f is connected to both the second power layer segmented region 232' and the fourth power layer segmented region 252' to both function as second power pins.
• a conductive contact pin 3 a is connected to both the first GND layer segmented region 224 and the third power layer segmented region 244, and a conductive contact pin 3h is connected to both the first GND layer segmented region 224' and the third power layer segmented region 244' to both function as first GND pins.
• a conductive contact pin 3d is connected to both the second GND layer segmented region 234 and the fourth power layer segmented region 254, and a conductive contact pin 3g is connected to both the second GND layer segmented region 234' and the fourth power layer segmented region 254' to both function as second GND pins.
• the conductive contact pin 3e is not connected to any of the conductive layers and thus functions as a signal pin.
• the C components which are configured by the high dielectrics (dielectric layer) sandwiched by the power layers and the GND layers, are preferably provided at positions as close as possible to the upper surface 26 and the lower surface 27 (respectively matching the upper and lower surfaces of the base material 21), i.e., the outsides, of the substrate 2.
• the reason for this is that a stable power supply can be achieved during IC device inspection if the distances between the conductive layers and the outer surfaces of the substrate 2 are small. More specifically, the smaller the distance between the upper surface 26 of the substrate 2 and the first and second dielectric layers 22 and 23, the greater the input sensitivity of the IC device subject to inspection.
• the first and second dielectric layers 22 and 23 are preferably arranged toward the upper surface 26 side compared to a midway point between the upper surface 26 and the lower surface 27 of the substrate 2.
• the third and fourth dielectric layers 24 and 25 are preferably arranged toward the lower surface 27 side compared to a midway point between the upper surface 26 and the lower surface 27 of the substrate 2.
• the substrate 2 is configured as a substantially integrated object in which are embedded the dielectric layers made up of high dielectrics each sandwiched by a power layer and a GND layer.
• the conductive contact pins 3 are substantially held by only the substrate 2.
• a C component having a required capacity can be arranged in a state divided into a plurality of segments at any position inside the substrate 2.
• the substrate 2 may include near the center thereof in the thickness direction a further C component including the dielectric layer and the conductive layers formed on both sides thereof.
• each conductive contact pin 3 is preferably shorter from the perspective of electrical characteristics and the like. However, as the length of the conductive contact pins 3 becomes shorter, the operation and assembly when replacing the pins become more difficult. Conversely according to the present basic structure, there is no need to consider a drop in performance of the IC device socket 1, even when using relatively long conductive contact pins 3, since similar effects can be achieved for electrical characteristics as a case when shorter pogo pins are actually used, due to the configuration of the above substrate 2.
• the conductive contact pins 3 also become effectively longer thus reducing the electrical characteristics.
• the axial direction length of the pin bodies 31 of the conductive contact pins 3 is preferably approximately equal to the thickness of the substrate 2.
• the thickness of the substrate 2 is preferably determined in consideration of the structural strength required for holding the conductive contact pins 3, and thus is preferably made as thin as possible while maintaining a suitable level of strength.
• the IC device socket 1 is equipped with, for example, a structure in which four dielectric layers 22 to 25 (with power layers and GND layers formed on both sides thereof) are laminated with portions of the base material 21 interspersed therebetween.
• different power settings and different ground settings are possible inside one package with the IC device socket 1 , since different electric potential settings are possible between, for example, the first power layer and the second power layer.
• different power settings and/or ground settings for each segmented region are possible even within the same layer. For example, different power settings may be set for the segmented region 222 and the segmented region 222' of the first power layer, and different power settings may be set for the segmented region 232 and the segmented region 232' of the second power layer.
• the first power layer has, for example, the planar shape shown in FIG. 5, while the first GND layer has, for example, the planar shape shown in FIG. 6.
• FIG. 5 is a plan view showing a first power layer configuration corresponding to the IV portion of the plan view shown in FIG. 3, and any of the other second to fourth conductive layers may also have similar planar shapes.
• FIG. 6 is a plan view showing a first GND layer configuration corresponding to the IV portion of the plan view shown in FIG. 3, and any of the other second to fourth GND layers may also have similar planar shapes.
• the first power layer is configured of the segmented region 222 and the segmented region 222' segmented horizontally with the insulation region 290 interspersed therebetween.
• the segmented regions 222 and 222' are provided with two types of openings 280a and 280b having different diameters at positions corresponding to the through holes 28 provided in the substrate 2.
• the two types of openings 280a and 280b provided in each of the segmented regions 222 and 222' are arranged in a direction along the arrow LI in FIG. 5.
• the arrow LI substantially matches the line II - II in FIG. 1 (substantially matching the cross-section shown in FIG. 4).
• the opening 280a has a diameter substantially matching the diameter of the through holes 28, or more specifically, has a bore diameter that allows a state of electric contact to be sufficiently maintained between the conductive member 281 formed on the inner surface of the through holes 28 and the segmented regions 222 and 222' that configure the first power layer.
• the opening 280b has a diameter larger than the diameter of the through holes 28, or more specifically, has a bore diameter, for example, about 50 ⁇ larger than the diameter of the through holes 28, and can sufficiently maintain a state of electrical separation between the conductive member 281 formed on the inner surface of the through holes 28 and the segmented regions 222 and 222' that configure the first power layer.
• the first GND layer is also configured of the segmented region 224 and the segmented region 224' segmented horizontally with the insulation region 290 interspersed therebetween.
• the segmented regions 224 and 224' are provided with two types of openings 280a and 280b having different diameters at positions corresponding to the through holes 28 provided in the substrate 2, similar to the segmented regions 222 and 222' of the first power layer described above.
• the two types of openings 280a and 280b provided in each of the segmented regions 224 and 224' are arranged in a direction along the arrow L2 in FIG. 6.
• the arrow L2 substantially matches the line II - II in FIG. 1 (substantially matching the cross-section shown in FIG.
• the opening 280a has a diameter substantially matching the diameter of the through holes 28, or more specifically, has a bore diameter that allows a suitable electric contact to be maintained with the conductive member 281 formed on the inner surface of the through holes 28 and the segmented regions 224 and 224' that make up the first GND layer.
• the opening 280b has a diameter larger than the diameter of the through holes 28, or more specifically, has a bore diameter, for example, that can maintain a suitable state of electrical separation between the conductive member 281 formed on the inner surface of the through holes 28 and the segmented regions 224 and 224' that make up the first GND layer.
• each of the power layers is arranged in a laminated state interspersed therebetween with portions of the base material 21 made up of insulating material within the substrate 2, thereby allowing for the first to fourth power layers to have different electric potential settings while also allowing for segmented regions within each power layer to have different electric potential settings.
• the structure of the present embodiment is effective since an increase can be avoided in the thickness (the interval between the upper surface 26 and the lower surface 27) of the substrate 2, which is caused by a higher number of layers to be laminated when the electric potential settings inside the IC device socket 1 become complex.
• the structure used to configure the C component (hereinafter referred to as a C component layer) including the dielectric layer and the conductive layers provided on both sides of the dielectric layer in the above embodiment shown in FIGS. 1 to 6 includes a structure of segmented conductive layers for each of the first to fourth dielectric layers 22 to 25. However a different segment pattern of conductive layers for each C component layer may also be used.
• FIG. 7 An example of a power layer that can be used in the structure shown in FIG. 9 is shown in FIG. 7.
• a power layer 2100 is segmented into a segmented region 2100a and a segmented region 2100b in the horizontal direction (a direction orthogonal to the direction from the upper surface 26 toward the lower surface 27 of the substrate 2) with an insulation region 2100c interspersed therebetween.
• the two types of openings 280a and 280b provided in the power layer 2100 are arranged in a direction along the arrow L3 in FIG. 7.
• the arrow L3 substantially matches the line II - II in FIG. 1 (substantially matching the cross-section shown in FIG. 4).
• a GND layer 2200 is also segmented horizontally into a segmented region 2200a and a segmented region 2200b with the insulation region 2200c interspersed therebetween.
• the segmented regions 2200a and 2200b also have formed therein openings 280a and 280b with two types of diameters. Note that the two types of openings 280a and 280b are arranged in a direction along the arrow L4 in FIG. 8.
• the arrow L4 substantially matches the line II - II in FIG. 1 (substantially matching the cross-section shown in FIG. 4).
• FIG. 9 is a perspective view showing a portion of the structure (C component layer) in which the dielectric layer is sandwiched by the power layer (power layer segmented into two or more segments by the insulation region) having the structure shown in FIG. 7 and the GND layer (power layer segmented into two or more segments by the insulation region) shown in FIG. 8, and also showing a substrate region corresponding to the portion IV shown in FIG. 3.
• a structure in which a plurality of C component layers are arranged in a laminated state in the substrate 2 may include a combination of the C component layer shown in FIG. 9 and yet another C component layer having a segmented conductive layer pattern.
• FIGS. 10 and 1 1 are perspective views following the example shown in FIG. 9 and show an example of a combination of a plurality of C component layers (configured by a dielectric and conductive layers provided on both sides thereof) arranged in a laminated state in the substrate.
• a first C component layer shown in FIG. 9 and a second C component layer having a different segmented conductive layer pattern are arranged in a laminated state in the substrate 2.
• the first C component layer is, as described above, configured of the dielectric layer 2000, the power layer 2100 that includes the segmented regions 2100a and 2100b provided on one surface of the dielectric layer 2000 and interspersed therebetween with the insulation region 2100c, and the GND layer 2200 that includes the segmented regions 2200a and 2200b provided on the other surface of the dielectric layer 2000 and interspersed therebetween with the insulation region 2200c.
• the second C component is configured of a dielectric layer 3000, a power layer 3100 that includes segmented regions 3100a and 3100b provided on one surface of the dielectric layer 3000 and interspersed with the insulation region 2100c, and a GND layer 3200 that is unsegmented and that is provided on the other surface of the dielectric layer 3000.
• the shape (segment pattern) of the insulation region 2100c in the power layer 2100 of the first C component layer, and the shape (segment pattern) of the insulation region 3100c in the power layer 3100 of the second C component layer may of course be different.
• the unsegmented GND layer 3200 of the second C component layer does not necessarily have a surface area matching the upper surface 26 or the lower surface 27 of the substrate 2. It is sufficient for the surface area of the GND layer 3200 to be just large enough to assure the required capacity between the segmented regions 3100a and 3100b of the power layer 3100.
• the first C component layer shown in FIG. 9 and a third C component layer having a different segmented conductive layer pattern are arranged in a laminated state inside the substrate 2.
• the structure of the first C component layer is the same as that of FIG. 9 and FIG. 10 described above.
• the third C component is configured of a dielectric layer 4000, a power layer 4100 that is unsegmented and is provided on one surface of the dielectric layer 4000, and a GND layer 4200 that is unsegmented and that is provided on the other surface of the dielectric layer 4000.
• the respective surface areas of the unsegmented power layer 4100 and the unsegmented GND layer 4200 of the third C component layer do not necessarily match the surface areas of the upper surface 26 or the lower surface 27 of the substrate 2.
• the capacity of the C component is determined by the surface area of a region in which the power layer 4100 and the GND layer 4200 overlap, as seen in the direction from the upper surface 26 toward the lower surface 27 of the substrate 2.
• the surface area and the planar shape of the power layer 4100 and the surface area and the planar shape of the GND layer 4200 may be determined within a range in which the required capacity of each can be assured.
• the insulation region that segments the conductive layer may be a gap such as for example an air gap.
• the insulation region 2100c that is an air gap preferably has a shape that extends so that the upper surface thereof reaches the upper surface 26 of the substrate 2, and a lower surface thereof reaches the lower surface 27 of the substrate 2 as shown in FIG. 12.
• the dielectric layer 2000 is segmented in the horizontal direction into two portions 2000a and 2000b, the power layer 2100 is also segmented in the horizontal direction into two portions 2100a and 2100b, and further the GND layer 2200 is also segmented in the horizontal direction into two portions 2200a and 2200b, as shown in FIG. 12.
• the insulation region 2100c that is an air gap.
• FIG. 12 shows an internal structure of the substrate 2 corresponding to the portion IV in FIG. 3.
• a plurality of dielectric layers may be arranged in a laminated state.
• another C component layer such as that shown in FIGS. 10 or 1 1 may be included in the configuration in FIG. 12.
• the power layer 2100 and the GND layer 2200, as well as the dielectric layer 2000 are segmented in the horizontal direction by the application of the air gap in the insulation region 2100c.
• no particular differences in the functions of the dielectric layers themselves occur when segmented by a different insulating material or the air gap.
• these segmented regions are defined as one dielectric layer.
• the configuration in which the dielectric layer 2000 and at least any one of the power layer 2100c and the GND layer 2200 configure the C component allows for a noticeable effect in suppressing an increase in the thickness of the substrate in comparison to a case where different power supplies and/or grounds are arranged in a laminated state in the substrate. Additionally, substrate manufacturing is simplified (manufacturing costs are reduced) since the number of processes involved in the process itself can be reduced for laminating the C component layer with portions of the base material interspersed therebetween.
• the arrangement of the conductive contact pins 3 held by the substrate 2 in the IC device socket 1 according to the present embodiment can employ various arrangement patterns without being limited to the rectangular shapes shown in FIG. 3.
• the surface area and the shape of the conductive layer and/or GND layer segmented by the sequential patterns of the employed conductive contact pins 3 can be set as desired.
• An example of such is shown in FIGS. 13 to 16.
• FIGS.13 to 16 are plan views of respective substrates of IC device sockets according to the present embodiment and illustrate other examples of positional relationships of the conductive layers divided into pin arrangements.
• the FIGS. 13 to 16 show positional relationships of elements corresponding to the substrate 2 and the segmented regions 222 and 222' of the first power layer based on the example shown in FIG. 3.
• the conductive contact pins 3 in a substrate 2a are arranged in a rectangular ring region sandwiched by a rectangular outer periphery and a rectangular inner periphery; and the conductive layer configuring the C component layer arranged in the substrate 2a is segmented into two segmented regions 222a and 222'a in the horizontal direction interspersed therebetween with an insulation region 290a.
• the conductive contact pins 3 are arranged in an inside rectangular region and also in a rectangular ring region that surrounds the inside rectangular region in a substrate 2b.
• any of the conductive layers that configure the C component layer arranged in the substrate 2b may be segmented such that, for example, a segmented region 222b surrounds a segmented region 222'b with an insulation region 290b interspersed therebetween.
• the conductive contact pins 3 are arranged along an outermost perimeter of a rectangular region in a substrate 2c.
• any of the conductive layers that configure the C component layer arranged in the substrate 2c may be segmented into, for example, segmented regions 222c and 222'c having shapes that follow a row of the conductive contact pins 3 with an insulation region 290c interspersed therebetween.
• the conductive contact pins 3 are arranged in two rows having a specific distance therebetween in a substrate 2d.
• any of the conductive layers that configure the C component layer arranged in the substrate 2d may be segmented into, for example, corresponding rows of segmented regions 222d and 222'd with an insulation region 290d interspersed therebetween.
• IC device socket 1, 2a, 2b, 2c, 2d... substrate; 21... base material; 22 to 25, 2000, 2000a, 2000b, 3000, 4000, 5000... dielectric layer; 222, 222', 222a, 222'a, 222b, 222'b, 222c, 222'c, 222d, 222'd, 232, 232', 242, 242', 252, 252', 2100, 2100a, 2100b, 3100, 3100a, 3100b, 4100... power layer; 224, 224', 234, 234', 244, 244', 254, 254', 2200, 2200a, 2200b, 3200, 4200... GND layer; 28 ...
• Embodiment 1 is an IC device socket comprising: a substrate having a first surface, a second surface facing the first surface, and plurality of through-holes that each communicate with the first surface and the second surface; and a plurality of conductive contact pins, a portion of which is inserted into any of the plurality of through holes; wherein the substrate comprises: a base material having the first surface, the second surface, and the plurality of through holes; at least one dielectric layer provided between the first surface and the second surface in an intersecting state with the plurality of through holes, the dielectric layer having a permittivity higher than that of the base material; and a first and a second conductive layer sandwiching the dielectric layer along a direction in which the first surface of the base material faces the second surface; wherein the plurality of conductive contact pins comprises: a plurality of first conductive contact pins, a portion of which is inserted into any of the plurality of through holes,
• Embodiment 2 is the IC device socket according to embodiment 1 wherein, the insulation region has a shape in which one surface thereof extends to reach the first surface of the base material, and another surface thereof opposing said one surface extends to reach the second surface of the base material.
• Embodiment 3 is the IC device socket according to embodiment 2 wherein, at least a portion of the insulation region is an air gap.
• Embodiment 4 is the IC device socket according to embodiment 1 wherein, any of the plurality of through holes is provided with a conductive member on an inner surface thereof, and the first conductive layer is electrically connected at least to any of the plurality of first conductive contact pins via the corresponding conductive member, and the second conductive layer is electrically connected via the corresponding conductive member to any of the plurality of first conductive contact pins other than those connected to the first conductive layer.
• Embodiment 5 is the IC socket according to embodiment 1 , further comprising a body that supports the substrate; wherein the body includes a guide portion that arranges an IC device to be inspected at a specific position on the substrate, and a positioning portion that arranges the IC device socket at a specific position of an inspecting device for inspecting the IC device.

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• Connecting Device With Holders (AREA)
• Testing Of Individual Semiconductor Devices (AREA)

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• 2011
  • 2011-02-01 JP JP2011019937A patent/JP6157047B2/ja not_active Expired - Fee Related
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