WO2012106103A1

WO2012106103A1 - Socket for ic device

Info

Publication number: WO2012106103A1
Application number: PCT/US2012/021504
Authority: WO
Inventors: Yoshihisa Kawate; Yuichi Tsubaki
Original assignee: 3M Innovative Properties Company
Priority date: 2011-02-01
Filing date: 2012-01-17
Publication date: 2012-08-09
Also published as: TW201246728A; JP2012159425A; JP6157048B2; TWI545860B

Abstract

The present invention relates to an IC device socket equipped with a structure that can effectively suppress instability of a power supply due to decreased voltages and higher speeds of an IC device. The IC device socket (1) includes a dielectric layer arranged so as to configure a capacitor in a space between a first surface (26) and a second surface (27) of a base material (21) composed of insulating materials, and a power layer (2104) and a GND layer (2201) formed on both sides of the dielectric layer. A surface area defined by an outermost perimeter of at least the power layer (2103) among the power layer (2103) and the GND layer (2201) is set to be smaller than a surface area defined by an outermost perimeter of the first surface (26), and a capacitance between the power layer (2103) and the GND layer (2201) is controlled by changing the surface area of a portion (AR) in which the power layer (2103) and the GND layer overlap as seen from the first surface (26) toward the second surface (27).

Description

SOCKET FOR IC DEVICE

Field of Invention

The present invention relates to a socket for an IC device used in inspecting CPUs, memories, and other types of semiconductor integrated circuits (hereinafter called "IC"), and in particular to an IC device socket equipped with a capacitor function for semiconductor package testing.

Related Technology

When conducting tests for evaluating signal transmission properties and the like of ball grid array (BGA) devices and other IC devices, a socket (hereinafter called an "IC device socket") is used having contacts that can each be electrically connected to terminals of the IC device. Recently, signals handled by IC devices tend to be high-frequency wave signals accompanying increases in processing speeds. IC device sockets are expected to be able to transmit high-speed signals corresponding to the higher speeds of these signals. Moreover, operating voltages of power supplies for IC devices continue to be lowered to reduce power consumption in electrical apparatuses. Thus there is a need to provide a stable power supply for an IC device so that the IC device can operate stably at high speeds. Providing a stable power supply is becoming more and more important but also more difficult due to the increased speeds and lower voltages of IC devices.

Controlling the impedance of the power supply and ground throughout high-frequency regions is important to allow for stable power supply during high-speed IC device operations. The self-inductance of conductive contact pins included in such an IC device socket is desirably lowered for IC device sockets. As a result, thick and short conductive contact pins are generally considered preferable.

Another method corresponding to an IC device socket focusing on high-speed signal transmission is disclosed in International Publication Pamphlet No. 2005-006003. As disclosed in International Publication Pamphlet No. 2005-006003, "an LSI socket 101 in accordance with the present invention is composed of three components: a printed board 102, pogo-pins 103, and a pogo-pin supporting casing portion 104. The printed board 102 is provided with a plurality of through holes 109 into which a first power supply pin 105 and a second power supply pin 106 in which voltage values to be applied are different, a GND pin 107, and the pogo-pin 103 coming into use as a signal pin 108 are each inserted, plating layers 1 16 being formed in inner surfaces of all the through holes 109 other than the through hole 109 through which the signal pin 108 passes."

As disclosed in Japanese Unexamined Patent Application Publication No. 2009-85948,

"generally, a capacitor for a power supply probe device is mounted on a wiring pattern as electrically close as possible to a device over a wiring substrate of a detecting socket bottom side," and "a chip capacitor must be mounted at a position directly below a detected device and at an upper part of a detecting socket."

Background Art Documents

Patent Documents

[Patent reference 1] International Publication Pamphlet No. 2005-006003

[Patent reference 2] Japanese Unexamined Patent Application Publication No. 2009-85948

Background

The inventors discovered the following problems according to results from examining conventional IC device sockets. Specifically, the conductive contact pin described above is preferably made thick and short. However, the thickness of the conductive contact pin is necessarily limited by the narrowing of the pitch between the IC device terminals. Meanwhile, the reliability of conductive contact pins decreases as they are used repeatedly, and thus they are generally replaced as needed due to the high cost of conductive contact pins. Therefore, conductive contact pins are required to have a certain length or longer in consideration of workability when replacing the conductive contact pins. Additionally, when spring probes are used for conductive contact pins, the operating length of the plunger is shortened if the probe length is short, and a beneficial contact state between the IC device terminals and such spring probes cannot be assured if the substrate or the semiconductor package is not flat.

Alternatively, an increase of impedance due to signal pin inductance caused by directly connecting a capacitor to the conductive contact pin power supply pin and ground pin mounted in the IC device socket or IC device socket housing is restituted by the capacitance of the capacitor thus lowering the impedance. However, the volume occupied by the IC device socket increases when the capacitor is directly connected to the conductive contact pins or the IC device socket housing. In this case, there is a fear that this may interfere with the arrangement of the conductive contact pins of the IC device socket in a high density pattern. Even if the capacitor can be arranged and connected close to the substrate or the housing of the IC device socket, the capacitor may only be able to be arranged and connected in a position several millimeters away from the conductive contact pins. In this case, there is a fear that the capacitor effects may not be effective due to self- inductance caused by the length of the wiring to the capacitor.

The present invention has a basic structure for solving the above problem. Specifically, the present invention is equipped with a structure that allows for stable operation of the IC device through characteristics provided on the socket side without causing a reduction in workability when exchanging the conductive contact pins.

Recently, the stability of the power supply has become increasingly important to allow for stable operation of IC devices accompanying the lower voltage and higher speeds of IC devices such as LSI devices and the like (in a low voltage drive IC device, lowering the impedance using a power distribution network (herebelow called a PDN) is important, and in high-speed operation IC devices, a reduced impedance of the PDN up through high frequencies is required). To allow for the suitable operation of an IC device in this way, a low impedance of the PDN is crucial and the impedances of the power supply paths and ground paths in the PDN need to be effectively reduced. The above PDN is made up of a circuit substrate (wiring and the like) of an inspection device, an IC device package, or the like, and circuit elements of an IC device socket arranged between the IC device and the circuit substrate. For example, in the basic structure of the present invention, a power layer and a ground layer are embedded inside a socket substrate through insulating materials such that the impedances of the power supply paths and the ground paths as seen throughout the entire PDN can be reduced to a certain extent due to the capacitor functions in the power supply and ground layers.

Conversely, the frequency response of each impedance of the power supply paths and the ground paths can be considered as a frequency response of the circuit elements that make up the above PDN. Specifically, since a conductor behaves as inductance and the relationship between two conductors such as the power layer and the ground layer are seen as capacitance and mutual inductance, the PDN behaves as one circuit made up of a plurality of inductances, capacitances, and resistances. As a result, the inductances of the power supply paths and the ground paths in the PDN exhibit frequency dependence and an increase in the total PDN inductance from characteristic frequencies caused by resonance and antiresonance may occur. When the PDN inductance increases in this way, careful control of the power supply becomes important due to the loss of power supply stability.

The present invention is formed to solve the above problem, and an object thereof is to provide an IC device socket equipped with a structure that can effectively suppress destabilization of the power supply due to the decreased voltages and higher speeds of IC devices.

Summary

To solve the above problem, an IC device socket according to the present invention includes a substrate and a plurality of conductive contact pins. The substrate includes a first surface, a second surface facing the first surface, and a plurality of through holes that each communicate with the first surface and the second surface and that are each provided with conductive material on an inner surface thereof. The plurality of conductive contact pins are held by the substrate in a state in which some of the conductive contact pins are inserted into any of the plurality of through holes. The substrate includes a base material, a dielectric layer, a first conductive layer, and a second conductive layer. The base material includes the first surface, the second surface, and the plurality of through holes. The dielectric layer is provided between the first surface and the second surface of the base material in an intersecting state with the plurality of through holes and has a permittivity higher than the base material. The first and second conductive layers of the base material sandwich the dielectric layer along a direction from the first surface of the substrate toward the second surface.

The IC device socket according to the present application is formed as a substantially integrated substrate by the dielectric layer and the conductive layer that make up the capacitor and the base material embedded in the dielectric and the conductive layers. Thus, the distance between the conductive contact pins and the capacitor is extremely small, and as a result the performance of such an IC device socket may be improved. Moreover, the conductive contact pins are held by being press fit into the base material. The base material functions as a support of the conductive contact pins thus removing the need for another component to support the conductive contact pins.

A particular feature of the IC device socket according to the present invention is that a surface area defined by an outermost perimeter of at least one of the first or second conductive layer is smaller than a surface area defined by an outermost perimeter of the first surface.

This plurality of conductive contact pins includes a plurality of first conductive contact pins and a plurality of second conductive contact pins that have a connection state different from the plurality of first conductive contact pins. Specifically, the plurality of first conductive contact pins is inserted in any of the plurality of through holes to make contact with conductive material corresponding to the groups. The plurality of second conductive contact pins is inserted in any of the plurality of through holes but remains in a state of non-contact with the first or second conductive layers. This state of non-contact refers to non-contact with conductive material corresponding to the pins, or to the corresponding conductive material being in a state of non-contact with the first and second conductive layers. In this case, the first conductive layer is electrically connected to any of the plurality of first conductive contact pins via the corresponding conductive material. Conversely, the second conductive layer is electrically connected to any of the plurality of first conductive contact pins other than those connected to the first conductive layer via the corresponding conductive material.

The above plurality of first conductive contact pins of the IC device socket according to the present invention are divided into a first group (e.g., a power supply pin group) that is electrically connected to only the first conductive layer, and a second group (e.g., a ground pin group) that is electrically connected to only the second conductive layer. Moreover, a plurality of second conductive contact pins not electrically connected to either the first or second conductive layers function as signal pins.

Note that the outermost perimeter of at least one of the first or second conductive layer is preferably positioned not less than 25 μηι to an inside of the outermost perimeter of the first surface of the substrate (or base material) in the IC device socket according to the present invention.

The IC device socket according to the present invention has a commutative structure as one PDN circuit element, and exhibits capacitance freely accommodated inside the substrate that holds the plurality of conductive pins. Power supply instability accompanying a low-voltage high-speed IC device can be effectively suppressed by incorporating the IC device socket as one PDN circuit element in this way.

Brief Description of the Drawings

FIG. 1 is a perspective view of a structure of a first embodiment of the IC device socket according to the present invention.

FIG. 2 shows a cross-section of the IC device socket shown in FIG. 1 along the line II - II.

FIG. 3 is a plan view of a structure of a substrate of the IC device socket shown in FIG. 1.

FIG. 4 is an enlarged view of a portion III of the cross-section structure shown in FIG. 2.

FIG. 5 describes a surface area of a power layer.

FIG. 6 shows a first arrangement example of a power layer facing a front surface of the substrate. FIG. 7 shows a second arrangement example of a power layer facing a front surface of the substrate.

FIG. 8 shows a sterical view of a conductive layer arrangement of a section near a through hole indicated in the portion V in FIG. 3.

FIG. 9 is a first plan view of a substrate of the IC device socket according to the present embodiment and describes another example of a positional relationship of the conductive layer divided into pin arrangements (part 1).

FIG. 10 is a second plan view of a substrate of the IC device socket according to the present embodiment and describes another example of a positional relationship of the conductive layer divided into pin arrangements (part 2).

FIG. 1 1 is a third plan view of a substrate of the IC device socket according to the present embodiment and describes another example of a positional relationship of the conductive layer divided into pin arrangements (part 3).

FIG. 12 is a fourth plan view of a substrate of the IC device socket according to the present embodiment and describes another example of a positional relationship of the conductive layer divided into pin arrangements (part 4).

Detailed Description

Embodiments of the IC device socket according to the present invention will be described below with reference to FIGS. 1 to 12. In the various figures, like references designate identical or similar elements and overlapping descriptions will be omitted.

A basic structure of the IC device socket according to the present embodiments will be described in detail herein with reference to FIGS. 1 to 4.

FIG. 1 is a perspective view of a structure of a first embodiment of the IC device socket according to the present invention. FIG. 2 shows a cross-section of the IC device socket shown in FIG. 1 along the line II - II. FIG. 3 is a plan view of a structure of a substrate 2 of the IC device socket 1 shown in FIG. 1. The arrow L in FIG. 3 substantially matches the line II - II in FIG. 2. An IC device socket 1 includes the substrate 2, a plurality of conductive contact pins 3 that are held by press fitting or the like in the substrate 2, and a guide body 4 that supports the substrate 2. The guide body 4 includes a guide portion or guide wall 41 for arranging an IC device (not shown) to be inspected in a specific position on the substrate 2, and further includes a positioning unit (a positioning pin 42 shown in FIG. 2 in the present embodiment) for arranging the IC device socket 1 in a specific position in an inspection device (not shown) for inspecting IC devices. The guide body 4 may be incorporated into the IC device socket 1 as needed. Moreover, the substrate 2 may have a positioning hole or notch to work in concert with positioning means.

FIG. 4 is an enlarged view of a portion III of the cross-section structure shown in FIG. 2. As shown in FIG. 4, the substrate 2 includes a base material 21 made up of a dielectric such as glass fiber epoxy resin, and at least one (four are shown as an example in FIG. 3) dielectric layer 22 to 25 (a first to fourth dielectric layer) embedded in the base material 21 , and a conductive layer of copper and the like is formed on the upper and lower surfaces of the dielectric layers. Therefore, the dielectric layers and the conductive layers formed on both surfaces thereof work in concert to compose a capacitor. Specifically, the substrate 2 is formed by stacking materials (a portion of the base material) composing the base material 21 , the conductive layers, and the dielectric layers. Permittivity of the dielectric layers is preferably high to improve the capacity of the capacitor. For example, the dielectric layers 22 to 25 are preferably made up of a high dielectric having a permittivity higher than the permittivity of the base material 21. For example, Embedded Capacitor Material (ECM) manufactured by 3M may be used as a high dielectric. ECM is made of dielectric material formed as a flexible sheet. This type of substrate may be manufactured using a method for manufacturing a printed circuit board.

The material making up the substrate 2, that is the base material 21 material, may include paper in place of glass fiber, and may include phenol resin or polyamide resin in place of epoxy resin. Silver or gold may also be used in place of copper as the material composing the conductive layers. The dielectric layers 22 to 25 may each include a polymer. The dielectric layers 22 to 25 preferably each include a polymer and a plurality of particles, and in particular are manufactured by mixing the resin and the particles. Desirable resins include epoxy, polyamide, polyvinylidene fluoride, cyanoethyl pullulan, benzocyclobutene, polynorbornene, polytetrafluoroethylene, acrylate or a combination thereof. The particles include dielectric (or insulating) particles, and representative examples include barium titanate, barium strontium titanate, titanium oxide, lead zirconium titanate, or a combination thereof.

The thickness of each of the dielectric layers 22 to 25 may be for example 0.5 μηι or greater, and 100 μηι or less. The thickness of the dielectric layers is preferably thinner, for example having a thickness of 15 μηι or less or 10 μηι or less, since the electrostatic capacity of the capacitors can be improved. However, the thickness of the dielectric layers preferably is, for example a thickness of 1 μηι or more from the point of view of bonding strength.

Moreover, the relative permittivity of the dielectric is preferably high, for example 10 or more, or 12 or more. Although there is no particular restraint on the upper limit, the relative permittivity may be for example 100 or less, 40 or less, or 20 or less.

It is beneficial to allow for a small distance between two adjacent capacitors by using a material having a high permittivity for the dielectric layers 22 to 25. When two capacitors are adjacent to each other, electrostatic capacity is formed between the power layer that composes one capacitor and the ground layer (hereinbelow referred to as GND layer) that composes the other adjacent capacitor. When using a high dielectric between conductive layers to preferably form electrostatic capacitance, the electrostatic capacitance generated by the one capacitor increases even when the distance between a dielectric layer that forms one capacitor is the same as the distance between two adjacent capacitors. The distance between adjacent capacitors can be made relatively small thus contributing to the manufacturing of a thin substrate 2.

One of the conductive layers formed on either side of the dielectric layers 22 to 25 is composed of a power layer electrically connected to power supply pins of the IC device socket 1, and the other conductive layer composes a GND layer electrically connected to ground pins (hereinbelow referred to as GND pins) of the IC device socket 1. Specifically, a first power layer 222 is formed on an upper surface 221 of the first dielectric layer 22 closest to a surface 26 (upper surface in FIG. 2) on the IC device side of the substrate 2, and a first GND layer 224 is formed on a lower surface 223. Similarly, a second power layer 232 is formed on an upper surface 231 of the second dielectric layer 23 positioned directly below the first dielectric layer 22, and a first GND layer 234 is formed on a lower surface 233. Further, a fourth power layer 252 is formed on an upper surface 251 of the fourth dielectric layer 25 closest to a surface 27 (lower surface in FIG. 2) on the inspection device side of the substrate 2, and a fourth GND layer 254 is formed on a lower surface 253. Similarly, a third power layer 242 is formed on an upper surface 241 of the third dielectric layer 24 positioned directly above the fourth dielectric layer 25, and a third GND layer 244 is formed on a lower surface 243. The basic structure illustrated in FIG. 4 shows that the upper surface 26 of the substrate 2 matches the upper surface of the base material 21 , and the lower surface 27 of the substrate 2 matches the lower surface of the base material 21.

The first power layer 222 has substantially the same electric potential as the third power layer

242, and the second power layer 232 has substantially the same electric potential as the fourth power layer 252. Similarly, the first GND layer 224 has substantially the same electric potential as the third GND layer 244, and the second GND layer 234 has substantially the same electric potential as the fourth GND layer 254. The dielectric layers and the conductive layers formed on both sides thereof are arranged throughout the whole substrate 2. Therefore, it is possible to form a surface area of the capacitor that is substantially equal to the surface area of the substrate 2.

Each of the conductive contact pins 3 penetrates the substrate 2 in a substantially vertical direction through the upper layer 26 and the lower layer 27 of the substrate 2. Specifically, through holes 28 in which the conductive contact pins 3 can be inserted are formed in the base material 21 as well as the dielectric layers and the conductive layers formed on both sides thereof that make up the substrate 2. A conductive material 281 of copper, gold, silver, or the like is formed by plating or the like on the inside surface of the through holes 28. Except for the conductive contact pins 3 that are signal pins, pin bodies 31 of the conductive contact pins 3 fitted into the through holes 28 are electrically connected to any of the conductive layers through the conductive material 281 according to a conductive connection of the conductive material 281 to any one of the conductive layers. The inner surface of holes for signal pins may or may not be formed with the conductive material 281.

The dimensions of the through holes 28 are determined so as to allow the conductive contact pins 3 to be held in the through holes without falling out due to a counterforce of springs mounted in the conductive contact pins 3 generated when arranging the IC device socket 1 on the inspecting device substrate. For example, a press fit gripping force of the conductive contact pins 3 is preferably 0.1 N or greater. The dimensions of the through holes 28 are determined in such a way that the conductive contact pins 3 may be removed fairly easily when replacing or maintaining the conductive contact pins 3.

Additionally, the dimensions of the through holes 28 are determined in such a way that the conductive material 281 on the inner surface of the through hole 28 is not peeled off when removing the conductive contact pins 3 from the substrate 2. For example, a press fit gripping force of the conductive contact pins 3 is preferably no more than 2.0 N.

Each of the conductive contact pins 3 include the substantially cylindrical pin body 31 that is held by press fitting in the substrate 2, a first contact portion 32 that is electrically contactable, i.e., conductively connects with, the inspection device (not shown) by protruding from one end (the lower end in FIG. 3) of the pin body 31, and a second contact portion 33 that is electrically contactable, i.e., conductively connects with, the IC device (not shown) by protruding from the other end (the upper end in FIG. 3) of the pin body 31. Although various modes are applicable as conductive contact pins 3, those such as, for example, so-called spring probe types, in which both contact portions 32 and 33 can be displaced in relation to the pin body 31 by a spring and the like (not shown) in the axial direction of the pin body 31, are preferable.

The pin bodies 31 of the conductive contact pins 3 are preferably cylindrical in shape. When the conductive contact pins 3 are shaped in this way, the conductive contact pins 3 can be easily arranged in a substantially axial direction of the through holes 28 since the outer surface of the pin bodies 31 make contact with the through holes 28 throughout a wide surface area. An electrically stable connection can be realized since the contact surface area of the conductive material 281 and the conductive contact pins 3 is increased.

The conductive contact pins 3 are divided into a power supply pin group electrically connected to the power layer described above, a GND pin group connected to the GND layer, and a signal pin group not connected to any of the layers. For example, as shown in FIG. 3, conductive contact pins 3b and 3i are each connected to both the first power layer 222 and the third power layer 242 to function as first power supply pins. Conductive contact pins 3c and 3f are each connected to both the second power layer 232 and the fourth power layer 252 to function as second power supply pins. Similarly, conductive contact pins 3a and 3h are each connected to both the first GND layer 224 and the third GND layer 244 to function as first GND pins. Conductive contact pins 3d and 3g are each connected to both the second

GND layer 234 and the fourth GND layer 254 to function as second GND pins. The conductive contact pin 3e is not connected to any of the conductive layers and thus functions as a signal pin.

According to the present basic structure, the substantially integrated substrate 2 is formed from the dielectric layers and the conductive layers formed on both sides thereof that make up the capacitor, and the base material that embeds the dielectric and conductive layers. Thus, the distance between the conductive contact pins 3 and the capacitor is extremely small, and as a result the performance of the IC device socket 1 may be improved. Moreover, the conductive contact pins 3 are held (or preferably press fit) by friction force in the substrate 2. As a result, the substrate 2 acts as a support of the conductive contact pins 3 thus removing the need for another component to support the conductive contact pins 3. Specifically, the conductive contact pins 3 are substantially held and positioned by only the substrate 2.

Additionally, further thinning of the substrate 2 can be achieved by using the dielectric layers made up of high dielectrics.

As shown in FIG. 4, the capacitors made up of the power layers sandwiched by the high dielectrics (dielectric layers) of the substrate 2 and the GND layers are preferably provided at positions as close as possible to the upper surface 26 and the lower surface 27 (respectively matching the upper and lower surfaces of the base material 21), i.e., the outsides, of the substrate 2. The reason for this is that a desirable power supply stability can be achieved during IC device inspections when the distances between the conductive layers and the outer surfaces of the substrate 2 are small. More specifically, the smaller the distance between the upper surface 26 of the substrate 2 and the first and second dielectric layers 22 and 23, the greater the input sensitivity of the IC device subject to inspection. Therefore, the first and second dielectric layers 22 and 23 are preferably arranged toward the upper surface 26 side compared to a midway point between the upper surface 26 and the lower surface 27 of the substrate 2. Additionally, the third and fourth dielectric layers 24 and 25 are preferably arranged toward the lower surface 27 side compared to a midway point between the upper surface 26 and the lower surface 27 of the substrate 2. In the present basic structure, the substrate 2 is formed as a substantially integrated object in which are embedded dielectric layers made up of high dielectrics sandwiched by power layers and GND layers. As a result, a structure in which the capacitors are arranged near the outer surfaces of the substrate 2 can be easily realized, thus allowing for accurate IC device inspections.

Specifically, the conductive contact pins 3 are substantially held by only the substrate 2. As a result, the capacitor may be arranged at any position in the substrate 2. Moreover, the substrate 2 may further include near the center thereof in the thickness direction a capacitor made up of a dielectric layer and conductive layers formed on both sides thereof.

The length of each conductive contact pin 3 is preferably shorter from the point of view of electrical characteristics and the like. However, as the length of the conductive contact pins 3 becomes shorter, the operation and assembly when replacing the pins become more difficult. Conversely, according to the present basic structure, there is no need to consider a drop in performance of the IC device socket 1, even when using relatively long conductive contact pins 3, since similar effects on electrical characteristics at or below a desired frequency can be achieved when shorter pogo pins are actually used due to the structure of the substrate 2 and the control of the capacitance value.

If the length of the pin bodies 31 is longer than the thickness of the substrate 2, the conductive contact pins 3 also become effectively longer thus reducing the electrical characteristics. Conversely, if the length of the pin body 31 is shorter than the thickness of the substrate 2 such that the axial direction ends of the pin body 31 are positioned farther toward the substrate center than any of the conductive layers, the paths from the conductive contact pins 3 to reach the conductive layers become complex, thus reducing the performance of the IC device socket. Therefore, the axial direction length of the pin bodies 31 of the conductive contact pins 3 is preferably approximately equal to the thickness of the substrate 2.

In addition, the abovementioned IC device socket 1 having the basic structure of the present invention includes, for example, a structure in which the four dielectric layers 22 to 25 (with power layers and GND layers formed on both sides of each of the dielectric layers 22 to 25) are stacked via portions of the base material 21. According to this structure, different power supply settings and different ground settings are possible inside one package with the IC device socket 1 , since different electric potential settings are possible with, for example, the first power layer 222 and the second power layer 224.

Impedance of the power supply system and ground paths in the PDN that includes the IC device socket 1 can be suppressed to a degree since a capacitor function can be realized inside the substrate 2 by the sandwiching of the dielectric layer with the power layer and the GND layer to improve signal transmission efficiency at high frequencies in the basic structure of the present invention as described above. However, in order to more effectively improve the stability of the power supply accompanying the lower voltage and higher speeds of IC devices, the IC device socket according to the present invention achieves a capacitance value that can be freely accommodated by using the structure realized by the capacitor function inside the substrate 2. Specifically, since the IC device socket has a structure that can be incorporated in a PDN that acts as a power supply supply for the IC device, the IC device socket can function as a principal element for controlling the impedance of the entire PDN. For example, impedance made up of inductance L and resistance R is given by the equation (R + jcoL) and by the equation (R + jcoL + 1 / (jcoC)) when capacitance C is directly connected (ω = 2πί, where f is frequency). By adding capacitance C, the effect of capacitance on impedance becomes dominant with low frequencies on one hand, and the effect of inductance on impedance becomes dominant with high frequencies on the other. As can be seen from the above equations, a circuit made up of a plurality of capacitances C and a plurality of inductances L shows complex behavior according to the frequencies. Therefore, by adding a plurality of different values of capacitance, it is possible to control impedance in a wide range of frequencies.

Conventionally, when capacitance affects only the impedance of a PDN in low frequency regions, adding one capacitance is enough. However, in high frequency regions, more precise control is necessary to maintain the impedance value at or below a desired level.

Since capacitance of a parallel plate capacitor is given by the equation ε * (S / d), where S is surface area, d is the distance between conducting plates, and ε is permittivity, a higher capacitance value can be achieved by providing a wider surface area. However, the capacitance value can be changed by modifying the surface area in order to conduct precise controls.

In view of the above technical considerations, a surface area defined by the outermost perimeter of at least one of the power layer or the GND layer that sandwiches the dielectric layer is set to be smaller than a surface area defined by the outermost perimeter of the upper surface 26 (or lower surface 27) of the substrate 2 (or the base material 21) such that a desired capacitance value can be achieved.

For simplification in the example explained below, the power layer in relation to the upper surface 27 and the lower surface 26 of the substrate 2 has a small surface area in relation to the upper surface 27 and the lower surface 26 of the substrate 2 on the one hand, and the GND layer that configures the capacitor via the power layer and the dielectric layer has a surface area that matches the upper surface 26 and the lower surface 27 of the substrate 2 on the other.

FIG. 5 describes a surface area of a power layer. FIG. 5 is a plan view of a structure of a portion of a power layer 2101 that corresponds to the portion IV in the plan view shown in FIG. 3. As shown in FIG. 5, the power layer 2101 is provided with two types of openings 280a and 280b having different diameters at positions corresponding to the through holes 28 provided in the substrate 2. The two types of openings 280a and 280b provided in the power layer 2101 are arranged in a direction along the arrow LI in FIG. 5, the arrow LI matching the line L in FIG. 3. The opening 280a has a diameter substantially matching the diameter of the through holes 28, or more specifically, has a bore diameter that allows a suitable electric contact to be maintained with the conductive material 281 formed on the inner surface of the through holes 28 and the power layer 2101. Conversely, the opening 280b has a diameter larger than the diameter of the through holes 28, or more specifically, has a bore diameter, for example, about 50 μηι larger than the diameter of the through holes 28 and can maintain a suitable electrically separated state from the conductive material 281 formed on the inner surface of the through holes 28 and the power layer 2101.

The GND layer also has a planar shape having two types of openings with different diameters similar to the abovementioned power layer 2101.

In the example shown in FIG. 5, the power layer 2101 is not arranged over the entire surface of the substrate 2 as described in the basic structure described above. Specifically, in the example shown in FIG. 5 in which the GND layer is arranged over the entire substrate 2 surface, the surface area of a region (region composing the capacitor) in which the GND layer and the power layer 2101 overlap, when seen along a direction from the upper surface 26 of the substrate 2 toward the lower surface 27, is

accommodated by modifying the surface area of the power layer 2101. Specifically, the surface area of the power layer 2101 is defined as the surface area of a region surrounded by a solid line S222 that indicates the outermost perimeter of the power layer 2101. Although the openings 280a and 280b are present inside the region surrounded by the solid line 222, the surface area occupied by the surface area of the openings 280a and 280b is not considered in the above definition of the surface area of the power layer 2101.

Next, examples of arrangements of power layers on the substrate 2 will be described with reference to FIGS. 6 and 7. In a first arrangement example shown in FIG. 6, a planar shape of a power layer 2102 has a similar shape to the substrate 2. However, the surface area of the power layer 2102 defined by the outermost perimeter thereof is smaller than the surface area of the upper surface 26 or the lower surface 27 of the substrate 2 defined by the outermost perimeter (solid line in FIG. 6) thereof. Specifically, the outermost perimeter of the power layer 2102 is positioned toward the inside of the substrate 2 by not less than 25 μηι from the outermost perimeter (solid line in FIG. 6) of the substrate 2.

When a parallel plate capacitor is configured by a structure in which a high permittivity dielectric layer is sandwiched by two conductive layers, a higher capacitance value can be achieved as the distance between the two conductive layers becomes smaller. Thus, the parallel plate capacitor with a small distance between conductive layers is employed to allow for a wide range of modifications of the capacitance value. However, in a substrate manufacturing process, defects may occur when the contour of the substrate is mechanically formed using a router or mold, or when holes are drilled in the substrate using a drill. Specifically, when the edges of both of the two conductive layers touch the outer surface of the substrate, the two conductive layers may short-out in the substrate forming process. As a

countermeasure, the substrate manufacturing yield rate is improved by offsetting the outermost perimeter of the conductive layer to the inside of the outermost perimeter of the substrate. Further, after making the planar shape of the conductive layer in the substrate manufacturing process, other defects may occur when forming the capacitor by thermal compression of the conductive layers on the dielectric layer, or when drilling holes in the substrate with a drill. Specifically, the complete removal of positional aberrations between the two conductive layers that sandwich the dielectric layer is impossible. Therefore, it is effective to set the outermost perimeter of the conductive layers not less than 25 μηι, or preferably not less than 50 μηι to the inside of the outermost perimeter of the substrate.

In the example shown in FIG. 7, a planar shape of a power layer 2103 is shaped differently than the substrate 2. The power layer 2103 may not include an entire region arranged with the conductive contact pins 3. In a first arrangement example shown in FIG. 7, the surface area of the power layer 2103 defined by the outermost perimeter thereof is smaller than the surface area of the upper surface 26 or the lower surface 27 of the substrate 2 defined by the outermost perimeter (solid line in FIG. 7) thereof.

An example of an arrangement relationship between the power layer having the planar shape described above and the GND layer is shown in FIG. 8. FIG. 8 shows a sterical view of a conductive layer arrangement of a section near a through hole indicated in the portion V in FIG. 3, and shows a structure near a through hole in which a conductive contact pin 3 that functions as a signal pin is inserted. The dielectric layer as well as insulating materials that make up a portion of the base material are omitted from FIG. 8.

As shown in FIG. 8, the conductive material 281 is formed on the inner surface of the through hole 28 through which the conductive contact pin 3 that functions as a signal pin is inserted, and the opening 280a in a power layer 2104 and the opening 280b in the GND layer 2201 are positioned at the position of the conductive material 281. According to this structure, the power layer 2104 is electrically contacting the conductive material 281 , and the GND layer 2201 is electrically separated from the conductive material 281 due to the opening 280b. The capacitance value of the capacitor configured by the power layer 2014 and the GND layer 2201 configured in this way is accommodated by the surface area of a region AR in which the power layer 2104 and the GND layer 2201 overlap, as seen in the direction from the upper surface 26 of the substrate 2 toward the lower surface 27 (in the direction along the central axis AX of the through hole 28).

In the above embodiment, while the GND layer is arranged over the entire surface of the substrate 2, the capacitance value of the IC device socket 1 is accommodated by accommodating the surface area of the power layer. However, the present invention is not limited to this embodiment. The IC device socket according to the present invention can be realized by a structure in which the surface area of the GND layer is accommodated while the power layer is arranged over the entire surface of the substrate 2. For example, it is obvious that the surface areas of both the power layer and the GND layer may be smaller than the surface areas of the upper surface 26 or the lower surface 27 of the substrate 2. Moreover, the surface areas of the power layer and the GND layer do not necessarily have to be different. The surface areas of the power layer and the GND layer that make up the capacitor may match, as long as these are smaller than the surface areas of the upper surface 26 or the lower surface 27 of the substrate 2.

The IC device socket according to the present invention as described above has a commutative structure as one PDN circuit element for supplying power to the IC device, and exhibits capacitance that can be freely accommodated inside the substrate that holds the plurality of conductive pins. Power supply instability accompanying a low-voltage, high-speed IC device can be effectively suppressed by incorporating the IC device socket as one PDN circuit element in this way.

Further, the arrangement of the conductive contact pins 3 held by the substrate 2 in the IC device socket 1 according to the present invention can employ various arrangement patterns without being limited to the rectangular shapes as shown in FIGS. 3, 6, and 7. Additionally, the surface area and the shape of the conductive layer (power layer and/or GND layer) divided by sequential patterns of the employed conductive contact pins 3 can be freely set. An example of such is shown in FIGS. 9 to 12. FIGS. 9 to 12 are plan views of substrates of IC device sockets according to the present embodiment and describe other examples of positional relationships of the conductive layers divided into pin

arrangements. The FIGS. 9 to 12 follow the examples in FIGS. 6 and 7 and positional relationships of elements (a conductive layer provided on one surface of one of the dielectric layers) corresponding to the substrate 2 and the conductive layer are indicated.

In the example shown in FIG. 9, the conductive contact pins 3 in a substrate 2a are arranged in a rectangular ring region sandwiched by a rectangular outer perimeter and a rectangular inner periphery; and the conductive layer arranged inside the substrate 2a is divided by an insulation region 2900a into two segmented regions 2105a and 2105b in the horizontal direction. The segmented regions 2105a and 2105b each have surface areas smaller than either of the upper surface 26 or the lower surface 27 of the substrate 2a, and shapes of the segmented regions 2105a and 2105b can be set freely.

In the example shown in FIG. 10, the conductive contact pins 3 are arranged in an inside rectangular region and also in a rectangular ring region that surrounds the inside rectangular region in a substrate 2b. In this case, the conductive layer arranged inside the substrate 2b may be divided, for example, by allowing a segmented region 2106a to surround a segmented region 2106b, for example via an insulation region 2900b, such that different electric potentials can be set for the segmented regions 2106a and 2106b. The segmented regions 2106a and 2106b each have surface areas smaller than either of the upper surface 26 or the lower surface 27 of the substrate 2b, and shapes of the segmented regions 2106a and 2106b can be set freely.

In the example shown in FIG. 1 1, the conductive contact pins 3 are arranged along an outermost perimeter of a rectangular region in a substrate 2c. In this case, the conductive layer arranged inside the substrate 2c is divided, for example via the insulating region 2900c, into segmented regions 2107a and 2107b with shapes that follow the sequential arrangement of the conductive contact pins 3 such that different electric potentials can be set for the segmented regions 2107a and 2107b. The segmented regions 2107a and 2107b each have surface areas smaller than either of the upper surface 26 or the lower surface 27 of the substrate 2b, and shapes of the segmented regions 2107a and 2107b can be set freely.

In the example shown in FIG. 12, the conductive contact pins 3 are arranged in two rows having a specific distance therebetween in a substrate 2d. In this case, the conductive layer arranged inside the substrate 2d may be divided, for example via an insulation region 2900d, into segmented regions 2108a and 2108b corresponding to the rows such that different electric potentials can be set for the segmented regions 2108a and 2108b. The segmented regions 2108a and 2108b each have surface areas smaller than either of the upper surface 26 or the lower surface 27 of the substrate 2d, and shapes of the segmented regions 2108a and 2108b can be set freely.

1... IC device socket; 2, 2a, 2b, 2c, 2d... substrate; 21... base material; 22 to 25 ... dielectric layer; 222, 232, 242, 252, 2101 to 2104, 2105a, 2105b, 2106a, 2106b, 2107a, 2107b, 2108a, 2108b ... power layer; 224, 234, 244, 254, 2201 ... GND layer; 28 ... through hole; 3, 3a to 3i ... conductive contact pin; 31 pin body; 32 ... first contact portion; 33 ... second contact portion; 4 ... guide body; 2900a, 2900b, 2900c, 2900d ... insulation region.

Following are exemplary embodiments of a socket for an IC device according to aspects of the present invention.

Embodiment 1 is an IC socket comprising: a substrate having a first surface, a second surface facing the first surface, and a plurality of through holes that each communicate with the first surface and the second surface and that are each provided with conductive material on an inner surface thereof; and a plurality of conductive contact pins, a portion of which is inserted into any of the plurality of through holes; wherein, the substrate comprises: a base material having the first surface, the second surface, and the plurality of through holes; a dielectric layer provided between the first surface and the second surface of the base material in an intersecting state with the plurality of through holes, the dielectric layer having a permittivity higher than that of the base material; and a first and a second conductive layer sandwiching the dielectric layer along a direction in which the first surface of the base material faces the second surface; and wherein, the plurality of conductive contact pins comprise: a plurality of first conductive contact pins for which portions thereof are inserted into any of the plurality of through holes such that the portions thereof touch corresponding conductive material; and a plurality of second conductive contact pins for which portions thereof are inserted into any of the plurality of through holes other than those into which the plurality of first conductive contact pins are inserted such that the portions thereof do not touch corresponding conductive material, or the corresponding conductive material does not touch the first and the second conductive layers; and wherein, the first conductive layer is electrically connected at least to any of the plurality of first conductive contact pins via corresponding conductive material, whereas the second conductive layer is electrically connected via corresponding conductive material to any of the plurality of first conductive contact pins other than those connected to the first conductive layer, and a surface area defined by an outermost perimeter of at least one of the first and second conductive layers is smaller than a surface area defined by an outermost perimeter of the first surface.

Embodiment 2 is the IC socket according to embodiment 1 , wherein the outermost perimeter of at least one of the first and second conductive layers is positioned not less than 25 μηι to an inside of the outermost perimeter of the first surface. Embodiment 3 is the IC socket according to embodiment 1, wherein a capacitance between the first and second conductive layers is controlled by changing a portion of a surface area in which the first conductive layer and the second conductive layer overlap when seen from the first surface toward the second surface.

Embodiment 4 is the IC socket according to embodiment 1 , further comprising a guide body that supports the substrate; wherein the guide body includes a guide portion that arranges an IC device to be inspected at a specific position on the substrate, and a positioning portion that arranges the IC device socket at a specific position of an inspecting device for inspecting the IC device.

Although specific embodiments have been illustrated and described herein for purposes of description of the preferred embodiment, it will be appreciated by those of ordinary skill in the art that a wide variety of alternate and/or equivalent implementations calculated to achieve the same purposes may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. Those with skill in the mechanical, electro-mechanical, and electrical arts will readily appreciate that the present invention may be implemented in a very vide variety of embodiments. This application is intended to cover any adoptions or variations of the preferred embodiments discussed herein. Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof.

Claims

What is claimed is:

1. An IC socket comprising: a substrate having a first surface, a second surface facing the first surface, and a plurality of through holes that each communicate with the first surface and the second surface and that are each provided with conductive material on an inner surface thereof; and a plurality of conductive contact pins, a portion of which is inserted into any of the plurality of through holes; wherein, the substrate comprises: a base material having the first surface, the second surface, and the plurality of through holes; a dielectric layer provided between the first surface and the second surface of the base material in an intersecting state with the plurality of through holes, the dielectric layer having a permittivity higher than that of the base material; and a first and a second conductive layer sandwiching the dielectric layer along a direction in which the first surface of the base material faces the second surface; and wherein, the plurality of conductive contact pins comprise: a plurality of first conductive contact pins for which portions thereof are inserted into any of the plurality of through holes such that the portions thereof touch corresponding conductive material; and a plurality of second conductive contact pins for which portions thereof are inserted into any of the plurality of through holes other than those into which the plurality of first conductive contact pins are inserted such that the portions thereof do not touch corresponding conductive material, or the corresponding conductive material does not touch the first and the second conductive layers; and wherein, the first conductive layer is electrically connected at least to any of the plurality of first conductive contact pins via corresponding conductive material, whereas the second conductive layer is electrically connected via corresponding conductive material to any of the plurality of first conductive contact pins other than those connected to the first conductive layer, and a surface area defined by an outermost perimeter of at least one of the first and second conductive layers is smaller than a surface area defined by an outermost perimeter of the first surface.

2. The IC socket according to claim 1, wherein the outermost perimeter of at least one of the first and second conductive layers is positioned not less than 25 μιη to an inside of the outermost perimeter of the first surface.

3. The IC socket according to claim 1, wherein a capacitance between the first and second conductive layers is controlled by changing a portion of a surface area in which the first conductive layer and the second conductive layer overlap when seen from the first surface toward the second surface.

4. The IC socket according to claim 1, further comprising a guide body that supports the substrate; wherein the guide body includes a guide portion that arranges an IC device to be inspected at a specific position on the substrate, and a positioning portion that arranges the IC device socket at a specific position of an inspecting device for inspecting the IC device.