201246727 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種用於檢測CPU、記憶體及其他類型之 半導體積體電路（下文稱作「1C」）之1C裝置之插座且特定 言之係關於一種配備有用於半導體封裝測試之電容器功能 之1C裝置插座。 【先前技術】 當進行用於評估球柵陣列（BGA)裝置及其他1C裝置的信 號傳輸性質及類似性質之測試時，使用具有可各電連接至 1C裝置之端子之接觸件的插座（下文稱作rIC裝置插 座」）。近來’伴隨處理速度的加快，1C裝置所處置的信 號趨於成為高頻波信號。期望1C裝置插座能夠傳輸對應於 此·#信號之更高速度之高速信號》此外，1C裝置之電源供 應器之操作電壓繼續降低以減小電氣設備的電力消耗。因 此’存在為1C裝置提供穩定電源供應器使得1C裝置能夠高 速穩定操作的需要。提供穩定的電源供應器變得越來越重 要’但是亦歸因於1C裝置更快的速度及更低的電壓而更困 難。 貫穿高頻區域控制電源供應器及接地之阻抗對於在高速 1C裝置操作期間允許穩定電源供應器很重要。需針對1(：裝 置插座降低此一 1C裝置插座中所包含的導電接觸接針之自 感。因此’厚且短的導電接觸接針通常被視作較佳。 國際公開案第2005-006003號中揭示對應於集中於高速 信號傳輸之1C裝置插座之另一方法。如國際公開案第 162093.doc 201246727 2005-006003號所揭示，「根據本發明的LSI插座1〇1由三個 組件組成：印刷板102、彈簧接針1〇3及彈簧接針支撐外殼 部分104。印刷板1〇2具有複數個通孔1〇9，被施加不同電 壓值之一第一電源供應接針1〇5及一第二電源供應接針 106、一GDN接針1〇7及用作信號接針1〇8之彈簧接針1〇3各 插入該複數個通孔1 〇9中，在除信號接針丨〇8所穿過之通孔 109外之所有通孔1〇9之内表面中形成電鍍層116。」 如曰本未審查專利申請公開案第2009-85948號所揭示， 「通常，電源供應探測裝置之電容器安裝在配線圖案上， 儘可能地電靠近偵測插座底側之配線基板上方之裝置」及 「晶片電容器必須安裝在所偵測之裝置正下方之位置及偵 測插座之上部分。」 發明者根據研究習知IC裝置插座之結果發現下列問題。 具體5之，上述導電接觸接針較佳製作成厚且短。但是， 導電接觸接針之厚度必定受限於Ϊ c裝置端子之間之間距之 I乍。同時，當導電接觸接針重複使用時，其等之可靠性 降低，且因此其等通常歸因於導電接觸接針之高成本而根 據需要被更換。因此，在更換導電接觸接針時，考慮到可 工作性及類似因素，導電接觸接針需具有特定長度或更 長’主意導電接觸接針越短，其使用壽命變得越短。在此 情況中，考慮在一些情況中，若基板或半導體封裝不平坦 則可flb無法使導電接觸接針順應，則具有至少一特定長度 之導電接觸接針之使用亦較佳。 或者，藉由直接在安裝在1C裝置插座或IC裝置插座外殼 162093.doc 201246727 中之導電接觸接針之電力接針與接地接針之間連接一電容 器而減小阻抗◊但是，當電容器直接連接至導電接觸接針 或ic裝置插座外殼時’ IC裝置插座所佔據的體積增大。在 此情況中，擔心此可能干擾配置1(：裝置插座之導電接觸接 針為高密度圖案。即使電容器可靠近IC裝置插座之基板或 外殼配置並連接，電容器仍僅可能配置及連接在與導電接 觸接針分離的位置。在此情況中，擔心電容器效果可能歸 因於由至電容器之配線之長度所導致之自感而無法生效。 本發明具有解決上述問題之基本結構。具體言之，本發 明配置有一種結構’其額外地在1(:裝置檢測期間允許穩定 信號傳輸，而在更換導電接觸接針時不導致可工作性之降 低。 最近得知在單個封裝内具有複數個電源及/或接地之半 導體裝置諸如月上系統（S()C)或系統級封裝（抑）。此等 半導體裝置包含在不同電壓下操作之各種功能實施在一單 個封裝内’但即使當電壓相同時，亦可能需要適應類比電 路與數位電路的共存（其要求獨立電源及/或接地正常操作） 之半導體裝置。 因此，本發明之目的係提供—種IC裝置插座其配備有 由知用上述基本組態容易地允許複數種類型之電源及/ 或接地之設定而不增大導電接觸接針所插人之基板本身之 厚度之組態。 【發明内容】 根 據本發月之ICI置插座包含—基板及複數個導電接觸 162093.doc 201246727 接針。基板包含一第一表面、面向第一表面之一第二表面 及各與第一表面及第二表面連通之複數個通孔。複數個導 電接觸接針藉由基板固持為導電接觸接針之一部分插入複 數個通孔之任意者中之狀態。基板至少包含一基底材料、 至少-介電層、一第一導電層及一第二導電層。基底材料 由絕緣材料組成且包含第一表面、第二表面及複數個通 孔。介電層以與複數個通孔交又之狀態提供在基底材料之 第一表面與第二表面之間且具有高於基底材料之介電常 數。第一導電層及第二導電層沿著從基底材料之第一表面 朝向第二表面之第一方向夾置介電層。此外，使用根據本 發明之ic裝置插座，第一導電層及第二導電層之至少一者 在水平方向上被穿插於其等間之一絕緣區域分段為兩個或 兩個以上部分。注意水平方向對應於與從基板之第一表面 朝向第二表面之第一方向正交之方向。 此外’當電源及接地數量高或當為了增大電容，電源及 接地無法在-個平面上分段時可提供對㈣分段電源及分 段接地之複數個導電層。具體言之，根據本職置插座複 數個介電層層壓在基板中之結構包含在其等之至少一表面 上具有被穿插於其等間之_絕緣區域分段之—導電層之複 數個^電層’而另—介電層可使用下列結構之任意者：在 " 表面上具有被穿插於其等間之一絕緣區域分段之 導電層之-結構；在兩個表面上具有導電層，纟等間穿插 絕緣區域之結構；及在兩個表面上具有未分段導電層之一 162093.doc 201246727 此外’電容器（下文稱作c組件）藉由在介電層之兩侧上 提供導電層而由彼此相對之導電層組成。本發明藉由採用 提供在介電層之至少一表面上之導電層被穿插於其等間之201246727 VI. Description of the Invention: [Technical Field] The present invention relates to a socket for detecting a 1C device of a CPU, a memory, and other types of semiconductor integrated circuits (hereinafter referred to as "1C"), and specifically It relates to a 1C device socket equipped with a capacitor function for semiconductor package testing. [Prior Art] When performing tests for evaluating signal transmission properties and the like of a ball grid array (BGA) device and other 1C devices, a socket having contacts each electrically connectable to a terminal of the 1C device is used (hereinafter referred to as a socket) As a rIC device socket"). Recently, as the processing speed is accelerated, the signal handled by the 1C device tends to become a high frequency wave signal. It is desirable that the 1C device socket can transmit a higher speed signal corresponding to the higher speed of the ## signal. Further, the operating voltage of the power supply of the 1C device continues to decrease to reduce the power consumption of the electrical device. Therefore, there is a need to provide a stable power supply for the 1C device so that the 1C device can operate stably at a high speed. It is becoming more and more important to provide a stable power supply, but it is also more difficult due to the faster speed and lower voltage of the 1C device. Controlling the power supply and ground impedance throughout the high frequency region is important to allow stable power supplies during high speed 1C device operation. It is necessary to reduce the self-inductance of the conductive contact pins contained in the socket of the 1C device for the device socket. Therefore, the thick and short conductive contact pins are generally regarded as preferred. International Publication No. 2005-006003 Another method corresponding to a 1C device socket focused on high-speed signal transmission is disclosed. As disclosed in International Publication No. 162093.doc 201246727 2005-006003, "The LSI socket 1.1 according to the present invention is composed of three components: The printing plate 102, the spring pin 1〇3 and the spring pin support the outer casing portion 104. The printing plate 1〇2 has a plurality of through holes 1〇9, and one of the different voltage values is applied to the first power supply pin 1〇5 and A second power supply pin 106, a GDN pin 1〇7, and a spring pin 1〇3 serving as a signal pin 1〇8 are respectively inserted into the plurality of through holes 1 〇9, except for the signal pin 丨A plating layer 116 is formed in the inner surface of all the through holes 1 to 9 outside the through hole 109 through which the crucible 8 passes. As disclosed in Japanese Laid-Open Patent Publication No. 2009-85948, The capacitor of the device is mounted on the wiring pattern and is as close as possible to the detector. The device above the wiring substrate on the bottom side of the socket and the "wafer capacitor must be mounted directly below the detected device and above the detection socket." The inventors found the following problems based on the results of research on the IC device socket. Specifically, the conductive contact pins are preferably made thick and short. However, the thickness of the conductive contact pins must be limited by the distance between the terminals of the device, and the conductive contact pins are repeatedly used. At the time, the reliability of the etc. is lowered, and therefore, etc. are usually replaced as needed due to the high cost of the conductive contact pins. Therefore, when the conductive contact pins are replaced, the workability and the like are considered, and the conductive is considered. The contact pin needs to have a specific length or longer. The shorter the contact conductive contact pin is, the shorter the service life becomes. In this case, it is considered that in some cases, if the substrate or the semiconductor package is not flat, flb cannot be made. The conductive contact pins are compliant, and the use of conductive contact pins having at least one specific length is also preferred. Alternatively, by mounting directly in the 1C device socket or IC Device socket 162093.doc 201246727 The contact between the power contact pin of the conductive contact pin and the ground pin reduces the impedance. However, when the capacitor is directly connected to the conductive contact pin or the ic device socket housing, 'IC The volume occupied by the device socket is increased. In this case, it is feared that this may interfere with configuration 1 (the conductive contact pin of the device socket is a high-density pattern. Even if the capacitor can be placed and connected to the substrate or housing of the IC device socket, the capacitor It is still only possible to configure and connect at a position separate from the conductive contact pins. In this case, it is feared that the capacitor effect may not be effective due to the self-inductance caused by the length of the wiring to the capacitor. The present invention has the basic structure for solving the above problems. In particular, the present invention is configured with a structure that additionally allows for stable signal transmission during device detection and does not result in reduced operability when replacing conductive contact pins. It has recently been found that in a single package A plurality of power and/or grounded semiconductor devices such as a system on the moon (S()C) or a system-in-package (suppression). These semiconductor devices include various functions operating at different voltages implemented in a single package 'but even When the voltages are the same, it may also be necessary to adapt to the semiconductor device in which the analog circuit and the digital circuit coexist (which requires independent power supply and/or grounding to operate normally). Therefore, the object of the present invention is to provide an IC device socket which is equipped with With the above basic configuration, it is easy to allow a plurality of types of power supply and/or grounding settings without increasing the thickness of the substrate itself to which the conductive contact pins are inserted. [Invention] According to the ICI of this month The socket comprises a substrate and a plurality of conductive contacts 162093.doc 201246727. The substrate comprises a first surface, one of the first surfaces facing the second surface And a plurality of through holes communicating with the first surface and the second surface. The plurality of conductive contact pins are inserted into any one of the plurality of through holes by the substrate holding part of the conductive contact pins. The substrate comprises at least one a base material, at least a dielectric layer, a first conductive layer and a second conductive layer. The base material is composed of an insulating material and comprises a first surface, a second surface and a plurality of through holes. The dielectric layer is connected to the plurality of through holes The state of the hole intersection is provided between the first surface and the second surface of the base material and has a dielectric constant higher than the base material. The first conductive layer and the second conductive layer are along the first surface from the base material toward a dielectric layer is interposed between the first surface of the two surfaces. Further, with the ic device socket according to the present invention, at least one of the first conductive layer and the second conductive layer is horizontally inserted in one of the insulating regions Segmented into two or more sections. Note that the horizontal direction corresponds to a direction orthogonal to the first direction from the first surface of the substrate toward the second surface. Further 'when the number of power supplies and grounds is high or In order to increase the capacitance, the power supply and the grounding cannot be segmented on a plane, and a plurality of conductive layers for the (four) segmented power supply and the segmented grounding can be provided. Specifically, a plurality of dielectric layers are laminated according to the occupational socket. The structure in the substrate comprises a plurality of electrical layers of the conductive layer segmented on at least one surface of the substrate, etc., and the dielectric layer may use any of the following structures. a structure having a conductive layer interspersed in one of the insulating regions of the space on the surface of the "surface; a structure having a conductive layer on both surfaces, interspersed with an insulating region; and on both surfaces Having one of the unsegmented conductive layers 162093.doc 201246727 Furthermore, a 'capacitor (hereinafter referred to as a c-component) is composed of conductive layers opposite each other by providing a conductive layer on both sides of the dielectric layer. The present invention provides by using a conductive layer on at least one surface of the dielectric layer is interposed between
一絕緣區域分段之一組態而允許在一平面上形成複數個C 組件。同時，雖然與導電層配置在基板之整個表面之上之 情況相比各C組件之電容必然較小，但是導電層之分段區 域之表面積基本上不受限於其表面積或平坦圖案（形式）， 只要所需最小電容能夠得到保證。在此情況中，即使在其 等之至少一表面上具有分段導電層之複數個介電層在基底 材料中配置為層壓狀，對於各介電層導電層之區段圖案仍 可不同。 上述絕緣區域之至少一部分可為一氣隙。絕緣材料亦可 為不同於介電層之材料（舉例而言，絕緣材料，諸如基底 材料之絕緣材料）。在此情況中，介電層本身連同導電層 具有在水平方向上分段之結構。但是，當被不同絕緣材料 或氣隙分段時，無介電層本身之功能之特定差異發生。因 此，在本說明書中，即使介電層具有在水平方向上分段之 結構’此等分段區域仍定義為一個介電層。 根據本揭示内容之發明之IC裝置插座由如上述由基底材 料組成之大致整合基板形成，其中嵌入提供在介電層之兩 側上一起組態C組件之介電層及導電層。因此，導電接觸 接針與C組件之間之距離極小，且因此1(：装置插座之效能 可改良。此外，導電接觸接針藉由壓配合或類似方法固持 至基板中。基板用作導電接觸接針之支撐體，因此免除對 162093.doc 201246727 支撐導電接觸接針之另一組件之需要。 此複數個導電接觸接針包含複數個第—導電接觸接針及 具有與複數個第-導電接觸接針不同之連接狀態之複數個 第二導電接觸接針。具體言之’複數個第一導電接觸接針 之π刀插人複數個通孔之任意者中以與對應於此等部分之 導電部件（提供在通孔之内表面上之金屬膜或類似物）接 觸。複數個第二導電接觸接針之部分插入複數個通孔之任 意其他者中但保持與第—導電層或第二導電層無接觸之狀 &與第導電層或第二導電層無接觸之此狀態指示第二 導電接觸接針不接觸提供在通孔之内表面上之導電部件或 該導電部件不提供在容納第二導電接觸接針之通孔之内表 面上。在此情;兄中，帛一導電層及第二導電層用穿插於其 等間之相應導電部件電連接至複數個第一導電接觸接針2 任意者。 根據本發明之ic裝置插座之上述複數個第一導電接觸接 針被劃分為僅電連接至第一導電層之第一群組（例如，電 力接針群組）及僅電連接至第二導電層之第二群組（例如， 接地接針群組）。此外’未電連接至第一導電層或第二導 電層任一者之複數個第二導電接觸接針用作信號接針。 根據本發明之1C裝置插座’連同介電層一起組態c組件 之第一導電層及第二導電層之至少任一者在水平方向上被 穿插於其等間之絕緣區域分段為兩個或兩個以上區段。根 據本組態’與不同電源供應器及/或接地在基板内配置為 層壓狀之情況相比，可更有效地抑制基板之厚度之择加 162093.doc 201246727 此外，由於可針對層壓其等間穿插有基底材料之部分之c 組件減少製程本身所涉及之製程數量，故基板製作簡化 (製作成本降低）。 【實施方式】 下文將參考圖1至圖16描述根據本發明之1C裝置插座之 實施例。注意在各圖式中，相同元件符號指定相同或類似 元件且省略重複描述。 首先，本文將參考圖1至圖6詳細描述根據本實施例之IC 裝置插座之基本結構。 圖1係根據本發明之1C裝置插座之一第一實施例之一結 構之一透視圖。圖2展示沿著線π-ΙΙ之圖1所示之ic裝置插 座之一截面。圖3係圖1所示之ic裝置插座1之一基板2之一 結構之一平面圖。注意圖3中的箭頭L大致匹配圖1中的線 II-II。一 1C裝置插座1包含基板2、藉由壓配合或類似方法 固持在基板2中之複數個導電接觸接針3及支撐基板2之一 本體4 ^本體4包含用於將一待檢IC裝置（未展示）配置在基 板2上之特定位置之一導引部分或導引壁41且進一步包含 用於將1C裝置插座1配置在用於檢測IC裝置之一檢測裝置 (未展不）中之特定位置之一定位單元（本實施例中圖2所示 之一定位接針42)。注意本體4根據需要可併入1(：裝置插座 1。此外，基板2可具有一定位孔或凹口以與定位構件協 作。 圖4係圖2所示之截面結構之一部分川之一放大圖。如圖 4所不’基板2包含由介電質（諸如玻璃纖維環氧樹脂或類 162093.doc 201246727 似物）組成之基底材料21及嵌入基底材料21之介電層22至 25(第一介電層至第四介電層）之至少一者（圖4中展示四個 作為實例）且銅及類似物質之導電層形成在介電層之上表 面側及下表面側上》如圖2所示，嵌入基底材料21之導電 層亦在水平方向上被穿插於其等間之一絕緣區域290分 段。絕緣區域290指的是由絕緣材料（諸如基底材料或導電 材料）組成之一區域。在圖4所示之實例申，絕緣區域290 中包含基底材料21之一部分及第一介電層22至第四介電層 2 5之一部分。 如上所述，一單個介電層與形成在其兩個表面上之導電 層協作以組態一 C組件。具體言之，藉由層壓組態基底材 料21、導電層及介電層之材料（基底材料之一部分）形成基 板2。介電層之介電常數較佳係高以改良^組件之電容。舉 例而言，第一介電層22至第四介電層25較佳由具有高於基 底材料21之介電常數之介電常數的高介電質組成。舉例而 言，由3M製造的嵌入電容器材料（ECM)可用作高介電質。 ECM由形成為可撓片之介電材料製成。可使用用於製作印 刷電路板之方法製作此類型之基板。 組成基板2之材料（其係基底材料21之材料）可為絕緣材 料且可包含紙取卩玻璃、纖維且彳包含祕樹脂&聚酿亞胺 樹脂取代環氧樹脂。亦可使用銀或金取代銅作為組成導電 層之材料。第一介電層22至第四介電層25可各包含聚合 物。第-介電層22至第四介電層25較佳各包含聚合物及： 數個顆粒且特定言之藉由將樹脂與顆粒混合而製作。所需 162093.doc • 11 · 201246727 樹脂包含環氧樹脂、聚醜胺、聚孰亞乙稀、氛基乙基支鏈 殿粉、苯並環丁稀、聚降冰片稀、聚四氣乙稀、丙稀酸醋 或其等之組合。顆粒包含介電（或絕緣）顆粒且代表性實例 包含鈦酸鋇、鈦酸鋇锶、氧化鈦、鍅鈦酸鉛及其等之組 合。 一第-介電層22至第四介電層25之各者之厚度可為舉例而 言0.5 μπι或更大及100㈣或更，】、。厚度較佳較薄舉例而 言15 μπι或更小或10㈣或更小之厚度，因此改良電容器之 靜電容量。但是，從接合強度之角度看介電層之厚度較佳 較厚舉例而言1 μπι或更大之厚度。 此外，介電質之相對介電常數較佳係高，例如1〇或更大 或12或更大《雖然不存在對上限的特定限制，但是相對介 電常數可為舉例而言30或更小、16或更小或2〇或更小。 形成在第一介電層22至第四介電層25之任一側上之導電 層之一者組態電連接至1(：裝置插座1之電力接針之一電力 層且另一導電層組態電連接至1(：裝置插座1之接地（下文稱 作GND)接針之一接地層。具體言之，組態一第一電力 層、其等間穿插絕緣區域290之分段區域222及222,形成在 最靠近基板2之1C裝置側上之一表面26(圖2中之上表面）之 第一介電層22之一上表面221上，且組態一第一 GND層、 其等間穿插絕緣區域290之分段區域224及224,形成在一下 表面223上。類似地’組態一第二電力層、其等間穿插絕 緣區域290之分段區域232及232'形成在定位在第一介電層 22正下方之第二介電層23之一上表面231上，且組態一第 162093.doc •12- 201246727 二GND層、其等間穿插絕緣區域290之分段區域234及234' 形成在一下表面233上。此外，組態一第四電力層、其等 間穿插絕緣區域290之分段區域252及252'形成在最靠近基 板2之檢測裝置側上之一表面27(圖2中之下表面）之第四介 電層25之一上表面251上，且組態一第四GND層、其等間 穿插絕緣區域290之分段區域254及254’形成在一下表面253 上。類似地，組態一第三電力層、其等間穿插絕緣區域 290之分段區域242及242’形成在定位在第四介電層25正上 方之第三介電層24之一上表面241上，且組態一第三GND 層、其等間穿插絕緣區域290之分段區域244及244'形成在 一下表面243上。注意圖4所示之截面結構展示基板2之上 表面26匹配基底材料21之上表面且基板2之下表面27匹配 基底材料21之下表面。 可針對第一電力層之分段區域222及222'設定不同電位 且不同GND設定（至不同GND接針之電連接）對於第一 GND 層之分段區域224及224'可行。可針對第二電力層之分段區 域232及232'設定不同電位且單獨GND設定對於第二GND 層之分段區域234及234'可行。可針對第三電力層之分段區 域242及242'設定不同電位，且第三GND層之分段區域244 及244'無需電連接至共用GND接針。可針對第四電力層之 分段區域252及252'設定不同電位且第四GND層之分段區 域254及254'無需電連接至共用GND接針。 注意在圖4所示之實例中，第一介電層22至第四介電層 至25之所有提供在其兩側上，導電層在水平方向上被穿插 162093.doc -13- 201246727 於其等間之絕緣區域290分段。但是，複數個介電層在美 板2内配置為層壓狀之組態中可包含提供在其兩側上之介 電層及未分段之導電層。舉例而言，當未分段導電層配置 在基板2之整個表面之上時，可形成表面積大致等於基板二 之表面積之C組件。此外，可根據c組件之所需電容判定 未分段導電層之表面積而無需確保表面積需匹配基板2之 整個表面。此外，可在基板2中判定導電層之任意平坦形 狀而不論導電層是否分段。 導電接觸接針3之各者在穿過基板2之上層26及下層27之 大致垂直方向上穿透基板2。具體言之，在基底材料21以 及形成在其兩側上之組成基板2之介電層及導電層中形成 可插入導電接觸接針3之通孔28。在通孔28之内側表面上 藉由電鍍或類似方法形成銅、金、銀或類似物之導電部件 281。壓配合至通孔28之導電接觸接針3(作為信號接針之 該等導電接觸接針3除外）之接針本體3丨透過導電部件28 1 電連接至導電層之任意者。注意信號接針之孔之内表面可 以或可以不必形成有導電部件2 8 J。 判定通孔28之尺寸以允許導電接觸接針3固持在通孔中 而不歸因於在將1C裝置插w配置在檢測裝置基板上時所 產生之安裝在導電接觸接針3中之彈簧之反作用力而掉 出。舉例而t，導電接觸接針3之壓配合&緊力較佳為〇1 N或更大。以在更換或維護導電接觸接針3時可相當容易地 將導電接觸接針3從通孔28中移除之方式判定通孔以之尺 寸。此外，以在將導電接觸接針3從基板2移除時通孔Μ之 162093.doc 201246727 内表面上之導電部件281不脫落之方式判定通孔28之尺 寸。舉例而言，導電接觸接針3之壓配合夾緊力較佳不大 於 2.0 N 。 導電接觸接針3之各者包含藉由壓配合固持在基板2中之 大致圓柱形接針本體31、可藉由從接針本體31之一末端 (圖4中之下端）突出而電接觸（即導電連接）檢測裝置（未展 示）之一第一接觸部32及可藉由從接針本體31之另一末端 (圖4中之上端）突出而電接觸（即導電連接）IC裝置（未展示） 之一第二接觸部33。雖然各種模式可用作導電接觸接針 3 ’但是所謂彈簧探針型（其中接觸部32與33兩者可藉由彈 簧及類似物（未展示）在接針本體31之軸向上相對於接針本 體31移位）較佳。 導電接觸接針3之接針本體31之形狀較佳為圓柱形。當 導電接觸接針3以此方式成形時，導電接觸接針3可容易地 配置在通孔28之大致軸向上，此係因為接針本體31之外表 面跨寬表面積接觸通孔28。因導電部件281與導電接觸接 針3之接觸表面積增大’故可實現電穩定連接。 導電接觸接針3劃分為電連接至上述電力層之電力接針 群組、連接至GND層之GND接針群組及不連接至該等層之 任意者之信號接針群組。舉例而言，如圖4所示，導電接 觸接針3b連接至第一電力層分段區域222與第三電力層分 段區域242兩者且導電接觸接針3丨連接至第一電力層分段 區域222’與第三電力層分段區域242,兩者以皆用作第一電 力接針。導電接觸接針3c連接至第二電力層分段區域232 162093.doc 15 201246727 與第四電力層分段區域252兩者且導電接觸接針3 f連接至 第二電力層分段區域232,與第四電力層分段區域252，以皆 用作第二電力接針。類似地，導電接觸接針3a連接至第一 GND層为奴區域224與第三電力層分段區域244兩者且導電 接觸接針3h連接至第一 GND層分段區域224，與第三電力層 分段區域244’兩者以皆用作第一GND接針。導電接觸接針 3d連接至第二GND層分段區域234與第四電力層分段區域 254兩者且導電接觸接針3g連接至第二GND層分段區域 234與第四電力層分段區域254，兩者以皆用作第二接 針。導電接觸接針3e不連接至導電層之任意者且因此用作 一信號接針。 如圖4所示，由被電力層與GND層夾置之高介電質（介電 層）組態之C組件較佳提供在儘可能靠近基板2之上表面26 及下表面2 7 (分別匹配基底材料2丨之上表面及下表面）即外 側之位置上。如此的原因在於若基板2之導電層與外表面 之間的距離小，則可在10：裝置檢測期間達成穩定電源供應 器。更具體吕之，基板2之上表面26與第一介電層22及第 二介電層23之間之距離越小，受檢IC裝置之輸入靈敏度越 大》因此，第一介電層22及第二介電層23較佳相對於基板 2之上表面26與下表面27之間的中間點朝向上表面26側配 置。此外，第三介電層24及第四介電層25較佳相對於基板 2之上表面26與下表面27之間的中間點朝向下表面27側配 置。在本貫施例中’基板2組態為大致整合物體，其中嵌 入由高介電質組成、各被電力層與GND層夾置之介電層。 162093.doc -16 - 201246727 因此，可容易地實現C組件配置在基板2之外表面附近之組 態’因此允許實現精確的1C裝置檢測。 如上所述，導電接觸接針3大致僅藉由基板2固持。因 此’具有所需電容之C組件可配置為在基板2内之任意位置 上被劃分為複數個區段之狀態。此外，基板2在其中心附 近之厚度方向上可包含又一C組件，該又一C組件包含形 成在其兩側上之介電層及導電層。 從電特性及類似特性之角度看，各導電接觸接針3之長 度較佳較短。但是’隨著導電接觸接針3之長度變得更 短’更換接針時的操作及組裝變得更困難。相反地，根據 本基本結構’即使在使用相對較長導電接觸接針3時，仍 無需考慮1C裝置插座1效能之降低，因為歸因於上述基板2 之組態可針對電特性達成與當實際上使用較短彈簣接針時 之情況類似之效果。 若接針本體31之長度長於基板2之厚度，則導電接觸接 針3亦有效地變得更長，因此降低電特性。相反地，若接 針本體31之長度短於基板2之厚度使得接針本體31之軸向 末端定位為比導電層之任意者離基板中心更遠，則從導電 接觸接針3到達導電層之路徑變得複雜，因此降低lc裝置 插座之效能。因此，導電接觸接針3之接針本體31之軸向 長度較佳大約等於基板2之厚度。注意基板2之厚度較佳考 慮固持導電接觸接針3所需之結構強度而判定且因此較佳 製作成儘可能薄同時維持適當等級的強度。 此外，根據本實施例之1C裝置插座1配備有舉例而言四 162093.doc •17- 201246727 個介電層22至25(電力層及GND層形成在其等之兩側上）層 壓成其等間穿插基底材料21之部分之一結構。根據本組 態，在具有1C裝置插座1之一封裝内不同電壓設定及不同 接也》又疋"J行，因為在舉例而言第一電力層與第二電力層 2間不同電位設定可行。此外，甚至在相同層内針對各 分段區域之不同電力設定及/或接地設定亦可行。舉例而 言，可針對第一電力層之分段區域222及分段區域222，設定 不同電力δ又疋且可針對第二電力層之分段區域232及分段 區域232’設定不同電力設定β 具體言之，第一電力層具有舉例而言圖5所示之平坦形 狀而第GND層具有舉例而言圖6所示之平坦形狀。注 意圖5係展示對應於圖3所示之平面圖之…部分之一第一電 力層組態且其他第二導電層至第四導電層之任意者亦可具 有類似平坦形狀。圖6係展示對應於圖3所示之平面圖之^ 刀之第一 GND層組態且其他第二GND層至第四GND層 之任意者亦可具有類似平坦形狀。 如圖5所不，第一電力層由被穿插於其等間之絕緣區域 290水平分段之分段區域222及分段區域222，組態。分段區 域222及222在對應於基板2中所提供之通孔28之位置上具 有具有不同直控之兩種類型之開口 28〇&及28〇b。注意提供 在/刀奴區域222及222,之各者中之兩種類型之開口 28〇&及 280b配置在沿著圖5中之箭頭以之方向上。箭頭li大致匹 配圖1中之線π-π(大致匹配圖4所示之截面）。開口 28〇&具 有大致匹配通孔28之直徑之一直徑或更具體言之具有允許 162093.doc -18- 201246727 在形成在通孔28之内表面上之導電部件281與組態第一電 力層之分段區域222及222’之間充分維持電接觸狀態之一孔 直徑。相反地，開口 280b具有大於通孔28之直徑之一直徑 或更具體言之具有舉例而言比通孔28之直徑大大約50 μιη 之孔直徑且可在形成在通孔28之内表面上之導電部件281 與組態第一電力層之分段區域222及222’之間充分維持電隔 離狀態。 此外，如圖6所示，第一 GND層亦由被穿插於其等間之 絕緣區域290水平分段之分段區域224及分段區域224'組 態。類似於上述第一電力層之分段區域222及222’，分段區 域224及224'在對應於基板2中所提供之通孔28之位置上具 有具有不同直徑之兩種類型之開口 280a及280b。注意提供 在分段區域224及221之各者中之兩種類型之開口 280a及 280b配置在沿著圖6中之箭頭L2之方向上。箭頭L2大致匹 配圖1中之線11-11(大致匹配圖4所示之截面）。開口 280a具 有大致匹配通孔28之直徑之一直徑或更具體言之具有允許 與形成在通孔28之内表面上之導電部件281及組成第一 GND層之分段區域224及224'維持適當的電接觸之一孔直 徑。相反地，開口 280b具有大於通孔28之直徑之一直徑或 更具體言之具有舉例而言可維持形成在通孔28之内表面上 之導電部件281與組成第一 GND層之分段區域224及224'之 間之適當的電隔離狀態之一孔直徑。 以根據本實施例之此方式，電力層之各者配置為其等間 穿插有組成基板2内之絕緣材料之基底材料21之部分之層 162093.doc •19- 201246727 壓狀’藉此允許第一電力層至第四電力層具有不同電位設 定同時亦允許各電力層内之分段區域具有不同電位設定。 特定言之，本發明之結構有效，因為可以避免基板2之厚 度（上表面26與下表面27之間之間隔）增大（其由當Ic裝置插 座1内之電位設定變得複雜時更高數量之層層壓在一起所 導致）。 用於組態圖1至圖6所示之上述實施例中之包含提供在介 電層之兩側上之介電層及導電層之C組件（下文稱作c組件 層）包含針對第一介電層22至第四介電層25之各者之分段 導電層之結構。但是’亦可針對各C組件層使用導電層之 不同區段圖案。 注意最基本結構係在基板2内包含一個c組件層（見圖9) 之結構。可用於圖9所示之結構中之一電力層之一實例展 示在圖7中。如圖7所示，電力層21〇〇在水平方向上（與從 基板2之上表面26朝向下表面27之方向正交之一方向上）被 穿插於其等間之一絕緣區域2100c分段為分段區域2100a及 分段區域21 〇〇b。注意提供在電力層21〇〇中之兩種類型之 開口 280a及280b配置在沿著圖7中之箭頭13之方向上。箭 頭L3大致匹配圖丄中之線π_π(大致匹配圖4所示之截面）。 如圖8所示，GND層2200亦被穿插於其等間之絕緣區域 22〇〇C水平分段為分段區域2200a及分段區域2200b。分段 區域220〇a及2200b亦具有形成在其中、具有兩種類型之直 徑之開口 280a及280b。注意兩種類型之開口 280a及280b配 置在沿著圖8中之箭頭L4之方向上。箭頭[4大致匹配圖1中 I62093.doc •20* 201246727 之線11-11(大致匹配圖4所示之截面）。 如上所述，可藉由提供用皆在水平方向上分段為兩個部 分之電力層2100與GND層2200夾置一介電層2〇〇〇之層結構 達成圖9所示之基本結構。在此情況中，可達成複數種類 型之電力設定而不增大基板2之厚度。注意圖9係展示結構 之一部分（C組件層）之一透視圖，其中介電層被具有圖7所 示之結構之電力層（電力層被絕緣區域分段為兩個或兩個 以上區段）及圖8所示之GND層（GND層被絕緣區域分段為 兩個或兩個以上區段）夾置且亦展示對應於圖3所示之部分 IV之一基板區域。 在圖9所示之上述實例中，雖然複數個c組件可實現在一 個平面上（對應於由介電層200及提供在介電層2〇〇之任一 側上之電力層2100及GND層2200組態之c組件層接地平 面），但是複數個C組件層在基板2中配置為層壓狀之一結 構可包含圖9所示之C組件層與具有分段導電層圖案之又一 C組件層之組合。 圖10及圖11係遵循圖9所示乏實例之透視圖且展示在基 板中配置為層壓狀之複數個C組件層（其等由提供在其等兩 側上之介電層及導電層組態）之組合之一實例。 在圖10所示之實例中’圖9所示之第一 c組件層及具有不 同分段導電層圖案之第二c組件層在基板2中配置為層壓 狀。如上所述，第一 C組件層由下列層組態：介電層 2000、包含提供在介電層2〇〇〇之一表面上且其等間穿插有 絕緣£域2100(：之分段區域2100a及2100b之電力層2100、 162093.doc •21 · 201246727 及包含提供在介電層2000之另一表面上且其等間穿插有絕 緣區域2200c之分段區域2200a及2200b之GND層2200組 態。同時，第二C組件由介電層3000、提供在介電層3〇〇〇 之一表面上且穿插有絕緣區域2100c之分段區域3 100a及 3 100b之電力層3100及未分段且提供在介電層3〇〇〇之另一 表面上之GND層3200。注意’第一 C組件層之電力層2100 中之絕緣區域2100c之形狀（區段圖案）與第二C組件層之電 力層3100中之絕緣區域3100c之形狀（區段圖案）當然可以不 同。此外，第二C組件層之未分段GND層3200不一定具有 與基板2之上表面26或下表面27匹配之表面積。GND層 3200之表面積剛好大至足以保證電力層3100之分段區域 3100a與3100b之間之所需電容足矣。 在圖11所示之實例中，圖9所示之第一 C組件層及具有不 同分段導電層圖案之第三C組件在基板2内配置為層壓狀。 第一 C組件層之結構與上述圖9及圖10之結構相同。第三c 組件由下列層组態：介電層4000、未分段且提供在介電層 4000之一表面上之電力層4100及未分段且提供在介電層 4000之另一表面上之GND層4200組態。第三C組件層之未 分段電力層4100及未分段GND層4200之各自表面積不一定 匹配基板2之上表面26或下表面27之表面積。如在從基板2 之上表面26朝向下表面27之方向所見，藉由電力層4100與 GND層4200重疊之一區域之表面積判定c組件之電容。因 此’可在可保證各者之所需電容之範圍内判定電力層41〇〇 之表面積及平坦形狀及GND層4200之表面積及平坦形狀。 162093.doc •22· 201246727 /主思將導電層分段之絕緣區域之至少一部分可為一間 隙’諸如舉例而言一氣隙。舉例而言，如圖12所示，當複 數個C組件層之所有（包含圖9所示之C組件層）具有分段導 電層時’作為氣隙之絕緣區域21〇〇c較佳具有延伸使得其 上表面到達基板2之上表面26且其下表面到達基板2之下表 面27之一形狀。如圖12所示，介電層2〇〇〇在水平方向上分 段為兩個部分2〇〇〇a及2〇〇〇b ;電力層2100亦在水平方向上 分段為兩個部分2i〇〇a及2i〇〇b且此外GND層2200亦在水平 方向上分段為兩個部分22〇〇&及22〇〇b。在根據本實施例之 ic裝置插座中’除上述介電層2〇〇〇、電力層21〇〇及〇>1〇層 2200以外之其他結構零件亦可在水平方向上被作為氣隙之 絕緣區域210〇c分段。注意圖12展示對應於圖3中之部分卩 之、’、《>構2之内部結構。此外，複數個介電層（即複數個匸組 件層）可配置為層壓狀。具體言之，除圖12所示之c組件層 以外，圖12中之組態中可包含諸如圖1〇或圖η中所示之另 一 C組件層。 在圖12所不之實例中，藉由在絕緣區域2100c中應用氣 隙而在水平方向上將電力層21〇〇及（}]^〇層22〇〇以及介電層 2000分段。但是，當被不同絕緣材料或氣隙分段時，無介 電層本身之功能之特定差異發生。因此，在本說明書中， 即使介電層具有在水平方向上分段之結構，此等分段區域 仍定義為一個介電層。 如上所述，與不同電源供應器及/或接地在基板中配置 為層壓狀之情况相比’介電層2〇〇〇及電力層21〇〇(；與〇]^1) I62093.doc •23- 201246727 層2200之至少任一者組態c組件之組態允許抑制基板厚度 增大之明顯效果。此外，由於可針對層壓其等間穿插有基 底材料之部分之C組件層減少製程本身所涉及之製程數 量’故基板製作簡化（製作成本降低）。 此外，藉由基板2固持在根據本實施例之1(：裝置插座1中 之導電接觸接針3之配置可採用各種配置圖案而不限於圖3 所示之矩形形狀。此外，可根據需要設定被所採用之導電 接觸接針3之連續圖案分段之導電層及/或gnd層之表面積 及形狀。此一貫例展示在圖13至圖16中。注意圖13至圖16 係根據本實施例之1C裝置插座之各自基板之平面圖且圖解 說明被劃分為接針配置之導電層之位置關係之其他實例。 此外’圖13至圖16基於圖3所示之實例展示對應於基板2及 第一電力層之分段區域222及222'之元件之位置關係。 在圖13所示之實例中’基板2a中之導電接觸接針3配置 在被矩形外周邊與矩形内周邊夾置之一矩形環形區域中； 且組態配置在基板2a中之C組件層之導電層在水平方向上 被其等間穿插之絕緣區域290a劃分為兩個分段區域222a及 222'a 〇 在圖14所示之實例中，導電接觸接針3配置在内矩形區 域中且亦配置在基板2b中圍繞内矩形區域之矩形環形區域 中。在此情況中，組態配置在基板2b中之c組件層之導電 層之任意者可分段使得舉例而言分段區域222b圍繞分段區 域222'b，其等間穿插絕緣區域290b。 在圖15所示之實例中，導電接觸接針3係沿著基板以中 162093.doc •24· 201246727 之一矩形區域之最外周邊配置。在此情況中，組態配置在 基板2c中之C組件層之導電層之任意者可分段為舉例而言 分段區域222c及222'c，該等分段區域222c及2224具有遵 循其等間穿插絕緣區域290c之一列導電接觸接針3之形 狀。 此外，在圖16所示之實例中，在基板2d中，導電接觸接 針3配置為在其等間真有特定距離之兩列。在此情況中， 組態配置在基板2d中之C組件層之導電層之任意者可分段 為舉例而言相應列之分段區域222d及222'd，其等間穿插絕 緣區域290d。 1... 1C裝置插座；2、2a、2b、2c、2d…基板；21·.·基底 材料；22 5. 25 ' 2000、2000a、2000b、3000 ' 4000、 5000.. .介電層；222、222'、222a、222，a、222b、222，b、 222c、222，c、222d、222'd ' 232、232' ' 242、242' ' 252、252'、2100、2100a、2100b、3100、3100a、3100b、 4100.. .電力層；224、224'、234、234'、244、244'、254、 254'、2200、2200a、2200b、3200、4200…GND層；28... 通孔；3、3a至3i...導電接觸接針；31接針本體；32...第一 接觸部；33…第二接觸部；4...本體；290、290a、290b、 290c、290d、2100c、2200c、3 100c…絕緣區域 ° 下文係根據本發明之態樣之IC裝置之一插座之例示性實 施例。 實施例1係一 1C裝置插座，其包括：一基板，其具有一 第一表面；一第二表面，其面向第一表面；及複數個通 162093.doc -25- 201246727 孔，其等各與第_矣& 及第一表面相連通；及複數個導電 接針’其等之-部分插入至複數個通孔之任意者中； '基板包括.一基底材料’其具有第一表面、第二表 面及複數個通孔，至少一介電層，其係以與複數個通孔交 又之狀態提供在第-表面與第二表面之間，介電層具有高 於基底材料之介電常數；及一第一導電層及一第二導電 層，其等沿著基底材料之第一表面面向第二表面之方向夹 置介電層；其中複數個導電接觸接針包括：複數個第 電接觸接針，其等之—部分插人至複數個通孔之任意者 中1部分電連接至第一導電層或第二導電層；及複數個 第-導電接觸接針’其等之一部分插入至除複數個第一導 電接觸接針所插人之通孔以外之複數個通孔之任意者中， 該部分未電連接至第-導電層或第二導電層；且其中第一 導電層及第二導電層之任意者在水平方向上被穿插於其等 間之一絕緣區域分段為兩個或兩個以上區段。 實施例2係根據實施例ric裝置插座，其中絕緣區域具 有其一表面延伸到達基底材料之第一表面且其之與該一表 面相對之另一表面延伸到達基底材料之第二表面之形狀。 實施例3係根據實施例2之1〇：裝置插座，其中絕緣區域之 至少一部分係一氣隙。 實施例4係根據實施例丨之1(：裝置插座，其中複數個通孔 之任意者在其一内表面上具有一導電部件且第一導電層至 少經由對應導電部件電連接至複數個第一導電接觸接針之 任意者且第二導電層經由對應導電部件電連接至除連接至 162093.doc •26· 201246727 第一導電層之第一導電接觸接針以外之複數個第一導電接 觸接針之任意者。 實施例5係根據實施例1之1C插座，其進一步包括支樓基 板之一本體；其中本體包含將待檢IC裝置配置在基板上之 特疋位置之一導引部分及將1C裝置插座配置在用於檢測ic 裝置之一檢測裝置之特定位置之一定位部分。 雖然本文已為了描述較佳實施例之目的闡釋及描述了特 定實施例，但是一般技術者應瞭解可在不脫離本發明之範 疇的情況下用經設想以達成相同目的之多種替代及/或等 效貫施方案取代所展示及描述之特定實施例。熟習機械、 電子機械及電氣技術者易瞭解本發明可實施為非常多種實 施例。本申請案旨在涵蓋本文所述之較佳實施例之任意選 用或變動。因此，本發明明顯旨在僅受限於申請專利範圍 及其等效物。 【圖式簡單說明】 圖1係根據本發明之1C裝置插座之一第一實施例之一組 態之一透視圖。 圖2展示沿著線II-II之圖i所示之IC裝置插座之一截面。 圖3係圖i所示之IC裝置插座之一基板之一平面圖且圖解 說明分段為接針配置之一導電層之位置關係之一實例。 圖4係圖2所示之截面結構之—部分m之一放大圖。 圖5係展示對應於圖3所示之平面圖之以部分之一電力層 之一組態之一平面圖。 圖6係展示對應於圖3所示之平面圖之以部分之一接地層 162093.doc -27- 201246727 之一組態之一平面圖。 圖7係展示根據本實施例之電力層之另一組態之—平面 圖。 圖8係展示除圖7所示之電力層以外其等間夾置一介電層 之接地層之一組態之一平面圖。 圖9係展示結構之一部分（c組件層）之一透視圖，其包含 具有圖7所示之結構之電力層（電力層被絕緣區域分段為兩 個或兩個以上區段）及圖8所示之接地層（電力層被絕緣區域 分段為兩個或兩個以上區段）以夾置介電層且亦展示對應 於圖3所示之部分IV之一基板區域。 圖10係遵循圖9所示之實例之一第一透視圖且展示在基 板内配置為層壓狀之複數個C組件層（其等由提供在其等兩 側上之介電層及導電層組態）之組合之一實例。 圖11係遵循圖9所示之實例之一第二透視圖且展示在基 板内配置為層壓狀之複數個C組件層之組合之一實例。 圖12係圖解說明當絕緣區域係一氣隙時ic裝置插座之一 組態作為圖9至圖11所示之組態之一替代實例之一透視 圖。 圖13係根據本實施例之1C裝置插座之一基板之一第一平 面圖且圖解說明劃分為接針配置之導電層之位置關係之另 一實例。 圖14係根據本實施例之1C裝置插座之一基板之一第二平 面圖且圖解說明劃分為接針配置之導電層之位置關係之另 一實例。 162093.doc -28- 201246727 圖15係根據本實施例之1(：裝置插座之一基板之一第三平 面圖且圖解說明劃分為接針配置之導電層之位置關係之另 一實例。 圖16係根據本實施例之1(：裝置插座之一基板之一第四平 面圖且圖解說明劃分為接針配置之導電層之位置關係之另 一實例。 【主要元件符號說明】 1 積體電路（IC)裝置插座 2 基板 2a 基板 2b 基板 2c 基板 2d 基板 3 導電接觸接針 3a 導電接觸接針 3b 導電接觸接針 3c 導電接觸接針 3d 導電接觸接針 3e 導電接觸接針 3f 導電接觸接針 3g 導電接觸接針 3h 導電接觸接針 3i 導電接觸接針 4 本體 162093.doc •29- 201246727 21 基底材料 22 介電層 23 介電層 25 介電層 26 表面 27 表面 28 通孔 31 接針本體 32 第一接觸部 33 第二接觸部 41 導引部分/導引壁 42 定位接針 221 上表面 222 電力層 222' 電力層 222a 電力層 222'a 電力層 222b 電力層 222'b 電力層 222c 電力層 222'c 電力層 222d 電力層 222'd 電力層 223 下表面 162093.doc -30- 201246727 224 接地（GND)層 224' 接地（GND)層 231 上表面 232 電力層 232' 電力層 233 下表面 234 接地（GND)層 234' 接地（GND)層 241 上表面 242 電力層 242' 電力層 243 下表面 244 接地（GND)層 244， 接地（GND)層 251 上表面 252 電力層 252' 電力層 253 下表面 254 接地（GND)層 254， 接地（GND)層 280a 開口 280b 開口 281 導電部件 290 絕緣區域 162093.doc -31- 201246727 290a 絕緣區域 290b 絕緣區域 290c 絕緣區域 290d 絕緣區域 2000 介電層 2000a 介電層 2000b 介電層 2100 電力層 2100a 電力層 2100b 電力層 2100c 絕緣區域 2200 接地（GND)層 2200a 接地（GND)層 2200b 接地（GND)層 2200c 絕緣區域 3000 介電層 3100 電力層 3100a 電力層 3100b 電力層 3100c 絕緣區域 3200 接地（GND)層 4000 介電層 4100 電力層 4200 接地（GND)層 162093.doc -32- 201246727 5000 介電層 II 線 III 部分 IV 部分 L 箭頭 LI 箭頭 L2 箭頭 L3 箭頭 L4 箭頭 162093.doc -33 -One of the insulated area segments is configured to allow a plurality of C components to be formed on a single plane. Meanwhile, although the capacitance of each C component is necessarily smaller than when the conductive layer is disposed over the entire surface of the substrate, the surface area of the segmented region of the conductive layer is not substantially limited by its surface area or flat pattern (form). As long as the required minimum capacitance can be guaranteed. In this case, even if a plurality of dielectric layers having segmented conductive layers on at least one of the surfaces thereof are arranged in a laminate in the base material, the pattern of the segments for the conductive layers of the respective dielectric layers may be different. At least a portion of the insulating region may be an air gap. The insulating material may also be a material different from the dielectric layer (for example, an insulating material such as an insulating material of a base material). In this case, the dielectric layer itself has a structure which is segmented in the horizontal direction together with the conductive layer. However, when segmented by different insulating materials or air gaps, specific differences in the function of the non-dielectric layer itself occur. Therefore, in the present specification, even if the dielectric layer has a structure which is segmented in the horizontal direction, such a segmented region is defined as a dielectric layer. An IC device socket in accordance with the invention of the present disclosure is formed from a substantially integrated substrate comprised of a base material as described above, wherein a dielectric layer and a conductive layer are provided which are provided together on both sides of the dielectric layer to configure the C component. Therefore, the distance between the conductive contact pin and the C component is extremely small, and thus the performance of the device socket can be improved. Further, the conductive contact pin is held in the substrate by press fitting or the like. The substrate serves as a conductive contact. The support of the pin, thus exempting 162093. Doc 201246727 The need to support another component of a conductive contact pin. The plurality of electrically conductive contact pins comprise a plurality of first conductive contact pins and a plurality of second conductive contact pins having a different connection state than the plurality of first conductive contact pins. Specifically, the plurality of first conductive contact pins are inserted into any of the plurality of through holes to correspond to the conductive members of the portions (the metal film or the like provided on the inner surface of the through hole) )contact. Portions of the plurality of second conductive contact pins are inserted into any of the plurality of through holes but remain in contact with the first conductive layer or the second conductive layer & no contact with the first conductive layer or the second conductive layer This state indicates that the second conductive contact pin does not contact the conductive member provided on the inner surface of the through hole or the conductive member is not provided on the inner surface of the through hole accommodating the second conductive contact pin. In this case, the first conductive layer and the second conductive layer are electrically connected to any of the plurality of first conductive contact pins 2 by respective conductive members interposed therebetween. The plurality of first conductive contact pins of the ic device socket according to the present invention are divided into a first group electrically connected only to the first conductive layer (eg, a power pin group) and only electrically connected to the second conductive The second group of layers (for example, a ground pin group). Further, a plurality of second conductive contact pins that are not electrically connected to either the first conductive layer or the second conductive layer serve as signal pins. According to the 1C device socket of the present invention, at least one of the first conductive layer and the second conductive layer configuring the c-component together with the dielectric layer is interspersed in the horizontal direction, and the insulating region is divided into two Or more than two sections. According to the present configuration, the thickness of the substrate can be more effectively suppressed compared with the case where different power supplies and/or grounds are arranged in a laminate in the substrate. Doc 201246727 In addition, since the number of processes involved in the process itself can be reduced for laminating the c-components in which the base material is interposed, the substrate fabrication is simplified (the production cost is lowered). [Embodiment] An embodiment of a 1C device socket according to the present invention will be described below with reference to Figs. Note that in the respective drawings, the same component symbols are designated the same or similar components and the repeated description is omitted. First, the basic structure of the IC device socket according to the present embodiment will be described in detail herein with reference to FIGS. 1 through 6. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a perspective view of one of the configurations of a first embodiment of a 1C device socket in accordance with the present invention. Figure 2 shows a cross section of the ic device socket shown in Figure 1 along line π-ΙΙ. Figure 3 is a plan view showing a structure of one of the substrates 2 of the ic device socket 1 shown in Figure 1. Note that the arrow L in Fig. 3 substantially matches the line II-II in Fig. 1. A 1C device socket 1 includes a substrate 2, a plurality of conductive contact pins 3 held by a press fit or the like in the substrate 2, and a body 4 of the support substrate 2. The body 4 includes a device for detecting an IC to be inspected ( Not shown) a guide portion or guide wall 41 disposed at a specific position on the substrate 2 and further including a specific one for arranging the 1C device socket 1 in a detecting device (not shown) for detecting an IC device One of the positions of the positioning unit (one of the positioning pins 42 shown in FIG. 2 in this embodiment). Note that the body 4 can be incorporated into 1 (: device socket 1 as needed. Further, the substrate 2 can have a positioning hole or a recess to cooperate with the positioning member. Fig. 4 is an enlarged view of a portion of the cross-sectional structure shown in Fig. 2. As shown in Figure 4, the substrate 2 is composed of a dielectric (such as fiberglass epoxy or class 162093. Doc 201246727, a substrate material 21 composed of at least one of dielectric layers 22 to 25 (first dielectric layer to fourth dielectric layer) embedded in base material 21 (four are shown as an example in FIG. 4) A conductive layer of copper and the like is formed on the upper surface side and the lower surface side of the dielectric layer. As shown in FIG. 2, the conductive layer embedded in the base material 21 is also horizontally inserted in one of the insulating regions. Section 290. The insulating region 290 refers to a region composed of an insulating material such as a base material or a conductive material. In the example shown in FIG. 4, the insulating region 290 includes a portion of the base material 21 and a portion of the first dielectric layer 22 to the fourth dielectric layer 25. As described above, a single dielectric layer cooperates with a conductive layer formed on both surfaces thereof to configure a C component. Specifically, the substrate 2 is formed by laminating the material of the base material 21, the conductive layer and the dielectric layer (a portion of the base material). The dielectric constant of the dielectric layer is preferably high to improve the capacitance of the device. For example, the first dielectric layer 22 to the fourth dielectric layer 25 are preferably composed of a high dielectric having a dielectric constant higher than the dielectric constant of the substrate material 21. For example, an embedded capacitor material (ECM) manufactured by 3M can be used as a high dielectric. The ECM is made of a dielectric material formed as a flexible sheet. A substrate of this type can be fabricated using a method for making a printed circuit board. The material constituting the substrate 2, which is the material of the base material 21, may be an insulating material and may include paper-cut glass, fibers, and bismuth-containing resin & polyaniline resin instead of epoxy resin. Silver or gold may be used instead of copper as the material constituting the conductive layer. The first to fourth dielectric layers 22 to 25 may each comprise a polymer. The first to fourth dielectric layers 22 to 25 preferably each comprise a polymer and: a plurality of particles and in particular are produced by mixing a resin with particles. Required 162093. Doc • 11 · 201246727 Resin contains epoxy resin, poly ugly amine, polyethylene terephthalate, ethyl acrylate chain powder, benzocyclobutene, polynorbornazole, polytetraethylene, acrylic acid A combination of vinegar or the like. The particles comprise dielectric (or insulating) particles and representative examples include a combination of barium titanate, barium titanate, titanium oxide, lead barium titanate, and the like. The thickness of each of the first dielectric layer 22 to the fourth dielectric layer 25 can be, for example, 0. 5 μπι or greater and 100 (four) or more, ],. The thickness is preferably thinner, for example, 15 μm or less or 10 (four) or less, thus improving the electrostatic capacity of the capacitor. However, the thickness of the dielectric layer is preferably thicker from the viewpoint of joint strength, for example, a thickness of 1 μm or more. Further, the relative dielectric constant of the dielectric is preferably high, for example, 1 〇 or more or 12 or more. "Although there is no specific limitation on the upper limit, the relative dielectric constant may be, for example, 30 or less. , 16 or less or 2 inches or less. One of the conductive layers formed on either side of the first dielectric layer 22 to the fourth dielectric layer 25 is electrically connected to 1 (: one of the power pins of the device socket 1 and another conductive layer The configuration is electrically connected to one of the grounding layers of the grounding (hereinafter referred to as GND) pin of the device socket 1. Specifically, a first power layer is disposed, and the segmented region 222 of the interpenetrating insulating region 290 is interposed. And 222 is formed on an upper surface 221 of the first dielectric layer 22 which is closest to one surface 26 (the upper surface in FIG. 2) on the device side of the substrate 2, and is configured with a first GND layer, The segmented regions 224 and 224 interspersed with the insulating regions 290 are formed on the lower surface 223. Similarly, a second power layer is disposed, and the segmented regions 232 and 232' interposed between the insulating regions 290 are formed in the positioning. On the upper surface 231 of the second dielectric layer 23 directly under the first dielectric layer 22, and configured a 162093. Doc • 12-201246727 Two GND layers, the inter-regional interleaved insulating regions 290 are formed on the lower surface 233 by segmented regions 234 and 234'. Further, a segmented region 252 and 252' configuring a fourth power layer, the inter-inserted insulating region 290 is formed on the surface 27 (lower surface in FIG. 2) on the side of the detecting device closest to the substrate 2. One of the four dielectric layers 25 is on the upper surface 251, and a fourth GND layer is disposed, and the segmented regions 254 and 254' of the intervening interposing insulating regions 290 are formed on the lower surface 253. Similarly, a segmented region 242 and 242' configuring a third power layer, interspersed with insulating regions 290, is formed on an upper surface 241 of the third dielectric layer 24 positioned directly above the fourth dielectric layer 25. The segmented regions 244 and 244' of the third GND layer, which are interposed between the insulating regions 290, are formed on the lower surface 243. Note that the cross-sectional structure shown in Fig. 4 shows that the upper surface 26 of the substrate 2 matches the upper surface of the base material 21 and the lower surface 27 of the substrate 2 matches the lower surface of the base material 21. Different potentials can be set for segmented regions 222 and 222' of the first power layer and different GND settings (electrical connections to different GND pins) are possible for segmented regions 224 and 224' of the first GND layer. Different potentials can be set for the segment regions 232 and 232' of the second power layer and a separate GND setting is possible for the segment regions 234 and 234' of the second GND layer. Different potentials can be set for the segment regions 242 and 242' of the third power layer, and the segment regions 244 and 244' of the third GND layer need not be electrically connected to the common GND pin. Different potentials can be set for the segmented regions 252 and 252' of the fourth power layer and the segment regions 254 and 254' of the fourth GND layer need not be electrically connected to the common GND pin. Note that in the example shown in FIG. 4, all of the first dielectric layer 22 to the fourth dielectric layer 25 are provided on both sides thereof, and the conductive layer is interspersed in the horizontal direction 162093. Doc -13- 201246727 is segmented in its insulating zone 290. However, a plurality of dielectric layers may be provided in a configuration in which the laminate 2 is laminated to provide a dielectric layer on both sides thereof and an unsegmented conductive layer. For example, when the unsegmented conductive layer is disposed over the entire surface of the substrate 2, a C-component having a surface area substantially equal to the surface area of the substrate 2 can be formed. In addition, the surface area of the unsegmented conductive layer can be determined based on the desired capacitance of the c-component without ensuring that the surface area needs to match the entire surface of the substrate 2. Further, any flat shape of the conductive layer can be determined in the substrate 2 regardless of whether or not the conductive layer is segmented. Each of the conductive contact pins 3 penetrates the substrate 2 in a substantially vertical direction passing through the upper layer 26 and the lower layer 27 of the substrate 2. Specifically, a through hole 28 into which the conductive contact pin 3 can be inserted is formed in the base material 21 and the dielectric layer and the conductive layer of the constituent substrate 2 formed on both sides thereof. A conductive member 281 of copper, gold, silver or the like is formed on the inner side surface of the through hole 28 by electroplating or the like. The pin body 3, which is press-fitted to the conductive contact pin 3 of the through hole 28 (except for the conductive contact pins 3 as signal pins), is electrically connected to any of the conductive layers through the conductive member 28 1 . Note that the inner surface of the hole of the signal pin may or may not be formed with the conductive member 28J. The through hole 28 is sized to allow the conductive contact pin 3 to be held in the through hole without being attributed to the spring mounted in the conductive contact pin 3 which is generated when the 1C device is inserted on the detecting device substrate. The reaction force falls out. For example, t, the press-fit & pressing force of the conductive contact pin 3 is preferably 〇1 N or more. The size of the through hole can be determined in such a manner that the conductive contact pin 3 can be removed from the through hole 28 relatively easily when the conductive contact pin 3 is replaced or maintained. In addition, the through hole is 162093 when the conductive contact pin 3 is removed from the substrate 2. Doc 201246727 The size of the through hole 28 is determined in such a manner that the conductive member 281 on the inner surface does not fall off. For example, the press-fit clamping force of the conductive contact pin 3 is preferably not more than 2. 0 N . Each of the conductive contact pins 3 includes a substantially cylindrical pin body 31 held in the substrate 2 by press-fitting, and can be electrically contacted by protruding from one end of the pin body 31 (lower end in FIG. 4) ( That is, one of the first contact portions 32 of the detecting device (not shown) and the IC device can be electrically contacted (ie, electrically connected) by protruding from the other end of the pin body 31 (the upper end in FIG. 4) (not Shown) One of the second contacts 33. Although various modes can be used as the conductive contact pin 3', the so-called spring probe type (where both the contact portions 32 and 33 can be axially opposed to the pin by the spring and the like (not shown) in the pin body 31 The body 31 is displaced) is preferred. The shape of the pin body 31 of the conductive contact pin 3 is preferably cylindrical. When the conductive contact pin 3 is formed in this manner, the conductive contact pin 3 can be easily disposed in the substantially axial direction of the through hole 28 because the surface of the pin body 31 contacts the through hole 28 across a wide surface area. Since the contact surface area of the conductive member 281 and the conductive contact pin 3 is increased, an electrically stable connection can be achieved. The conductive contact pin 3 is divided into a power pin group electrically connected to the power layer, a GND pin group connected to the GND layer, and a signal pin group not connected to any of the layers. For example, as shown in FIG. 4, the conductive contact pin 3b is connected to both the first power layer segment region 222 and the third power layer segment region 242 and the conductive contact pin 3 is connected to the first power layer. The segment region 222' and the third power layer segment region 242 are both used as the first power pin. The conductive contact pin 3c is connected to the second power layer segment region 232 162093. Doc 15 201246727 and the fourth power layer segmentation region 252 and the conductive contact pins 3 f are connected to the second power layer segment region 232 and the fourth power layer segment region 252 for use as the second power connection needle. Similarly, the conductive contact pins 3a are connected to the first GND layer as the slave region 224 and the third power layer segment region 244 and the conductive contact pins 3h are connected to the first GND layer segment region 224, with the third power Both of the layer segmentation regions 244' are used as the first GND pins. The conductive contact pin 3d is connected to both the second GND layer segment region 234 and the fourth power layer segment region 254 and the conductive contact pin 3g is connected to the second GND layer segment region 234 and the fourth power layer segment region 254, both of which are used as the second pin. The conductive contact pin 3e is not connected to any of the conductive layers and thus serves as a signal pin. As shown in FIG. 4, the C component configured by the high dielectric (dielectric layer) sandwiched between the power layer and the GND layer is preferably provided as close as possible to the upper surface 26 and the lower surface 27 of the substrate 2 (respectively The surface of the base material 2 is matched with the upper surface and the lower surface, that is, the outer side. The reason for this is that if the distance between the conductive layer of the substrate 2 and the outer surface is small, a stable power supply can be achieved during the 10: device detection. More specifically, the smaller the distance between the upper surface 26 of the substrate 2 and the first dielectric layer 22 and the second dielectric layer 23, the greater the input sensitivity of the IC device under inspection. Therefore, the first dielectric layer 22 The second dielectric layer 23 is preferably disposed toward the upper surface 26 side with respect to an intermediate point between the upper surface 26 and the lower surface 27 of the substrate 2. Further, the third dielectric layer 24 and the fourth dielectric layer 25 are preferably disposed toward the lower surface 27 side with respect to an intermediate point between the upper surface 26 and the lower surface 27 of the substrate 2. In the present embodiment, the substrate 2 is configured as a substantially integrated object in which a dielectric layer composed of a high dielectric and each of which is sandwiched between the power layer and the GND layer is embedded. 162093. Doc -16 - 201246727 Therefore, the configuration of the C component disposed near the outer surface of the substrate 2 can be easily realized' thus allowing accurate 1C device detection. As described above, the conductive contact pins 3 are held substantially only by the substrate 2. Therefore, the C component having the required capacitance can be configured to be divided into a plurality of segments at any position within the substrate 2. Further, the substrate 2 may include a further C component in the thickness direction in the vicinity of its center, the further C component including a dielectric layer and a conductive layer formed on both sides thereof. The length of each of the conductive contact pins 3 is preferably shorter from the viewpoint of electrical characteristics and the like. However, as the length of the conductive contact pin 3 becomes shorter, the operation and assembly at the time of replacing the pin become more difficult. Conversely, according to the present basic structure, even when a relatively long conductive contact pin 3 is used, there is no need to consider the reduction in the performance of the 1C device socket 1, since the configuration due to the above substrate 2 can be achieved with respect to electrical characteristics. The effect is similar when using a shorter magazine pin. If the length of the pin body 31 is longer than the thickness of the substrate 2, the conductive contact pin 3 is also effectively made longer, thereby lowering electrical characteristics. Conversely, if the length of the pin body 31 is shorter than the thickness of the substrate 2 such that the axial end of the pin body 31 is positioned farther than the center of the substrate than any of the conductive layers, the conductive contact pin 3 reaches the conductive layer. The path becomes complicated, thus reducing the performance of the lc device socket. Therefore, the axial length of the pin body 31 of the conductive contact pin 3 is preferably approximately equal to the thickness of the substrate 2. Note that the thickness of the substrate 2 is preferably determined in consideration of the structural strength required to hold the conductive contact pins 3 and is therefore preferably made as thin as possible while maintaining an appropriate level of strength. Further, the 1C device socket 1 according to the present embodiment is provided with, for example, four 162093. Doc • 17- 201246727 The dielectric layers 22 to 25 (on which power and GND layers are formed on both sides thereof) are laminated into one of the portions of the interstitial substrate material 21 interposed therebetween. According to the configuration, different voltage settings and different connections in a package having a 1C device socket 1 are also referred to as "J rows" because, for example, different potential settings between the first power layer and the second power layer 2 are feasible. . In addition, different power setting and/or grounding settings for each segmented area may be performed even within the same layer. For example, different power δ may be set for the segment region 222 and the segment region 222 of the first power layer, and different power settings may be set for the segment region 232 and the segment region 232 ′ of the second power layer. Specifically, the first power layer has a flat shape as shown, for example, in FIG. 5 and the GND layer has a flat shape as shown, for example, in FIG. Note Intention 5 shows that the first power layer configuration corresponding to one of the portions of the plan view shown in Fig. 3 and any of the other second to fourth conductive layers may have a similar flat shape. Fig. 6 shows the first GND layer configuration corresponding to the plan of the plan shown in Fig. 3 and any of the other second GND layer to the fourth GND layer may have a similar flat shape. As shown in Fig. 5, the first power layer is configured by a segmented region 222 and a segmented region 222 that are horizontally interspersed by the insulating region 290 interposed therebetween. The segmented regions 222 and 222 have openings 28〇& and 28〇b having different types of direct control at positions corresponding to the through holes 28 provided in the substrate 2. Note that the two types of openings 28 〇 & and 280b provided in each of the / knife slave areas 222 and 222 are disposed in the direction of the arrow in FIG. The arrow li roughly matches the line π-π in Fig. 1 (substantially matches the cross section shown in Fig. 4). The opening 28〇& has a diameter that substantially matches one of the diameters of the through hole 28 or, more specifically, has a tolerance of 162093. Doc -18-201246727 A hole diameter of one of the electrical contact states is sufficiently maintained between the conductive member 281 formed on the inner surface of the through hole 28 and the segmented regions 222 and 222' configuring the first power layer. Conversely, the opening 280b has a diameter larger than one of the diameters of the through holes 28 or, more specifically, a hole diameter of, for example, about 50 μm larger than the diameter of the through hole 28 and may be formed on the inner surface of the through hole 28. The electrically conductive component 281 is sufficiently maintained in electrical isolation from the segmented regions 222 and 222' configuring the first power layer. Further, as shown in Fig. 6, the first GND layer is also configured by the segmented region 224 and the segmented region 224' which are horizontally segmented by the insulating region 290 interposed therebetween. Similar to the segmented regions 222 and 222' of the first power layer, the segment regions 224 and 224' have two types of openings 280a having different diameters at positions corresponding to the through holes 28 provided in the substrate 2. 280b. Note that the two types of openings 280a and 280b provided in each of the segment areas 224 and 221 are disposed in the direction of the arrow L2 in Fig. 6. The arrow L2 roughly matches the line 11-11 in Fig. 1 (substantially matching the cross section shown in Fig. 4). The opening 280a has a diameter that substantially matches one of the diameters of the through holes 28 or, more specifically, allows the conductive members 281 formed on the inner surface of the through holes 28 and the segmented regions 224 and 224' constituting the first GND layer to be properly maintained. The electrical contact is one of the hole diameters. Conversely, the opening 280b has a diameter larger than one of the diameters of the through holes 28 or, more specifically, the conductive member 281 which is formed on the inner surface of the through hole 28 and the segmented region 224 which constitutes the first GND layer, for example. One of the appropriate electrical isolation states between 224' and the diameter of the hole. In this manner according to this embodiment, each of the power layers is disposed such that a layer 162093 is interposed between portions of the base material 21 constituting the insulating material in the substrate 2. Doc • 19-201246727 Pressured' thereby allows the first power layer to the fourth power layer to have different potential settings while also allowing the segmented regions within each power layer to have different potential settings. In particular, the structure of the present invention is effective because the thickness of the substrate 2 (the interval between the upper surface 26 and the lower surface 27) can be prevented from increasing (which is higher when the potential setting in the socket 1 of the Ic device becomes complicated) The layers of the number are laminated together). A C component (hereinafter referred to as a c component layer) for configuring a dielectric layer and a conductive layer provided on both sides of a dielectric layer in the above-described embodiments shown in FIGS. 1 to 6 includes The structure of the segmented conductive layer of each of the electrical layer 22 to the fourth dielectric layer 25. However, different segment patterns of the conductive layer can also be used for each C component layer. Note that the most basic structure is a structure including a c-component layer (see Fig. 9) in the substrate 2. An example of one of the power layers that can be used in the structure shown in Figure 9 is shown in Figure 7. As shown in FIG. 7, the power layer 21 is inserted in the horizontal direction (in one direction orthogonal to the direction from the upper surface 26 of the substrate 2 toward the lower surface 27), and is interposed between one of the insulating regions 2100c. The segment area 2100a and the segment area 21 〇〇b. Note that the two types of openings 280a and 280b provided in the power layer 21A are disposed in the direction of the arrow 13 in Fig. 7. The arrow L3 roughly matches the line π_π in the figure (substantially matches the section shown in Fig. 4). As shown in FIG. 8, the GND layer 2200 is also interspersed between its insulating regions 22C horizontally into a segmented region 2200a and a segmented region 2200b. The segmented regions 220a and 2200b also have openings 280a and 280b formed therein having two types of diameters. Note that the two types of openings 280a and 280b are arranged in the direction of the arrow L4 in Fig. 8. The arrow [4 roughly matches I62093 in Figure 1. Doc •20* 201246727 Line 11-11 (roughly matching the section shown in Figure 4). As described above, the basic structure shown in Fig. 9 can be achieved by providing a layer structure in which a dielectric layer 2100 is sandwiched between the power layer 2100 and the GND layer 2200 which are both divided into two in the horizontal direction. In this case, a plurality of types of power settings can be achieved without increasing the thickness of the substrate 2. Note that FIG. 9 is a perspective view showing a portion (C component layer) of the structure in which the dielectric layer is formed by the power layer having the structure shown in FIG. 7 (the power layer is segmented into two or more sections by the insulating region). And the GND layer (the GND layer is segmented into two or more segments by the insulating region) shown in FIG. 8 and also exhibits a substrate region corresponding to one of the portions IV shown in FIG. In the above example shown in FIG. 9, although a plurality of c-components can be implemented on one plane (corresponding to the power layer 2100 and the GND layer provided by the dielectric layer 200 and on either side of the dielectric layer 2? 2200 configuration c component layer ground plane), but a plurality of C component layers are arranged in a laminated form in the substrate 2, and the structure may include the C component layer shown in FIG. 9 and another C with a segmented conductive layer pattern. A combination of component layers. 10 and FIG. 11 are perspective views of the reduced example shown in FIG. 9 and showing a plurality of C component layers arranged in a laminate in a substrate (the dielectric layer and the conductive layer provided on both sides thereof, etc.) An example of a combination of configurations). In the example shown in Fig. 10, the first c-component layer shown in Fig. 9 and the second c-component layer having a pattern of different segmented conductive layers are arranged in a laminated shape in the substrate 2. As described above, the first C component layer is configured by the following layers: the dielectric layer 2000, which is provided on one surface of the dielectric layer 2 and interspersed with an insulating region 2100 (: a segmented region) 2100a and 2100b power layer 2100, 162093. Doc • 21 · 201246727 and a GND layer 2200 configuration comprising segmented regions 2200a and 2200b provided on the other surface of dielectric layer 2000 with intervening regions 2200c interposed therebetween. At the same time, the second C component is provided by the dielectric layer 3000, the power layer 3100 provided on one surface of the dielectric layer 3 and interspersed with the segment regions 3 100a and 3 100b of the insulating region 2100c, and is not segmented and provided. A GND layer 3200 on the other surface of the dielectric layer 3〇〇〇. Note that the shape (segment pattern) of the insulating region 2100c in the power layer 2100 of the first C component layer and the shape (segment pattern) of the insulating region 3100c in the power layer 3100 of the second C component layer may of course be different. Moreover, the unsegmented GND layer 3200 of the second C component layer does not necessarily have a surface area that matches the upper surface 26 or the lower surface 27 of the substrate 2. The surface area of the GND layer 3200 is just large enough to ensure that the required capacitance between the segmented regions 3100a and 3100b of the power layer 3100 is sufficient. In the example shown in Fig. 11, the first C component layer shown in Fig. 9 and the third C component having the different segmented conductive layer patterns are arranged in a laminate shape in the substrate 2. The structure of the first C component layer is the same as that of the above-described Figs. 9 and 10. The third c-component is configured by a dielectric layer 4000, a power layer 4100 that is unsegmented and provided on one surface of the dielectric layer 4000, and is un-segmented and provided on the other surface of the dielectric layer 4000. GND layer 4200 configuration. The respective surface areas of the unsegmented power layer 4100 and the unsegmented GND layer 4200 of the third C component layer do not necessarily match the surface area of the upper surface 26 or the lower surface 27 of the substrate 2. As seen from the direction of the upper surface 26 of the substrate 2 toward the lower surface 27, the capacitance of the c-component is determined by the surface area of a region where the power layer 4100 overlaps the GND layer 4200. Therefore, the surface area and the flat shape of the power layer 41 and the surface area and the flat shape of the GND layer 4200 can be determined within a range in which the required capacitance of each can be secured. 162093. Doc • 22· 201246727 / The main idea is that at least a portion of the insulating region of the conductive layer segment can be an interspace gap such as, for example, an air gap. For example, as shown in FIG. 12, when all of the plurality of C component layers (including the C component layer shown in FIG. 9) have segmented conductive layers, the insulating region 21〇〇c as an air gap preferably has an extension. The upper surface thereof is brought to the upper surface 26 of the substrate 2 and the lower surface thereof is shaped to one of the lower surfaces 27 of the substrate 2. As shown in FIG. 12, the dielectric layer 2 is segmented into two portions 2〇〇〇a and 2〇〇〇b in the horizontal direction; the power layer 2100 is also segmented into two portions 2i in the horizontal direction. 〇〇a and 2i〇〇b and further the GND layer 2200 is also segmented into two portions 22〇〇& and 22〇〇b in the horizontal direction. In the ic device socket according to the present embodiment, other structural components other than the dielectric layer 2, the power layer 21, and the 〇1 layer 2200 may be used as an air gap in the horizontal direction. The insulating region 210〇c is segmented. Note that Fig. 12 shows the internal structure corresponding to the portion 卩, > In addition, a plurality of dielectric layers (i.e., a plurality of germanium component layers) may be configured to be laminated. Specifically, in addition to the c component layer shown in Fig. 12, the configuration in Fig. 12 may include another C component layer such as that shown in Fig. 1A or Fig. In the example of FIG. 12, the power layer 21 and the dielectric layer 22 and the dielectric layer 2000 are segmented in the horizontal direction by applying an air gap in the insulating region 2100c. However, When segmented by different insulating materials or air gaps, specific differences in the function of the dielectric-free layer itself occur. Therefore, in the present specification, even if the dielectric layer has a structure that is segmented in the horizontal direction, such segmented regions Still defined as a dielectric layer. As described above, the dielectric layer 2 and the power layer 21 are compared with the case where different power supplies and/or grounds are arranged in a laminate in the substrate (; 〇]^1) I62093. Doc •23- 201246727 At least one of the layers 2200 configuration c component configuration allows for a significant effect of increasing the thickness of the substrate. Further, since the number of processes involved in the process itself can be reduced for laminating a C-component layer in which a portion of the base material is interposed, etc., the substrate fabrication is simplified (the production cost is lowered). Further, the arrangement of the conductive contact pins 3 in the device socket 1 by the substrate 2 can be employed in various configurations without being limited to the rectangular shape shown in FIG. 3. Further, it can be set as needed The surface area and shape of the conductive layer and/or gnd layer of the continuous pattern segmentation of the conductive contact pins 3 used. This consistent example is shown in Figures 13 to 16. Note that Figures 13 to 16 are in accordance with the present embodiment. A plan view of the respective substrates of the 1C device socket and illustrating other examples of the positional relationship of the conductive layers divided into the pin configurations. Further, FIGS. 13 to 16 are shown corresponding to the substrate 2 and the first based on the example shown in FIG. The positional relationship of the elements of the segmented regions 222 and 222' of the power layer. In the example shown in Fig. 13, the conductive contact pins 3 in the substrate 2a are disposed in a rectangular ring shape sandwiched by the outer periphery of the rectangle and the inner periphery of the rectangle. And the conductive layer of the C component layer configured in the substrate 2a is divided into two segmented regions 222a and 222'a in the horizontal direction by the intervening insulating region 290a, as shown in FIG. In the example, the conductive connection The pin 3 is disposed in the inner rectangular region and is also disposed in the rectangular annular region surrounding the inner rectangular region in the substrate 2b. In this case, any one of the conductive layers configuring the c component layer disposed in the substrate 2b can be divided. The segment is such that, for example, the segmented region 222b surrounds the segmented region 222'b, which is interspersed with the insulating region 290b. In the example shown in Figure 15, the conductive contact pins 3 are along the substrate at 162093. Doc •24· 201246727 The outermost perimeter configuration of one of the rectangular areas. In this case, any of the conductive layers configuring the C component layer disposed in the substrate 2c may be segmented into, for example, segmented regions 222c and 222'c, which have follow-up, etc. The shape of the conductive contact pins 3 is interposed between one of the insulating regions 290c. Further, in the example shown in Fig. 16, in the substrate 2d, the conductive contact pins 3 are arranged in two columns having a certain distance between them. In this case, any of the conductive layers configuring the C component layer disposed in the substrate 2d may be segmented into, for example, segmented regions 222d and 222'd of respective columns interspersed with the insulating regions 290d. 1. . . 1C device socket; 2, 2a, 2b, 2c, 2d... substrate; 21·. ·Substrate material; 22 5. 25 '2000, 2000a, 2000b, 3000 '4000, 5000. . . Dielectric layers; 222, 222', 222a, 222, a, 222b, 222, b, 222c, 222, c, 222d, 222'd '232, 232'' 242, 242' ' 252, 252', 2100, 2100a, 2100b, 3100, 3100a, 3100b, 4100. . . Power layer; 224, 224', 234, 234', 244, 244', 254, 254', 2200, 2200a, 2200b, 3200, 4200... GND layer; . . Through hole; 3, 3a to 3i. . . Conductive contact pin; 31 pin body; 32. . . First contact portion; 33... second contact portion; 4. . . Body; 290, 290a, 290b, 290c, 290d, 2100c, 2200c, 3 100c... Insulation area ° The following is an illustrative embodiment of a socket of an IC device according to aspects of the present invention. Embodiment 1 is a 1C device socket, comprising: a substrate having a first surface; a second surface facing the first surface; and a plurality of passes 162093. Doc -25- 201246727 holes, each of which is in communication with the first _ 矣 & and the first surface; and a plurality of conductive pins ‘the part of which is inserted into any of the plurality of through holes; 'the substrate comprises. a base material having a first surface, a second surface, and a plurality of through holes, at least one dielectric layer being provided between the first surface and the second surface in a state of being intersected with the plurality of through holes The electric layer has a dielectric constant higher than the base material; and a first conductive layer and a second conductive layer, etc. sandwich the dielectric layer along the first surface of the base material facing the second surface; The conductive contact pin includes: a plurality of first electrical contact pins, and the like - a portion of the plurality of through holes is electrically connected to the first conductive layer or the second conductive layer; and the plurality of - One of the conductive contact pins' is inserted into any of a plurality of through holes other than the through holes through which the plurality of first conductive contact pins are inserted, the portion not being electrically connected to the first conductive layer or the second a conductive layer; and wherein any one of the first conductive layer and the second conductive layer is interspersed in the horizontal direction, and one of the insulating regions is segmented into two or more segments. Embodiment 2 is the ric device socket according to the embodiment, wherein the insulating region has a shape in which a surface extends to the first surface of the base material and another surface opposite the surface extends to reach the second surface of the base material. Embodiment 3 is the device socket according to Embodiment 2, wherein at least a portion of the insulating region is an air gap. Embodiment 4 is the device socket according to the embodiment, wherein any one of the plurality of through holes has a conductive member on an inner surface thereof and the first conductive layer is electrically connected to the plurality of first portions via at least the corresponding conductive member Any one of the conductive contact pins and the second conductive layer is electrically connected to the second conductive layer via the corresponding conductive member to be connected to 162093. Doc •26· 201246727 Any of a plurality of first conductive contact pins other than the first conductive contact pins of the first conductive layer. Embodiment 5 is the 1C socket according to Embodiment 1, further comprising a body of the support substrate; wherein the body comprises a guiding portion for configuring the IC device to be inspected on the substrate, and the 1C device socket is disposed at A positioning portion for detecting a specific position of one of the detecting devices of the ic device. Although specific embodiments have been illustrated and described herein for purposes of describing the preferred embodiments, those skilled in the art The specific embodiments shown and described are replaced by the embodiments. Those skilled in the art, mechanical, electrical, and electrical, will appreciate that the present invention can be embodied in a wide variety of embodiments. This application is intended to cover any selection or variation of the preferred embodiments described herein. Therefore, the invention is obviously intended to be limited only by the scope of the claims and the equivalents thereof. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a perspective view showing one of the configurations of a first embodiment of a 1C device socket according to the present invention. Figure 2 shows a cross section of the socket of the IC device shown in Figure i along line II-II. Figure 3 is a plan view showing one of the substrates of one of the IC device sockets shown in Figure i and illustrating an example of the positional relationship of one of the conductive layers in the pin configuration. Figure 4 is an enlarged view of a portion m of the cross-sectional structure shown in Figure 2. Fig. 5 is a plan view showing one of the configurations of one of the power layers corresponding to the plan view shown in Fig. 3. Figure 6 shows a portion of the ground plane 162093 corresponding to the plan view shown in Figure 3. Doc -27- 201246727 One of the configurations of one of the plans. Fig. 7 is a plan view showing another configuration of the power layer according to the present embodiment. Fig. 8 is a plan view showing one of the configurations of a ground layer in which a dielectric layer is interposed, except for the power layer shown in Fig. 7. Figure 9 is a perspective view showing a portion (c component layer) of the structure including the power layer having the structure shown in Figure 7 (the power layer is segmented into two or more segments by the insulating region) and Figure 8 The illustrated ground plane (the power layer is segmented into two or more sections by the insulating regions) to sandwich the dielectric layer and also exhibits a substrate region corresponding to one of the portions IV shown in FIG. Figure 10 is a first perspective view of one of the examples shown in Figure 9 and showing a plurality of C component layers arranged in a laminate in a substrate (these are provided by dielectric layers and conductive layers on both sides thereof) An example of a combination of configurations). Figure 11 is an example of a combination of a plurality of C component layers that follow a second perspective view of the example shown in Figure 9 and that is configured to be laminated in a substrate. Fig. 12 is a perspective view showing an alternative configuration of one of the configurations of the ic device socket as an alternative to the configuration shown in Figs. 9 to 11 when the insulating region is an air gap. Figure 13 is a first plan view showing one of the substrates of the 1C device socket according to the present embodiment and illustrating another example of the positional relationship of the conductive layers divided into the pin configurations. Figure 14 is a second plan view of one of the substrates of the 1C device socket according to the present embodiment and illustrates another example of the positional relationship of the conductive layers divided into the pin configurations. 162093. Doc -28-201246727 Figure 15 is a third plan view of one of the substrates of the device socket according to the present embodiment and illustrates another example of the positional relationship of the conductive layers divided into the pin configurations. Embodiment 1 (1: a fourth plan view of one of the substrates of the device socket and illustrating another example of the positional relationship of the conductive layers divided into the pin configurations. [Description of main component symbols] 1 Integrated circuit (IC) device socket 2 substrate 2a substrate 2b substrate 2c substrate 2d substrate 3 conductive contact pin 3a conductive contact pin 3b conductive contact pin 3c conductive contact pin 3d conductive contact pin 3e conductive contact pin 3f conductive contact pin 3g conductive contact pin 3h conductive contact pin 3i conductive contact pin 4 body 162093. Doc •29- 201246727 21 Base material 22 Dielectric layer 23 Dielectric layer 25 Dielectric layer 26 Surface 27 Surface 28 Through hole 31 Connector body 32 First contact 33 Second contact 41 Guide portion / Guide wall 42 Positioning pin 221 upper surface 222 power layer 222' power layer 222a power layer 222'a power layer 222b power layer 222'b power layer 222c power layer 222'c power layer 222d power layer 222'd power layer 223 lower surface 162093. Doc -30- 201246727 224 Ground (GND) Layer 224' Ground (GND) Layer 231 Upper Surface 232 Power Layer 232' Power Layer 233 Lower Surface 234 Ground (GND) Layer 234' Ground (GND) Layer 241 Upper Surface 242 Power Layer 242' Power layer 243 Lower surface 244 Ground (GND) layer 244, Ground (GND) layer 251 Upper surface 252 Power layer 252' Power layer 253 Lower surface 254 Ground (GND) layer 254, Ground (GND) layer 280a Opening 280b Opening 281 conductive part 290 insulation area 162093. Doc -31- 201246727 290a Insulation Zone 290b Insulation Zone 290c Insulation Zone 290d Insulation Zone 2000 Dielectric Layer 2000a Dielectric Layer 2000b Dielectric Layer 2100 Power Layer 2100a Power Layer 2100b Power Layer 2100c Insulation Area 2200 Ground (GND) Layer 2200a Ground ( GND) Layer 2200b Ground (GND) Layer 2200c Insulation Area 3000 Dielectric Layer 3100 Power Layer 3100a Power Layer 3100b Power Layer 3100c Insulation Area 3200 Ground (GND) Layer 4000 Dielectric Layer 4100 Power Layer 4200 Ground (GND) Layer 162093. Doc -32- 201246727 5000 Dielectric Layer II Line III Part IV Part L Arrow LI Arrow L2 Arrow L3 Arrow L4 Arrow 162093. Doc -33 -