WO2012074271A2 - 전계방출 표시장치와 그 제조방법 - Google Patents
전계방출 표시장치와 그 제조방법 Download PDFInfo
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- WO2012074271A2 WO2012074271A2 PCT/KR2011/009156 KR2011009156W WO2012074271A2 WO 2012074271 A2 WO2012074271 A2 WO 2012074271A2 KR 2011009156 W KR2011009156 W KR 2011009156W WO 2012074271 A2 WO2012074271 A2 WO 2012074271A2
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- carbon nanotubes
- seed metal
- metal layer
- insulating layer
- substrate
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J9/00—Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
- H01J9/02—Manufacture of electrodes or electrode systems
- H01J9/18—Assembling together the component parts of electrode systems
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J1/00—Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
- H01J1/02—Main electrodes
- H01J1/30—Cold cathodes, e.g. field-emissive cathode
- H01J1/304—Field-emissive cathodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J3/00—Details of electron-optical or ion-optical arrangements or of ion traps common to two or more basic types of discharge tubes or lamps
- H01J3/02—Electron guns
- H01J3/021—Electron guns using a field emission, photo emission, or secondary emission electron source
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J31/00—Cathode ray tubes; Electron beam tubes
- H01J31/08—Cathode ray tubes; Electron beam tubes having a screen on or from which an image or pattern is formed, picked up, converted, or stored
- H01J31/10—Image or pattern display tubes, i.e. having electrical input and optical output; Flying-spot tubes for scanning purposes
- H01J31/12—Image or pattern display tubes, i.e. having electrical input and optical output; Flying-spot tubes for scanning purposes with luminescent screen
- H01J31/123—Flat display tubes
- H01J31/125—Flat display tubes provided with control means permitting the electron beam to reach selected parts of the screen, e.g. digital selection
- H01J31/127—Flat display tubes provided with control means permitting the electron beam to reach selected parts of the screen, e.g. digital selection using large area or array sources, i.e. essentially a source for each pixel group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J9/00—Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
- H01J9/02—Manufacture of electrodes or electrode systems
- H01J9/022—Manufacture of electrodes or electrode systems of cold cathodes
- H01J9/025—Manufacture of electrodes or electrode systems of cold cathodes of field emission cathodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J9/00—Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
- H01J9/02—Manufacture of electrodes or electrode systems
- H01J9/14—Manufacture of electrodes or electrode systems of non-emitting electrodes
- H01J9/148—Manufacture of electrodes or electrode systems of non-emitting electrodes of electron emission flat panels, e.g. gate electrodes, focusing electrodes or anode electrodes
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2201/00—Electrodes common to discharge tubes
- H01J2201/30—Cold cathodes
- H01J2201/304—Field emission cathodes
- H01J2201/30446—Field emission cathodes characterised by the emitter material
- H01J2201/30453—Carbon types
- H01J2201/30469—Carbon nanotubes (CNTs)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2329/00—Electron emission display panels, e.g. field emission display panels
- H01J2329/02—Electrodes other than control electrodes
- H01J2329/04—Cathode electrodes
- H01J2329/0407—Field emission cathodes
- H01J2329/0439—Field emission cathodes characterised by the emitter material
- H01J2329/0444—Carbon types
- H01J2329/0455—Carbon nanotubes (CNTs)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2329/00—Electron emission display panels, e.g. field emission display panels
- H01J2329/46—Arrangements of electrodes and associated parts for generating or controlling the electron beams
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/902—Specified use of nanostructure
- Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
- Y10S977/952—Display
Definitions
- the present invention relates to a field emission display device including a carbon nanotube (CNT) serving as an electron emission source and a method of manufacturing the same.
- CNT carbon nanotube
- the field emission display device forms an electric field between electron emitters (Field Emitter) and gate electrodes arranged at regular intervals on the cathode electrode to control the emission of electrons from the electron emitter, and the electrons are fluorescence on the anode electrode.
- An image is displayed by colliding with a substance.
- Carbon nanotubes have been considered as electron emission sources of field emission displays because of their very low work function and sharpness.
- Carbon nanotube synthesis methods include arc-discharge, laser vaporization, and pyrolysis. These methods require complex purification to obtain high purity after synthesizing carbon nanotubes. And structural control and vertical growth are difficult.
- chemical vapor deposition CVD
- the CVD method can be classified into thermal CVD method, DC plasma CVD method, RF plasma CVD method, and microwave plasma CVD method. Even in the known CVD method, it is difficult to synthesize carbon nanotubes with a stable structure of carbon nanotubes at a low temperature of 600 ° C. or lower, so that carbon nanotubes having a stable structure can be grown on a low-cost glass substrate mainly used in display devices. There was no.
- the present invention provides a field emission display device having a structure capable of stably growing vertically grown carbon nanotubes having a single crystal structure at a low temperature, and lowering a threshold voltage at which electrons are emitted from the carbon nanotubes.
- the field emission display device of the present invention includes an upper plate including an anode electrode and a phosphor formed on an upper substrate, a lower plate opposing the upper plate with a vacuum space gap therebetween and a plurality of thin film patterns formed on the lower substrate, and the upper plate. And a spacer disposed between the substrate and the lower plate to maintain the vacuum space gap.
- the lower plate may include a cathode electrode formed on a substrate including at least one metal of molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), or an alloy thereof;
- a diffusion barrier layer formed on the cathode electrode including any one or a mixture of titanium (Ti), tungsten (W), tantalum (Ta), silicon (Si), and a silicon compound;
- a gate insulating layer formed on a substrate on which the cathode electrode, the diffusion blocking layer, and the seed metal layer are formed to cover the carbon nanotubes;
- a gate electrode formed on the gate insulating layer including at least one metal of molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), or an alloy thereof. An upper end of the carbon nano
- the method of manufacturing the lower plate may include forming a cathode electrode including molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr) or one or more metals thereof on a substrate and patterning the cathode electrode; A diffusion barrier layer including any one or a mixture of titanium (Ti), tungsten (W), tantalum (Ta), silicon (Si), and a silicon compound is formed on the cathode electrode, and nickel (Ni) and iron (Fe) are formed.
- Mo molybdenum
- Al aluminum
- Cu copper
- Cr chromium
- a diffusion barrier layer including any one or a mixture of titanium (Ti), tungsten (W), tantalum (Ta), silicon (Si), and a silicon compound is formed on the cathode electrode, and nickel (Ni) and iron (Fe) are formed.
- the substrate including the cathode electrode, the diffusion barrier layer, and the seed metal layer is introduced into a chamber of a DC PECVD apparatus, the temperature of the substrate is heated to a temperature of 350 ° C. to 600 ° C., and the plasma energy is 2W / cm 3 in the chamber.
- the gate insulating layer by forming a gate insulating layer including one of an organic insulating material and an inorganic insulating material on the cathode electrode, the diffusion blocking layer, and the seed metal layer; And forming a gate electrode on the gate insulating layer including at least one metal of molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), or an alloy thereof, and patterning the gate electrode to form the carbon nano Forming a gate hole through which the top ends of the tubes are exposed.
- Mo molybdenum
- Al aluminum
- Cu copper
- Cr chromium
- the carbon nanotube growth process is performed while removing polycrystalline / amorphous carbons acting as an interference element of the single crystal carbon nanotubes (CNT), so that the single crystal carbon nanotubes (CNT) can be stably grown even at a low temperature of less than 600 ° C. have.
- the present invention lowers the threshold voltage by embedding the carbon nanotubes in the insulating layer and forms a diffusion barrier layer between the cathode electrode and the seed metal layer to prevent the seed metal from diffusing into other metals and disappearing, thereby stably growing the carbon nanotubes. Can be done.
- the present invention can increase the electron emission efficiency by lowering the threshold voltage by growing the carbon nanotubes (CNT) of the single crystal structure in the form of a cone cone that becomes sharper toward the top.
- CNT carbon nanotubes
- the present invention is a crystallization preliminary process that is usually performed to further lower the growth temperature of single crystal carbon nanotubes, and grows single crystal carbon nanotubes (CNT) in a state in which granulation and the above-described photoresist (PR) are left and decomposed.
- CNT single crystal carbon nanotubes
- PR photoresist
- the field emission display device of the present invention since the bottom panel of the field emission display device can be manufactured using the equipment of the TFT LCD production line, the field emission display device can be produced through the TFT LCD production line without additional equipment investment. .
- the present invention uses the photolithography process and the etching method to produce a spacer by patterning any one of the glass substrate and the ceramic substrate in the form of a mesh.
- the present invention has a stable structure, can be easily manufactured, and a low cost field emission display spacer can be manufactured.
- the upper and lower portions of the carbon nanotubes are covered by the gate insulating layer and are not exposed.
- the gate insulating layer can lower the electron emission threshold voltage of the carbon nanotubes.
- a separate electrode for drawing electrons is not necessary.
- FIG. 1 is a cross-sectional view schematically showing a DC PECVD equipment.
- FIG. 2 is a flowchart illustrating a method of synthesizing carbon nanotubes in accordance with an embodiment of the present invention.
- FIG. 3 is a flowchart illustrating a method of synthesizing carbon nanotubes in accordance with another embodiment of the present invention.
- 4A to 4C are cross-sectional views illustrating the growth process of carbon nanotubes step by step.
- FIG. 5 is a perspective view illustrating an example in which single crystal carbon nanotubes are grown in a cylindrical structure.
- FIG. 6 is a perspective view illustrating an example in which single crystal carbon nanotubes are grown in a conical structure.
- FIG. 7 is a plan view illustrating a portion of an electrode structure of a lower plate in a field emission display device according to an exemplary embodiment of the present invention.
- FIG. 8 is a cross-sectional view illustrating a cross-sectional structure of the field emission display according to the first exemplary embodiment of the present invention, taken along the line "I-I '" in FIG. 7.
- 9A through 9F are cross-sectional views illustrating a method of manufacturing a lower plate of the field emission display shown in FIG. 8.
- FIG. 10A through 10C are cross-sectional views illustrating a method of growing carbon nanotubes in a state in which a photoresist layer remains on a seed metal layer in the method of manufacturing a bottom panel of the field emission display shown in FIG. 8.
- FIG. 11 is a cross-sectional view illustrating a bottom plate cross-sectional structure of the field emission display device according to the second exemplary embodiment, taken along the line “I-I” in FIG. 7.
- 12A through 12F are cross-sectional views illustrating a method of manufacturing a bottom plate of the field emission display shown in FIG. 11.
- 13A to 13C are cross-sectional views illustrating a method of growing carbon nanotubes in a state in which a photoresist layer remains on a seed metal layer in the lower plate manufacturing method of the field emission display shown in FIG. 11.
- FIG. 14 and 15 are scanning electron microscope (Scanning Electron Microscope, SEM) images showing single crystal carbon nanotubes grown in a conical structure as a result of the carbon nanotube synthesis method as shown in FIG. 3.
- 16 is an exploded cross-sectional view illustrating an upper plate, a lower plate, and a spacer in a field emission display device according to an exemplary embodiment of the present invention.
- FIG. 17 is an exploded perspective view illustrating an upper plate, a lower plate, and a spacer in FIG. 16.
- 18A to 18C are plan views illustrating various structures of the spacer according to the embodiment of the present invention.
- 19A and 19B are views illustrating an exhaust path formed in a spacer according to an embodiment of the present invention.
- 20 is a flowchart illustrating a method of manufacturing a spacer according to an embodiment of the present invention.
- FIG. 21 is a cross-sectional view illustrating a method of manufacturing the spacer illustrated in FIG. 20.
- FIG. 22 is a cross-sectional view illustrating an example of an anisotropic wet etching method which may be applied to a method of manufacturing a spacer according to an embodiment of the present invention.
- FIG. 23 is a diagram illustrating an apparatus for processing the anisotropic wet etching method illustrated in FIG. 22.
- the field emission display device of the present invention includes an upper plate including an anode electrode and a phosphor formed on an upper substrate, a lower plate opposing the upper plate with a vacuum space gap therebetween and a plurality of thin film patterns formed on the lower substrate, and the upper plate. And a spacer disposed between the substrate and the lower plate to maintain the vacuum space gap.
- the lower plate may include a cathode electrode formed on a substrate including at least one metal of molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), or an alloy thereof;
- a diffusion barrier layer formed on the cathode electrode including any one or a mixture of titanium (Ti), tungsten (W), tantalum (Ta), silicon (Si), and a silicon compound;
- a gate insulating layer formed on a substrate on which the cathode electrode, the diffusion blocking layer, and the seed metal layer are formed to cover the carbon nanotubes;
- a gate electrode formed on the gate insulating layer including at least one metal of molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), or an alloy thereof. An upper end of the carbon nano
- the present invention can vertically grow carbon nanotubes (CNT) using DC PECVD, which is a modification of PECVD equipment that is also applied to a TFT LCD production line.
- DC PECVD is a modification of PECVD equipment that is also applied to a TFT LCD production line.
- the carbon nanotubes (CNT) are grown by the conventional RF PECVD process, the polarity of the electric field is periodically reversed in the chamber.
- the carbon nanotubes (CNT) are grown by the conventional RF PECVD process, the carbon nanotubes (CNTs) do not grow vertically, but grow in a spiral or twisted shape to increase the threshold voltage and decrease the electron emission efficiency. .
- the present invention vertically grows carbon nanotubes (CNT) on any one of a glass substrate, a plastic substrate, and a metal substrate at a temperature of 600 ° C. or lower using a DC PECVD apparatus as shown in FIG. 1.
- the DC PECVD apparatus includes a positive electrode PE and a negative electrode NE for applying a DC electric field into a chamber, a heater HT for raising a temperature of a substrate, a reactive gas supply unit for injecting a reactive gas, and the like.
- the substrate SUBSL is placed on the negative electrode plate NE.
- the DC PECVD apparatus generates a plasma energy by supplying a current to the heater HT to heat the substrate SUBSL at about 350 ° C. to 600 ° C. and applying a direct current (DC) electric field into the chamber CH in an atmosphere of thermal energy. .
- the DC PECVD apparatus heats the substrate SUBSL to crystallize the seed metal formed on the substrate SUBSL, and then the hydrocarbon-based CNT synthesis source gas and the dry etching reaction gas for dry etching the polycrystalline / amorphous carbon residues.
- the carbon nanotubes CNT having a single crystal structure are vertically grown from the substrate SUBSL by alternately supplying or simultaneously supplying the gases into the chamber CH.
- FIG. 2 is a flowchart illustrating a method of synthesizing carbon nanotubes in accordance with a first embodiment of the present invention.
- the present invention deposits a cathode metal on the substrate SUBSL as shown in FIG. 4C, and then patterns the cathode metal to form the cathode electrode CE on the substrate SUBSL.
- the diffusion barrier material and the seed metal are sequentially formed, and then the diffusion barrier material and the seed metal are patterned together to form a diffusion barrier layer (BAR) and a seed metal layer (SEED).
- BAR diffusion barrier layer
- SEED seed metal layer
- the substrate SUBSL may be selected from a glass substrate, a plastic substrate, and a metal substrate, which may be easily manufactured in a large area and manufactured at low cost.
- the cathode metal comprises one or more metals of molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr) or their alloys and is formed on the substrate SUBSL with a thickness between approximately 1000 kPa and 4000 kPa do.
- the seed metal comprises one or more metals from nickel (Ni), iron (Fe) or an alloy thereof and is formed on the diffusion barrier material to a thickness between 50 kPa and 400 kPa.
- the diffusion barrier material is formed between the cathode metal and the seed metal so that the seed metal is not diffused, for example, one or more metals of titanium (Ti), tungsten (W), tantalum (Ta) or alloys thereof, or silicon (Si). ) And a silicon compound, and are formed on the cathode metal to a thickness between approximately 400 kPa and 4000 kPa.
- the thickness of the diffusion barrier material is preferably about 400 GPa to 2000 GPa.
- the seed metal when the seed metal is in direct contact with the cathode metal without the diffusion barrier material, atoms of the seed metal diffuse into the cathode metal, so that the seed metal may hardly remain when the growth process time of the carbon nanotubes (CNT) is long.
- CNT carbon nanotubes
- the carbon nanotube bundles Refers to a portion where a plurality of carbon nanotubes (CNT) are concentrated.
- the gate insulating layer may be embedded in the bundle of carbon nanotubes, thereby increasing the dielectric constant of the carbon nanotube bundle, thereby lowering the threshold voltage at which electrons may be emitted.
- polycrystalline or amorphous carbon residues generated during deposition of carbon nanotubes having a single crystal structure may be ammonia (NH 3 ) or carbon tetrachloride.
- a dry etching reaction gas comprising at least one of (CCl 4 ), carbon tetrafluoride (CF 4 ), and nitrogen trifluoride (NF 3 ) is alternately fed with the CNT synthesis source gas to remove polycrystalline / amorphous carbon residue.
- Step S4 is a granulation process of the seed metal layer SEED.
- a DC electric field is applied to the chamber CH while the substrate temperature is maintained at a temperature of 350 ° C. to 600 ° C. by supplying a current to the heater HT.
- plasma energy in the chamber CH is 2W / cm 3 to 40. Apply at the W / cm 3 level.
- the CNT synthesis raw material gas is not supplied into the chamber CH.
- grains GR in which carbon nanotubes may be grown as single crystals, are formed in the seed metal layer SEED as shown in FIG. 4B.
- the grains GR are close to each other with a grain boundary in between.
- the surface of the grains GR has a molecular structure that can bond well with carbon atoms.
- step S5 the CNT synthesis raw material gas is supplied to the DC PECVD equipment. Carbon atoms of the CNT synthesis source gas decomposed by the plasma energy are deposited on the grains GR of the seed metal layer SEED. As a result, in the step S5, carbon nanotubes (CNT) having a single crystal structure are vertically grown on the grains GR of the seed metal layer SEED. At the same time, undesired but inevitably carbon atoms on the seed metal layer (SEED) mismatch the atoms of the seed metal layer (SEED) in the process, so that polycrystalline or amorphous carbon residues on the seed metal layer (SEED) Is deposited.
- CNT carbon nanotubes having a single crystal structure
- Such polycrystalline / amorphous carbon residues act as a factor that hinders the growth of single crystal carbon nanotubes (CNT) at a low temperature of less than 600 °C.
- the CNT synthesis source gas and the dry etching reaction gas are alternately supplied to the DC PECVD apparatus at a predetermined time interval, thereby alternately performing the deposition process of the carbon atoms and the dry etching process (S5 and S6).
- the atomic deposition process and the dry etching process may be performed alternately at intervals of about 10 seconds.
- the substrate temperature is maintained at 350 °C ⁇ 600 °C level and the plasma energy in the chamber (CH) is maintained at 2W / cm 3 ⁇ 40 W / cm 3 level. If the plasma energy is higher than 40 W / cm 3 , arc discharge occurs. If the plasma energy is lower than 2 W / cm 3 , carbon atoms are hardly decomposed in the CNT synthesis source gas, and particles generated by aggregation of the CNT synthesis source gas are generated. Particles may remain on the substrate.
- step S6 polycrystalline / amorphous carbon residues having a weaker interatomic bonding force than the single crystal carbon nanotubes (CNT) deposited on the grains GR of the seed metal layer SEED are more easily removed by the dry etching reaction gas. It is decomposed and exhausted to the outside, and the single crystal carbon nanotubes remain on the seed metal layer (SEED).
- Steps S5 and S6 are repeated until the height of the carbon nanotubes grown to single crystal reaches a desired target value as shown in FIG. 4C. (S5 to S7) When the single crystal carbon nanotubes grow by the target value, the process proceeds to the next step.
- the method for synthesizing carbon nanotubes of the present invention is performed at a temperature of 600 ° C. or less by performing a seed metal granulation process of step S4 and a dry etching process to remove polycrystalline / amorphous carbon residues of step S6.
- Carbon nanotubes with a single crystal structure can be grown vertically.
- steps S1 to S4 are substantially the same as those of the first embodiment, and thus a detailed description thereof will be omitted.
- the CNT synthesis source gas and the dry etching reaction gas are simultaneously introduced into the chamber CH of the DC PECVD apparatus at step S21.
- the substrate temperature is maintained at 350 °C ⁇ 600 °C level and the plasma energy in the chamber (CH) is maintained at 2W / cm 3 ⁇ 40W / cm 3 level.
- step S21 the CNT synthesis source gas is decomposed by plasma energy so that carbon atoms are deposited on the grain GR of the seed metal layer SEED so that single crystal carbon nanotubes are vertically grown on the grain GR, and the seed metal layer SEED is grown.
- the polycrystalline / amorphous impurities deposited on the) react with the dry etching reaction gas to be decomposed and exhausted to the outside.
- the process of step S21 is continued until the height of the carbon nanotubes grown as single crystal reaches a desired target value as shown in FIG. 4C. (S21 and S22) When the single crystal carbon nanotubes grow by the target value, the process proceeds to the next step.
- the step S4 is performed.
- Nickel silicide (NSI) is formed on the seed metal layer SEED as shown in 4c.
- Grain (GR) of the nickel silicide (NSI) layer serves as a seed of single crystal carbon nanotubes.
- the single crystal carbon nanotubes (CNTs) grow in a conical structure, electrons can be emitted even at relatively low voltages, resulting in higher electron emission efficiency and lower threshold voltages for emitting electrons than cylindrical carbon nanotubes.
- titanium (Ti), tungsten (W), and tantalum (Ta) are used in addition to the silicon film as the diffusion barrier layer (BAR)
- carbon nanotubes (CNT) having a single crystal structure are grown in a cylindrical structure as shown in FIG. Therefore, in consideration of electron emission efficiency and threshold voltage, silicon or a silicon compound is more preferable as the diffusion barrier layer (BAR).
- the diffusion barrier layer is not limited to silicon or silicon compounds.
- the lower plate structure includes carbon nanotubes formed by the above-described carbon nanotube synthesis method and may be implemented in various structures.
- FIG. 7 is a plan view illustrating a portion of an electrode structure of a lower plate in a field emission display device according to an exemplary embodiment of the present invention.
- FIG. 8 is a cross-sectional view illustrating a cross-sectional structure of the lower plate cut along the line "I-I '" in FIG. 7.
- the field emission display device of the present invention includes an upper plate and a lower plate facing each other with the electron emission space ESP in a vacuum state therebetween.
- the upper and lower plates are hermetically sealed with a sealant with an electron emission space therebetween.
- the degree of vacuum of the electron emission space ESP may be approximately 10 ⁇ 5 to 10 ⁇ 7 torr.
- a plurality of gate holes GHALL is present in the pixel region PIX, and a carbon nanotube bundle including a plurality of carbon nanotubes CNTs is formed in each of the gate holes GHALL. Therefore, even if there are problems with some carbon nanotubes in the pixel region, the pixel defects hardly occur, so that the yield can be increased and the driving reliability can be improved.
- the top plate includes an anode electrode AE formed on the upper substrate SUBSU and a phosphor PHOS covering the anode electrode AE.
- a positive voltage of about 4 kV to 12 kV is applied to the anode AE. Since the top structure and its manufacturing method are substantially the same as the existing field emission display device, detailed description thereof will be omitted. Hereinafter, the lower plate structure and the manufacturing method thereof will be described.
- the lower plate may include the cathode electrode CE, the diffusion barrier layer BAR, the seed metal layer SEED, the carbon nanotubes CNT, the gate insulation layer GI, and the gate electrode GE stacked on the lower substrate SUBSL. Include.
- Each of the upper substrate SUBSU and the lower substrate SUBSL may be implemented as any one of a glass substrate, a ceramic substrate, a plastic substrate, and a metal substrate, which may be easily manufactured at a large area and manufactured at low cost.
- Cathode bus lines CBL connecting the cathode electrodes CE and the cathode electrodes CE are formed on the lower substrate SUBSL, and molybdenum (Mo), aluminum (Al), copper (Cu), Chromium (Cr) or one or more metals thereof.
- the seed metal layer SEED includes one of nickel (Ni) and iron (Fe).
- a barrier metal layer (BAR) is formed between the cathode electrode CE and the seed metal layer SEED so that the seed metal is not diffused, for example, titanium (Ti), tungsten (W), and tantalum (Ta). At least one metal, or silicon (Si) or a silicon compound.
- the gate electrode GE is formed on the insulating film GI.
- the gate bus line GBL connecting the gate electrode GE and the gate electrode GE includes at least one metal of molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), or an alloy thereof. And partially etched to form the gate hole GHALL.
- Cathode bus lines CBL and gate bus lines GBL are orthogonal.
- Carbon nanotubes (CNT) are vertically grown on the grain (GR) of the seed metal layer (SEED) through the above-described carbon nanotube synthesis method.
- the carbon nanotubes (CNT) have a substantially single crystal structure and are vertically erected on the seed metal layer (SEED).
- the carbon nanotubes CNT emit electrons when the voltage difference Vgc between the anode voltage and the cathode voltage is greater than or equal to the threshold voltage Vth.
- the gate insulating layer GI includes an inorganic insulating material or an organic insulating material capable of spin coating or chemical vapor deposition.
- the gate insulating layer G1 is formed between the cathode electrode CE and the gate electrode GE to insulate the electrodes CE and GE, and also covers the lower portion of the carbon nanotubes CNT to cover electrons. Lower the threshold voltage (Vth) for emitting.
- the top of the carbon nanotubes CNT exposed above the gate insulating layer GI is gate-insulated by dry etching or ashing after forming the gate insulating layer GI.
- the thickest portion of the layer GI is cut to be equal to or less than the surface of the gate insulating layer GI.
- the gate insulating layer GI is etched to a predetermined depth in the gate hole GHALL from which the gate electrode GE is removed.
- the predetermined depth is set to a depth of 20% to 60% of the thickest portion of the gate insulating layer GI. Accordingly, upper ends of the carbon nanotubes CNT are exposed in the gate hole GHALL formed through the etching process of the gate insulating layer GI.
- the upper and lower portions thereof are covered by the gate insulating layer GI and thus are not exposed.
- the electron emission threshold voltage of the carbon nanotubes CNT may be lowered. This is because when the gate insulating layer GI covers the carbon nanotubes CNT, the dielectric constant is increased at the portion where the carbon nanotube bundles are formed, thereby increasing the electric field strength applied to the carbon nanotubes CNT.
- the dielectric constant is substantially the same at the portion where the carbon nanotube bundle is formed by the gate insulating layer GI covering the carbon nanotubes CNT and at the portion where the carbon nanotube bundle is not formed.
- the gate insulating layer GI is buried in the gate hole GHALL to make the average dielectric constant of the carbon nanotube bundle portion substantially the same as the average dielectric constant of the carbon nanotube-free portion around the carbon nanotube bundle.
- the gate insulating layer GI may be selected as an organic / inorganic insulating material having a dielectric constant of about 2 to about 8.
- the dielectric constant of the portion where the carbon nanotube bundles are formed by the gate insulating layer GI and the dielectric constant of the portion without the carbon nanotube bundles are substantially equal to about 2 to 8.
- the gate electrode GE of the present invention serves as a focus electrode for focusing the electron beam by applying a negative voltage instead of the electron extraction electrode.
- electrons are emitted and accelerated into an electric field between the cathode electrode and the anode electrode.
- the gate insulating layer GI is not formed in the gate hole GHALL.
- the dielectric constant (vacuum dielectric constant) of the portion where the carbon nanotube bundles are formed is lower than that of the portion without the carbon nanotube bundles (the dielectric constant of the gate insulating layer), so that the electric field strength of the portion where the carbon nanotube bundles is formed is lowered.
- the threshold voltage for electron emission is high due to the difference in dielectric constant between the bundle of carbon nanotubes and its surroundings. After withdrawing, electrons were accelerated toward the anode electrode by an electric field applied between the cathode electrode and the anode electrode.
- the field emission display device of the present invention does not need a separate focus electrode because it can focus the electron beam toward the anode electrode AE by applying a negative voltage to the gate electrode GE.
- the field emission display device of the present invention can express the gray level of the input image by controlling the electron emission amount according to the data voltage of the video data applied to the cathode electrode CE.
- the threshold voltage Vth is 3 V / ⁇ m or less, and reaches a saturated emission condition at an electric field of about 5 V / ⁇ m.
- a DC positive voltage (anode voltage) of about 4 to 12 kV is applied to the anode AE, carbon nanotubes ( The electric field applied to the CNT reaches the electron emission saturation region so that the phosphor PHOS emits light with maximum brightness.
- a video data voltage (or cathode voltage) whose voltage varies depending on the gray value of the input image data is applied to the cathode electrode CE. Therefore, the field emission display device of the present invention can control the electric field applied to the carbon nanotubes CNT through the control of the cathode voltage, and as a result, can adjust the brightness of the phosphor PHOS to express the gray level of the input image. .
- 9A through 9F are cross-sectional views illustrating a method of manufacturing a lower plate of the field emission display shown in FIG. 8.
- At least one cathode metal of molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), or an alloy thereof may be formed using a deposition process such as sputtering on a lower substrate SUBSL. Is deposited to a thickness of between 1000 mV and 4000 mV. Subsequently, the present invention applies a photoresist (PR) on the cathode metal and performs a first photolithography process including a series of first photo mask alignment, exposure, development, and etching processes. ) And the cathode bus line (CBL).
- Mo molybdenum
- Al aluminum
- Cu copper
- Cr chromium
- the cathode metal is deposited to a thickness lower than 1000 ⁇ , the resistance of the cathode metal is increased and may be disconnected in the etching process. On the other hand, if the cathode metal is deposited thicker than 4000 ⁇ , the deposition time is excessively consumed, thus increasing the process time and increasing the stress of the substrate.
- the present invention deposits a diffusion barrier material of at least one of titanium (Ti), tungsten (W), tantalum (Ta), silicon (Si) or a silicon compound using a deposition process such as sputtering to a thickness of 400 kPa to 4000 kPa.
- a deposition process such as sputtering to a thickness of 400 kPa to 4000 kPa.
- nickel (Ni) or iron (Fe) which is a seed metal, is subsequently deposited to a thickness of 50 kPa to 400 kPa. If the diffusion barrier material is deposited to a thickness of less than 400 microns, it can diffuse into the cathode metal during the process and cannot serve as a diffusion barrier layer of the seed metal.
- the present invention provides a diffusion barrier layer (BAR) and a seed metal layer (SEED) through a second photolithography process including applying a photoresist (PR), second photo mask alignment, exposure, development, and etching.
- BAR diffusion barrier layer
- SEED seed metal layer
- the diffusion barrier layer BAR and the seed metal layer SEED are defined in the pixel region PIX as illustrated in FIG. 9B.
- the pattern in which the diffusion barrier layer BAR and the seed metal layer SEED are stacked is formed in the pixel region PIX including the gate holes GHALL and a peripheral region to be formed in a subsequent process.
- the present invention provides the single crystal carbon on the grain (GR) of the seed metal layer (SEED) until the height of the single crystal carbon nanotubes (CNT) becomes between 2 ⁇ m and 20 ⁇ m using the aforementioned carbon nanotube synthesis methods. Nanotubes (CNT) are grown vertically.
- the present invention coats an insulating material to a predetermined thickness on the lower substrate SUBSL to cover the single crystal carbon nanotubes CNT to form the gate insulating layer GI.
- the insulating material coating method may coat an insulating material including inorganic or organic insulators such as silicon oxide, silicon nitride, and acrylic with a thickness of 0.2 ⁇ m to 10 ⁇ m by spin coating or chemical vapor deposition. The insulating material is cured through a curing process (Fig. 9C).
- an O 2 plasma, dry etching, or ashing method may be used as shown in FIG. 9D. Ashing is used to completely remove the single crystal carbon nanotubes CNT protruding from the first gate insulating layer GI1.
- silicon oxide, silicon nitride, acrylic, etc. may be formed by spin coating or chemical vapor deposition on the first gate insulating layer GI1 as shown in FIG. 9E so that the entire single crystal carbon nanotubes may be covered by the insulating layer.
- the second gate insulating layer GI2 may be further formed by further coating an insulating material including an inorganic or organic insulator to a thickness of about 1000 ⁇ m to about 10 ⁇ m.
- the process of additionally forming the second gate insulating layer GI2 may be omitted. In other embodiments described below, a process of additionally forming the second gate insulating layer GI2 may be included.
- the present invention provides a gate insulating layer by depositing 1000 to 4000 microns of gate metal of at least one of molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), or an alloy thereof using a deposition process such as sputtering.
- the gate electrode GE is formed on the GI1 and GI12.
- the present invention includes a series of processes including applying photoresist PR, aligning a third photo mask, exposing, developing, and etching to remove the gate electrode GE at the position where the gate hole GHALL is to be formed.
- the gate metal is patterned through the photolithography process to form the gate electrode GE and the gate hole GHALL.
- the gate insulating layer GI1 is exposed through the gate holes GHALL passing through the gate electrode GE as shown in FIG. 9F.
- an upper end of the gate insulating layer GI1 exposed through the gate holes GHALL is etched to a depth of 0.1 ⁇ m or more and 5 ⁇ m or less, using the gate metal pattern as a mask.
- Each of the GHALLs exposes the top of the carbon nanotubes (CNT).
- the gate insulating layer GI1 has a thickness of about 0.2 ⁇ m in FIG. 9D
- the upper end of the gate insulating layer GI1 in the gate hole GHALL is etched to a depth of 0.1 ⁇ m or less.
- the gate insulating layer GI1 has a thickness of about 10 ⁇ m in FIG.
- the upper end of the gate insulating layer GI1 in the gate hole GHALL is etched to a depth of 5 ⁇ m or less. Therefore, the upper end of the gate insulating layer GI1 under the gate hole GHALL is removed to a depth less than 1/2 of the thickness of the gate insulating layer GI1.
- the threshold voltage increases.
- the method of manufacturing the field emission display device according to the first exemplary embodiment of the present invention may complete the lower plate (or cathode plate) of the field emission display device using only three photolithography processes.
- the carbon nanotubes CNT may be grown with the photoresist layer remaining on the seed metal layer SEED. This method is described in detail with reference to FIGS. 10A to 10C as follows.
- FIG. 10A through 10C are cross-sectional views illustrating a method of growing carbon nanotubes in a state in which a photoresist layer remains on a seed metal layer in the method of manufacturing a bottom panel of the field emission display shown in FIG. 8.
- a diffusion barrier material is deposited on the cathode electrode CE to a thickness of 400 ⁇ s to 4000 ⁇ s, as illustrated in FIG. 10A. Seed metal is deposited on the material to a thickness between 50 kPa and 400 kPa.
- the present invention is subjected to a photoresist through a second photolithography process including a series of second photo mask alignment, exposure, development, and etching processes.
- the pattern PR is formed, and portions other than the diffusion barrier layer BAR and the seed metal layer SEED under the pattern resist pattern PR are etched to form a diffusion barrier layer BAR in the pixel region PIX.
- the seed metal layer SEED is defined.
- the pattern of the diffusion barrier layer BAR and the seed metal layer SEED may be formed in a single pattern in the pixel region PIX by the second photo mask shape.
- the present invention provides the single crystal carbon nanotubes using the above-described carbon nanotube synthesis methods in conjunction with FIGS. 2 to 4C while the photoresist pattern PR is covered on the seed metal layer SEED as shown in FIG. 10C.
- Single crystal carbon nanotubes (CNT) are vertically grown on the grain (GR) of the seed metal layer (SEED) until the height of the (CNT) is between 2 ⁇ m and 20 ⁇ m. Processes after the growth process of carbon nanotubes (CNT) are substantially the same as the processes of FIGS. 9D to 9F, and thus a detailed description thereof will be omitted.
- the photoresist PR pattern is burned at the process temperature of the DC PECVD process and the photoresist is applied.
- the carbon component of (PR) acts as a growth catalyst for carbon nanotubes (CNT), thereby lowering the growth temperature of the single crystal carbon nanotubes (CNT) and increasing the growth rate.
- materials other than carbon in the photoresist PR are decomposed and exhausted out of the chamber of the DC PECVD.
- the diffusion barrier layer BAR and the seed metal layer SEED are patterned in the pixel region PIX without patterning the gate hole.
- carbon nanotubes (CNT) are grown on the entire surface in the pixel region, and there is no need to align the gate hole (GHALL) with the carbon nanotube bundles.
- FIG. 11 is a cross-sectional view illustrating a bottom plate cross-sectional structure of a field emission display device according to a second exemplary embodiment of the present invention.
- the diffusion barrier layer BAR and the seed metal layer remain only in the gate hole GHALL and the seed metal layer SEED. (SEED) is patterned. Since other features are substantially the same as the first embodiment described above, detailed description thereof will be omitted.
- 12A through 12F are cross-sectional views illustrating a method of manufacturing a bottom plate of the field emission display shown in FIG. 11.
- the shape of the second photo mask is different from that of the first embodiment in the patterning process of the diffusion barrier layer BAR and the seed metal layer SEED. It is substantially the same as the embodiment.
- the present invention provides a thickness of 1000 to 4000 mm of a cathode metal of molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), or an alloy thereof on the lower substrate SUBSL.
- a cathode metal of molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), or an alloy thereof on the lower substrate SUBSL.
- the cathode electrode CE and the cathode bus line CBL are patterned through a first photolithography process.
- the present invention is to deposit a diffusion barrier material of at least one of titanium (Ti), tungsten (W), tantalum (Ta), silicon (Si), or a silicon compound as shown in Figure 12b and 12c to a thickness of 400 ⁇ 4000 ⁇
- a seed metal such as nickel (Ni) or iron (Fe) is subsequently deposited to a thickness between 50 kPa and 400 kPa.
- the present invention provides a diffusion barrier layer (BAR) and a seed metal layer (SEED) through a second photolithography process including applying a photoresist (PR), second photo mask alignment, exposure, development, and etching. Batch patterning.
- the diffusion barrier layer BAR and the seed metal layer SEED remain only in the gate hole GHALL, and the rest of the rest is removed. Therefore, the pattern in which the diffusion barrier layer BAR and the seed metal layer SEED are stacked is formed only under each of the gate holes GHALL to be formed in a subsequent process.
- the first gate insulating layer GI1 is formed, and the single crystal carbon nanotubes CNT are formed as the seed metal layer (CNT) as shown in FIG. 12F by using the above-described carbon nanotube synthesis methods.
- the seed metal layer CNT
- FIG. 12F Vertical growth on the grain GR of SEED). Carbon nanotubes CNT grow only in the gate hole GHALL.
- the present invention includes a process of forming a gate electrode GE including a gate hole GHALL by patterning a gate metal using a third photolithography process.
- 12A to 12F may complete the lower plate of the field emission display device using only three photolithography processes.
- the carbon nanotubes CNT may be grown with the photoresist layer remaining on the seed metal layer SEED. This method is described in detail with reference to FIGS. 13A to 13C as follows.
- FIGS. 13A to 13C are cross-sectional views illustrating a method of growing carbon nanotubes in a state in which a photoresist layer remains on a seed metal layer SEED in the method of manufacturing a bottom panel of the field emission display shown in FIG. 11.
- the remaining photoresist PR may serve as a catalyst for promoting growth of carbon nanotubes (CNT).
- a diffusion barrier material is deposited on the cathode electrode CE to a thickness between 400 ⁇ s and 4000 ⁇ s, as shown in FIG. 13A, and the diffusion barrier is performed. Seed metal is deposited on the material to a thickness between 50 kPa and 400 kPa. Subsequently, after the photoresist is applied onto the seed metal layer SEED as shown in FIG. 13B, the present invention uses a second photolithography process including a series of second photo mask alignment, exposure, development, and etching processes.
- a pattern is formed, and the volcanic barrier layer and the seed metal layer except for the diffusion barrier layer (BAR) and the seed metal layer (SEED) under the photoresist pattern are collectively etched to form the diffusion barrier layer (BAR) and the seed metal layer (in the pixel region).
- Pattern SEED the pattern of the diffusion barrier layer BAR and the seed metal layer SEED may remain only at the gate hole position to be formed in a subsequent process by the second photo mask shape. Thus, the diffusion barrier layer and the seed metal layer are separated into many in the pixel region.
- the heights of the single crystal carbon nanotubes (CNT) are 2 ⁇ m to ⁇ using the above-described carbon nanotube synthesis methods.
- Single crystal carbon nanotubes (CNT) are vertically grown on the grain (GR) of the seed metal layer (SEED) until the height is between 20 ⁇ m.
- the carbon nanotubes CNT are grown only in the gate hole GHALL formed in a subsequent process according to the pattern of the seed metal layer SEED. Since the processes after the growth process of the carbon nanotubes (CNT) are substantially the same as those of FIGS. 12D to 12F, a detailed description thereof will be omitted.
- 14 and 15 are scanning electron microscope (Scanning Electron Microscope, SEM) images showing single crystal carbon nanotubes grown in a conical structure as a result of the carbon nanotube synthesis method as shown in FIG. 3.
- 15 is an enlarged image of a part of the image of FIG. 14.
- the substrate used in this experiment was selected as Samsung Corning's glass substrate, which is widely used as a substrate for TFT LCD.
- a photoresist PR is formed on a substrate such as a cathode electrode CE, a diffusion barrier layer (BAR) containing silicon (Si), a seed metal layer (SEED) containing nickel (Ni), and a gate insulating film (GI).
- a substrate such as a cathode electrode CE, a diffusion barrier layer (BAR) containing silicon (Si), a seed metal layer (SEED) containing nickel (Ni), and a gate insulating film (GI).
- the method of manufacturing the field emission display device of the present invention described above can manufacture the bottom plate of the field emission display device using the equipment of the TFT LCD production line, the field emission display device can be produced through the TFT LCD production line without additional equipment investment. have.
- the present invention proceeds the carbon nanotube growth process while removing polycrystalline / amorphous carbons acting as a blocking element of the single crystal carbon nanotubes (CNT), so that the single crystal carbon nanotubes are stably at a low temperature below 600 ° C. CNT) can be grown.
- CNT single crystal carbon nanotubes
- the carbon nanotubes may be embedded in the insulating layer to lower the threshold voltage, thereby emitting electrons at a low voltage, and by applying a negative voltage to the gate electrode, the electrons may be focused without a separate focus electrode. Furthermore, as shown in FIGS. 14 and 15, since the carbon nanotubes (CNT) having a single crystal structure are grown in a conical cone shape that becomes sharper toward the top, the electron emission efficiency may be increased to lower the threshold voltage.
- the manufacturing method of the field emission display device of the present invention can manufacture the bottom plate of the field emission display device using only three photo processes using the equipment of the TFT LCD production line, which can significantly lower the equipment investment cost and the bottom plate manufacturing cost.
- the mass production of the emission display device is increased to enable mass production.
- the spacer is a structure that maintains the electron emission space ESP formed by the vacuum space gap Gap between the upper plate and the lower plate, and has a great influence on the performance and lifespan of the field emission display device FED.
- the spacer material must have a mechanical strength that can withstand the pressure difference between the internal vacuum pressure of the display panel and the external atmospheric pressure of the display panel and has an insulation strength that can withstand the anode voltage.
- the spacers must be manufactured in a precise structure that does not invade the effective opening surface in the pixels of the display panel and have a proper volume resistance so as not to cause electron beam distortion.
- the spacer of the present invention will be described in detail.
- the top plate includes the anode electrode AE formed on the upper substrate SUBSU, the phosphors covering the anode electrode AE (PHOS (R), PHOS (G), PHOS (B)), and a black matrix. (BM) and the like.
- the lower plate includes a cathode electrode CE, an electron emission source, and the like formed on the lower substrate SUBSL. Since the lower plate structure and its manufacturing method are substantially the same as in the above-described embodiment, a detailed description thereof will be omitted.
- the spacer SP is manufactured based on a glass substrate or a ceramic substrate to maintain a vacuum space gap between the upper and lower plates.
- the spacer SP is patterned in a mesh shape in which opening holes 10 exposing the lower pixel areas PIX are disposed in a matrix form.
- the spacer SP may be bonded to the upper substrate SUBSU and the lower substrate SUBSL through the glass frit FR.
- the top surface of the barrier rib of the spacer SP overlaps the black matrix BM, and the bottom surface of the barrier rib of the spacer SP overlaps the metal bus line BUS.
- the metal bus line BUS includes a cathode bus line CBL and a gate bus line GBL as shown in FIG. 7.
- a spacer is manufactured by processing a glass substrate or a ceramic substrate in a mesh form using a photolithography process and an anisotropic etching process.
- Anisotropic etching methods are widely used in microelectromechanical systems (MEMS) process technology.
- the glass substrate may be a 0.7 mm thick glass substrate widely used as a substrate of a flat panel display panel such as a TFT LCD.
- the substrate material can be shared.
- the ceramic substrate may be a ceramic substrate based on alumina (Al 2 O 3 ).
- the pixels of the field emission display device may include red (R), green (G), and blue (B) subpixels as shown in FIGS. 18A to 18C.
- the spacer SP is manufactured in a mesh structure in which the opening holes 10 are arranged in a matrix form.
- the opening holes 10 of the spacer SP are partitioned with the partition wall therebetween.
- the partition wall of the spacer SP overlaps the black matrix BM of the upper plate and the metal bus line BUS of the lower plate.
- the openings 10 of the spacer SP may be partitioned in units of subpixels R, G, and B, as shown in FIG. 18A.
- the openings 10 of the spacer SP may be partitioned in pixel units including RGB subpixels as shown in FIG. 18B.
- 18A and 18B, Px and Py represent the horizontal and vertical pitches of the pixel.
- the openings 10 of the spacer SP may be divided into two or more pixel units as shown in FIG. 18C.
- the manufacturing process of the field emission display device includes an exhaust process of exhausting internal gas existing between the upper and lower plates after joining the upper and lower plates in order to maintain an appropriate degree of vacuum in the display panel.
- the spacer SP may include grooves 12 formed in the partition walls in both directions (x and y directions) as shown in FIG. 19A so that exhaust of the internal gas may be smoothed in the exhaust process.
- the grooves 12 pass through the partition walls of the spacer SP in the exhaust process to form an exhaust path.
- Such grooves 12 may be formed in partition walls in two directions (x and y directions) orthogonal to each other as shown in FIG. 19B.
- a photo mask (PM) is applied thereon.
- the substrate GLS may be a glass substrate or a ceramic substrate.
- the photo mask PM includes a light transmitting portion facing the opening hole 10 of the spacer SP and a light blocking portion facing the partition portion of the spacer SP.
- the photo mask PM may be selected as a half tone mask.
- the halftone mask includes a light transmitting portion facing the opening hole 10 of the spacer SP, a light blocking portion facing the partition wall portion of the spacer SP, and a halftone transmitting portion facing the exhaust groove 12.
- the photoresist PR is exposed through the photomask PM and then developed to leave the photoresist pattern PRP on the substrate GLS.
- the substrate GLS is etched by using an anisotropic etching method.
- an anisotropic etching method a dry etching method such as a plasma etching method, or an anisotropic wet etching method may be applied.
- reactive gases capable of etching the substrate GLS include HF 6 , NF 3 , HCl 4 , and HNO 3 .
- an etchant capable of etching the substrate GLS includes an HF solution and a BHF solution.
- the wet etching method may apply a known anisotropic wet etching method, and may also apply the wet etching method of FIGS. 22 and 23 newly developed by the applicant of the present application.
- the etching ratio of the thickness direction (or vertical direction) of the substrate GLS is higher than that of the surface direction (or horizontal direction) of the substrate GLS. For this reason, the substrate GLS is etched more vertically at portions other than the photoresist pattern PRP in the anisotropic etching process.
- the photoresist pattern PRP is removed in the strip process (S34).
- step S36 In the step S36 in which the spacer SP is bonded to the upper plate and the lower plate, the degree of vacuum is reduced. It may be carried out in a vacuum chamber on the order of 10 -5 to 10 -7 torr. The vacuum chamber is heated to approximately 400 ° C. to 500 ° C., which is the temperature at which the glass frit can be sintered.
- the present invention aligns the spacer SP with the upper plate and the lower plate such that the alignment key formed on the spacer SP coincides with an alignment key formed on at least one of the upper plate and the lower plate coated with glass frit. .
- the upper plate and the lower plate are loaded and fixed in the heated vacuum chamber, and then maintained for a predetermined time, the glass frit is sintered to firmly bond the spacer SP to the upper plate and the lower plate.
- the present invention facilitates the development and selection of a glass frit for vacuum sealing by using the same glass substrate or ceramic substrate as the upper and lower substrates as the spacer material.
- the present invention manufactures a spacer using a MEMS process technology or a wet etching technique, it is possible to accurately manufacture a high-definition spacer SP having an aperture hole 10 of 50,000 ⁇ m 2 or less at low cost.
- FIG. 22 is a cross-sectional view illustrating an example of an anisotropic wet etching method.
- the manufacturing method of this spacer is processed by the wet etching apparatus as shown in FIG.
- the anisotropic wet etching method of the present invention applies a laser beam to the substrate GLS in an exposed portion (opening portion) not covered by the photoresist pattern PRP.
- Micropores IH penetrating the substrate GLS are formed by irradiating or using a mechanical processing method or a conventional photolithography process and an etching method.
- the fine holes IH have a diameter smaller than the opening holes (10 in FIGS. 7 and 8) of the finished spacer SP.
- the present invention aligns the nozzle NZ to the fine hole IH and injects the etchant ETC to the fine hole IH through the nozzle NZ.
- the etchant ETC injected into the fine holes IH flows down through the fine holes IH and is discharged to the outside to etch the sidewall of the fine holes IH to enlarge the size of the fine holes IH.
- the etchant ETC is simultaneously sprayed into a plurality of neighboring micropores IH. 22 and 23, the nozzle NZ is represented with a smaller size than actually.
- the photoresist pattern PRP protects the substrate GLS from the etchant to define the size and shape of the opening 10 exposed to the etchant ETC. .
- the photoresist pattern PRP is removed in the strip process. The completed spacer SP is bonded to the upper plate and the lower plate which are already manufactured through glass frit powder.
- the etchant (ETC) is recovered through the fine hole (IH) to the recovery vessel (TNK) with the substrate particles etched, as shown in Figure 23 after the foreign matter is removed through the filter (FIL) through the circulation pipe (CIR) It is supplied to the nozzle NZ and recycled. Substrate particles caught in the filter FIL may be supplied to the collector COL and recycled to manufacture the substrate. Accordingly, the etching system as shown in FIG. 23 may minimize material waste and implement an eco-friendly spacer manufacturing process.
- the present invention can stably grow single crystal carbon nanotubes (CNT) using carbon nanotubes used as an electron emission source in a field emission display device, and embeds carbon nanotubes in an insulating layer to lower a threshold voltage and a cathode electrode and a seed metal layer. By forming a diffusion barrier layer therebetween, it is possible to stably prevent the seed metal from diffusing into the other metal and disappearing.
- CNT single crystal carbon nanotubes
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Abstract
Description
Claims (20)
- 상부 기판 상에 형성된 애노드 전극과 형광체를 포함한 상판, 진공 공간 갭을 사이에 두고 상기 상판과 대향하고 하부기판 상에 형성된 다수의 박막 패턴을 포함하는 하판, 및 상기 상판과 상기 하판 사이에 배치되어 상기 진공 공간 갭을 유지하는 스페이서를 포함하는 전계방출 표시장치에 있어서,상기 하판은,몰리브덴(Mo), 알루미늄(Al), 구리(Cu), 크롬(Cr) 또는 이들 합금 중에서 하나 이상의 금속을 포함하여 기판 상에 형성되는 캐소드전극;티타늄(Ti), 텅스텐(W), 탄탈륨(Ta), 실리콘(Si), 실리콘 화합물 중 어느 하나 또는 그 혼합물을 포함하여 상기 캐소드전극 상에 형성되는 확산 차단층;니켈(Ni)과 철(Fe) 중 어느 하나로 상기 확산 차단층 상에 형성되고 입상화된 그레인들을 포함하는 씨드 금속층;상기 씨드 금속층의 그레인들 상에서 단결정으로 성장된 탄소나노튜브들;상기 탄소나노튜브들을 덮도록 상기 캐소드전극, 상기 확산 차단층, 및 상기 씨드 금속층이 형성된 기판 상에 형성되는 게이트 절연층; 및몰리브덴(Mo), 알루미늄(Al), 구리(Cu), 크롬(Cr) 또는 이들 합금 중에서 하나 이상의 금속을 포함하여 상기 게이트 절연층 상에 형성된 게이트전극을 포함하고,상기 게이트전극 내의 게이트홀을 통해 상기 탄소나노튜브들의 상단이 노출되는 것을 특징으로 하는 전계방출 표시장치.
- 제 1 항에 있어서,상기 확산 차단층이 상기 실리콘(Si)과 상기 실리콘 화합물 중 어느 하나로 상기 캐소드전극과 상기 게이트전극 사이에 형성되면,상기 씨드 금속층은 니켈실리사이드를 포함하는 것을 특징으로 하는 전계방출 표시장치.
- 제 1 항에 있어서,상기 확산 차단층과 상기 씨드 금속층이 적층된 패턴은 상기 게이트홀 아래에만 형성되는 것을 특징으로 하는 전계방출 표시장치.
- 제 1 항에 있어서,상기 확산 차단층과 상기 씨드 금속층이 적층된 패턴은 상기 게이트홀과 그 주변 영역을 포함한 픽셀 영역에 형성되는 것을 특징으로 하는 전계방출 표시장치.
- 제 1 항에 있어서,상기 캐소드전극의 두께는 1000Å~4000Å 사이의 두께이고,상기 확산 차단층의 두께는 400Å ~ 4000Å 사이의 두께이고,상기 씨드 금속층의 두께는 50Å ~ 400Å 사이의 두께이고,상기 탄소나노튜브들의 높이는 2μm ~ 20μm 사이의 높이이고,상기 게이트 절연층의 두께는 0.2μm ~ 20μm 사이의 두께이고,상기 게이트전극의 두께는 1000Å~4000Å 사이의 두께이고,상기 탄소나노튜브들을 덮은 상기 게이트 절연층에 의해 상기 탄소나노튜브들이 밀집된 탄소나노튜브 다발 부분의 유전율과, 상기 탄소나노튜브 다발 주변에서 탄소나노튜브들이 없는 부분의 유전율이 2~8 정도로 실질적으로 동일한 것을 특징으로 하는 전계방출 표시장치.
- 제 1 항에 있어서,상기 게이트홀 아래에서 상기 게이트 절연층의 상단이 상기 게이트 절연층의 두께 대비 1/2 이하의 깊이로 제거되고,상기 탄소나노튜브들의 최상단은 상기 게이트 절연층에서 가장 두꺼운 부분의 표면 이하에 위치하는 것을 특징으로 하는 전계방출 표시장치.
- 제 1 항에 있어서,상기 탄소나노튜브들은 원추형 구조와 원통형 구조 중 어느 한 구조로 상기 씨드 금속층 상에서 수직으로 세워진 것을 특징으로 하는 전계방출 표시장치.
- 제 1 항에 있어서,상기 스페이서는,유리와 세라믹 중 어느 하나를 주성분으로 하고, 매트릭스 형태로 배치된 개구공들을 포함하고,상기 스페이서의 개구공들 각각의 피치는 상기 하판에 매트릭스 형태로 배치된 픽셀이나 서브픽셀의 피치와 실질적으로 동일한 것을 특징으로 하는 전계방출 표시장치.
- 제 8 항에 있어서,상기 상부 기판, 상기 하부 기판 및 상기 스페이서는 동일한 재료와 동일한 두께를 갖는 것을 특징으로 하는 전계방출 표시장치.
- 제 8 항에 있어서,상기 스페이서는,상기 개구공들을 구획하기 위한 격벽들; 및상기 격벽들에 소정 깊이로 형성되어 배기로를 형성하는 배기 홈들을 포함하는 것을 특징으로 하는 전계방출 표시장치.
- 상부 기판 상에 형성된 애노드 전극과 형광체를 포함한 상판, 진공 공간 갭을 사이에 두고 상기 상판과 대향하고 하부기판 상에 형성된 다수의 박막 패턴을 포함하는 하판, 및 상기 상판과 상기 하판 사이에 배치되어 상기 진공 공간 갭을 유지하는 스페이서를 포함하는 전계방출 표시장치의 제조 방법에 있어서,상기 하판의 제조 방법은,몰리브덴(Mo), 알루미늄(Al), 구리(Cu), 크롬(Cr) 또는 이들 합금 중에서 하나 이상의 금속을 포함한 캐소드전극을 기판 상에 형성하고 상기 캐소드전극을 패터닝하는 단계;티타늄(Ti), 텅스텐(W), 탄탈륨(Ta), 실리콘(Si), 실리콘 화합물 중 어느 하나 또는 그 혼합물을 포함한 확산 차단층을 상기 캐소드전극 상에 형성하고, 니켈(Ni)과 철(Fe) 중 어느 하나를 포함한 씨드 금속층을 상기 확산 차단층 상에 형성하는 단계;상기 확산 차단층과 상기 씨드 금속층을 패터닝하는 단계;상기 캐소드전극, 상기 확산 차단층 및 상기 씨드 금속층을 포함한 상기 기판을 DC PECVD 장비의 챔버 내에 투입하고 상기 기판의 온도를 350℃ ~ 600℃ 의 온도로 가열하고 상기 챔버 내에 플라즈마 에너지를 2W/cm3 ~ 40W/cm3 수준으로 인가하여 상기 씨드 금속층에 입상화된 그레인들을 형성하는 단계;상기 기판의 온도를 350℃ ~ 600℃ 의 온도로 유지하고 상기 챔버 내에 플라즈마 에너지를 2W/cm3 ~ 40W/cm3 수준으로 유지한 상태에서 탄화 수소를 포함한 CNT 합성 원료 가스와, 암모니아(NH3), 사염화탄소(CCl4), 사불화탄소(CF4), 및 삼불화질소(NF3) 중 적어도 어느 하나를 포함한 건식 식각 반응 가스를 상기 챔버 내에 공급하여 상기 씨드 금속층의 그레인들 상에 탄소나노튜브들을 단결정 구조로 성장시키는 단계;상기 캐소드전극, 상기 확산 차단층, 및 상기 씨드 금속층이 형성된 기판 상에 유기 절연물질과 무기 절연물질 중 어느 하나를 포함한 게이트 절연층을 형성하여 상기 탄소나노튜브들을 상기 게이트 절연층으로 매립하는 단계; 및몰리브덴(Mo), 알루미늄(Al), 구리(Cu), 크롬(Cr) 또는 이들 합금 중에서 하나 이상의 금속을 포함한 게이트전극을 상기 게이트 절연층 상에 형성하고, 상기 게이트전극을 패터닝하여 상기 탄소나노튜브들의 최상단이 노출되는 게이트홀을 형성하는 단계를 포함하는 것을 특징으로 하는 전계방출 표시장치의 제조방법.
- 제 11 항에 있어서,상기 탄소나노튜브들을 단결정 구조로 성장시키는 단계는,상기 CNT 합성 원료 가스와 상기 건식 식각 반응 가스를 소정 시간 간격으로 교대로 상기 챔버 내에 공급하는 단계를 포함하는 것을 특징으로 하는 전계방출 표시장치의 제조방법.
- 제 11 항에 있어서,상기 탄소나노튜브들을 단결정 구조로 성장시키는 단계는,상기 CNT 합성 원료 가스와 상기 건식 식각 반응 가스를 동시에 공급하는 단계를 포함하는 것을 특징으로 하는 전계방출 표시장치의 제조방법.
- 제 11 항에 있어서,상기 게이트 절연층을 형성한 후에 상기 탄소나노튜브들의 최상단이 상기 게이트 절연층에서 가장 두꺼운 부분의 표면 이하에 위치하도록 상기 게이트 절연층 위에 돌출된 탄소나노튜브들을 식각하는 단계;상기 탄소나노튜브들을 완전히 덮을 수 있도록 1000Å~10μm 정도의 두께로 제2 게이트 절연층을 상기 게이트 절연층 상에 추가 코팅하는 단계; 및상기 게이트전극과 상기 게이트홀을 마스크로 하여 상기 게이트홀 아래에 위치하는 상기 게이트 절연층의 상단 일부를 상기 게이트 절연층의 두께 대비 1/2 이하의 깊이로 제거하는 단계를 더 포함하는 것을 특징으로 하는 전계방출 표시장치의 제조방법.
- 제 11 항에 있어서,상기 캐소드전극의 두께는 1000Å~4000Å 사이의 두께이고,상기 확산 차단층의 두께는 400Å ~ 4000Å 사이의 두께이고,상기 씨드 금속층의 두께는 50Å ~ 400Å 사이의 두께이고,상기 탄소나노튜브들의 높이는 2μm ~ 20μm 사이의 높이이고,상기 절연층의 두께는 0.2μm ~ 20μm 사이의 두께이며,상기 게이트전극의 두께는 1000Å~4000Å 사이의 두께이고,상기 탄소나노튜브들을 덮은 상기 게이트 절연층에 의해 상기 탄소나노튜브들이 밀집된 탄소나노튜브 다발 부분의 유전율과, 상기 탄소나노튜브 다발 주변에서 탄소나노튜브들이 없는 부분의 유전율이 2~8 정도로 실질적으로 동일한 것을 특징으로 하는 전계방출 표시장치의 제조방법.
- 제 11 항에 있어서,상기 확산 차단층과 상기 씨드 금속층을 패터닝하는 단계는,상기 씨드 금속층 상에 포토레지스트를 도포하고 포토리소그래피 공정을 실시하여 포토레지스트 패턴을 상기 씨드 금속층 상에 형성하고 상기 확산 차단층과 상기 씨드 금속층을 패터닝하는 단계를 포함하는 것을 특징으로 하는 전계방출 표시장치의 제조방법.
- 제 16 항에 있어서,상기 탄소나노튜브들을 단결정 구조로 성장시키는 단계는,상기 포토레지스트 패턴이 잔류한 상태에서 상기 씨드 금속층 상에 탄소나노튜브들을 단결정 구조로 성장시키는 단계를 포함하는 것을 특징으로 하는 전계방출 표시장치의 제조방법.
- 제 11 항에 있어서,상기 스페이서는,유리와 세라믹 중 어느 하나를 주성분으로 하고, 매트릭스 형태로 배치된 개구공들을 포함하고,상기 스페이서의 개구공들 각각의 피치는 상기 하판에 매트릭스 형태로 배치된 픽셀이나 서브픽셀의 피치와 실질적으로 동일한 것을 특징으로 하는 전계방출 표시장치의 제조방법.
- 제 18 항에 있어서,상기 상부 기판, 상기 하부 기판 및 상기 스페이서는 동일한 재료와 동일한 두께를 갖는 것을 특징으로 하는 전계방출 표시장치의 제조방법.
- 제 18 항에 있어서,상기 스페이서는,상기 개구공들을 구획하기 위한 격벽들; 및상기 격벽들에 소정 깊이로 형성되어 배기로를 형성하는 배기 홈들을 포함하는 것을 특징으로 하는 전계방출 표시장치의 제조방법.
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CN201180058047.8A CN103270571B (zh) | 2010-12-01 | 2011-11-29 | 场发射显示器装置及其制造方法 |
JP2013539781A JP2014500593A (ja) | 2010-12-01 | 2011-11-29 | 電界放出表示装置とその製造方法 |
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JP6589124B2 (ja) * | 2015-04-09 | 2019-10-16 | パナソニックIpマネジメント株式会社 | 樹脂構造体とその構造体を用いた電子部品、電子機器 |
CN104882345A (zh) | 2015-05-13 | 2015-09-02 | 京东方科技集团股份有限公司 | 阵列基板及制作方法、显示面板及制作方法和显示装置 |
KR102492733B1 (ko) | 2017-09-29 | 2023-01-27 | 삼성디스플레이 주식회사 | 구리 플라즈마 식각 방법 및 디스플레이 패널 제조 방법 |
CN110299388B (zh) * | 2019-06-24 | 2021-07-06 | 深圳市华星光电半导体显示技术有限公司 | 一种显示面板及其制备方法 |
CN111987111B (zh) * | 2020-08-12 | 2023-09-05 | Tcl华星光电技术有限公司 | 一种阵列基板、阵列基板制程方法及显示面板 |
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US11776793B2 (en) * | 2020-11-13 | 2023-10-03 | Applied Materials, Inc. | Plasma source with ceramic electrode plate |
KR102526595B1 (ko) * | 2021-01-22 | 2023-04-28 | 주식회사 일렉필드퓨처 | 캐소드 에미터 기판의 제조방법, 이에 의해 제조된 캐소드 에미터 기판 그리고, 이를 포함하는 엑스레이소스 |
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