WO2012042846A1 - ソルダーレジストの形成方法 - Google Patents

ソルダーレジストの形成方法 Download PDF

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Publication number
WO2012042846A1
WO2012042846A1 PCT/JP2011/005425 JP2011005425W WO2012042846A1 WO 2012042846 A1 WO2012042846 A1 WO 2012042846A1 JP 2011005425 W JP2011005425 W JP 2011005425W WO 2012042846 A1 WO2012042846 A1 WO 2012042846A1
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WIPO (PCT)
Prior art keywords
curable resin
protective film
resin layer
via hole
solder resist
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Application number
PCT/JP2011/005425
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English (en)
French (fr)
Japanese (ja)
Inventor
遠藤　新
直之 小池
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太陽ホールディングス株式会社
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Application filed by 太陽ホールディングス株式会社 filed Critical 太陽ホールディングス株式会社
Priority to KR1020137003399A priority Critical patent/KR101471794B1/ko
Priority to JP2012536202A priority patent/JP5572714B2/ja
Publication of WO2012042846A1 publication Critical patent/WO2012042846A1/ja

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0035—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/26—Cleaning or polishing of the conductive pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/288—Removal of non-metallic coatings, e.g. for repairing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/09—Treatments involving charged particles
    • H05K2203/095—Plasma, e.g. for treating a substrate to improve adhesion with a conductor or for cleaning holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1377—Protective layers
    • H05K2203/1383—Temporary protective insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0055—After-treatment, e.g. cleaning or desmearing of holes

Definitions

  • the present invention relates to a method for forming a solder resist formed on, for example, a circuit board.
  • solder is prevented from adhering to unnecessary parts, and circuit conductors are exposed to oxidize or humidity.
  • a solder resist is formed in a region excluding the via hole on the circuit board.
  • a photosensitive resin composition is selected as the solder resist, and the via hole / patterning is carried out by developing and peeling off the unexposed portion with an alkaline aqueous solution after exposing and cross-linking the portion other than the via hole forming portion through a mask. I went. At this time, the exposed portion serves as a permanent protective film (solder resist).
  • solder resist an alkaline aqueous solution
  • a curable resin layer serving as a solder resist is formed on a wiring pattern, cured, and then opened by irradiation with a laser beam such as a carbon dioxide laser. It is disclosed.
  • smear which is a residue of the curable resin coating film, remains on the bottom of the via after opening the via hole by laser irradiation. If the smear remains and the process proceeds to the plating process, which is a surface finishing process, unplated plating occurs, resulting in poor solder connection. Therefore, a desmear process for removing smear is required. However, since the vicinity of the via hole is damaged by the laser light irradiation, there is a problem that the surface layer of the solder resist is etched during the desmear process or the opening diameter of the via is increased.
  • Etching (roughening) of the surface layer is preferable if it is an inner layer because it can improve the adhesion to the upper layer, but damage to the solder resist as a permanent protective film in the outer layer decreases reliability. Leads to. Therefore, in order to suppress irradiation damage, it has been proposed to provide a protective film on the curable resin layer and irradiate laser light from the protective film (see, for example, Patent Document 1).
  • This invention is made in view of such a situation, and provides the formation method of the soldering resist which can suppress irradiation of a laser beam and the damage of a desmear process, and can improve reliability. .
  • the method for forming a solder resist of one embodiment of the present invention includes forming a semi-cured curable resin layer having a protective film adhered to a surface on a circuit board, and irradiating a laser beam on the protective film.
  • a feature is that a via hole is formed in a cured curable resin layer, smear in the via hole is removed by a desmear process using plasma, a protective film is peeled off, and a semi-cured curable resin layer is cured. To do.
  • the semi-cured curable resin layer is formed by laminating a dry film of a curable resin on a circuit board, or the curable resin composition on the circuit board. It is preferably formed by coating and drying to form a curable resin layer. With such a configuration, the curable resin layer can be easily formed.
  • the method for forming a solder resist according to one embodiment of the present invention includes curing a curable resin layer formed on a circuit board and having a protective film adhered to the surface, and irradiating the protective film with laser light to be curable.
  • a via hole is formed in the resin layer, smear in the via hole is removed by a desmear process using oxygen plasma, and the protective film is peeled off.
  • solder resist forming method it is preferable to perform ultrasonic cleaning after desmear treatment. With such a configuration, it is possible to suppress residual inorganic components.
  • the solder resist forming method according to one embodiment of the present invention can suppress laser light irradiation and damage of desmear treatment, and can improve reliability.
  • the inventors of the present invention have made extensive studies on the above problems, and as a result, in the formation of the solder resist, a semi-cured curable resin layer having a protective film adhered to the surface is formed on the circuit board, and the protective film is formed.
  • Laser light is irradiated from above to form a via hole in the semi-cured curable resin layer, smear in the via hole is removed by desmear treatment using plasma, the protective film is peeled off, and the semi-cured state is cured
  • the present inventors have found that by curing the curable resin layer, it is possible to suppress damage of laser light irradiation and desmear treatment and improve the reliability of the solder resist, thereby completing the present invention.
  • the laser beam is irradiated to the semi-cured curable resin layer formed on the substrate, the irradiation energy can be suppressed as compared with the cured resin layer, and the laser beam is protected. Since the resin layer is irradiated through the film, irradiation damage near the via hole can be suppressed. Furthermore, by setting the desmear process to a plasma process, the desmear process can be performed without causing damage due to penetration into the interface between the protective film and the curable resin layer during the chemical process. Therefore, the solder resist formed according to the present embodiment can improve the reliability when used as a printed wiring board or the like.
  • FIG. 1 shows a solder resist formation process diagram of the present embodiment.
  • a pretreatment such as degreasing and soft etching is performed on the circuit board 11 in which the conductive layer 11b such as a circuit pattern is formed on the base material 11a.
  • the curable resin dry film 12a is laminated using a vacuum laminator or the like.
  • the dry film is formed on a carrier film, and a cover film is laminated as necessary, and the exposed surface side is adhered to the circuit board with the protective film 13 as any film adhered to the surface.
  • the conditions of laminating there is no particular limitation on the conditions of laminating
  • the temperature 60 ⁇ 140 ° C., vacuum of 20mmHg or less can be carried out at a pressure 1 ⁇ 15kgf / cm 2.
  • a step of smoothing the curable resin layer after lamination by pressing is performed.
  • the smoothing step is performed under normal pressure, and the same conditions as in the laminating step can be used for heating and pressing conditions.
  • the vacuum laminator used in these steps include CVP-300 (manufactured by Nichigo Morton) and MVLP-500 (manufactured by Meiki Seisakusho).
  • the protective film 13 may be laminated after the curable resin composition is applied and dried on the circuit board to form the curable resin layer 12a.
  • the circuit board is not particularly limited, but a multilayer printed wiring such as a single-sided or double-sided printed board provided with a conductive layer such as copper or a build-up board using an insulating core material such as prepreg.
  • a known circuit board such as a board or a flexible printed board is used.
  • thermosetting resin composition As the curable resin composition used for forming the curable resin layer, a thermosetting resin composition, a photocurable resin composition, a photosensitive resin composition, or the like can be used.
  • a thermosetting resin composition containing an epoxy resin, an inorganic filler, and a curing agent is preferably used.
  • epoxy resin examples include bisphenol A type epoxy resin, bisphenol F type epoxy resin, hydrogenated bisphenol A type epoxy resin, brominated bisphenol A type epoxy resin, bisphenol S type epoxy resin, phenol novolac type epoxy resin, and cresol novolac type.
  • the inorganic filler for example, barium sulfate, calcium sulfate, silica, clay, talc, aluminum hydroxide and the like can be used. These have an absorption peak in the range of wave numbers 900 to 1300 cm ⁇ 1 , which is the wavelength band of a carbon dioxide laser described later, and sublimate or decompose during laser processing, so that residues after laser processing can be suppressed. These can be used alone or in combination of two or more.
  • curing agent examples include imidazoles, AZINE compounds of imidazole, isocyanurate of imidazole, imidazole hydroxymethyl, dicyandiamide and derivatives thereof, melamine and derivatives thereof, diaminomaleonitrile and derivatives thereof, diethylenetriamine, triethylenetetramine, tetra Amines such as ethylenepentamine, bis (hexamethylene) triamine, triethanolamine, diaminodiphenylmethane, organic acid dihydrazide, 1,8-diazabicyclo [5,4,0] undecene-7, 3,9-bis (3- Aminopropyl) -2,4,8,10-tetraoxaspiro [5,5] undecane, triphenylphosphine, tricyclohexylphosphine, tributylphosphine, methyldiphenylphosphine, etc.
  • Organic phosphine compounds such as are used. These can be used alone or in combination
  • phenoxy resin, polyvinyl acetal resin, polyimide, polyamideimide, etc. may be added alone or in combination of two or more in order to improve the film-forming property of the cured resin and improve the mechanical strength of the cured coating film.
  • a solvent or the like may be contained in order to adjust the concentration and improve the coatability.
  • the protective film 13 is provided in order to suppress laser irradiation damage around the via hole without reaching the curable resin layer.
  • PET polyethylene terephthalate
  • other polyesters such as polyethylene naphthalate, polypropylene (PP), polyethylene (PE), polycarbonate, polymethyl methacrylate (PMMA), cyclic polyolefin, triacetyl.
  • Cellulose, polyether sulfide, polyether ketone, polyimide and the like can be used.
  • the protective film 13 preferably has a thickness of 8-60 ⁇ m. Although the laser workability described later is improved as the thickness is thinner, it is difficult to suppress laser irradiation damage around the via hole when the thickness is less than 8 ⁇ m. On the other hand, when it exceeds 60 ⁇ m, the transmittance of the laser beam is lowered and the aperture diameter is reduced. More preferably, it is 10-50 ⁇ m, and still more preferably 12-38 ⁇ m.
  • a semi-cured curable resin layer is formed on the circuit board by laminating the dry film on the circuit board or by applying the curable resin composition on the circuit board and evaporating and drying it.
  • the semi-cured state refers to a state that is not completely cured, and it is preferable that the curing rate is about 20-80%.
  • the curing rate is less than 20%, fusion or the like is likely to occur at room temperature, and workability is deteriorated.
  • it exceeds 80% the laser processability is deteriorated, the embedding in the circuit during lamination, and the flatness are impaired.
  • the cure rate is 30-75%, more preferably the cure rate is 40-70%.
  • the curing rate is determined by the gelation time (GT1) in the solution of the curable resin composition (before the dry film is produced and before being applied on the circuit board), and on the dry film and the circuit board.
  • GT1 gelation time in the dried state
  • GT1-GT2 gelation time in the dried state
  • the gelation time (curing time) is determined according to 5.7 “curing time test” of JIS C 6521 “Multi-Ply Printed Wiring Board Pre-Preg Test Method”, respectively, curable resin composition solution, dry film, circuit board About 0.3g (solution is 0.3ml) about the state apply
  • laser light such as a carbon dioxide laser
  • an excimer laser or the like
  • a carbon dioxide laser is preferred from the viewpoint of via hole processing speed and cost.
  • a desmear process is performed to remove the smear 15 that is a residue of the curable resin remaining at the bottom of the via hole 14.
  • plasma treatment is used instead of chemical treatment using KMnO 4 or the like.
  • a vacuum plasma apparatus for example, a vacuum plasma apparatus, an atmospheric pressure plasma apparatus, or the like can be used.
  • a known plasma such as a plasma using a reactive gas such as oxygen plasma, a plasma using an inert gas such as argon plasma or helium plasma, or a plasma of a mixed gas thereof may be used. it can.
  • oxygen plasma it is particularly preferable to use oxygen plasma.
  • a highly reactive oxygen plasma used in forming an inner layer via cannot be used because the surface is roughened.
  • the protective film since the protective film is provided, it is possible to more effectively remove smear in the via hole without causing surface roughening.
  • the oxygen plasma treatment in the desmear treatment is also effective when laser irradiation is performed after the curable resin to which the protective film is bonded is cured. In that case, it is preferable to perform a mold release treatment in advance on the protective film.
  • the inorganic component such as filler may not remain sufficiently reactive and may remain, but the inorganic component is removed by ultrasonic cleaning. can do.
  • the protective film 13 is peeled off and heated at 130 to 180 ° C. for 15 to 90 minutes, for example, as shown in FIG. 1 (d).
  • the semi-cured curable resin layer is cured to form the solder resist 12b.
  • a method using a hot air circulation drying furnace, an IR furnace, a hot plate, a convection oven, or the like equipped with a heat source of an air heating method using steam, and a method in which hot air in the dryer is brought into countercurrent contact and supported by a nozzle A method of spraying on the body can be used.
  • a solder resist having a via hole is formed on the circuit board.
  • thermosetting resin composition As the curable resin composition, the compositions shown in Table 1 were blended so as to have a blending ratio, premixed with a stirrer, and then kneaded using a three-roll mill to prepare a thermosetting resin composition of the formulation. did.
  • thermosetting resin composition was coated on a 38 ⁇ m-thick PET film (AL-5 Lintec Co., Ltd.) treated with a release agent (alkyd type) using an applicator, and the film thickness after drying was a circuit. It applied uniformly with a reverse coater so that it may become 20 micrometers above.
  • the amount of residual solvent was 1%, and the gelation time at 170 ° C. was 60 seconds.
  • a 400 mm ⁇ 300 mm ⁇ 0.8 mmt double-sided copper clad laminate (MCL-E-679FGR manufactured by Hitachi Chemical Co., Ltd.) on which a conductive layer having a copper thickness of 18 ⁇ m is formed is used as a circuit board, and pretreatment (CZ-8100 + CL A profile corresponding to a copper etching amount of 1 ⁇ m was formed.
  • a dry film from which a polypropylene film has been peeled off is applied to a pre-treated copper clad laminate using a two-chamber vacuum laminator (CVP-300 manufactured by Nichigo Morton) to laminate temperature: 100 ° C., vacuum: 5 mmHg or less, pressure : Laminated under the condition of 5 kg / cm 2 . Furthermore, by press molding at a press temperature of 100 ° C. and a pressure of 5 kg / cm 2 , a curable resin layer (on a circuit) in which a PET film (protective film) is adhered to each surface on both sides of the copper-clad laminate. An evaluation substrate having a thickness of about 20 ⁇ m was obtained.
  • thermosetting resin composition (the gelation time of the solution at 170 ° C. for 120 seconds) was similarly pretreated (CZ-8100 + CL-8300, manufactured by MEC Co., Ltd.) so that the copper etching amount corresponding to 1 ⁇ m of the circuit board was equivalent.
  • CZ-8100 + CL-8300 manufactured by MEC Co., Ltd.
  • the film thickness after drying is 20 ⁇ m on the circuit.
  • Other screen printing methods, die coating methods, and the like may be used.
  • the amount of residual solvent was similarly 1%, and the gelation time at 170 ° C. was 60 seconds.
  • a PET film manufactured by AL-5 Lintec was laminated as a protective film on the surface of the curable resin layer in a semi-cured state by a roll laminator.
  • the above-described two-chamber vacuum laminator may be used, and a flat substrate can be manufactured by a pressing process.
  • a carbon dioxide gas laser (LC-2K2 manufactured by Hitachi Via Mechanics Co., Ltd.) is used to irradiate a laser beam having a wavelength of 9.3 ⁇ m, and the curable resin layer.
  • a via hole was formed. Irradiation conditions were such that the top opening diameter was 65 ⁇ m on the substrate without the protective film, aperture: 1.9 mm, output: 1.5 W, pulse width: 20 ⁇ sec, burst mode: 3 shot.
  • the protective film was peeled off and the same processing was performed.
  • the evaluation substrate was heated at 170 ° C. for 60 minutes in a hot air circulating drying oven (DF610, manufactured by Yamato Kagaku Co., Ltd.) to cure the curable resin layer.
  • DF610 hot air circulating drying oven
  • Plasma treatment 1 Plasma treatment (dry type)
  • the evaluation substrate after forming the via hole was subjected to plasma treatment using a plasma treatment apparatus (AP-1000 March) without peeling off the protective film.
  • the plasma treatment conditions were as follows: plasma gas: oxygen gas, argon gas, degree of vacuum: 200 mtorr, output: 500 W, treatment time: 5 minutes.
  • the protective film was peeled off and the same treatment was performed.
  • ultrasonic cleaning About the evaluation board
  • Table 2 shows the processing contents of each example and comparative example.
  • Comparative Example 1 shows a general inner layer via formation step.
  • Example 1-6 The evaluation substrates of Example 1-6 and Comparative Example 1-6 on which such processing was performed were evaluated as follows.
  • the via hole bottom residue was determined based on the degree of exposure of Cu at the bottom of the via hole, since a brighter image can be obtained with an atom having a larger atomic number in the BEC image.
  • the evaluation results are shown in Table 3. The evaluation criteria are as follows. A: No via hole bottom residue is observed. ⁇ : A slight residue at the bottom of the via hole is observed. ⁇ : A slight residue at the bottom of the via hole is observed. ⁇ : The curable resin is eluted and the penetration of the desmear liquid is severe.
  • FIG. 2 shows a laser processing
  • FIG. 3 shows (a) SEI after desmear treatment + ultrasonic cleaning
  • FIG. 4 shows (a) SEI after laser processing
  • FIG. 5 shows (a) SEI, (b) (a) a partially enlarged image of the ⁇ portion, and (c) BEC image after processing.
  • FIG. 6 shows (a) a BEC image and (b) an optical micrograph after plasma processing after laser processing
  • FIG. 8 shows a BEC image after ultrasonic cleaning
  • FIG. 9 shows (a) a BEC image and (b) an optical micrograph after plasma processing after laser processing
  • FIG. 11 shows a BEC image after ultrasonic cleaning, respectively.
  • the plasma treatment time was the same.
  • the metallic luster is increased by performing ultrasonic cleaning on the plasma-treated material.
  • ultrasonic cleaning can remove residues such as inorganic components remaining in the plasma treatment.
  • Example 1 the optical microscope photograph on the protective film after laser processing in FIG. 12 and after desmearing in FIG. 13 is shown. Moreover, the optical micrograph on the protective film after the desmear of the comparative example 2 is shown in FIG. The state after the laser processing in Comparative Example 2 is the same as that in Example 1.
  • Example 1 damage around the hole was not observed, and the surface layer was in a good state.
  • Comparative Example 2 although the PET film itself used as the protective film has desmear liquid resistance, the protective film is not sufficiently resistant, and thus the protective film is displaced. Further, it can be seen that the chemical solution penetrates into the interface between the protective film and the curable resin layer, so that a large damage is generated around the via hole.
  • FIG. 15 shows an optical micrograph on the protective film after laser processing and FIG. 16 after desmearing. Moreover, the optical microscope photograph on the protective film after the desmear of Example 6 is shown in FIG. In addition, the state after laser processing of Example 4 and Example 6 is the same as that of Example 1, and the state after desmear of Example 4 is the same as FIG.
  • the via hole diameter approaches that obtained by laser processing without providing a protective film.
  • the ultrasonic cleaning may be performed before or after curing of the curable resin layer.
  • FIG. 18 shows an optical micrograph after laser processing and FIG. 19 after desmear treatment with a chemical solution. As shown in these drawings, it is understood that the curable resin layer is completely eluted by performing a desmear treatment with a chemical solution in a semi-cured state.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Laser Beam Processing (AREA)
PCT/JP2011/005425 2010-09-27 2011-09-27 ソルダーレジストの形成方法 WO2012042846A1 (ja)

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JP2012536202A JP5572714B2 (ja) 2010-09-27 2011-09-27 ソルダーレジストの形成方法

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001192536A (ja) * 2000-01-11 2001-07-17 Mitsubishi Gas Chem Co Inc 高比誘電率ｂステージシート、それを用いたプリント配線板
JP2003017849A (ja) * 2001-06-29 2003-01-17 Ibiden Co Ltd 多層プリント配線板の製造方法
JP2004186231A (ja) * 2002-11-29 2004-07-02 Ngk Spark Plug Co Ltd 配線基板の製造方法
JP2010062478A (ja) * 2008-09-05 2010-03-18 Ajinomoto Co Inc 回路基板の製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200503152A (en) * 2003-07-10 2005-01-16 Macronix Int Co Ltd Methods of fabricating shallow trench isolation and patterning
JP2005347429A (ja) * 2004-06-02 2005-12-15 Ktech Research Corp プリント基板の製造方法
TW201031302A (en) * 2009-02-04 2010-08-16 Unimicron Technology Corp Fabrication method of circuit board

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001192536A (ja) * 2000-01-11 2001-07-17 Mitsubishi Gas Chem Co Inc 高比誘電率ｂステージシート、それを用いたプリント配線板
JP2003017849A (ja) * 2001-06-29 2003-01-17 Ibiden Co Ltd 多層プリント配線板の製造方法
JP2004186231A (ja) * 2002-11-29 2004-07-02 Ngk Spark Plug Co Ltd 配線基板の製造方法
JP2010062478A (ja) * 2008-09-05 2010-03-18 Ajinomoto Co Inc 回路基板の製造方法

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103052271A (zh) * 2012-12-17 2013-04-17 天津市德中技术发展有限公司 制作阻焊图案的同时对焊接区表面进行可焊性处理的方法
JP2016111373A (ja) * 2012-12-27 2016-06-20 ウシオ電機株式会社 デスミア処理装置
JP2014127604A (ja) * 2012-12-27 2014-07-07 Ushio Inc デスミア処理方法
JP2014127605A (ja) * 2012-12-27 2014-07-07 Ushio Inc デスミア処理方法
KR101748054B1 (ko) * 2012-12-27 2017-06-15 우시오덴키 가부시키가이샤 디스미어 처리 방법 및 디스미어 처리 장치
JP2015041728A (ja) * 2013-08-23 2015-03-02 ウシオ電機株式会社 デスミア処理方法およびデスミア処理装置
JP2015126227A (ja) * 2013-12-26 2015-07-06 ウシオ電機株式会社 デスミア処理装置
JP2016092307A (ja) * 2014-11-07 2016-05-23 株式会社アルバック 樹脂基板の加工方法
JP2016190435A (ja) * 2015-03-31 2016-11-10 積水化学工業株式会社 積層構造体の製造方法及び積層構造体
JPWO2018101404A1 (ja) * 2016-12-02 2019-04-18 株式会社アルバック 配線基板の加工方法
US11510320B2 (en) 2016-12-02 2022-11-22 Ulvac, Inc. Method of processing wiring substrate
CN107960017A (zh) * 2017-12-25 2018-04-24 广州兴森快捷电路科技有限公司 线路板阻焊层的加工方法
CN107960017B (zh) * 2017-12-25 2020-12-18 广州兴森快捷电路科技有限公司 线路板阻焊层的加工方法
JP2019016811A (ja) * 2018-10-09 2019-01-31 味の素株式会社 回路基板の製造方法
EP4132236A4 (en) * 2020-03-30 2024-05-01 Kyocera Corp PRINTED CIRCUIT BOARD AND METHOD FOR PRODUCING A PRINTED CIRCUIT BOARD
CN113141717A (zh) * 2021-04-21 2021-07-20 丰顺县和生电子有限公司 一种电路板母板的钻孔方法

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