WO2012013416A1 - Modul und herstellungsverfahren - Google Patents
Modul und herstellungsverfahren Download PDFInfo
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- WO2012013416A1 WO2012013416A1 PCT/EP2011/059961 EP2011059961W WO2012013416A1 WO 2012013416 A1 WO2012013416 A1 WO 2012013416A1 EP 2011059961 W EP2011059961 W EP 2011059961W WO 2012013416 A1 WO2012013416 A1 WO 2012013416A1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0032—Packages or encapsulation
- B81B7/007—Interconnections between the MEMS and external electrical signals
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- B81B7/0032—Packages or encapsulation
- B81B7/0058—Packages or encapsulation for protecting against damages due to external chemical or mechanical influences, e.g. shocks or vibrations
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/81139—Guiding structures on the body
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01058—Cerium [Ce]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/0665—Epoxy resin
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
Definitions
- the invention relates to a module in which a component chip is applied to a carrier substrate in a flip-chip method.
- the component chip is, in particular, a SAW filter chip which is sensitive on its surface
- component structures are mechanically sensitive and can be protected, for example, by a cavity. This could serve, for example, a housing of the component chip.
- DE 10 2006 025 162 B3 discloses a component encapsulation in which a component chip carrying the component structures is mounted on a carrier substrate in flip-chip technology with the aid of bump connections and spaced apart from one another
- Carrier substrate is disposed above this.
- a frame is formed on the surface of the carrier substrate, which rests on the surface of the component chip or leaves a narrow gap and thus forms a component structures receiving cavity.
- the cavity is sealed to the outside by a sealing material.
- DE 10 2007 025 992 A1 discloses a MEMS package in which a support frame is mounted on a substrate
- this frame structure is applied. In an alternative embodiment this frame structure is applied on the chip itself. The electrical connections between component chip and carrier substrate via bumps.
- the object of the present invention is a module
- Claim 8 relates to a manufacturing method for a module according to the invention.
- a module which comprises a device chip applied in flip-chip technology on a single-layer or multilayer carrier substrate.
- Carrier substrate facing surface has this
- Component chip component structures a support frame and support elements. Furthermore, by the support elements and / or the support frame, an electrical connection between the component structures of the component chip and the
- Carrier substrate produced.
- Support frames are produced in a common process step on the surface of the component chip, so that in the manufacture of the heights of the support elements and the
- module according to the invention it is possible, in a single or a plurality of method steps, to use one or more component chips in flip-chip technology on the carrier substrate apply, electrically connect them to the carrier substrate and between the chip and the surface of the
- the electrical connection between the component chip and the carrier substrate is effected by support elements which are applied to the surface of the chip.
- the support frame is mechanically fixed to the carrier substrate and z. B. soldered. The soldering of the support frame with the
- Carrier substrate mainly serves a mechanical
- Attachment of the support frame is usually also possible that the frame is connected to ground.
- the support frame forms a cavity in which the
- a component structure is understood to mean in particular a microelectromechanical one
- MEMS component Component
- / or acoustic wave electroacoustic component structures
- Microelectromechanical components can be sensors and
- actuators which are usually mechanically sensitive or must remain mobile for their function in the encapsulated state. To protect the components even better, the actuators
- This encapsulation layer is, for example, a glob top mass.
- This may comprise a liquid processable and thermally curable resin, for. B. on epoxy basis.
- the support elements and the support frame consist essentially of metal, in particular of copper.
- the carrier substrate may additionally
- the present invention further relates to a method for producing a module as described above.
- a supporting frame and supporting elements are produced on the surface of the component chip facing the carrier substrate in a common method step, so that their heights coincide. Since support frames and support elements are matched in their heights, a hermetically sealed cavity can form during the connection to the planar surface of the carrier substrate.
- Device chip is flip-chip on the
- the carrier substrate has an integrated electrical
- Wiring up may be formed in multiple layers, wherein on and between individual layers of a mechanically stable and electrically insulating material structured metallization levels are provided, which realize a corresponding wiring.
- the individual metallization levels are preferably offset from each other
- Carrier substrate applied metallic pads and arranged on the underside of the carrier substrate
- metallization can also cause passive electrical components such as resistors,
- the circuit is preferably with the
- LTCC low temperature cofired ceramic
- Carrier substrate have a solderable or bondable surface, in particular a UBM metallization (under bump
- Regions of this metallization layer are patterned into connection or contact surfaces.
- a metallic growth layer or seed layer is applied to the surface of the carrier substrate for subsequent metallization, for example, without current or in a PVD method. Over this growth layer becomes a galvanostabiler resist applied and structured according to the desired structure of the support frame and the support elements, for. B.
- Carrier substrate can also be exposed photolithographically via a mask.
- the growth layer is galvanically reinforced, for example by electrodepositing copper.
- a passivation layer can also be applied to the copper, for example nickel.
- a planarization process can be carried out in which the surfaces of the electroplating resist and the reinforced growth layer are removed until an overall planar surface is produced. Subsequently, the galvanic resist is removed and etched away the underlying residues of the growth layer.
- a support frame and supporting elements with a flat surface are formed on the component chip so that they can be flush or almost flush with the likewise planar surface of the carrier substrate.
- the support elements are electrically connected to the carrier substrate.
- the support frame is also soldered to the carrier substrate in the same step.
- Carrier substrate may be electrically connected to each other via the support elements, wherein at the same time a
- Component chip and the other components are applied. This may, for example, be a glob top cover.
- Figure 1 shows a device chip with support elements and a
- FIG. 2 shows the module according to the invention in unconnected
- FIG. 3 shows the module according to the invention, in which the
- Component chip has been connected to the carrier substrate and an encapsulation layer has been applied.
- FIG. 1 shows a component chip 1 as a bare chip, so-called bare die. In that shown in Figure 1
- Component chip 1 is a SAW filter that has on its upper side 2 component structures 3.
- the upper side 2 of the component chip 1 also has a
- Support frame 4 and 5 support elements.
- the support elements may be seated on connection surfaces of the component structures or may be electrically connected thereto.
- Support frame 4 and support elements 5 are matched in height to each other, since they are in a common
- Process step are prepared and optionally still planarized.
- Support frame 4 and support elements 5 project beyond the component structures 3 in height.
- Component structures 3 are within the frame 4
- FIG. 2 shows the module according to the invention in cross-section in a method step before the bonding or soldering of the component chip.
- the device chip 1 is on a
- Carrier substrate 6 bonded or soldered.
- Carrier substrate 6 may be formed one or more layers. On the surface 7 of the carrier substrate 6 are the first and second layers.
- Connection or contact surfaces 8 structured.
- Component chip 1 are arranged such that they can be connected to the connection or contact surfaces 8 of the carrier substrate 6.
- the support elements 5 and the support frame 4 consist essentially of metal, in particular copper. At its ends facing the carrier substrate 6, soldering material 9 is located in this embodiment.
- FIG. 3 shows the module m in a later method step, in which the component chip 1 is soldered to the carrier substrate 6 and in which an encapsulation layer 10 has also been applied over the component chip.
- Carrier substrate 6 an electrical connection between the component structures 3 of the device chip 1 and the carrier substrate 6 is made.
- a cavity 11 is further formed between support frame 4,
- one or more bare dies can do so in flip-chip processes on the carrier substrate 6
- the height of the module can be reduced.
- the height of the module can be reduced.
- Encapsulation layer 10 applied to the module This may be a polymer compound, a film or a resin, for example a glob top layer.
- This may be a polymer compound, a film or a resin, for example a glob top layer.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013521030A JP2013539253A (ja) | 2010-07-28 | 2011-06-15 | モジュール及びその製造方法 |
US13/812,490 US9253886B2 (en) | 2010-07-28 | 2011-06-15 | Module and production method |
KR1020137004889A KR101917716B1 (ko) | 2010-07-28 | 2011-06-15 | 모듈 및 제조 방법 |
CN2011800370056A CN103038871A (zh) | 2010-07-28 | 2011-06-15 | 模块和制造方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102010032506A DE102010032506A1 (de) | 2010-07-28 | 2010-07-28 | Modul und Herstellungsverfahren |
DE102010032506.6 | 2010-07-28 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2012013416A1 true WO2012013416A1 (de) | 2012-02-02 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2011/059961 WO2012013416A1 (de) | 2010-07-28 | 2011-06-15 | Modul und herstellungsverfahren |
Country Status (6)
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US (1) | US9253886B2 (de) |
JP (1) | JP2013539253A (de) |
KR (1) | KR101917716B1 (de) |
CN (1) | CN103038871A (de) |
DE (1) | DE102010032506A1 (de) |
WO (1) | WO2012013416A1 (de) |
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JP5999302B2 (ja) * | 2012-02-09 | 2016-09-28 | セイコーエプソン株式会社 | 電子デバイスおよびその製造方法、並びに電子機器 |
DE102013215246A1 (de) * | 2013-08-02 | 2015-02-05 | Robert Bosch Gmbh | Elektronikmodul mit Leiterplatten und anspritzbarem Kunststoff-Dichtring, insbesondere für ein Kfz-Getriebesteuergerät, und Verfahren zum Fertigen desselben |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH07212181A (ja) * | 1994-01-10 | 1995-08-11 | Toyo Commun Equip Co Ltd | 表面実装型圧電部品の構造 |
WO2003058810A1 (de) * | 2001-12-28 | 2003-07-17 | Epcos Ag | Verkapseltes bauelement mit geringer bauhöhe sowie verfahren zur herstellung |
WO2005102910A1 (de) * | 2004-04-22 | 2005-11-03 | Epcos Ag | Verkapseltes elektrisches bauelement und verfahren zur herstellung |
DE102006025162B3 (de) | 2006-05-30 | 2008-01-31 | Epcos Ag | Flip-Chip-Bauelement und Verfahren zur Herstellung |
DE102007025992A1 (de) | 2007-06-04 | 2008-12-11 | Epcos Ag | Verfahren zur Herstellung eines MEMS-Packages |
DE102007028288A1 (de) * | 2007-06-20 | 2008-12-24 | Epcos Ag | MEMS Bauelement und Verfahren zur Herstellung |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0637143A (ja) | 1992-07-15 | 1994-02-10 | Toshiba Corp | 半導体装置および半導体装置の製造方法 |
JP4766831B2 (ja) | 2002-11-26 | 2011-09-07 | 株式会社村田製作所 | 電子部品の製造方法 |
DE102005026243B4 (de) * | 2005-06-07 | 2018-04-05 | Snaptrack, Inc. | Elektrisches Bauelement und Herstellungsverfahren |
CN101183673A (zh) * | 2006-11-13 | 2008-05-21 | 中芯国际集成电路制造(上海)有限公司 | 堆叠式多芯片半导体封装结构及封装方法 |
DE102007020288B4 (de) * | 2007-04-30 | 2013-12-12 | Epcos Ag | Elektrisches Bauelement |
JP4998073B2 (ja) * | 2007-05-07 | 2012-08-15 | ソニー株式会社 | 半導体チップおよびその製造方法 |
JP5115524B2 (ja) * | 2009-07-08 | 2013-01-09 | パナソニック株式会社 | 電子部品ユニット及び補強用接着剤 |
-
2010
- 2010-07-28 DE DE102010032506A patent/DE102010032506A1/de not_active Ceased
-
2011
- 2011-06-15 KR KR1020137004889A patent/KR101917716B1/ko active IP Right Grant
- 2011-06-15 JP JP2013521030A patent/JP2013539253A/ja active Pending
- 2011-06-15 CN CN2011800370056A patent/CN103038871A/zh active Pending
- 2011-06-15 WO PCT/EP2011/059961 patent/WO2012013416A1/de active Application Filing
- 2011-06-15 US US13/812,490 patent/US9253886B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07212181A (ja) * | 1994-01-10 | 1995-08-11 | Toyo Commun Equip Co Ltd | 表面実装型圧電部品の構造 |
WO2003058810A1 (de) * | 2001-12-28 | 2003-07-17 | Epcos Ag | Verkapseltes bauelement mit geringer bauhöhe sowie verfahren zur herstellung |
WO2005102910A1 (de) * | 2004-04-22 | 2005-11-03 | Epcos Ag | Verkapseltes elektrisches bauelement und verfahren zur herstellung |
DE102006025162B3 (de) | 2006-05-30 | 2008-01-31 | Epcos Ag | Flip-Chip-Bauelement und Verfahren zur Herstellung |
DE102007025992A1 (de) | 2007-06-04 | 2008-12-11 | Epcos Ag | Verfahren zur Herstellung eines MEMS-Packages |
DE102007028288A1 (de) * | 2007-06-20 | 2008-12-24 | Epcos Ag | MEMS Bauelement und Verfahren zur Herstellung |
Also Published As
Publication number | Publication date |
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KR20130136440A (ko) | 2013-12-12 |
US20130176686A1 (en) | 2013-07-11 |
JP2013539253A (ja) | 2013-10-17 |
KR101917716B1 (ko) | 2019-01-29 |
CN103038871A (zh) | 2013-04-10 |
US9253886B2 (en) | 2016-02-02 |
DE102010032506A1 (de) | 2012-02-02 |
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