WO2012011258A1 - 基板及びその製造方法、表示装置 - Google Patents
基板及びその製造方法、表示装置 Download PDFInfo
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- WO2012011258A1 WO2012011258A1 PCT/JP2011/004038 JP2011004038W WO2012011258A1 WO 2012011258 A1 WO2012011258 A1 WO 2012011258A1 JP 2011004038 W JP2011004038 W JP 2011004038W WO 2012011258 A1 WO2012011258 A1 WO 2012011258A1
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
- H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
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- G—PHYSICS
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B33/00—Electroluminescent light sources
- H05B33/02—Details
- H05B33/06—Electrode terminals
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
Definitions
- a source electrode and a drain electrode are formed on the semiconductor layer by dry etching or the like to form a TFT, and then, for example, a silicon nitride film is formed on the entire substrate on which the source electrode and the drain electrode are formed by plasma CVD. Etc., and an interlayer insulating film covering the semiconductor layer, the source electrode, and the drain electrode is formed (see, for example, Patent Document 1).
- the TFT 5a has a bottom gate structure. As shown in FIGS. 3 and 4, the gate electrode 11aa provided on the insulating substrate 10a, and the gate insulating film 12 provided so as to cover the gate electrode 11aa, And an oxide semiconductor layer 13a having a channel region C provided in an island shape so as to overlap the gate electrode 11aa on the gate insulating film 12.
- the TFT 5a includes a source electrode 16aa and a drain electrode 16b provided on the oxide semiconductor layer 13a so as to overlap the gate electrode 11aa and to face each other with the channel region C interposed therebetween.
- the first terminal cover 24 formed of an oxide semiconductor is made into a conductor by plasma processing such as plasma etching, the first terminal is formed in the region R between the adjacent source terminals 15. Since the cover 24 is removed, it is possible to prevent the occurrence of a leak failure between the source terminals 15 arranged at a narrow pitch. Accordingly, it is possible to maintain insulation between the source terminals 15 arranged at a narrow pitch.
- the oxide semiconductor layer 13a is formed as shown in FIGS. The thickness of the channel region C and the first terminal cover 24 is reduced.
- etching process either dry etching or wet etching described above may be used. However, when processing a large area substrate, it is preferable to use dry etching.
- a fluorine-based gas such as CF 4 , NF 3 , SF 6 , or CHF 3
- a chlorine-based gas such as Cl 2 , BCl 3 , SiCl 4 , or CCl 4
- an oxygen gas or the like
- an inert gas such as argon may be added.
- any etching liquid can be used as long as the oxide semiconductor constituting the first terminal cover 24 can be removed and the first terminal cover 24 can be removed reliably. There is no particular limitation.
- the source terminal forming process, the gate, An insulating film forming step and an oxide semiconductor layer / first terminal cover forming step are performed.
- a silicon nitride film or the like is formed on the entire substrate on which the first terminal cover 24 is formed by the plasma CVD method. Thereafter, the first terminal cover 24 is protected on the first terminal cover 24 by patterning the resist by photolithography using a sixth photomask, performing wet etching on the silicon nitride film, removing the resist, and washing.
- a terminal cover protective layer (etching stopper layer) 29 is formed to a thickness of about 50 to 200 nm.
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Abstract
Description
以下、本発明の実施形態について、図面を参照しながら詳細に説明する。尚、本発明は以下の実施形態に限定されるものではない。
まず、ガラス基板、シリコン基板、耐熱性を有するプラスチック基板などの絶縁基板10aの基板全体に、スパッタリング法により、例えば、モリブテン膜(厚さ150nm程度)などを成膜する。その後、そのモリブテン膜に対して、第1フォトマスクを用いたフォトリソグラフィによるレジストのパターニング、モリブテン膜のウエットエッチング及びレジストの剥離、及び洗浄を行うことにより、図3、図6(a)、図7(a)に示すように、絶縁基板10a上に、走査配線11a、ゲート電極11aa、ゲート端子19b、補助容量配線11b、中継配線11c、及びソース端子15を形成する。
次いで、走査配線11a、ゲート電極11aa、補助容量配線11b、中継配線11c及びソース端子15が形成された絶縁基板10a全体に、CVD法により、例えば、窒化シリコン膜(厚さ100nm~600nm程度)を成膜して、図6(b)、図7(b)に示すように、絶縁基板10a上にゲート電極11aa、補助容量配線11b、中継配線11c及びソース端子15を覆うようにゲート絶縁膜12を形成する。
その後、スパッタリング法により、例えば、IGZO膜(厚さ30nm~150nm程度)を成膜する。その後、そのIGZO膜に対して、第2フォトマスクを用いたフォトリソグラフィによるレジストのパターニング、IGZO膜のウエットエッチング及びレジストの剥離、及び洗浄を行うことにより、図6(b)、図7(b)に示すように、ゲート絶縁膜12上に酸化物半導体層13a及び第1端子カバー24を形成する。
さらに、酸化物半導体層13aが形成された基板全体に、スパッタリング法により、例えば、チタン膜(厚さ20nm~150nm)及びアルミニウム膜(厚さ50nm~400nm程度)などを順に成膜する。その後、第3フォトマスクを用いたフォトリソグラフィーによるレジストのパターニング、チタン膜のウエットエッチングを行うとともに、チタン膜に対してドライエッチング(プラズマエッチング)、並びにレジストの剥離と洗浄を行うことにより、図6(c)に示すように、ソース電極16aa、ドレイン電極16b、信号配線16a(図3参照)、及び補助容量幹線16c(図3参照)を形成するとともに、酸化物半導体層13aのチャネル領域Cを露出させる。
次いで、ソース電極16aa、ドレイン電極16b(即ち、TFT5a)、及び信号配線16aが形成された基板の全体に、プラズマCVD法により、例えば、窒化シリコン膜、酸化シリコン膜、窒化酸化シリコン膜などを成膜し、図6(d)に示すように、TFT5aを覆う(即ち、酸化物半導体層13a、ソース電極16aa及びドレイン電極16bを覆う)層間絶縁膜17を厚さ300nm程度に形成する。
次いで、層間絶縁膜17が形成された基板の全体に、スピンコート法又はスリットコート法により、感光性のアクリル樹脂等からなる感光性の有機絶縁膜を厚さ2.0μm~4.0μm程度に塗布する。そして、フォトリソグラフィーによる有機絶縁膜のパターニングにより、図6(e)に示すように、層間絶縁膜17の表面上にパターニングされた平坦化膜18を形成する。
次いで、平坦化膜18をマスク(第4フォトマスク)として、ゲート絶縁膜12及び層間絶縁膜17に対してドライエッチング(プラズマエッチング)を行うことにより、図3、図6(f)に示すように、ゲート絶縁膜12、及び層間絶縁膜17に、ドレイン電極16bに到達するコンタクトホールCaを形成するとともに、中継配線11c及び信号配線16aに到達するコンタクトホールCbを形成する。
次いで、図6(f)、図7(d)に示すように、層間絶縁膜17及び平坦化膜18が形成された基板全体に、スパッタリング法により、例えば、インジウム錫酸化物からなるITO膜(厚さ50nm~200nm程度)等の導電膜36を成膜する。
まず、ガラス基板などの絶縁基板10bの基板全体に、スピンコート法又はスリットコート法により、例えば、黒色に着色された感光性樹脂を塗布した後に、その塗布膜を露光及び現像することにより、図8(a)に示すように、ブラックマトリクス31を厚さ1.0μm程度に形成する。
まず、上記薄膜トランジスタ基板作製工程で作製された薄膜トランジスタ基板20a、及び上記対向基板作製工程で作製された対向基板30の各表面に、印刷法によりポリイミドの樹脂膜を塗布した後に、その塗布膜に対して、焼成及びラビング処理を行うことにより、配向膜を形成する。
次に、本発明の第2の実施形態について説明する。図9は、本発明の第2の実施形態に係る薄膜トランジスタ基板の断面図であり、上述の図4に相当する図である。なお、本実施形態においては、上記第1の実施形態と同様の構成部分については同一の符号を付してその説明を省略する。また、液晶表示装置の全体構成については、上述の第1の実施形態において説明したものと同様であるため、ここでは詳しい説明を省略する。
次いで、酸化物半導体層13aが形成された基板全体に、プラズマCVD法により、例えば、窒化シリコン膜、酸化シリコン膜、窒化酸化シリコン膜などを成膜する。その後、第6フォトマスクを用いたフォトリソグラフィによるレジストのパターニング、窒化シリコン膜等に対するウエットエッチング、レジストの剥離、及び洗浄を行うことにより、図10(a)に示すように、酸化物半導体層13aのチャネル領域Cに、チャネル領域Cを保護するためのチャネル保護層(エッチングストッパ層)28を厚さ50~200nm程度に形成する。
9 集積回路チップ(電子部品)
10a 絶縁基板
11aa ゲート電極
12 ゲート絶縁膜
13a 酸化物半導体層
15 ソース端子(端子)
16aa ソース電極
16b ドレイン電極
17 層間絶縁膜
18 平坦化膜
19a 画素電極
19c 保護カバー
20a 薄膜トランジスタ基板(基板)
23 第2端子カバー(他の端子カバー)
24 第1端子カバー(端子カバー)
28 チャネル保護層
29 端子カバー保護層
30 対向基板(他の基板)
36 導電膜
40 液晶層(表示媒体層)
50 液晶表示装置
60 有機EL表示装置
71 有機EL表示素子(表示素子)
72 基体層(絶縁基板)
83 表示装置用基板(基板)
D 表示領域
P ピッチ
R ソース端子間の領域(端子間の領域)
T 端子領域
Claims (13)
- 絶縁基板上に設けられ、金属により形成された複数の端子と、前記端子の各々の一部を覆うように設けられ、酸化物半導体により形成された端子カバーとを備え、隣接する前記端子間の領域において、前記端子カバーが除去されていることを特徴とする基板。
- 前記端子と前記端子カバーとの間に設けられ、前記端子の一部が露出するコンタクトホールが形成された絶縁膜と、導電体により形成され、前記端子カバー及び前記コンタクトホールの表面に設けられた他の端子カバーとを更に備えることを特徴とする請求項1に記載の基板。
- 前記端子間の領域において、前記他の端子カバーが除去されており、前記端子間の領域側の前記端子カバーの端面と、前記端子間の領域側の前記他の端子カバーの端面とが面一であることを特徴とする請求項2に記載の基板。
- 前記端子間のピッチが、5~30μmであることを特徴とする請求項1~請求項3のいずれか1項に記載の基板。
- 前記酸化物半導体が、インジウム(In)、ガリウム(Ga)、アルミニウム(Al)、銅(Cu)、ニッケル(Ni)、ハフニウム(Hf)及び亜鉛(Zn)からなる群より選ばれる少なくとも1種を含む金属酸化物からなることを特徴とする請求項1~請求項4のいずれか1項に記載の基板。
- 前記酸化物半導体が、酸化インジウムガリウム亜鉛(IGZO)であることを特徴とする請求項5に記載の基板。
- 酸化物半導体層を有する薄膜トランジスタを更に備えることを特徴とする請求項1~請求項6のいずれか1項に記載の基板。
- 請求項1~請求項7のいずれか1項に記載の前記基板と、
前記基板に対向して配置された他の基板と、
前記基板及び前記他の基板の間に設けられた表示媒体層と
を備えることを特徴とする表示装置。 - 前記表示媒体層が液晶層であることを特徴とする請求項8に記載の表示装置。
- 請求項1~請求項7のいずれか1項に記載の前記基板と、
前記基板上に形成された表示素子と
を備えることを特徴とする表示装置。 - 前記表示素子が有機EL表示素子であることを特徴とする請求項10に記載の表示装置。
- 絶縁基板上に金属からなる複数の端子を形成する端子形成工程と、
前記絶縁基板上に前記端子を覆うように絶縁膜を形成する絶縁膜形成工程と、
前記絶縁膜上に酸化物半導体からなる端子カバーを形成する端子カバー形成工程と、
前記端子カバーをマスクとして、前記絶縁膜に対して、ドライエッチングを行うことにより、前記絶縁膜に前記端子に到達するコンタクトホールを形成するコンタクトホール形成工程と、
前記端子カバー上に導電体からなる導電膜を成膜した後、前記導電膜に対してエッチングを行うことにより、前記端子カバー及び前記コンタクトホールの表面上に他の端子カバーを形成し、前記端子カバーに対してエッチングを行うことにより、隣接する前記端子間の領域に存在する前記端子カバーを除去して、前記端子間の領域において、前記端子カバーを除去する端子カバー除去工程と
を少なくとも備えることを特徴とする基板の製造方法。 - 前記端子カバー形成工程の後、前記端子カバー上に該端子カバーを保護するための端子カバー保護層を形成する端子カバー保護層形成工程を更に備えることを特徴とする請求項12に記載の基板の製造方法。
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US9087752B2 (en) | 2010-10-07 | 2015-07-21 | Sharp Kabushiki Kaisha | Semiconductor device, display device, and method for manufacturing semiconductor device and display device |
WO2012137711A1 (ja) | 2011-04-08 | 2012-10-11 | シャープ株式会社 | 半導体装置および表示装置 |
JP2021119608A (ja) * | 2014-03-20 | 2021-08-12 | 株式会社半導体エネルギー研究所 | 半導体装置 |
JP7275189B2 (ja) | 2014-03-20 | 2023-05-17 | 株式会社半導体エネルギー研究所 | 半導体装置 |
JP2020113548A (ja) * | 2014-05-30 | 2020-07-27 | 株式会社半導体エネルギー研究所 | 発光装置 |
US11387422B2 (en) | 2014-05-30 | 2022-07-12 | Semiconductor Energy Laboratory Co., Ltd. | Light-emitting element, light-emitting device, electronic device, and lighting device |
US11832465B2 (en) | 2014-05-30 | 2023-11-28 | Semiconductor Energy Laboratory Co., Ltd. | Light-emitting element, light-emitting device, electronic device, and lighting device |
JPWO2017051791A1 (ja) * | 2015-09-24 | 2018-07-05 | シャープ株式会社 | 半導体装置およびその製造方法 |
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JP5275517B2 (ja) | 2013-08-28 |
KR20130044327A (ko) | 2013-05-02 |
CN103026398B (zh) | 2014-07-09 |
KR101320787B1 (ko) | 2013-10-23 |
JPWO2012011258A1 (ja) | 2013-09-09 |
CN103026398A (zh) | 2013-04-03 |
US8829517B2 (en) | 2014-09-09 |
US20130270548A1 (en) | 2013-10-17 |
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