WO2012001837A1 - Dispositif à semi-conducteur de puissance - Google Patents

Dispositif à semi-conducteur de puissance Download PDF

Info

Publication number
WO2012001837A1
WO2012001837A1 PCT/JP2011/000684 JP2011000684W WO2012001837A1 WO 2012001837 A1 WO2012001837 A1 WO 2012001837A1 JP 2011000684 W JP2011000684 W JP 2011000684W WO 2012001837 A1 WO2012001837 A1 WO 2012001837A1
Authority
WO
WIPO (PCT)
Prior art keywords
insulating film
well
well region
semiconductor device
region
Prior art date
Application number
PCT/JP2011/000684
Other languages
English (en)
Japanese (ja)
Inventor
史郎 日野
三浦　成久
中田　修平
大塚　健一
昭裕 渡辺
古川　彰彦
中尾　之泰
昌之 今泉
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=45401589&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=WO2012001837(A1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP2012522420A priority Critical patent/JP5692227B2/ja
Publication of WO2012001837A1 publication Critical patent/WO2012001837A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7804—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs

Definitions

  • the present invention relates to a power semiconductor device such as a silicon carbide semiconductor device.
  • FIGS. 1 and 2 of the same document A power semiconductor device composed of a vertical metal-oxide-semiconductor field-effect transistor (Metal Oxide Semiconductor Effect Transistor: MOSFET) and a diode described in Patent Document 1 is shown in FIGS. 1 and 2 of the same document.
  • diodes are arranged in at least one row in the peripheral portion of the cell region of the MOSFET, that is, in the region adjacent to the gate pad portion.
  • Each of these diodes is injected during forward bias into the N-type semiconductor layer on the drain side from the P well and P base shown in FIG. 2 when the MOSFET switches from the on state to the off state. Absorbs holes.
  • the above-mentioned structure of the same document can prevent the parasitic transistor shown in FIG. 3 of the same document from being turned on when the MOSFET is switched from the forward bias to the reverse bias.
  • the P base which is the P well of the MOSFET is electrically connected to the source electrode via the back gate.
  • the drain voltage of the MOSFET that is, the voltage of the drain electrode rises rapidly, and in some cases reaches about several hundred volts. May reach. Due to the rise of the drain voltage, displacement currents are generated on the drain electrode side and the source electrode side via the depletion layer capacitance formed between the P well and the N ⁇ drain layer in the off state. This displacement current is generated not only in the P well of the MOSFET but also in the diode if the P-type region is provided in the N ⁇ drain layer like the P well or the P well.
  • the displacement current generated in this way flows to the drain electrode as it is generated on the drain electrode side, but the displacement current generated on the source electrode side flows to the source electrode via the P-well or P-type region. .
  • the source electrode and the field plate are electrically connected as described in the description of the conventional example.
  • the displacement current that has flowed into the P well under the gate pad flows in the P well under the gate pad from the MOSFET cell direction toward the contact hole connected to the field plate, and passes through the field plate. Flows into the source electrode.
  • the area of the P well under the gate pad is very large with respect to the area of the P well of the MOSFET cell and the P well of the diode cell. Since the well itself and the contact hole have a resistance with a certain large resistance value, a voltage of a value that cannot be ignored is generated in the P well. As a result, at a position in the P well where the distance in the plane direction is large from a place (contact hole) where the P well is electrically connected to the source electrode (usually connected to the ground potential) via the field plate. A large potential will be generated.
  • This potential increases as the displacement current increases, and increases as the fluctuation dV / dt of the drain voltage V with respect to time t increases.
  • the voltage of the gate electrode is changed immediately after switching the MOSFET from the on state to the off state at a location where the gate insulating film of the MOSFET is sandwiched between the P well and the gate electrode.
  • the voltage is close to 0 V, a high voltage is generated in the P-well as described above, and the gate insulating film may be destroyed by a high electric field due to the high voltage.
  • the present invention was made to solve such a problem, and in a power semiconductor device including a MOSFET that switches at high speed, the occurrence of dielectric breakdown between the gate electrode and the source electrode during switching can be suppressed.
  • An object of the present invention is to provide a highly reliable power semiconductor device and a method for manufacturing the same.
  • the power semiconductor device includes a first conductivity type semiconductor substrate, a first conductivity type drift layer formed on the first main surface of the semiconductor substrate, and a plurality of the surface layers of the drift layer. Surrounding the formed first well region of the second conductivity type, the source region of the first conductivity type formed in a part of the surface layer of each of the plurality of first well regions, and the plurality of first well regions. As described above, the second conductivity type second well region having a larger area than the first well region formed apart from the first well region, a plurality of the first well regions, the source regions, and the first well regions.
  • Field insulation film and the field insulation A gate electrode formed on and on the gate insulating film; a source contact hole formed on the first well region through the gate insulating film; and the gate insulating film on the second well region
  • a power semiconductor device having a drain electrode provided on a second main surface of a semiconductor substrate and switching between an on state and an off state, wherein the distance to the well contact hole in the second well region is the largest the distance position from the (P) to the position of the well contact hole closest (Q) and x P, from the well contact hole on a straight line PQ
  • the power semiconductor device of the present invention includes a first conductivity type semiconductor substrate, a first conductivity type drift layer formed on a first main surface of the semiconductor substrate, and a part of a surface layer of the drift layer.
  • a second well region of a second conductivity type having a larger area than the first well region formed so as to surround the first well region, and a plurality of the first well regions and the source regions, and A gate insulating film formed on the first well region side on the second well region and a film thickness formed on the opposite side of the first well region side on the second well region from the gate insulating film.
  • Large field insulating film and the field A gate electrode formed on the insulating film and on the gate insulating film; a source contact hole formed on the first well region through the gate insulating film; and the gate on the second well region.
  • a source pad that electrically connects the first well region and the second well region through a well contact hole formed through the insulating film; a gate pad that is electrically connected to the gate electrode;
  • a power semiconductor device having a drain electrode provided on the second main surface of the semiconductor substrate and switching between an on state and an off state, the power semiconductor device being the most of the second well region below the field insulating film On a straight line connecting each position (P ′) on the outer periphery of the second well region far from the first well region to the position (Q ′) of the nearest well contact hole.
  • the power semiconductor device of the present invention includes a first conductivity type semiconductor substrate, a first conductivity type drift layer formed on a first main surface of the semiconductor substrate, and a part of a surface layer of the drift layer.
  • a second well region of a second conductivity type having a larger area than the first well region formed so as to surround the first well region, and a plurality of the first well regions and the source regions, and A gate insulating film formed on the first well region side on the second well region and a film thickness formed on the opposite side of the first well region side on the second well region from the gate insulating film.
  • Large field insulating film and the field A gate electrode formed on the insulating film and on the gate insulating film; a source contact hole formed on the first well region through the gate insulating film; and the gate on the second well region.
  • the power semiconductor device of the present invention includes a first conductivity type semiconductor substrate, a first conductivity type drift layer formed on a first main surface of the semiconductor substrate, and a part of a surface layer of the drift layer.
  • a second well region of a second conductivity type having a larger area than the first well region formed so as to surround the first well region, and a plurality of the first well regions and the source regions, and A gate insulating film formed on the first well region side on the second well region and a film thickness formed on the opposite side of the first well region side on the second well region from the gate insulating film.
  • Large field insulating film and the field A gate electrode formed on the insulating film and on the gate insulating film; a source contact hole formed on the first well region through the gate insulating film; and the gate on the second well region.
  • a source pad that electrically connects the first well region and the second well region through a well contact hole formed through the insulating film; a gate pad that is electrically connected to the gate electrode;
  • a power semiconductor device having a drain electrode provided on the second main surface of the semiconductor substrate and switching between an on state and an off state, the power semiconductor device being the most of the second well region below the field insulating film On a straight line connecting each position (P ′) on the outer periphery of the second well region far from the first well region to the position (Q ′) of the nearest well contact hole.
  • the gate insulating film or the field insulating film is insulated without applying a strong electric field to the gate insulating film and the field insulating film. It is possible to provide a power semiconductor device with higher reliability that can be prevented from being destroyed.
  • 1 is a plan view schematically showing a power semiconductor device according to a first embodiment of the present invention.
  • 1 is a plan view schematically showing a power semiconductor device according to a first embodiment of the present invention. It is sectional drawing which represents typically the one part cross section of the semiconductor device for electric power in Embodiment 1 of this invention. It is sectional drawing which represents typically the one part cross section of the semiconductor device for electric power in Embodiment 1 of this invention. It is sectional drawing which represents typically a part of power semiconductor device for demonstrating the manufacturing process of the power semiconductor device in Embodiment 1 of this invention. It is sectional drawing which represents typically a part of power semiconductor device for demonstrating the manufacturing process of the power semiconductor device in Embodiment 1 of this invention.
  • FIG. 1 is a plan view schematically showing a power semiconductor device according to a first embodiment of the present invention. It is sectional drawing which represents typically the one part cross section of the semiconductor device for electric power in Embodiment 1 of this invention. It is a top view which represents typically the electric power semiconductor device in Embodiment 2 of this invention. It is a top view which represents typically the electric power semiconductor device in Embodiment 2 of this invention. It is sectional drawing which represents typically the one part cross section of the semiconductor device for electric power in Embodiment 2 of this invention.
  • Embodiment 1 FIG.
  • the first conductivity type is n-type and the second conductivity type is p-type.
  • the semiconductor conductivity type may be reversed.
  • FIG. 1 is a plan view of a power semiconductor device mainly including a silicon carbide MOSFET, which is a power semiconductor device according to the first embodiment of the present invention, as viewed from above.
  • a source pad 10 is provided at the center of the upper surface of the power semiconductor device.
  • a gate pad 11 is provided on one side of the source pad 10 as viewed from above.
  • a gate wiring 12 is provided so as to extend from the gate pad 11 and surround the source pad 10.
  • the source pad 10 is electrically connected to the source electrode of the unit cell of the MOSFET provided in a plurality under the source pad 10, and the gate pad 11 and the gate wiring 12 are electrically connected to the gate electrode of the unit cell. And a gate voltage supplied from an external control circuit is applied to the gate electrode.
  • FIG. 2 is a plan view in which layers below the layers such as the source pad 10 and the gate pad 11 of the power semiconductor device in the present embodiment shown in FIG. 1 are seen through from above.
  • a well contact hole 62 is formed in the lower part around the source pad 10 shown in FIG. 1 through an interlayer insulating film (not shown) and a gate insulating film (not shown) thereunder.
  • a p-type silicon carbide second well region 42 is formed in a layer made of silicon carbide below well contact hole 62.
  • An n-type silicon carbide field stopper region 81 is formed outside the second well region 42 at a predetermined interval.
  • a cell region provided with a large number of the unit cells described above is provided inside the well contact hole 62 and the second well region 42.
  • a plurality of source contact holes 61 formed in the interlayer insulating film and a first well region 41 of p-type silicon carbide below each are formed.
  • a gate electrode (not shown) is formed on a part of the upper portion of the second well region 42 via a gate insulating film or a field insulating film, and the gate pad 11, the gate wiring 12, the gate electrode, A gate contact hole 64, which is a hole for electrically connecting the two, is formed through the interlayer insulating film.
  • 3 and 4 are schematic cross-sectional views of the power semiconductor device according to the present embodiment, schematically showing the cross-section of the AA portion and the cross-section of the BB portion of the plan view of FIG. 2, respectively.
  • a drift layer 21 made of n-type silicon carbide is formed on the surface of a semiconductor substrate 20 made of n-type and low-resistance silicon carbide.
  • a second well region 42 made of p-type silicon carbide is provided in the surface layer portion of the drift layer 21 at a position substantially corresponding to the region where the gate pad 11 and the gate wiring 12 described in FIG. 2 are provided. ing.
  • the second well region is located on both sides of the second well region 42 in FIG. 3 and on the surface layer portion of the drift layer 21 on the right side of the second well region 42 in FIG. 4 (inner side surrounded by the second well region 42 in FIG. 2).
  • a plurality of first well regions 41 made of p-type silicon carbide are provided at least at a predetermined interval from 42.
  • the region where the first well region 41 and the like are formed corresponds to the cell region described with reference to FIG.
  • a source region 80 made of n-type silicon carbide is formed at a position inside the first well region 41 at a predetermined interval from the outer periphery.
  • a low resistance p-type well contact region 46 made of silicon carbide is provided in the inner surface layer portion surrounded by the source region 80 of the first well region 41.
  • a low resistance p-type well contact region 47 made of silicon carbide is provided below the well contact hole 62 in the surface layer portion of the second well region 42.
  • An n-type field stopper region 81 made of silicon carbide is formed at a predetermined interval on the surface layer portion of the drift layer 21 on the left side (outside of FIG. 2) of the second well region 42 in FIG. ing.
  • a field insulating film 31 made of 30 or silicon dioxide is formed.
  • the gate insulating film 30 is formed on the first well region 41 that is a cell region and the upper part of the periphery of the first well region 41 and the upper part of the second well region 42, and the field insulating film 31 is formed on the first well region 41 side.
  • the upper side of the second well region 42 is formed on the side opposite to the first well region 41 side (inner side of FIG. 3, left side of FIG. 4, outer side of FIG. 2).
  • the gate insulating film field insulating film boundary 33 which is the boundary between the gate insulating film 30 and the field insulating film 31, is formed above the second well region 42.
  • a gate electrode 50 is formed on part of the gate insulating film 30 and the field insulating film 31 in contact with the gate insulating film 30 and the field insulating film 31.
  • the gate electrode 50 is provided on the gate insulating film 30 on the outer periphery of the first well region 41 and is electrically connected from a portion on the gate insulating film 30 to a portion on the field insulating film 31.
  • the gate electrode 50 is connected to the gate pad 11 or the gate wiring 12 by a gate contact hole 64 formed on the field insulating film 31 through the interlayer insulating film 32 formed on the field insulating film 31. Yes.
  • a source contact hole 61 provided through the interlayer insulating film 32 and the gate insulating film 30 is provided above the source region 80 and the well contact region 46 in the first well region 41.
  • a well contact hole 62 provided through the insulating film including the interlayer insulating film 32 is provided above the well contact region 47 of the second well region 42.
  • the well contact hole 62 is provided through the interlayer insulating film 32 and the gate insulating film 30.
  • the first well region 41 and the second well region 42 are electrically connected to each other by the source contact hole 61 and the source pad 10 in the well contact hole 62 with the ohmic electrode 71 interposed therebetween.
  • drain electrode 13 is formed on the back surface side of the semiconductor substrate 20 via the back surface ohmic electrode 72.
  • FIGS. 5 and 6 are cross-sectional views schematically showing a part of the power semiconductor device for explaining the manufacturing process of the power semiconductor device of the present embodiment.
  • (A) corresponds to the AA cross section of FIG. 2
  • (b) corresponds to the cross section of the BB cross section of FIG.
  • 1 ⁇ 10 13 cm ⁇ 3 to 1 ⁇ 10 10 is formed on the surface (first main surface) of the n-type low-resistance silicon carbide semiconductor substrate 20 by a chemical vapor deposition (CVD) method.
  • a drift layer 21 made of silicon carbide having an n-type impurity concentration of 18 cm ⁇ 3 and a thickness of 4 to 200 ⁇ m is epitaxially grown.
  • the semiconductor substrate 20 of silicon carbide a substrate whose first principal plane has a (0001) plane and has a 4H polytype and is tilted to 8 ° or less with respect to the c-axis direction is used.
  • the plane orientation, polytype, and inclination angle may be sufficient, or may not be inclined.
  • a p-type first well region 41, a p-type second well region 42, and an n-type source region 80 are formed at predetermined positions on the surface layer of the drift layer 21 by ion implantation.
  • the n-type field stopper region 81 and the p-type well contact regions 46 and 47 are formed.
  • Al (aluminum) or B (boron) is preferable as the p-type impurity to be ion-implanted, and N (nitrogen) or P (phosphorus) is preferable as the n-type impurity to be ion-implanted.
  • the semiconductor substrate 20 may not be positively heated at the time of ion implantation, or may be heated at 200 to 800 ° C.
  • each of the first well region 41 and the second well region 42 needs to be set so as not to be deeper than the bottom surface of the drift layer 21 that is an epitaxial growth layer.
  • the depth is in the range of 0.3 to 2 ⁇ m.
  • the p-type impurity concentration of each of the first well region 41 and the second well region 42 is higher than the impurity concentration of the drift layer 21 and is in the range of 1 ⁇ 10 15 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3 .
  • the depth of the source region 80 is set so that its bottom surface does not exceed the bottom surface of the first well region 41, its n-type impurity concentration is higher than the p-type impurity concentration of the first well region 41, and 1 It is set within the range of ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 21 cm ⁇ 3 .
  • the field stopper region 81 may be formed under the same conditions as the source region 80.
  • the p-type impurity concentration of each of the first well region 41 and the second well region 42 is set to n of the drift layer 21 in order to increase the conductivity in the channel region of the MOSFET. It may be lower than the type impurity concentration.
  • the well contact regions 46 and 47 are provided to obtain good electrical contact between the first well region 41 and the second well region 42 and the source pad 10 with the ohmic electrode 71 interposed therebetween. It is desirable to set the impurity concentration higher than the p-type impurity concentration of the first well region 41 and the second well region 42. Further, when ion-implanting these high-concentration impurities, it is desirable to ion-implant by heating the semiconductor substrate 20 to 150 ° C. or higher in order to reduce the resistance of the well contact regions 46 and 47.
  • annealing is performed in an inert gas atmosphere such as argon (Ar) gas or nitrogen gas, or in a vacuum, in a temperature range of 1500 to 2200 ° C. for a time in the range of 0.5 to 60 minutes.
  • the activated impurities are electrically activated.
  • the semiconductor substrate 20 and the film formed thereon may be annealed while being covered with a carbon film.
  • a carbon film By covering and annealing with the carbon film, it is possible to prevent the occurrence of surface roughness of the silicon carbide caused by residual moisture or residual oxygen in the apparatus during annealing.
  • a thermal oxide film is formed by sacrificing the surface of the drift layer 21 ion-implanted as described above, and the thermal oxide film is removed with hydrofluoric acid to thereby form the ion-implanted drift layer 21.
  • the surface alteration layer is removed to expose a clean surface.
  • a silicon dioxide film having a thickness of about 0.5 to 2 ⁇ m which is referred to as a field insulating film 31, is formed in a region other than the position substantially corresponding to the above-described cell region by using a CVD method, a photolithography technique, or the like.
  • the field insulating film 31 at a position substantially corresponding to the cell region may be removed by photolithography, etching, or the like.
  • a gate insulating film 30 is formed.
  • the film thickness of the gate insulating film 30 may be 30 nm or more and 300 nm or less, and more preferably 50 nm or more and 150 nm or less.
  • a gate electrode 50 made of a polycrystalline silicon material is formed on the gate insulating film 30 and the field insulating film 31 at a predetermined position by using a CVD method, a photolithography technique, or the like.
  • the polycrystalline silicon used for the gate electrode 50 preferably contains P and B and has a low resistance. P and B may be introduced during the film formation of the polycrystalline silicon, or may be introduced by an ion implantation method after the film formation.
  • the gate electrode 50 may be a multilayer film of polycrystalline silicon and metal or a multilayer film of polycrystalline silicon and metal silicide.
  • the outermost end face of the gate electrode 50 may be disposed on the field insulating film 31. By doing so, it is possible to prevent the quality deterioration of the gate insulating film 30 exposed at the end face due to the over-etching of the end face by the dry etching process.
  • an interlayer insulating film 32 composed of a silicon dioxide film is formed on the gate electrode 50 and the like by a deposition method such as a CVD method. Subsequently, the interlayer insulating film 32 is removed from the portion that becomes the source contact hole 61 and the well contact hole 62 by using a photolithography technique and a dry etching technique.
  • the formation of the metal film mainly composed of Ni by sputtering or the like is followed by heat treatment at a temperature of 600 to 1100 ° C. to react the metal film mainly composed of Ni with the silicon carbide layer, thereby carbonizing.
  • Silicide is formed between the silicon layer and the metal film.
  • the metal film remaining on the interlayer insulating film 32 other than the silicide formed by the reaction is removed by wet etching using one of sulfuric acid, nitric acid, hydrochloric acid, or a mixed solution of these and hydrogen peroxide. .
  • the silicide formed in the source contact hole 61 and the well contact hole 62 in this way becomes the ohmic electrode 71 shown in FIGS. 3 and 4, and the n-type silicon carbide region such as the source region 80 and the first well. Ohmic connection is made to both p-type silicon carbide regions such as region 41.
  • the interlayer insulating film 32 at the location that becomes the gate contact hole 64 is removed by using a photolithography technique and a dry etching technique.
  • a back surface ohmic electrode 72 is formed on the back side of the semiconductor substrate 20 by forming a metal mainly composed of Ni on the back surface (second main surface) of the semiconductor substrate 20 and performing a heat treatment.
  • a wiring metal such as Al is formed on the surface of the semiconductor substrate 20 that has been processed so far by sputtering or vapor deposition, and processed into a predetermined shape by photolithography, whereby the source pad 10, the gate pad 11 and the gate are formed.
  • the wiring 12 is formed.
  • the drain electrode 13 is formed by forming a metal film on the surface of the back ohmic electrode 72 on the back surface of the substrate, and the power semiconductor device whose cross-sectional views are shown in FIGS. 3 and 4 is completed.
  • the second conductivity type (p-type in this embodiment) second well region 42 connected to the source pad 10 by the well contact hole 62, the semiconductor substrate 20, and the back surface ohmic.
  • a diode is formed between the first conductivity type (n-type in this embodiment) drift layer 21 connected to the drain electrode 13 via the electrode 72.
  • the region (channel region) in contact with the gate insulating film 30 in the second conductivity type first well region 41 between the first conductivity type source region 80 and the first conductivity type drift layer 21 is electrically connected.
  • the source and gate of a MOSFET are the second conductivity type electrodes of the pn diode, and the drain of the MOSFET is the pn diode first.
  • Each of the electrodes is integrated with one conductivity type electrode, and a diode is connected in parallel between the source and drain of the MOSFET.
  • FIGS. 7A and 7B are schematic cross-sectional views of the power semiconductor device according to the present embodiment corresponding to FIGS. 3 and 4, respectively, and arrows in the drawing indicate current flows.
  • the voltage applied to the gate of the MOSFET (the gate pad 11 in this embodiment) is changed so that the MOSFET switches from the on state to the off state
  • the voltage of the drain (in this embodiment, the drain electrode 13) rises rapidly and changes from approximately 0V to several hundred volts.
  • the displacement current is p-type via the parasitic capacitance generated between the p-type first well region 41, the second well region 42, and the n-type drift layer 21. It flows in both n-type regions.
  • the p-type region as schematically shown by the solid line arrows in FIG.
  • a displacement current flows from the p-type first well region 41 and the second well region 42 to the source pad 10 through the ohmic electrode 71. Flowing. In the n-type region, a displacement current flows from the n-type drift layer 21 to the drain electrode 13 through the semiconductor substrate 20 and the back surface ohmic electrode 72 as schematically shown by the broken-line arrows in FIG.
  • the MOSFET When the gate electrode 50 is formed on the portion (well region) where such a large voltage is generated via the gate insulating film 30 and the field insulating film 31, the MOSFET is turned off and the voltage becomes approximately 0V. In some cases, a high electric field is applied to the insulating film between the gate electrode 50 and a portion (well region) where a large voltage is generated, causing the insulating film to break down.
  • the dielectric breakdown of the insulating film is suppressed. it can.
  • the source pad 10 In the pn junction formed between the n-type drift layer 21 and the p-type second well region 42 of the power semiconductor device of the present embodiment of the present invention, there is a gap between the source pad 10 and the drain electrode 13. In some cases, a depletion layer is formed by this voltage, and the charge density of this depletion layer is determined by the potential difference between the source pad 10 and the drain electrode 13. Since the voltage of the source pad 10 is usually 0 V, the voltage of the drain electrode 13 (drain voltage V D ) becomes the potential difference between the source pad 10 and the drain electrode 13 as it is.
  • epsilon 0 is the vacuum dielectric constant
  • .epsilon.s dielectric constant of the drift layer 21 q is the elementary charge
  • N D is when the effective first conductivity type impurity concentration (drift layer 21 of the drift layer 21 is n-type the amount obtained by subtracting the acceptor concentration from the donor concentration)
  • [Phi bi is the diffusion potential of the pn junction
  • the impurity concentration N a of the second well region 42 is made sufficiently higher than the impurity concentration N D of the drift layer 21.
  • the voltage of the drain electrode 13 (drain voltage V D ) changes from the drain voltage V ON in the on state to the drain voltage V OFF in the off state. increase also increases the depletion charge density Q D accordingly.
  • the time change rate dQ D / dt of the depletion charge density during the switching from the on state to the off state is expressed by the following equation.
  • holes having the same charge density are generated in the second well region 42, and the displacement current is transferred to the source pad 10 via the ohmic electrode 71 closest to the generated position. Flowing. In this current path, holes are generated in the second well region 42 as shown in FIG. 7, and move toward the same ohmic electrode 71 (well contact hole 62).
  • the position in the wafer plane where the distance to the ohmic electrode 71 (well contact hole 62) is the largest is P, and the ohmic electrode 71 (well contact hole 62) closest to the position P.
  • Q be the position in the wafer plane, and determine the current and potential generated between the straight lines PQ.
  • the point Q is a position where the distance to the position P is the shortest in the ohmic electrode 71 (well contact hole 62) formed with a size of about several ⁇ m on the wafer plane.
  • the current magnitude I H (x 1 ) at the position x 1 on the straight line PQ (where 0 ⁇ x 1 ⁇ x P ) is the amount of holes generated per hour in the range of x 1 ⁇ x ⁇ x P. Since they are equal, they can be expressed by the following equation.
  • the electric field applied to the gate insulating film 30 is calculated.
  • the region where the gate electrode 50 is located through the field insulating film 31 whose film thickness is d FL when viewed from the position Q is the region where the gate electrode 50 is located via the gate insulating film 30 whose film thickness is d OX. Since the field insulating film 31 is farther away, a higher voltage than the gate insulating film 30 is applied to the field insulating film 31, but the field insulating film 31 can be designed to be thicker than the gate insulating film 30. The applied electric field strength can be reduced. On the other hand, since it is difficult to increase the thickness of the gate insulating film 30 for the purpose of reducing the on-resistance, a high electric field is likely to be generated.
  • the position where the electric field having the highest electric field strength is generated in the gate insulating film 30 on the straight line connecting the position P and the position Q is the position of the gate insulating film field insulating film boundary 33.
  • 71 on the straight line PQ connecting the position of the (well contact hole 62) (position Q) by a distance x R of the gate insulating film field insulating film boundary 33 from the position Q is set so as to satisfy the equation (9), a gate insulating film
  • the electric field applied to 30 can be set to a predetermined value or less. For example, when Emax is 10 MV / cm, the electric field applied to the gate insulating film 30 can be 10 MV / cm or less, and a highly reliable power semiconductor device can be obtained. Further, when Emax is 3 MV / cm, a more reliable power semiconductor device can be obtained.
  • the region where the gate electrode 50 is located through the field insulating film 31 whose film thickness is d FL when viewed from the position Q is the region where the gate electrode 50 is located via the gate insulating film 30 whose film thickness is d OX. Since it is further away, a voltage higher than that of the gate insulating film 30 is applied to the field insulating film 31.
  • FIG. 9 is a schematic cross-sectional view of the power semiconductor device of the present embodiment.
  • the electric field applied to the field insulating film 31 can be made a predetermined value or less. For example, when E max is 3 MV / cm, the electric field applied to the field insulating film 31 can be 3 MV / cm or less, and a highly reliable power semiconductor device can be obtained.
  • silicon dioxide is generally used for the gate insulating film 30 and the field insulating film 31, and the breakdown electric field strength thereof is 10 MV / cm.
  • the E max 10MV / cm in the number 9 and number 12
  • the interlayer insulating film 32 formed by the CVD method is also deposited on the side surface of the field insulating film 31 by a film thickness approximately equal to the film thickness deposited on the field insulating film 31. Therefore, the film thickness of the interlayer insulating film 32 in the vertical direction of the wafer increases in the range of a distance equal to the film thickness of the interlayer insulating film 32 from the gate insulating film field insulating film boundary 33 to the gate insulating film 30 side.
  • the well contact hole 62 is formed so as to penetrate the interlayer insulating film 32, but in the range where the distance between the well contact hole 62 and the gate insulating film field insulating film boundary 33 is larger than the film thickness of the interlayer insulating film 31, the well contact hole 62 is formed.
  • the contact hole 62 is formed, the thickness of the interlayer insulating film 32 to be etched is uniform within the well contact hole 62, so that under-etching and over-etching are unlikely to occur and the process is facilitated.
  • the position where the distance from the well contact hole 62 connected to the second well region 42 in the second well region 42 is farthest is as shown in FIG. in the outermost circumference of the second well region 42, a position P 1 as a position closest to the center of the second well region 42, the well contact hole 62 closest to the position P 1 is the position Q 1 shown in FIG.
  • each position on the outermost periphery of the second well region 42 (the second well region far from the first well region).
  • the distance between P′Q ′ and the position Q ′ of the nearest well contact hole 62 on the straight line connecting P ′ and the position Q ′ of the nearest well contact hole 62 is xP ′, and the gate from the position (Q ′) of the well contact hole
  • the distance to the insulating film field insulating film boundary 33 (R ′) is x R ′
  • the distance to the position (S ′) where the gate electrode 50 is located farthest from the position (Q ′) of the well contact hole 62 is x.
  • S ′ the relationship of Equations 9 and 12 may be satisfied.
  • E max is set to 10 MV / cm
  • the distance x P from the point where the distance to the inner well contact hole in the second well region is the largest to the position of the well contact hole is set to several 9 Therefore, the electric field applied to the gate insulating film 30 can be 10 MV / cm or less, and a highly reliable power semiconductor device in which the gate insulating film 30 is not broken can be obtained.
  • E max is 10 MV / cm
  • a conventional Si-MOSFET using Si is operated at a relatively high operating speed of 20 V / nsec or more, but when operated at a high voltage of about 1 kV or higher. Since the conduction loss becomes very large, the operating voltage is limited to several tens to several hundreds volts. Therefore, an Si-IGBT (Insulated Gate Bipolar Transistor) has been used exclusively in a high voltage region from about 1 kV to higher.
  • the IGBT is a bipolar element, it is difficult to obtain high-speed switching characteristics like a unipolar element due to the influence of minority carriers. That is, since switching loss cannot be greatly reduced even if dV / dt is increased, it is not necessary to drive at high dV / dt, and it is used at an operating speed of about several V / nsec at most.
  • a MOSFET using a wide band gap semiconductor material such as silicon carbide can obtain a low conduction loss even in a high voltage region of 1 kV or higher, and can operate at high speed because it is a unipolar element. Since switching loss can be reduced by high-speed switching, loss during inverter operation can be further reduced.
  • the power semiconductor device of the present embodiment formed of a wide band gap semiconductor material, silicon dioxide that is the gate insulating film 30 even when operated under a high dV / dt condition such as 10 V / nsec.
  • the electric field applied to the film can be reduced, and a highly reliable power semiconductor device can be obtained.
  • well contact regions 46 and 47 are provided to reduce the contact resistance between the ohmic electrode 71 and the first well region 41 and the second well region 42, respectively.
  • the well contact regions 46 and 47 are not essential and may be omitted. That is, if the contact resistance having a sufficiently low contact resistance is obtained by changing the metal forming the ohmic electrode 71 to one suitable for p-type silicon carbide, the well contact regions 46 and 47 need not be formed.
  • a p-type junction termination structure (JTE) region that is a pressure-resistant structure may be provided on a part of the outside of the second well region 42.
  • the field stopper region 81 is not essential and may be omitted.
  • the source contact hole 61 and the well contact hole 62 and the gate contact hole 64 are formed separately.
  • the well contact hole 62 and the gate contact hole 64 may be formed at the same time.
  • silicide may be formed on the surface of the gate electrode 50 on the bottom surface of the gate contact hole 64 depending on the selection of the material of each component.
  • the temperature sensor electrode and the current sensor electrode may be formed in a part of the power semiconductor device, but these electrodes are included in the power semiconductor device in the present embodiment. May be formed. The presence / absence of the temperature sensor electrode and the current sensor electrode does not affect the effect of the power semiconductor device of the present embodiment.
  • a silicon nitride film or polyimide is left, leaving openings for connecting the source pad 10, gate pad 11, and gate wiring 12 on the upper surface of the power semiconductor device to an external control circuit. It may be covered with a protective film.
  • the gate pad In some cases, the potential of the gate electrode 50 at a location distant from the connection position with the gate 11 may be temporally shifted from the potential of the gate pad 11 and the gate wiring 12. This time shift is determined by a time constant determined by a resistance component such as the resistance of the gate electrode 50 and a parasitic capacitance formed between the source pad 10 and the like.
  • the low-resistance gate wiring 12 is provided in parallel with the gate electrode 50 in the outer peripheral portion, so that the occurrence of the time shift as described above is suppressed.
  • the first well region 41 and the second well region 42 have been described and illustrated as having the same p-type impurity concentration and depth.
  • the impurity concentration and the depth of each need not be the same, and may be different values.
  • the well contact regions 46 and 47 have been described as being individually located below the contact holes. However, the well contact regions 46 and 47 are continuous with the cross-sectional depth method. May be formed.
  • FIG. 10 is a plan view of a power semiconductor device mainly including a silicon carbide MOSFET, which is a power semiconductor device according to the second embodiment of the present invention, as viewed from above.
  • a source pad 10 is provided at the center of the upper surface of the power semiconductor device.
  • a gate pad 11 is formed inside the source pad 10 as viewed from above, and one or more gate wirings 12 having a line width narrower than the gate pad 11 are formed extending from the gate pad 11.
  • FIG. 11 is a plan view of the layers below the layers such as the source pad 10 and the gate pad 11 shown in FIG. Further, FIG. 12 shows the position S 2 on the straight line P 2 Q 2 in FIG. 11.
  • FIG. 12 is a schematic cross-sectional view of the power semiconductor device of the present embodiment.
  • the arrangement of the source pad 10 and the gate pad 11 on the plane shown in FIG. 11 the arrangement of the second well region 42 is also different from that in the first embodiment (FIG. 2). In this case, "in the second well region 42, farthest distance from the well contact hole 62 connected to the second well region 42 ', as shown with P 2 in FIG.
  • the position and number of the gate pads 11 and the shape of the source pad 10 may have a wide variety of cases, but this does not affect the effect of the power semiconductor device of the present invention.
  • the semiconductor element formed in the cell region is a vertical MOSFET.
  • the semiconductor substrate 20 of FIG. 3 and the back surface ohmic electrode 72 on the back surface side are disclosed.
  • the scope of the present invention is a semiconductor element as a switching element having a MOS structure such as MOSFET or IGBT.
  • E max is set to 10 MV / cm, more preferably 3 MV / cm, so that the relations of Equations 9 and 12 are satisfied.
  • the effect of the present invention does not depend on the manufacturing method, and other than the manufacturing method described in the first and second embodiments. Also in the power semiconductor device structure manufactured by using this manufacturing method, a highly reliable power semiconductor device structure can be obtained.
  • the present invention is not limited to power semiconductor devices composed of silicon carbide.
  • a power semiconductor device composed of a wide band gap semiconductor material such as gallium nitride, another semiconductor material such as a gallium arsenide material, or a Si material has the same effect.
  • the effect of the present invention is remarkable when the semiconductor material is a wide gap semiconductor.
  • the present invention is applied to a semiconductor device used for semiconductor materials such as silicon carbide, gallium nitride, aluminum nitride, and diamond. This is particularly effective when
  • the gate insulating film 30 of the power semiconductor device described as the vertical MOSFET in the first and second embodiments does not necessarily need to be an oxide film such as silicon dioxide as the name of the MOS.
  • An insulating film such as an aluminum film may be used.
  • the semiconductor element itself having the MOSFET structure described in the first and second embodiments as a “semiconductor device” in a narrow sense
  • a semiconductor element having this MOSFET structure A semiconductor element such as a freewheel diode connected in antiparallel to the semiconductor element and an inverter module mounted on a lead frame and sealed together with a control circuit for generating and applying a gate voltage of the semiconductor element.
  • the incorporated power module itself can also be defined as a “semiconductor device” in a broad sense.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Cette invention concerne un dispositif à semi-conducteur de puissance pouvant résoudre un problème lié aux dispositifs classiques à semi-conducteur de puissance à commutation rapide. En effet, lors d'une commutation, il peut arriver dans ces dispositifs classiques qu'un courant de déplacement qui circule génère une tension élevée du fait de la résistance du canal dans lequel circule ledit courant de déplacement, et cette tension peut provoquer le claquage d'une couche mince isolante telle qu'une couche d'isolation de grille, et la rupture du dispositif à semi-conducteur. Le dispositif à semi-conducteur de puissance de l'invention comprend : un substrat semi-conducteur d'un premier type de conductivité ; une couche de dérive du premier type de conductivité formée sur la première surface principale du substrat semi-conducteur ; une seconde région de puits d'un second type de conductivité formée de façon à entourer la première région de puits de la couche de dérive ; une couche d'isolation de champ formée sur une partie de la seconde région de puits située à l'opposé de la première région de puits ; et une plage source qui connecte électriquement la seconde région de puits et une région de source par l'intermédiaire d'un trou de contact de puits obtenu par perforation de la couche d'isolation de grille formée sur une partie de la seconde région de puits située du côté de la première région de puits. La distance séparant le trou de contact de puits et la limite entre la couche d'isolation de grille et la couche d'isolation de champ est fixée de façon à être inférieure ou égale à une valeur prédéterminée.
PCT/JP2011/000684 2010-06-30 2011-02-08 Dispositif à semi-conducteur de puissance WO2012001837A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2012522420A JP5692227B2 (ja) 2010-06-30 2011-02-08 電力用半導体装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010-149090 2010-06-30
JP2010149090 2010-06-30

Publications (1)

Publication Number Publication Date
WO2012001837A1 true WO2012001837A1 (fr) 2012-01-05

Family

ID=45401589

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2011/000684 WO2012001837A1 (fr) 2010-06-30 2011-02-08 Dispositif à semi-conducteur de puissance

Country Status (2)

Country Link
JP (2) JP5692227B2 (fr)
WO (1) WO2012001837A1 (fr)

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014162969A1 (fr) * 2013-04-03 2014-10-09 三菱電機株式会社 Dispositif semi-conducteur
WO2016052261A1 (fr) * 2014-10-01 2016-04-07 三菱電機株式会社 Dispositif à semiconducteurs
EP2927939A4 (fr) * 2012-11-28 2016-08-10 Sumitomo Electric Industries Dispositif à semi-conducteurs en carbure de silicium, et son procédé de fabrication
CN108886038A (zh) * 2016-04-11 2018-11-23 三菱电机株式会社 半导体装置
JPWO2018037701A1 (ja) * 2016-08-25 2019-02-14 三菱電機株式会社 半導体装置
WO2019092871A1 (fr) 2017-11-13 2019-05-16 新電元工業株式会社 Dispositif à semi-conducteur à large bande interdite
WO2019116481A1 (fr) 2017-12-14 2019-06-20 新電元工業株式会社 Dispositif à semi-conducteur à large bande interdite
CN110061051A (zh) * 2014-05-12 2019-07-26 英飞凌科技股份有限公司 半导体器件和有隔离源区的反向导电绝缘栅双极晶体管
CN110137240A (zh) * 2018-02-08 2019-08-16 松下知识产权经营株式会社 碳化硅半导体装置
JP2019161181A (ja) * 2018-03-16 2019-09-19 株式会社 日立パワーデバイス 半導体装置、パワーモジュールおよび電力変換装置
WO2019186853A1 (fr) 2018-03-29 2019-10-03 新電元工業株式会社 Dispositif à semi-conducteur à large bande interdite
JP2020036045A (ja) * 2019-11-29 2020-03-05 ローム株式会社 半導体装置
CN111295764A (zh) * 2017-11-13 2020-06-16 新电元工业株式会社 宽带隙半导体装置
JP2020113633A (ja) * 2019-01-10 2020-07-27 国立研究開発法人産業技術総合研究所 炭化珪素半導体装置
CN111564497A (zh) * 2020-04-30 2020-08-21 西安理工大学 一种具有非均匀体二极管的SiC MOSFET器件
CN112768447A (zh) * 2021-01-11 2021-05-07 杭州士兰集昕微电子有限公司 逆导型绝缘栅双极型晶体管及其制造方法
IT202100003653A1 (it) * 2021-02-17 2022-08-17 St Microelectronics Srl Dispositivo mosfet di carburo di silicio, a conduzione verticale, avente struttura di polarizzazione di porta perfezionata e relativo procedimento di fabbricazione

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01276770A (ja) * 1988-04-28 1989-11-07 Fuji Electric Co Ltd 半導体装置
JPH03252166A (ja) * 1990-03-01 1991-11-11 Toshiba Corp Ｍｏｓ型電界効果トランジスタ
JPH04229661A (ja) * 1990-06-08 1992-08-19 Nippondenso Co Ltd 絶縁ゲート型バイポーラトランジスタおよびその製造方法
JPH07249765A (ja) * 1994-03-10 1995-09-26 Nippondenso Co Ltd 絶縁ゲート型電界効果トランジスタ
JPH08102495A (ja) * 1994-09-30 1996-04-16 Toshiba Corp 半導体装置
JP2000294770A (ja) * 1999-04-09 2000-10-20 Rohm Co Ltd 半導体装置
JP2004363477A (ja) * 2003-06-06 2004-12-24 Sanken Electric Co Ltd 絶縁ゲート型半導体装置
JP2005243674A (ja) * 2004-02-24 2005-09-08 Renesas Technology Corp 半導体装置
JP2009302091A (ja) * 2008-06-10 2009-12-24 Denso Corp 炭化珪素半導体装置およびその製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05343692A (ja) * 1992-06-09 1993-12-24 Nec Corp 縦型電界効果トランジスタ
JP4696356B2 (ja) * 2000-12-14 2011-06-08 株式会社デンソー 半導体装置
JP4286877B2 (ja) * 2007-03-13 2009-07-01 Ｏｋｉセミコンダクタ株式会社 炭化珪素半導体装置およびその製造方法

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01276770A (ja) * 1988-04-28 1989-11-07 Fuji Electric Co Ltd 半導体装置
JPH03252166A (ja) * 1990-03-01 1991-11-11 Toshiba Corp Ｍｏｓ型電界効果トランジスタ
JPH04229661A (ja) * 1990-06-08 1992-08-19 Nippondenso Co Ltd 絶縁ゲート型バイポーラトランジスタおよびその製造方法
JPH07249765A (ja) * 1994-03-10 1995-09-26 Nippondenso Co Ltd 絶縁ゲート型電界効果トランジスタ
JPH08102495A (ja) * 1994-09-30 1996-04-16 Toshiba Corp 半導体装置
JP2000294770A (ja) * 1999-04-09 2000-10-20 Rohm Co Ltd 半導体装置
JP2004363477A (ja) * 2003-06-06 2004-12-24 Sanken Electric Co Ltd 絶縁ゲート型半導体装置
JP2005243674A (ja) * 2004-02-24 2005-09-08 Renesas Technology Corp 半導体装置
JP2009302091A (ja) * 2008-06-10 2009-12-24 Denso Corp 炭化珪素半導体装置およびその製造方法

Cited By (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2927939A4 (fr) * 2012-11-28 2016-08-10 Sumitomo Electric Industries Dispositif à semi-conducteurs en carbure de silicium, et son procédé de fabrication
US9450060B2 (en) 2012-11-28 2016-09-20 Sumitomo Electric Industries, Ltd. Method of manufacturing a silicon carbide semiconductor device
US9716157B2 (en) 2012-11-28 2017-07-25 Sumitomo Electric Industries, Ltd. Silicon carbide semiconductor device
CN112368809A (zh) * 2012-11-28 2021-02-12 住友电气工业株式会社 碳化硅半导体器件及其制造方法
CN105074921A (zh) * 2013-04-03 2015-11-18 三菱电机株式会社 半导体装置
JP5992094B2 (ja) * 2013-04-03 2016-09-14 三菱電機株式会社 半導体装置
US9577086B2 (en) 2013-04-03 2017-02-21 Mitsubishi Electric Corporation Semiconductor device
WO2014162969A1 (fr) * 2013-04-03 2014-10-09 三菱電機株式会社 Dispositif semi-conducteur
CN110061051A (zh) * 2014-05-12 2019-07-26 英飞凌科技股份有限公司 半导体器件和有隔离源区的反向导电绝缘栅双极晶体管
WO2016052261A1 (fr) * 2014-10-01 2016-04-07 三菱電機株式会社 Dispositif à semiconducteurs
US10128370B2 (en) 2014-10-01 2018-11-13 Mitsubishi Electric Corporation Semiconductor device
CN108886038A (zh) * 2016-04-11 2018-11-23 三菱电机株式会社 半导体装置
JPWO2018037701A1 (ja) * 2016-08-25 2019-02-14 三菱電機株式会社 半導体装置
CN111295764B (zh) * 2017-11-13 2024-03-01 新电元工业株式会社 宽带隙半导体装置
US11264494B2 (en) 2017-11-13 2022-03-01 Shindengen Electric Manufacturing Co., Ltd. Wide-gap semiconductor device
CN111295764A (zh) * 2017-11-13 2020-06-16 新电元工业株式会社 宽带隙半导体装置
WO2019092871A1 (fr) 2017-11-13 2019-05-16 新電元工業株式会社 Dispositif à semi-conducteur à large bande interdite
WO2019116481A1 (fr) 2017-12-14 2019-06-20 新電元工業株式会社 Dispositif à semi-conducteur à large bande interdite
US11342435B2 (en) 2017-12-14 2022-05-24 Shindengen Electric Manufacturing Co., Ltd. Wide-gap semiconductor device
CN110137240A (zh) * 2018-02-08 2019-08-16 松下知识产权经营株式会社 碳化硅半导体装置
US10672878B2 (en) 2018-02-08 2020-06-02 Panasonic Intellectual Property Management Co., Ltd. Silicon carbide semiconductor device
JP6994991B2 (ja) 2018-03-16 2022-02-04 株式会社 日立パワーデバイス 半導体装置、パワーモジュールおよび電力変換装置
JP2019161181A (ja) * 2018-03-16 2019-09-19 株式会社 日立パワーデバイス 半導体装置、パワーモジュールおよび電力変換装置
US11309415B2 (en) 2018-03-29 2022-04-19 Shindengen Electric Manufacturing Co., Ltd. Wide gap semiconductor device
WO2019186853A1 (fr) 2018-03-29 2019-10-03 新電元工業株式会社 Dispositif à semi-conducteur à large bande interdite
JP2020113633A (ja) * 2019-01-10 2020-07-27 国立研究開発法人産業技術総合研究所 炭化珪素半導体装置
JP7310144B2 (ja) 2019-01-10 2023-07-19 富士電機株式会社 炭化珪素半導体装置
JP2020036045A (ja) * 2019-11-29 2020-03-05 ローム株式会社 半導体装置
CN111564497A (zh) * 2020-04-30 2020-08-21 西安理工大学 一种具有非均匀体二极管的SiC MOSFET器件
CN111564497B (zh) * 2020-04-30 2023-04-18 西安理工大学 一种具有非均匀体二极管的SiC MOSFET器件
CN112768447A (zh) * 2021-01-11 2021-05-07 杭州士兰集昕微电子有限公司 逆导型绝缘栅双极型晶体管及其制造方法
IT202100003653A1 (it) * 2021-02-17 2022-08-17 St Microelectronics Srl Dispositivo mosfet di carburo di silicio, a conduzione verticale, avente struttura di polarizzazione di porta perfezionata e relativo procedimento di fabbricazione
EP4047664A1 (fr) * 2021-02-17 2022-08-24 STMicroelectronics S.r.l. Dispositif mosfet en carbure de silicium à conduction verticale ayant une structure de polarisation de grille améliorée et son procédé de fabrication

Also Published As

Publication number Publication date
JP6008145B2 (ja) 2016-10-19
JPWO2012001837A1 (ja) 2013-08-22
JP2015057850A (ja) 2015-03-26
JP5692227B2 (ja) 2015-04-01

Similar Documents

Publication Publication Date Title
JP6008145B2 (ja) 電力用半導体装置
JP6233484B2 (ja) 電力用半導体装置
US8492836B2 (en) Power semiconductor device
JP5606529B2 (ja) 電力用半導体装置
KR101230680B1 (ko) 반도체 장치 및 그 제조 방법
US8354715B2 (en) Semiconductor device and method of fabricating the same
JP5321377B2 (ja) 電力用半導体装置
WO2013001677A1 (fr) Dispositif à semi-conducteurs et son procédé de fabrication
WO2013042406A1 (fr) Dispositif à semi-conducteur de puissance
WO2011007387A1 (fr) Dispositif à semi-conducteurs de puissance et procédé de fabrication du dispositif à semi-conducteurs de puissance
US20180294350A1 (en) Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device
JP5233158B2 (ja) 炭化珪素半導体装置
WO2012105170A1 (fr) Dispositif semi-conducteur et procédé de fabrication associé
JP5059989B1 (ja) 半導体装置とその製造方法
JP7074173B2 (ja) 半導体装置および半導体装置の製造方法
JP3931805B2 (ja) 炭化珪素半導体装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11800316

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2012522420

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 11800316

Country of ref document: EP

Kind code of ref document: A1