WO2012000442A1 - 三维多值非挥发存储器及其制备方法 - Google Patents

三维多值非挥发存储器及其制备方法 Download PDF

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Publication number
WO2012000442A1
WO2012000442A1 PCT/CN2011/076632 CN2011076632W WO2012000442A1 WO 2012000442 A1 WO2012000442 A1 WO 2012000442A1 CN 2011076632 W CN2011076632 W CN 2011076632W WO 2012000442 A1 WO2012000442 A1 WO 2012000442A1
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Prior art keywords
region
gate
dielectric layer
channel region
source
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English (en)
French (fr)
Inventor
刘明
朱晨昕
霍宗亮
闫锋
王琴
龙世兵
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority claimed from CN2010102233563A external-priority patent/CN102315173A/zh
Priority claimed from CN2010102233544A external-priority patent/CN102315222A/zh
Application filed by Institute of Microelectronics of CAS filed Critical Institute of Microelectronics of CAS
Priority to US13/376,925 priority Critical patent/US8705274B2/en
Publication of WO2012000442A1 publication Critical patent/WO2012000442A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Definitions

  • the present invention relates to the field of microelectronics manufacturing and memory technology, and in particular, to a three-dimensional multi-valued non-volatile memory having three-dimensional integrated characteristics and localized stored charge, and a method for fabricating the same.
  • Non-volatile memory is the ability to maintain stored information for long periods of time without power. It has the characteristics of read-only memory (ROM), high access speed, and easy to erase and rewrite.
  • ROM read-only memory
  • non-volatile Sex memory especially flash memory, has become a more and more important memory type in the market for semiconductor devices.
  • the conventional flash memory is a silicon-based non-volatile memory using a polysilicon film floating gate structure, and the tunnel dielectric layer of the memory is generally an oxide layer, and a defect thereon forms a fatal discharge channel.
  • the charge trapping memory utilizes the charge localization storage characteristic of the trapping layer to realize discrete charge storage.
  • the defects on the tunneling dielectric layer only cause local charge leakage without forming a fatal discharge channel, thus making the charge retention more. stable. More importantly, with this charge localized storage feature, multiple relatively independent physical storage points can be implemented in a single device, enabling multi-bit storage and increased storage density.
  • the conventional flash memory adopts a planar structure, and the vertical structure memory can effectively utilize the side wall surface to form a vertical channel and increase the channel area, thereby obtaining superior device performance.
  • the present invention provides a three-dimensional multi-valued non-volatile memory having a plurality of memory cells, the plurality of memory cells further constituting a memory array having a gate stacked structure and periodically alternately arranged Gate stack region and channel region space, charge discrete memory gate dielectric layer, periodic channel region, symmetric source doped region and drain doped region, and doped by the source doped region and drain respectively
  • the location of the region and the gate stack region lead to bit lines and word lines.
  • the memory provides physical storage points by the charge discrete memory gate dielectric layer to achieve unit or multi-bit operation to achieve high memory density.
  • the gate stack structure is formed by sequentially stacking an isolation dielectric layer and a conductive gate layer, wherein the gate isolation dielectric layer is made of silicon dioxide, and the conductive gate layer is made of polysilicon, metal, or metal silicide. Or a structure that is stacked from multiple layers of material.
  • the periodically alternately arranged gate stack region and the channel region space are formed by etching the gate stack structure, and the gate stack region is defined by a photoresist or a hard mask.
  • the pattern is then etched until the dielectric layer is exposed, and after etching, a gate stack region and a channel region space which are alternately arranged periodically are formed.
  • the charge discrete memory gate dielectric layer is located on the sidewall of the gate stack region on both sides of the channel region, and the charge blocking layer, the charge storage layer and the gate layer are formed outward from the sidewall of the gate stack region.
  • the tunneling dielectric layer is formed.
  • the material used for the charge blocking layer is silicon dioxide, a metal oxide or a structure in which a plurality of materials are stacked, and the charge storage layer is made of silicon nitride, a high-k material or a stacked structure.
  • the material used to penetrate the dielectric layer is silicon dioxide, a high-k material, or a structure in which a plurality of layers of materials are stacked.
  • the memory uses channel hot electron injection CHE to complete the programming operation.
  • the electrons will enter the substrate into the charge storage layer below the gate.
  • the memory cell employs an FN gate erase operation to tunnel storage electrons from the charge storage layer into a gate stack structure of the memory array, or a band tunneling hot hole injection BBTH method to cause hot holes from the substrate Entry into the charge storage layer completes recombination with electrons to effect an erase operation.
  • the periodic channel region is formed by depositing polysilicon in the channel region between adjacent two tunnel dielectric layers and completely filling the channel region.
  • the doping type of the symmetric source doping region and the drain doping region is opposite to the doping type of the channel region, and the symmetric source doping region and the drain doping region are heavily doped.
  • the doping region has the same doping condition as the channel region, and the symmetric source doping region and the drain doping region are periodically distributed along the channel region.
  • the symmetric source doped region and the drain doped region are made of doped polysilicon or metal silicide.
  • the present invention also provides a method for preparing a three-dimensional multi-valued non-volatile memory, comprising: forming a gate stacked structure on a semiconductor substrate; etching the gate stacked structure to form a periodic alternating arrangement a gate stack region and a channel region space; depositing a charge blocking layer, a charge storage layer and a tunnel dielectric layer from the sidewalls of the gate stack region to form a charge discrete memory gate dielectric layer; a channel region between the tunnel dielectric layers is formed by depositing polysilicon to form a periodic channel region; etching the channel region in a direction perpendicular to the channel region to form a plurality of periodically arranged source doped regions and a drain doped region position; depositing a source/drain dopant material in the source doped region and the drain doped region to form a symmetric source doped region and a drain doped region; and the source doped region and the source doped region respectively The drain doped region position and the gate stack
  • the forming a gate stack structure on the semiconductor substrate comprises: depositing a dielectric layer capable of buffering isolation on the semiconductor substrate by chemical vapor deposition; sequentially depositing and isolating on the dielectric layer by chemical vapor deposition The dielectric layer and the conductive gate layer form a gate stack structure.
  • the semiconductor substrate is a silicon wafer, a silicon germanium wafer or a multilayer substrate material including an epitaxial silicon layer and a germanium silicon layer;
  • the dielectric layer is silicon dioxide;
  • the isolation dielectric layer and the conductive gate layer are sequentially stacked, and the isolation dielectric layer is made of silicon dioxide, and the conductive gate layer is made of polysilicon, metal, metal silicide or stacked by multiple layers of materials. Structure of a similar nature.
  • the etching the gate stacked structure forms a gate stack which is periodically arranged alternately
  • the space of the region and the channel region includes: defining a pattern of the gate stack region by a photoresist or a hard mask, etching the gate stack structure until the dielectric layer is exposed, and forming a periodic alternating arrangement after etching Gate stacking region and channel region space.
  • the charge blocking layer, the charge storage layer and the tunnel dielectric layer are sequentially deposited from the sidewall of the gate stack region to form a charge discrete memory gate dielectric layer, comprising: forming an alternating arrangement in the etching Depositing a charge blocking layer, a charge storage layer and a tunnel dielectric layer on the gate stack structure of the gate stack region and the channel region space; etching is performed on the gate stack region and the dielectric layer The charge blocking layer, the charge storage layer and the tunnel dielectric layer are etched to expose the uppermost isolation dielectric layer and the substrate, thereby preserving the charge blocking layer, the charge storage layer and the charge storage layer formed along the sidewall of the gate stacked region. Tunneling the dielectric layer to form a charge discrete memory gate dielectric layer.
  • the channel region between the adjacent two tunnel dielectric layers is spatially deposited with polysilicon to form a periodic channel region, including: a trench between adjacent two tunnel dielectric layers
  • the channel region space deposits polysilicon, completely filling the channel region space to form a periodic channel region.
  • the etching the channel region in a direction perpendicular to the channel region to form a plurality of periodically arranged source doped regions and drain doped regions including: using a photoresist or a hard mask To define a pattern of the position of the source doped region and the drain doped region, and then etch the channel region in a direction perpendicular to the channel region until the substrate is exposed, and a plurality of periodically arranged square holes are formed on the channel region The square hole is the position of the source doping region and the drain doping region.
  • the source/drain dopant material is deposited in the source doped region and the drain doped region to form a symmetric source doped region and a drain doped region, including: in the source doped region and A source/drain dopant material is deposited in the drain doped region, and the surface is planarized by chemical mechanical polishing to form symmetric source and drain doped regions along the periodic distribution of the channel region.
  • the method further includes: performing a heat treatment process to form the channel region and the source doping region and the drain doping region to form single crystal silicon.
  • the step of forming a non-volatile three-dimensional multi-valued non-volatile memory by the source doped region and the drain doped region and the gate stacked region respectively to form a non-volatile three-dimensional multi-valued non-volatile memory is a source
  • the doped region and the drain doped region lead to a bit line, and the bit line is disposed in a direction perpendicular to the channel region, and a word line is drawn from the gate stacked region, and the word line is disposed in a direction parallel to the channel region.
  • the bit line is made of polysilicon, metal, metal silicide or more
  • the layer material stack has a structure having similar properties
  • the word line is made of polysilicon, metal, metal silicide or a structure having similar properties stacked by a plurality of layers of materials.
  • the present invention has the following beneficial effects:
  • the three-dimensional multi-valued non-volatile memory and the preparation method thereof provided by the invention comprehensively utilize the charge localized storage property of the charge trapping layer and the effective channel length increase and density improvement of the vertical structure memory, so that a single storage structural unit With multiple physical storage points, the three-dimensional integration of the memory array is realized on the basis of realizing multi-bit storage, and the storage density is fundamentally improved while ensuring high-speed storage performance such as high speed.
  • the three-dimensional multi-valued non-volatile memory and the preparation method thereof provided by the invention are compatible with a conventional silicon planar CMOS process, and can be integrated by a conventional memory array structure, which is advantageous for wide application.
  • FIG. 1 is a schematic view showing a gate stack structure formed on a semiconductor substrate in accordance with an embodiment of the present invention
  • FIG. 2 is a schematic view showing etching of the gate stack structure in accordance with an embodiment of the present invention
  • FIG. 3 is a schematic diagram of depositing a charge discrete memory gate dielectric layer after etching a stacked structure in accordance with an embodiment of the present invention
  • FIG. 4 is a schematic diagram of etching a charge discrete memory gate dielectric layer deposited over a gate stack region and a dielectric layer in accordance with an embodiment of the present invention
  • FIG. 5 is a schematic diagram showing spatial deposition of polysilicon in a channel region between two adjacent tunnel dielectric layers to form a periodic channel region in accordance with an embodiment of the present invention
  • FIG. 6 is a schematic diagram showing the position of a source/drain doping region by etching in accordance with an embodiment of the present invention
  • FIG. 7 is a source/drain doping material forming source at a source/drain doping region in accordance with an embodiment of the present invention. Schematic diagram of a drain doped region;
  • FIG. 8 is a schematic diagram of single-crystalization of a channel region and a source/drain doped region according to an embodiment of the present invention
  • FIG. 9 is a schematic diagram of a bit line drawn from a source/drain doped region according to an embodiment of the present invention
  • FIG. 10 is a schematic diagram of drawing a word line from a gate stack region in accordance with an embodiment of the present invention.
  • FIG. 11 is a single layer equivalent circuit diagram of a three-dimensional multi-valued non-volatile memory in accordance with an embodiment of the present invention. Intention
  • Figure 12 is a three-dimensional equivalent circuit diagram of a three-dimensional multi-valued non-volatile memory in accordance with an embodiment of the present invention.
  • FIG. 1 to 10 illustrate a schematic diagram of preparing a three-dimensional multi-valued non-volatile memory according to an embodiment of the present invention, and the specific preparation process is as follows:
  • FIG. 10 is a schematic view showing the formation of a gate stack structure on a semiconductor substrate in accordance with an embodiment of the present invention.
  • the semiconductor substrate 100 is a silicon wafer, a germanium silicon wafer, other similar semiconductor materials, or a multilayer substrate material including an epitaxial silicon layer and a germanium silicon layer.
  • Dielectric layer 101 is a silicon dioxide or other material having similar properties that acts as a buffer barrier.
  • 102a, 102b, 102c, 102d, 102e are isolation dielectric layers, the material used is silicon dioxide or other materials having similar properties,
  • 103a, 103b, 103c, 103d are conductive electrical gate layers, the material used is polysilicon, Metal, metal silicide or a structure having similar properties stacked by multiple layers of material.
  • the isolation dielectric layer and the conductive gate layer are sequentially stacked to form a gate stacked structure. The process is chemical vapor deposition (CVD) or the like.
  • FIG. 2 is a schematic view of etching the gate stack structure in accordance with an embodiment of the present invention.
  • the pattern of the gate stack region 201 is defined by a photoresist or a hard mask, and the gate stack structure is etched until the dielectric layer 0 101 is exposed. After etching, a periodic gate stack region 201 is formed and engraved. The channel area 202 opened after etching.
  • FIG. 3 is a schematic diagram of depositing a charge discrete memory gate dielectric layer after etching a stacked structure in accordance with an embodiment of the present invention.
  • a charge blocking layer 301, a charge storage layer 302, and a tunnel dielectric layer 303 are sequentially deposited from the sidewalls of the gate stack region 201 to form a charge discrete memory gate dielectric layer.
  • the material used for the charge blocking layer 301 is silicon dioxide, metal oxide, other materials having similar properties or composed of multiple layers.
  • the charge storage layer 302 is made of silicon nitride, high-k material, other charge storage material or stacked structure
  • the tunnel dielectric layer 303 is made of silicon dioxide and high. k material, other materials having similar properties or structures having similar properties stacked by multiple layers of materials. The preparation method and the thickness of each layer can be adjusted depending on the materials used.
  • 4 is a schematic diagram of etching a charge discrete memory gate dielectric layer deposited over the gate stack region 201 and the dielectric layer 101 in accordance with an embodiment of the present invention. After etching, the uppermost isolation dielectric layer 102e and the substrate 100 are exposed. The charge blocking layer 301, the charge storage layer 302, and the tunnel dielectric layer 303 which are sequentially formed along the sidewalls of the gate stack region are retained.
  • Figure 5 is a schematic illustration of the deposition of polysilicon to form a periodic channel region in a channel region space 202 between adjacent two tunnel dielectric layers 303 in accordance with an embodiment of the present invention.
  • Polysilicon is deposited in the channel region space 202 between adjacent two tunnel dielectric layers 303, completely filling the channel region space 202 to form a periodic channel region 401.
  • FIG. 6 is a schematic diagram showing the position of a source/drain doping region by etching in accordance with an embodiment of the present invention.
  • the pattern of the source/drain doping region position 502 is defined by a photoresist or a hard mask or the like, and then the channel region 401 is etched in a direction perpendicular to the channel region 401 until the substrate 100 is exposed, in the channel region 401.
  • a plurality of periodically arranged square holes 502 are formed thereon, which are the source/drain doping regions.
  • an unetched channel region 501 remains in the channel region 401.
  • FIG. 7 is a schematic diagram of the formation of a source/drain dopant material to form a source/drain doping region at a source/drain doping region 502 in accordance with an embodiment of the present invention.
  • a source/drain dopant material is deposited in the source/drain doping region 502 to form a source/drain doping region 601 which is a heavily doped polysilicon of opposite type to the channel region doping.
  • the source/drain dopant material fills the source/drain doping region 502 opened by etching, and then planarizes the surface of the device by chemical mechanical polishing. Since the doping conditions of the source/drain doping regions are the same, symmetric source doping regions and drain doping regions 601a are formed, and the source doping regions and the drain doping regions are periodically distributed along the channel region 401.
  • Fig. 8 is a schematic view showing the single-crystalization of a channel region and a source/drain impurity region according to an embodiment of the present invention. After the heat treatment process, both the channel region and the source/drain doped regions form single crystal silicon.
  • Figure 9 is a schematic diagram of a bit line drawn from a source/drain miscellaneous region in accordance with an embodiment of the present invention.
  • the bit line 701 is taken out from the source/drain doping region and disposed along the direction perpendicular to the channel region.
  • the bit line 701 is made of polysilicon, metal, metal silicide or has a similar property by stacking multiple layers of material. structure.
  • Figure 10 is a schematic illustration of a word line taken from a gate stack region in accordance with an embodiment of the present invention.
  • the word line 801 is taken out from the gate stack region and disposed in a direction parallel to the channel region.
  • the material of the word line 801 is polysilicon, metal, metal silicide or a structure having similar properties stacked by a plurality of layers of material. .
  • FIG. 11 is a schematic diagram showing a single layer equivalent circuit of a three-dimensional multi-valued non-volatile memory according to an embodiment of the invention
  • FIG. 12 further illustrates a three-dimensional equivalent circuit of a three-dimensional multi-valued non-volatile memory according to an embodiment of the invention.
  • the three-dimensional structure greatly increases the storage density compared to the conventional planar structure. Programming, erasing, reading, etc.
  • the three-dimensional multi-valued non-volatile memory has a plurality of memory cells, the plurality of memory cells further constituting a memory array having a gate stacked structure and periodically alternately arranged. a gate stack region and a channel region space, a charge discrete memory gate dielectric layer, a periodic channel region, a symmetric source doped region and a drain doped region, and the source doped region and the drain doped region, respectively
  • the location and the gate stack region lead to bit lines and word lines.
  • the memory provides physical storage points by the charge discrete memory gate dielectric layer to achieve unit or multi-bit operation to achieve high memory density.
  • the gate stack structure is formed by sequentially stacking an isolation dielectric layer and a conductive gate layer, wherein the gate isolation dielectric layer is made of silicon dioxide, and the conductive gate layer is made of polysilicon, metal, metal silicide or multiple layers. A structure in which materials are stacked.
  • the doping type of the symmetric source doping region and the drain doping region is opposite to the doping type of the channel region, and the symmetric source doping region and the drain doping region are heavily doped regions, and doping thereof
  • the conditions are the same as the doping conditions of the channel region, and the symmetric source doping region and the drain doping region are periodically distributed along the channel region.
  • the materials used in the symmetric source doping region and the drain doping region are doped polysilicon or metal silicide.
  • the charge discrete memory gate dielectric layer is located on the side wall of the gate stack region on both sides of the channel region, and is composed of a charge blocking layer, a charge storage layer and a tunnel dielectric layer which are sequentially formed outward from the sidewall of the gate stacked region.
  • the material used for the charge blocking layer is silicon dioxide, a metal oxide or a structure in which a plurality of materials are stacked, and the charge storage layer is made of silicon nitride, a high-k material or a stacked structure, and the tunneling medium
  • the material used for the layer is silica, a high-k material or a structure in which a plurality of layers of materials are stacked.
  • the preparation process of the three-dimensional multi-valued non-volatile memory includes a chemical vapor deposition process, a sputtering process, an atomic layer deposition process, a thermal evaporation process, a pulsed laser deposition process, an electron beam evaporation process, or the like.
  • Structured processes such as photolithography, etching, surface planarization, annealing, and the like.
  • the memory is completed by channel hot electron injection (CHE) Programming operation, at which point electrons will enter the charge storage layer from under the gate to the underside of the gate.
  • CHE channel hot electron injection
  • Each memory cell in the memory employs an FN gate erase operation to tunnel storage electrons from the charge storage layer into the gate stack structure of the memory array, or a band tunneling hot hole injection (BBTH) method to make hot holes Entry into the charge storage layer from the substrate completes recombination with electrons to effect an erase operation.
  • CHE channel hot electron injection
  • BBTH band tunneling hot hole injection
  • the reading operation of the device information can be performed by the reverse reading mode.
  • the structure pointed out by the present invention can also adopt other methods such as direct tunneling, FN tunneling, band tunneling hot hole injection (BBTH) to implement programming and erasing operations. Due to the characteristics of the discrete storage of charge in the charge storage layer and the symmetric source/drain structure design, multiple physical storage points can be obtained in a single device, and the programming, erasing, and reading operations of the respective storage points can be realized according to the above manner, thereby Implement multi-bit operations and increase storage density
  • the multi-valued non-volatile memory has a three-dimensional structure, and each unit has a plurality of physical storage points based on characteristics of charge local area storage, thereby realizing characteristics of multi-value storage. Based on the stereo structure of a single device, three-dimensional integration of the memory array can be realized, thereby greatly increasing the storage density.
  • the three-dimensional multi-valued non-volatile memory of the invention has high density and easy integration, and can be realized by using an existing memory manufacturing process, which is advantageous for the promotion and application of the present invention.
  • the nature of the charge localized storage in the charge trapping layer and the spatial characteristics of the vertical stacked structure are utilized in combination, and multiple physical storage points are obtained in a single device to realize multi-value storage in the memory device array.
  • the three-dimensional integration is formed, thereby fundamentally increasing the storage density.
  • the memory of the present invention can obtain better device performance such as programming, erasing, and holding.
  • the charge trapping type multi-valued non-volatile memory preparation process of the present invention is compatible with the conventional silicon planar CMOS process, and can be integrated by a conventional memory array structure, which is advantageous for a wide range of applications.

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Description

三维多值非挥发存储器及其制备方法 技术领域 本发明涉及微电子制造及存储器技术领域， 尤其涉及一种具有三维集成 特性、 局域化存储电荷的三维多值非挥发存储器及其制备方法。
背景技术 目前的微电子产品主要分为逻辑器件与存储器件两大类， 而现今几乎所 有的电子产品中都需要用到存储器件， 因而存储器件在微电子领域占有非常 重要的地位。 存储器件一般可分为挥发性存储器与非挥发存储器。 非挥发性 存储器的主要特点是在不加电的情况下也能够长期保持存储的信息。 它既有 只读存储器 （ROM) 的特点， 又有很高的存取速度， 而且易于擦除和重写， 随着多媒体应用、 移动通信等对大容量、 低功耗存储的需要， 非挥发性 存储器， 特别是闪速存储器 （Flash) , 所占半导体器件的市场份额变得越来 越大， 也越来越成为一种相当重要的存储器类型。
传统的 Flash存储器是采用多晶硅薄膜浮栅结构的硅基非挥发存储器， 该存储器的隧穿介质层一般是氧化层， 其上的一个缺陷即会形成致命的放电 通道。 而电荷俘获型存储器利用俘获层的电荷局域化存储特性， 实现分立电 荷存储， 隧穿介质层上的缺陷只会造成局部的电荷泄漏， 而不会形成致命的 放电通道， 这样使电荷保持更加稳定。 更为重要的是， 利用这种电荷局域化 存储特性， 可在单个器件中实现多个相对独立的物理存储点， 从而实现多位 存储， 提高存储密度。 传统的 Flash存储器采用平面结构， 垂直结构存储器 可以有效利用侧墙表面， 形成垂直沟道， 增大沟道面积， 从而获得更优的器 件性能。
随着微电子技术的迅猛发展， 半导体器件的尺寸进一步按比例缩小， 除 了对非挥发存储器的编程、 擦除、 保持性能的要求不断提高外， 实现高密度 存储从而获得更低的成本成为非挥发存储器发展中的重点。 三维集成技术是 提高存储密度的有效方法之一。专利 US5825296描述了一种三维结构只读存 储器，专利 US20080023747公开了基于多叠层结构的半导体存储器件阵列的 构成与制备方法， 但是这两个专利中所述存储阵列存储密度相对于实际需求 仍然偏低， 如何提高存储密度仍是非挥发存储器领域研究的重要方向。
发明内容 有鉴于此， 本发明的主要目的在于提供一种三维多值非挥发存储器及其 制备方法， 以提高存储密度， 获得性能优的多值存储器。
为达到上述目的， 本发明提供了一种三维多值非挥发存储器， 该存储器 具有多个存储单元， 该多个存储单元进一步构成存储阵列， 该存储阵列具有 栅极叠层结构、 周期性交替排列的栅极叠层区和沟道区空间、 电荷分立存储 栅介质层、 周期性的沟道区、 对称的源掺杂区与漏掺杂区， 以及分别由该源 掺杂区与漏掺杂区位置及该栅极叠层区引出位线及字线， 该存储器由该电荷 分立存储栅介质层提供物理存储点，实现单位或多位操作，获得高存储密度。
上述方案中， 所述栅极叠层结构由隔离介质层与导电栅极层依次堆叠而 成， 其中栅隔离介质层采用的材料为二氧化硅， 导电栅极层采用多晶硅、 金 属、 金属硅化物或由多层材料堆叠而成的结构。
上述方案中， 所述周期性交替排列的栅极叠层区和沟道区空间是通过刻 蚀该栅极叠层结构形成的， 由光刻胶或硬质掩模定义栅极叠层区的图形， 然 后刻蚀该栅极叠层结构直至露出介质层， 刻蚀后形成了周期性交替排列的栅 极叠层区和沟道区空间。
上述方案中， 所述电荷分立存储栅介质层位于沟道区两侧的栅极叠层区 侧墙上， 由自栅极叠层区侧墙向外依次形成的电荷阻挡层、 电荷存储层和隧 穿介质层构成。 所述电荷阻挡层采用的材料为二氧化硅、 金属氧化物或由多 层材料堆叠而成的结构， 所述电荷存储层采用的材料为氮化硅、 高 k材料或 堆叠结构， 所述隧穿介质层采用的材料为二氧化硅、 高 k材料或由多层材料 堆叠而成的结构。该存储器采用沟道热电子注入 CHE方式完成编程操作，此 时电子将从衬底进入到栅极下方的所述电荷存储层中。所述存储单元采用 FN 栅擦除操作使得存储电子从所述电荷存储层隧穿进入存储阵列的栅极叠层结 构， 或者采用带带隧穿热空穴注入 BBTH方式使得热空穴从衬底进入所述电 荷存储层完成与电子的复合， 从而实现擦除操作。
上述方案中， 所述周期性的沟道区是通过在相邻的两个隧穿介质层之间 的沟道区空间淀积多晶硅， 并完全填充该沟道区空间而形成的。
上述方案中， 所述对称的源掺杂区和漏掺杂区的惨杂类型与所述沟道区 的掺杂类型相反， 且所述对称的源掺杂区与漏掺杂区是重掺杂区域， 其掺杂 条件与所述沟道区的掺杂条件相同， 该对称的源掺杂区与漏掺杂区沿所述沟 道区周期性分布。 所述对称的源掺杂区与漏掺杂区采用的材料为掺杂多晶硅 或金属硅化物。
为达到上述目的， 本发明还提供了一种制备三维多值非挥发存储器的方 法， 包括： 在半导体衬底上形成栅极叠层结构； 刻蚀该栅极叠层结构形成周 期性交替排列的栅极叠层区和沟道区空间； 自该栅极叠层区的侧墙依次淀积 电荷阻挡层、 电荷存储层和隧穿介质层， 形成电荷分立存储栅介质层； 在相 邻的两个隧穿介质层之间的沟道区空间淀积多晶硅形成周期性的沟道区； 沿 垂直于该沟道区的方向刻蚀该沟道区形成多个周期性排列的源掺杂区与漏掺 杂区位置； 在该源掺杂区与漏掺杂区位置中淀积源 /漏掺杂材料， 形成对称的 源掺杂区与漏掺杂区； 以及分别由该源掺杂区与漏掺杂区位置及该栅极叠层 区引出位线及字线， 形成非挥发的三维多值非挥发存储器。
上述方案中， 所述在半导体衬底上形成栅极叠层结构包括： 采用化学气 相沉积在半导体衬底上沉积起缓冲隔离作用的介质层； 采用化学气相沉积在 该介质层上依次交错沉积隔离介质层与导电栅极层， 形成栅极叠层结构。
上述方案中， 所述半导体衬底为硅片、 锗硅片或是包含外延硅层、 锗硅 层的多层衬底材料； 所述介质层为二氧化硅； 所述栅极叠层结构由隔离介质 层与导电栅极层依次堆叠而成， 所述隔离介质层采用的材料为二氧化硅， 所 述导电栅极层采用的材料为多晶硅、 金属、 金属硅化物或由多层材料堆叠具 有类似性质的结构。
上述方案中， 所述刻蚀该栅极叠层结构形成周期性交替排列的栅极叠层 区和沟道区空间， 包括： 由光刻胶或硬质掩模定义栅极叠层区的图形， 刻蚀 该栅极叠层结构直至露出介质层， 刻蚀后形成了周期性交替排列的栅极叠层 区和沟道区空间。
上述方案中， 所述自该栅极叠层区的侧墙依次淀积电荷阻挡层、 电荷存 储层和隧穿介质层， 形成电荷分立存储栅介质层， 包括： 在刻蚀形成有交替 排列的栅极叠层区和沟道区空间的该栅极叠层结构上依次淀积电荷阻挡层、 电荷存储层和隧穿介质层； 刻蚀在该栅极叠层区及介质层之上淀积的电荷阻 挡层、 电荷存储层和隧穿介质层， 经刻蚀后露出最上层隔离介质层及衬底， 进而保留沿该栅极叠层区侧墙依次形成的电荷阻挡层、 电荷存储层和隧穿介 质层， 形成电荷分立存储栅介质层。
上述方案中， 所述在相邻的两个隧穿介质层之间的沟道区空间淀积多晶 硅形成周期性的沟道区， 包括： 在相邻的两个隧穿介质层之间的沟道区空间 淀积多晶硅， 完全填充该沟道区空间， 形成周期性的沟道区。
上述方案中， 所述沿垂直于该沟道区的方向刻蚀该沟道区形成多个周期 性排列的源掺杂区与漏掺杂区位置， 包括： 采用光刻胶或硬质掩模来定义源 掺杂区与漏掺杂区位置的图形， 然后沿垂直于该沟道区的方向刻蚀该沟道区 直至露出衬底， 在沟道区上形成多个周期性排列的方形孔洞， 该方形孔洞即 是源掺杂区与漏掺杂区位置。
上述方案中， 所述在该源掺杂区与漏掺杂区位置中淀积源 /漏掺杂材料， 形成对称的源掺杂区与漏掺杂区， 包括： 在该源掺杂区与漏掺杂区位置中淀 积源 /漏掺杂材料， 并通过化学机械抛光对表面进行平坦化， 形成沿沟道区周 期分布的对称的源掺杂区和漏掺杂区。
上述方案中， 所述形成对称的源掺杂区与漏掺杂区之后， 还包括： 进行 热处理工艺， 将沟道区以及源掺杂区与漏掺杂区均形成单晶硅。
上述方案中， 所述分别由该源掺杂区与漏掺杂区位置及该栅极叠层区引 出位线及字线， 形成非挥发的三维多值非挥发存储器的步骤中， 是由源掺杂 区与漏掺杂区引出位线， 且该位线沿与沟道区垂直方向设置， 并由该栅极叠 层区引出字线， 且该字线沿与沟道区平行方向设置。
上述方案中， 所述位线采用的材料为多晶硅、 金属、 金属硅化物或由多 层材料堆叠具有类似性质的结构， 所述字线采用的材料为多晶硅、 金属、 金 属硅化物或由多层材料堆叠具有类似性质的结构。
从上述技术方案可以看出， 本发明具有以下有益效果：
1、本发明提供的三维多值非挥发存储器及其制备方法，综合利用了电荷 俘获层的电荷局域化存储性质及垂直结构存储器有效沟道长度增加和密度提 高的特性， 使单个存储结构单元具有多个物理存储点， 从而在实现多位存储 的基础上， 进行存储器阵列的三维集成， 在保证高速等较优的存储性能的同 时， 从根本上提高了存储密度。
2、本发明提供的三维多值非挥发存储器及其制备方法，其制备工艺与传 统的硅平面 CMOS工艺兼容， 可采用传统存储器阵列结构集成， 利于广泛应 用。
附图说明 图 1是依照本发明实施例在半导体衬底上形成栅极叠层结构的示意图； 图 2是依照本发明实施例刻蚀该栅极叠层结构的示意图；
图 3是依照本发明实施例在刻蚀叠层结构后淀积电荷分立存储栅介质层 的示意图；
图 4是依照本发明实施例刻蚀栅极叠层区及介质层之上淀积的电荷分立 存储栅介质层的示意图；
图 5是依照本发明实施例在相邻的两个隧穿介质层之间的沟道区空间淀 积多晶硅形成周期性的沟道区的示意图；
图 6是依照本发明实施例通过刻蚀方式定义源 /漏掺杂区位置的示意图； 图 7为依照本发明实施例在源 /漏掺杂区位置淀积源 /漏掺杂材料形成源 / 漏掺杂区的示意图；
图 8为依照本发明实施例对沟道区、 源 /漏掺杂区进行单晶化的示意图； 图 9为依照本发明实施例从源 /漏掺杂区引出位线的示意图；
图 10为依照本发明实施例从栅极叠层区引出字线的示意图；
图 11 是依照本发明实施例的三维多值非挥发存储器的单层等效电路示 意图；
图 12 是依照本发明实施例的三维多值非挥发存储器的三维等效电路示 意图。
5 具体实施方式 为使本发明的目的、 技术方案和优点更加清楚明白， 以下结合具体实施 例， 并参照附图， 对本发明进一步详细说明。
图 1至图 10示出了依照本发明实施例的制备三维多值非挥发存储器的示 意图， 具体制备过程如下：
10 图 1是依照本发明实施例在半导体衬底上形成栅极叠层结构的示意图。
半导体衬底 100为硅片、 锗硅片、 其他类似半导体材料或是包含外延硅层、 锗硅层的多层衬底材料。介质层 101为二氧化硅或其它具有类似性质的材料， 起缓冲隔离的作用。 102a、 102b, 102c, 102d、 102e为隔离介质层， 采用的 材料为二氧化硅或其它具有类似性质的材料， 103a、 103b, 103c, 103d为导 i s 电栅极层， 采用的材料为多晶硅、 金属、 金属硅化物或由多层材料堆叠具有 类似性质的结构。 如图所示， 隔离介质层与导电栅极层依次堆叠， 形成栅极 叠层结构。 其工艺方法为化学气相沉积 (CVD)等。
图 2是依照本发明实施例刻蚀该栅极叠层结构的示意图。 由光刻胶或硬 质掩模等定义栅极叠层区 201 的图形， 刻蚀栅极叠层结构直至露出介质层 0 101，刻蚀后形成了周期性的栅极叠层区 201及刻蚀后打开的沟道区空间 202。
图 3是依照本发明实施例在刻蚀叠层结构后淀积电荷分立存储栅介质层 的示意图。 自栅极叠层区 201 的侧墙依次淀积电荷阻挡层 301、 电荷存储层 302 和隧穿介质层 303， 形成电荷分立存储栅介质层。 其中电荷阻挡层 301 采用的材料是二氧化硅、 金属氧化物、 其它具有类似性质的材料或由多层材
25 料堆叠具有类似性质的结构， 电荷存储层 302采用的材料为氮化硅、 高 k材 料、 其它具有电荷存储能力的材料或堆叠结构， 隧穿介质层 303采用的材料 为二氧化硅、 高 k材料、 其它具有类似性质的材料或由多层材料堆叠具有类 似性质的结构。 制备方法及各薄层厚度可根据所用材料不同调整。 图 4是依照本发明实施例刻蚀栅极叠层区 201及介质层 101之上淀积的 电荷分立存储栅介质层的示意图，经刻蚀后露出最上层隔离介质层 102e及衬 底 100，而保留了沿栅极叠层区侧墙依次形成的电荷阻挡层 301、电荷存储层 302和隧穿介质层 303。
图 5是依照本发明实施例在相邻的两个隧穿介质层 303之间的沟道区空 间 202淀积多晶硅形成周期性的沟道区的示意图。 在相邻的两个隧穿介质层 303之间的沟道区空间 202淀积多晶硅，完全填充该沟道区空间 202，形成周 期性的沟道区 401。
图 6是依照本发明实施例通过刻蚀方式定义源 /漏掺杂区位置的示意图。 首先用光刻胶或硬质掩模等定义源 /漏掺杂区位置 502的图形，然后沿垂直于 沟道区 401的方向刻蚀沟道区 401直至露出衬底 100， 在沟道区 401上形成 多个周期性排列的方形孔洞 502， 该方形孔洞 502即是源 /漏掺杂区位置。 另 夕卜， 在沟道区 401中还剩下未被刻蚀的沟道区域 501。
图 7为依照本发明实施例在源 /漏掺杂区位置 502淀积源 /漏掺杂材料形 成源 /漏掺杂区的示意图。 在源 /漏掺杂区位置 502中淀积源 /漏掺杂材料， 形 成源 /漏掺杂区 601，该源 /漏掺杂材料是与沟道区掺杂类型相反的重掺杂多晶 硅。 淀积完源 /漏掺杂区材料后， 该源 /漏掺杂材料填充了刻蚀所打开的源 /漏 掺杂区位置 502， 然后通过化学机械抛光对器件表面进行平坦化。 由于源 /漏 掺杂区掺杂条件相同， 即形成了对称的源掺杂区与漏掺杂区 601a， 且源惨杂 区与漏掺杂区沿沟道区 401周期分布。
图 8为依照本发明实施例对沟道区、 源 /漏惨杂区进行单晶化的示意图。 经热处理工艺后， 沟道区及源 /漏掺杂区均形成单晶硅。
图 9为依照本发明实施例从源 /漏惨杂区引出位线的示意图。位线 701由 源 /漏掺杂区引出， 沿与沟道区垂直方向设置， 如图 9所示， 位线 701的材料 为多晶硅、 金属、 金属硅化物或由多层材料堆叠具有类似性质的结构。
图 10 为依照本发明实施例从栅极叠层区引出字线的示意图。 字线 801 由栅极叠层区引出， 沿与沟道区平行方向设置， 如图 10所示， 字线 801的材 料为多晶硅、 金属、 金属硅化物或由多层材料堆叠具有类似性质的结构。
至此， 完成了三维多值非挥发存储器的制备， 得到了三维多值非挥发存 储器。图 11进一歩示出了依照本发明实施例的三维多值非挥发存储器的单层 等效电路示意图，图 12进一步示出了依照本发明实施例的三维多值非挥发存 储器的三维等效电路示意图。 与传统的平面结构相比， 三维结构大大提高了 存储密度。 通过对字线 WLi、 WLi+1、 WLi+2…及位线 BLj、 BLj+1、 BLi+2的 操作可实现对图中单个存储单元的编程、 擦除、 读取等操作。 而在每个存储 单元内， 又可以实现多位操作， 进一步提高存储密度。
再次参照图 10， 在本发明的实施例中， 三维多值非挥发存储器具有多个 存储单元， 该多个存储单元进一步构成存储阵列， 该存储阵列具有栅极叠层 结构、周期性交替排列的栅极叠层区和沟道区空间、电荷分立存储栅介质层、 周期性的沟道区、 对称的源掺杂区与漏掺杂区， 以及分别由该源掺杂区与漏 掺杂区位置及该栅极叠层区引出位线及字线， 该存储器由该电荷分立存储栅 介质层提供物理存储点， 实现单位或多位操作， 获得高存储密度。
其中， 栅极叠层结构由隔离介质层与导电栅极层依次堆叠而成， 其中栅 隔离介质层采用的材料为二氧化硅， 导电栅极层采用多晶硅、 金属、 金属硅 化物或由多层材料堆叠而成的结构。
对称的源掺杂区和漏掾杂区的惨杂类型与所述沟道区的掺杂类型相反， 且所述对称的源掺杂区与漏掺杂区是重掺杂区域， 其掺杂条件与所述沟道区 的掺杂条件相同， 该对称的源掺杂区与漏掺杂区沿所述沟道区周期性分布。 对称的源掺杂区与漏惨杂区采用的材料为掺杂多晶硅或金属硅化物。
电荷分立存储栅介质层位于沟道区两侧的栅极叠层区侧墙上， 由自栅极 叠层区侧墙向外依次形成的电荷阻挡层、 电荷存储层和隧穿介质层构成。 电 荷阻挡层采用的材料为二氧化硅、金属氧化物或由多层材料堆叠而成的结构， 所述电荷存储层采用的材料为氮化硅、 高 k材料或堆叠结构， 所述隧穿介质 层采用的材料为二氧化硅、 高 k材料或由多层材料堆叠而成的结构。
在本发明的实施例中， 三维多值非挥发存储器的制备工艺包括化学气相 淀积工艺、 溅射工艺、 原子层淀积工艺、 热蒸发工艺、 脉冲激光淀积工艺、 电子束蒸发工艺或其它可实现结构的工艺， 如光刻、 刻蚀、 表面平坦化、 退 火等传统方法。
在本发明的实施例中， 该存储器采用沟道热电子注入 （CHE) 方式完成 编程操作， 此时电子将从衬底进入到栅极下方的电荷存储层中。 该存储器中 的各存储单元采用 FN栅擦除操作使得存储电子从电荷存储层隧穿进入存储 阵列的栅极叠层结构， 或者采用带带隧穿热空穴注入 （BBTH) 方式使得热 空穴从衬底进入所述电荷存储层完成与电子的复合， 从而实现擦除操作。
在本发明的实施例中， 器件信息的读取操作可以通过反向读取方式
(Reverse read)完成， 即靠近存储栅极的漏区加低电压， 而远离存储栅极的 源区加高电压来完成。为适应特别应用，本发明指出的结构也可以采用其他， 如直接隧穿、 FN隧穿、 带带隧穿热空穴注入 (BBTH)等各种方式实现编程、 擦除操作。 由于电荷存储层中电荷分立存储的特性及对称源 /漏结构设计， 可 在单个器件中获得多个物理存储点， 并根据上述方式实现对各个存储点的编 程、 擦除、 读取操作， 从而实现多位操作， 提高存储密度
在本发明的实施例中， 多值非挥发存储器具有立体结构， 基于电荷局域 存储的特性， 每个单元具有多个物理存储点， 从而实现多值存储的特性。 基 于单个器件的立体结构， 可以实现存储器阵列三维集成， 从而大幅度提高存 储密度。 本发明三维多值非挥发存储器密度高、 易集成， 采用现有存储器制 造工艺即可实现， 有利于本发明的推广和应用。
在本发明的实施例中， 综合利用了电荷俘获层中电荷局域化存储的性质 和垂直堆叠结构的空间特性， 在单个器件中获得多个物理存储点， 实现多值 存储， 在存储器件阵列上形成三维集成， 从而根本上提高了存储密度。 同时 本发明存储器可获得较优的编程、 擦除、 保持等器件性能。 本发明电荷俘获 型多值非挥发存储器制备工艺与传统的硅平面 CMOS工艺兼容，可采用传统 存储器阵列结构集成， 利于广泛应用。
以上所述的具体实施例， 对本发明的目的、 技术方案和有益效果进行了 进一步详细说明， 所应理解的是， 以上所述仅为本发明的具体实施例而巳， 并不用于限制本发明， 凡在本发明的精神和原则之内， 所做的任何修改、 等 同替换、 改进等， 均应包含在本发明的保护范围之内。

Claims

权 利 要 求
1、一种三维多值非挥发存储器， 其特征在于， 该存储器具有多个存储单 元， 该多个存储单元进一步构成存储阵列， 该存储阵列具有栅极叠层结构、 周期性交替排列的栅极叠层区和沟道区空间、 电荷分立存储栅介质层、 周期 性的沟道区、 对称的源掺杂区与漏掺杂区， 以及分别由该源惨杂区与漏掺杂 区位置及该栅极叠层区引出位线及字线， 该存储器由该电荷分立存储栅介质 层提供物理存储点， 实现单位或多位操作， 获得高存储密度。
2、根据权利要求 1所述的三维多值非挥发存储器， 其特征在于， 所述栅 极叠层结构由隔离介质层与导电栅极层依次堆叠而成， 其中栅隔离介质层采 用的材料为二氧化硅， 导电栅极层采用多晶硅、 金属、 金属硅化物或由多层 材料堆叠而成的结构。
3、根据权利要求 1所述的三维多值非挥发存储器， 其特征在于， 所述周 期性交替排列的栅极叠层区和沟道区空间是通过刻蚀该栅极叠层结构形成 的， 由光刻胶或硬质掩模定义栅极叠层区的图形， 然后刻蚀该栅极叠层结构 直至露出介质层，刻蚀后形成了周期性交替排列的栅极叠层区和沟道区空间。
4、根据权利要求 1所述的三维多值非挥发存储器， 其特征在于， 所述电 荷分立存储栅介质层位于沟道区两侧的栅极叠层区侧墙上， 由自栅极叠层区 侧墙向外依次形成的电荷阻挡层、 电荷存储层和隧穿介质层构成。
5、根据权利要求 4所述的三维多值非挥发存储器， 其特征在于， 所述电 荷阻挡层采用的材料为二氧化硅、金属氧化物或由多层材料堆叠而成的结构， 所述电荷存储层采用的材料为氮化硅、 高 k材料或堆叠结构， 所述隧穿介质 层采用的材料为二氧化硅、 高 k材料或由多层材料堆叠而成的结构。
6、根据权利要求 4所述的三维多值非挥发存储器， 其特征在于， 该存储 器采用沟道热电子注入 CHE方式完成编程操作，此时电子将从衬底进入到栅 极下方的所述电荷存储层中。
7、根据权利要求 4所述的三维多值非挥发存储器， 其特征在于， 所述存 储单元采用 FN栅擦除操作使得存储电子从所述电荷存储层隧穿进入存储阵 列的栅极叠层结构， 或者采用带带隧穿热空穴注入 BBTH方式使得热空穴从 衬底进入所述电荷存储层完成与电子的复合， 从而实现擦除操作。
8、根据权利要求 1所述的三维多值非挥发存储器， 其特征在于， 所述周 期性的沟道区是通过在相邻的两个隧穿介质层之间的沟道区空间淀积多晶 硅， 并完全填充该沟道区空间而形成的。
9、根据权利要求 1所述的三维多值非挥发存储器， 其特征在于， 所述对 称的源掺杂区和漏掺杂区的掺杂类型与所述沟道区的掺杂类型相反， 且所述 对称的源掺杂区与漏掺杂区是重掺杂区域， 其惨杂条件与所述沟道区的掺杂 条件相同， 该对称的源掺杂区与漏掺杂区沿所述沟道区周期性分布。
10、 根据权利要求 9所述的三维多值非挥发存储器， 其特征在于， 所述 对称的源掺杂区与漏掺杂区采用的材料为掺杂多晶硅或金属硅化物。
11、 一种制备权利要求 1所述三维多值非挥发存储器的方法， 其特征在 于， 包括：
在半导体衬底上形成栅极叠层结构；
刻蚀该栅极叠层结构形成周期性交替排列的栅极叠层区和沟道区空间； 自该栅极叠层区的侧墙依次淀积电荷阻挡层、电荷存储层和隧穿介质层， 形成电荷分立存储栅介质层；
在相邻的两个隧穿介质层之间的沟道区空间淀积多晶硅形成周期性的沟 道区；
沿垂直于该沟道区的方向刻蚀该沟道区形成多个周期性排列的源掺杂区 与漏掺杂区位置；
在该源掺杂区与漏惨杂区位置中淀积源 /漏掺杂材料，形成对称的源掺杂 区与漏掺杂区； 以及
分别由该源掺杂区与漏掺杂区位置及该栅极叠层区引出位线及字线， 形 成非挥发的三维多值非挥发存储器。
12、根据权利要求 11所述的制备三维多值非挥发存储器的方法， 其特征 在于， 所述在半导体衬底上形成栅极叠层结构包括：
采用化学气相沉积在半导体衬底上沉积起缓冲隔离作用的介质层； 采用化学气相沉积在该介质层上依次交错沉积隔离介质层与导电栅极 层， 形成栅极叠层结构。
13、根据权利要求 12所述的制备三维多值非挥发存储器的方法，其特征 在于，
所述半导体衬底为硅片、 锗硅片或是包含外延硅层、 锗硅层的多层衬底 材料； 所述介质层为二氧化硅；
所述栅极叠层结构由隔离介质层与导电栅极层依次堆叠而成， 所述隔离 介质层采用的材料为二氧化硅，所述导电栅极层采用的材料为多晶硅、金属、 金属硅化物或由多层材料堆叠具有类似性质的结构。
14、根据权利要求 1 1所述的制备三维多值非挥发存储器的方法， 其特征 在于， 所述刻蚀该栅极叠层结构形成周期性交替排列的栅极叠层区和沟道区 空间， 包括：
由光刻胶或硬质掩模定义栅极叠层区的图形， 刻蚀该栅极叠层结构直至 露出介质层， 刻蚀后形成了周期性交替排列的栅极叠层区和沟道区空间。
15、根据权利要求 11所述的制备三维多值非挥发存储器的方法， 其特征 在于， 所述自该栅极叠层区的侧墙依次淀积电荷阻挡层、 电荷存储层和隧穿 介质层， 形成电荷分立存储栅介质层， 包括：
在刻蚀形成有交替排列的栅极叠层区和沟道区空间的该栅极叠层结构上 依次淀积电荷阻挡层、 电荷存储层和隧穿介质层；
刻蚀在该栅极叠层区及介质层之上淀积的电荷阻挡层、 电荷存储层和隧 穿介质层， 经刻蚀后露出最上层隔离介质层及衬底， 进而保留沿该栅极叠层 区侧墙依次形成的电荷阻挡层、 电荷存储层和隧穿介质层， 形成电荷分立存 储栅介质层。
16、根据权利要求 11所述的制备三维多值非挥发存储器的方法， 其特征 在于， 所述在相邻的两个隧穿介质层之间的沟道区空间淀积多晶硅形成周期 性的沟道区， 包括：
在相邻的两个隧穿介质层之间的沟道区空间淀积多晶硅， 完全填充该沟 道区空间， 形成周期性的沟道区。
17、根据权利要求 1 1所述的制备三维多值非挥发存储器的方法， 其特征 在于， 所述沿垂直于该沟道区的方向刻蚀该沟道区形成多个周期性排列的源 掺杂区与漏掺杂区位置， 包括： 采用光刻胶或硬质掩模来定义源掺杂区与漏掺杂区位置的图形， 然后沿 垂直于该沟道区的方向刻蚀该沟道区直至露出衬底， 在沟道区上形成多个周 期性排列的方形孔洞， 该方形孔洞即是源掺杂区与漏掺杂区位置。
1 8、根据权利要求 1 1所述的制备三维多值非挥发存储器的方法，其特征 在于， 所述在该源掺杂区与漏掺杂区位置中淀积源 /漏掺杂材料， 形成对称的 源掺杂区与漏掺杂区， 包括：
在该源惨杂区与漏掺杂区位置中淀积源 /漏掺杂材料，并通过化学机械抛 光对表面进行平坦化，形成沿沟道区周期分布的对称的源掺杂区和漏掺杂区。
19、根据权利要求 1 1所述的制备三维多值非挥发存储器的方法，其特征 在于， 所述形成对称的源掺杂区与漏掺杂区之后， 还包括：
进行热处理工艺， 将沟道区以及源惨杂区与漏掺杂区均形成单晶硅。
20、根据权利要求 1 1所述的制备三维多值非挥发存储器的方法，其特征 在于， 所述分别由该源掺杂区与漏惨杂区位置及该栅极叠层区引出位线及字 线， 形成非挥发的三维多值非挥发存储器的步骤中， 是由源掺杂区与漏掺杂 区引出位线， 且该位线沿与沟道区垂直方向设置， 并由该栅极叠层区引出字 线， 且该字线沿与沟道区平行方向设置。
21、根据权利要求 20所述的制备三维多值非挥发存储器的方法，其特征 在于， 所述位线采用的材料为多晶硅、 金属、 金属硅化物或由多层材料堆叠 具有类似性质的结构， 所述字线采用的材料为多晶硅、 金属、 金属硅化物或 由多层材料堆叠具有类似性质的结构。
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