WO2011153721A1 - Procédé et appareil pour le réglage de fréquences - Google Patents

Procédé et appareil pour le réglage de fréquences Download PDF

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Publication number
WO2011153721A1
WO2011153721A1 PCT/CN2010/074667 CN2010074667W WO2011153721A1 WO 2011153721 A1 WO2011153721 A1 WO 2011153721A1 CN 2010074667 W CN2010074667 W CN 2010074667W WO 2011153721 A1 WO2011153721 A1 WO 2011153721A1
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Prior art keywords
clock
frequency
branch
adjustment period
last
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PCT/CN2010/074667
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English (en)
Chinese (zh)
Inventor
郑伟
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中兴通讯股份有限公司
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Publication of WO2011153721A1 publication Critical patent/WO2011153721A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop

Definitions

  • the present invention relates to the field of digital products, and more particularly to a method and apparatus for adjusting frequency.
  • Clock signals are found in almost all digital products. Depending on the requirements and application scenarios, the requirements for performance specifications such as clock accuracy and stability are also different. In most applications, the device's local clock source does not need to be functioning externally, and the clock's performance metrics can meet the demand. In contrast, the industrial measurement and communication field requires high performance specifications for clocks. In most cases, it is necessary to use an auxiliary means to calibrate the clock, for example, using a cesium atomic clock or satellite timing as a reference to adjust the clock frequency.
  • the clock source sends the clock to the phase-locked loop and adjusts the output to the desired frequency.
  • Most phase-locked loops can adjust the frequency of the clock source to a preset value and output multiple clocks of the same frequency and different phases.
  • this method cannot dynamically adjust the clock source frequency.
  • the technical problem to be solved by the present invention is to provide a method and apparatus for adjusting the frequency, which can dynamically adjust the frequency of the clock source.
  • a method of adjusting a frequency including:
  • the frequency synthesizing module outputs a first clock of the last sampling period, the control module inputs a reference clock of the last sampling period and a first clock of the last sampling period, and outputs the reference clock according to the reference clock and the first clock The length of the generated adjustment period;
  • the phase-locked loop module inputs a source clock of the current sampling period, and outputs a second clock of a current sampling period according to a preset multiplication factor, and each branch has a predetermined phase difference;
  • the frequency synthesis module inputs the second clock, sequentially selects each branch of the second clock, performs frequency synthesis according to the duration of the adjustment period, a preset frequency combination coefficient, and outputs a current adjustment week.
  • the first clock of the period The first clock of the period.
  • the method further includes: the control module configuring a frequency multiplication coefficient of the phase locked loop module according to a frequency of the reference clock and a frequency of the source clock;
  • the control module configures a total number of branches of the second clock and a phase difference between each branch of the second clock according to an accuracy requirement of a frequency of the first clock;
  • the control module configures a frequency combining coefficient of the frequency synthesizing module according to a frequency of the reference clock and a frequency multiplication coefficient of the phase locked loop.
  • the frequency synthesizing module inputs the second clock, sequentially selects each branch of the second clock, performs frequency synthesis according to the duration of the adjustment period, a preset combining frequency coefficient, and outputs a first clock of the current adjustment period.
  • the steps include:
  • Step 31 The frequency synthesizing module receives the duration of the adjustment period from the control module.
  • Step 32 The frequency synthesizing module determines whether the branch of the second clock selected in the last adjustment period is the last one, if The branch of the second clock selected in the last adjustment period is the last one, and step 33 is performed. If the branch of the second clock selected in the previous adjustment period is not the last one, proceed to step 34;
  • Step 33 switching to the first branch of the second clock, frequency synthesis by the first branch of the second clock of the current adjustment period, and then proceeding to step 35;
  • Step 34 switching to the next branch of the second clock, performing frequency synthesis by the next branch of the second clock of the current adjustment period, and then performing step 35;
  • Step 35 After the duration of the adjustment period, enter a next adjustment period.
  • the step of performing frequency synthesis by the first branch of the second clock of the current adjustment period includes:
  • the step of performing frequency synthesis by the next branch of the second clock of the current adjustment period includes:
  • control module inputting the reference clock of the last sampling period and the first clock of the previous sampling period, and outputting the duration of the adjustment period generated according to the reference clock and the first clock,
  • the control module calculates an absolute value of a difference between a frequency of a reference clock of the last sample period and a frequency of a first clock of the last sample period to generate a frequency difference value
  • the control module generates and outputs an adjustment period according to the frequency difference, the frequency of the second clock, the total number of branches of the second clock, and the frequency of the reference clock.
  • the duration T of the adjustment period is l/(
  • R is the frequency of the reference clock of the last adjustment period
  • D is the first period of the previous adjustment period
  • M is the frequency of the second clock
  • N is the total number of branches of the second clock.
  • the phase difference between the n-1th branch and the nth branch of the second clock is ⁇ / ⁇ , where ⁇ is the branch number of the second clock, 0 ⁇ n ⁇ N, and ⁇ is the second clock The total number of branches.
  • an apparatus for adjusting a frequency includes: a control module, a phase locked loop module, and a frequency synthesizing module; wherein
  • the control module is configured to: input a reference clock of the last sample period and a first clock of the last sample period output by the frequency synthesis module, and output an adjustment period generated according to the reference clock and the first clock Length of time;
  • the phase-locked loop module is configured to: input a source clock of a current sampling period, and output a second clock of a current sampling period according to a preset multiplication factor, and each of the branches has a predetermined phase difference;
  • the frequency synthesis module is configured to: input the second clock, and select the second clock in sequence Each of the branches, and frequency synthesis according to the duration of the adjustment period and the preset frequency coefficient, and outputs the first clock of the current adjustment period.
  • the control module is further configured to: configure a frequency multiplication coefficient of the phase locked loop module according to a frequency of the reference clock and a frequency of the source clock; configured to configure the frequency according to an accuracy requirement of a frequency of the first clock a total number of branches of the second clock and a phase difference between the branches of the second clock; and configuring the combination of the frequency synthesis module according to a frequency of the reference clock and a frequency multiplication coefficient of the phase locked loop Frequency factor.
  • the frequency synthesis module includes:
  • a receiving submodule configured to receive a duration of the adjustment period from the control module; and a determining submodule configured to determine whether the branch of the second clock selected by the last adjustment period is the last path, and generate a determination result ;
  • a switching sub-module configured to switch to the first branch of the second clock when the determination result is that the branch of the second clock selected by the last adjustment period is the last one, when the determination result Switching to the next branch of the second clock when the branch of the second clock selected for the last adjustment period is not the last one;
  • a frequency synthesizing subunit configured to: when the judging result is that the branch of the second clock selected in the last adjustment period is the last one, the frequency is performed by the first branch of the second clock of the current adjustment period Synthesizing; when the result of the determination is that the branch of the second clock selected in the previous adjustment period is not the last one, the frequency is synthesized by the next branch of the second clock of the current adjustment period; the timing sub-module, It is set to enter the next adjustment period after the duration of the adjustment period.
  • the frequency synthesizing subunit is further configured to output a square wave;
  • the number of occurrences of the rising edge of the first branch of the second clock of the current adjustment period reaches the sum Triggering the high level of the square wave; when the number of falling edges of the first branch of the second clock of the current adjustment period reaches the reciprocal of the combining coefficient, triggering the Square wave level;
  • the result of the determination is that the branch of the second clock selected in the last adjustment period is not the last one
  • the number of occurrences reaches a high level of the square wave when the reciprocal of the frequency combining coefficient is reached;
  • the number of falling edges of the next branch of the second clock of the current adjustment period reaches a reciprocal of the combining frequency coefficient, Triggering a low level of the square wave; the reciprocal of the combining frequency coefficient is a natural number.
  • the control module includes:
  • phase detector module configured to calculate an absolute value of a difference between a frequency of a reference clock of the last sample period and a frequency of a first clock of the last sample period to generate a frequency difference value
  • the adjustment submodule is configured to generate and output an adjustment period according to the frequency difference, the frequency of the second clock, the total number of branches of the second clock, and the frequency of the reference clock.
  • Embodiments of the present invention have the following beneficial effects:
  • the frequency of the first clock of the output of the current adjustment period is adjusted, and the output frequency can be dynamically adjusted, which is relatively simple.
  • FIG. 1 is a schematic flow chart of an embodiment of a method for adjusting a frequency according to the present invention
  • FIG. 2 is a schematic flow chart of another embodiment of a method for adjusting a frequency according to the present invention
  • FIG. 3 is a schematic structural diagram of an embodiment of a frequency adjustment device according to the present invention
  • FIG. 5 is a schematic flow chart of an application scenario of the frequency adjustment device illustrated in FIG. 4;
  • an embodiment of a method for adjusting a frequency according to the present invention includes: Step 11: A control module configures the phase lock according to a frequency of the reference clock and a frequency of the source clock. The multiplication factor of the ring module;
  • Step 12 The control module configures the foregoing according to an accuracy requirement of a frequency of the first clock a total number of branches of the second clock and a phase difference between the branches of the second clock;
  • Step 13 The control module configures a frequency combining coefficient of the frequency synthesizing module according to a frequency of the reference clock and a frequency multiplication coefficient of the phase locked loop.
  • Step 14 The frequency synthesizing module outputs a first clock of the last sampling period, and the control module inputs a reference clock of the last sampling period and a first clock of the previous sampling period, and outputs the reference clock according to the reference clock.
  • Step 15 The phase-locked loop module inputs a source clock of the current sampling period, and outputs a second clock of a current sampling period according to a preset multiplication factor, and each branch has a predetermined phase difference; and then respectively jumps Go to step 16 and step 14; in step 14, start the loop from the next sample cycle; step 16, the frequency synthesis module inputs the second clock, and sequentially selects each branch of the second clock, according to the The duration of the adjustment period and the preset combination coefficient are used for frequency synthesis, and the first clock of the current adjustment period is output.
  • the frequency of the first clock of the output of the current adjustment period is adjusted, and the output frequency can be dynamically adjusted, which is relatively simple.
  • control module inputting the reference clock of the last sampling period and the first clock of the previous sampling period, and outputting the duration of the adjustment period generated according to the reference clock and the first clock,
  • the control module calculates an absolute value of a difference between a frequency of a reference clock of the last sample period and a frequency of a first clock of the last sample period to generate a frequency difference value
  • the control module generates and outputs an adjustment period according to the frequency difference, the frequency of the second clock, the total number of branches of the second clock, and the frequency of the reference clock.
  • the duration T of the adjustment period is l/(
  • the last adjustment period is the previous sampling period.
  • Step 21 A control module configures the lock according to a frequency of the reference clock and a frequency of the source clock. a multiplication factor of the phase loop module, the multiplication factor being a positive integer;
  • Step 22 The control module configures a total number of branches of the second clock and a phase difference between each branch of the second clock according to an accuracy requirement of a frequency of the first clock.
  • Step 23 The control module configures a frequency combining coefficient of the frequency synthesizing module according to a frequency of the reference clock and a frequency multiplication coefficient of the phase locked loop, where the combining frequency coefficient is a reciprocal of a positive integer.
  • Step 24 The control module inputs a reference clock of the last sample period and a first clock of the last sample period output by the frequency synthesis module, and outputs a duration of the adjustment period generated according to the reference clock and the first clock;
  • Step 25 The phase-locked loop module inputs a source clock of the current sampling period, and outputs a second clock of a current sampling period according to a preset multiplication factor, and each branch has a predetermined phase difference; and then respectively jumps Go to step 26 and step 24; in step 24, start the loop from the next sample cycle; step 26, the frequency synthesis module receives the duration of the adjustment period from the control module; step 27, the frequency synthesis The module determines whether the branch of the second clock selected in the last adjustment period is the last one, if yes, proceed to step 28, otherwise proceed to step 29;
  • Step 28 Switch to the first branch of the second clock, perform frequency synthesis by the first branch of the second clock of the current adjustment period, and then proceed to step 210; Step 29, switch to the second clock The next branch, the frequency is synthesized by the next branch of the second clock of the current adjustment period, and then proceeds to step 210;
  • Step 210 After the duration of the adjustment period, enter the next adjustment period, and then jump to step 26. In step 26, the loop begins from the next adjustment period.
  • the step of performing frequency synthesis by the first branch of the second clock of the current adjustment period is specifically:
  • the frequency of the source clock output from the clock source is S Hz
  • the phase-locked loop outputs the second clock with the frequency of N
  • the frequency of the adjusted first clock generated according to the second clock with the frequency of MHz is D.
  • the preset frequency of the reference frequency is RHz.
  • Step 1 Adjust the phase and frequency of the second clock whose output frequency is the MHz of the phase-locked loop to be an integer multiple of the frequency of the reference clock, and the clock phase of the first branch of the second clock is 0 degrees.
  • the clock phase of the second branch is ⁇ / ⁇
  • the clock phase of the third branch is 2 ⁇ / ⁇ ... and so on
  • the clock phase of the second branch is ( ⁇ -1) ⁇ / ⁇ .
  • Step 2 Perform phase discrimination with the first clock of the adjusted D Hz using a reference clock with a preset frequency of R Hz, and obtain a frequency difference (RD) Hz of the two clocks; calculate according to the frequency difference (RD) Hz
  • the compensation value of the first clock D Hz, the compensation formula is as follows: The number of compensations per second
  • Step 4 Repeat step 3 after adjusting the period l/(
  • a frequency adjustment device includes: a control module 31, a phase locked loop module 32, and a frequency synthesizing module 33.
  • the control module 31 is configured to: input a reference clock of the last sample period and a first clock of the last sample period output by the frequency synthesis module, and output an adjustment period generated according to the reference clock and the first clock duration;
  • the phase locked loop module 32 is configured to: input a source clock of the current sampling period, according to a preset multiple a frequency coefficient, a second clock that outputs a predetermined total number of branches and each of the branches has a predetermined phase difference of the current sampling period;
  • the frequency synthesizing module 33 is configured to: input the second clock, sequentially select each branch of the second clock, perform frequency synthesis according to the duration of the adjustment period, a preset combining frequency coefficient, and output current adjustment The first clock of the cycle.
  • the control module 31 is further configured to: configure a frequency multiplication coefficient of the phase locked loop module according to a frequency of the reference clock and a frequency of the source clock; configured to configure the frequency according to a frequency accuracy requirement of the first clock a total number of branches of the second clock and a phase difference between the branches of the second clock; and configuring the combination of the frequency synthesis module according to a frequency of the reference clock and a frequency multiplication coefficient of the phase locked loop Frequency factor.
  • the frequency of the first clock of the output of the current adjustment period is adjusted, and the output frequency can be dynamically adjusted, which is relatively simple.
  • the control module 31 includes:
  • phase detector module configured to calculate an absolute value of a difference between a frequency of a reference clock of the last sample period and a frequency of a first clock of the last sample period to generate a frequency difference value
  • the adjustment submodule is configured to generate and output an adjustment period according to the frequency difference, the frequency of the second clock, the total number of branches of the second clock, and the frequency of the reference clock.
  • the frequency synthesis module 33 includes:
  • a receiving submodule configured to receive a duration of the adjustment period from the control module; and a determining submodule configured to determine whether the branch of the second clock selected by the last adjustment period is the last path, and generate a determination result ;
  • a switching sub-module configured to switch to the first branch of the second clock when the determination result is that the branch of the second clock selected by the last adjustment period is the last one, when the determination result Switching to the next branch of the second clock when the branch of the second clock selected for the last adjustment period is not the last one;
  • the frequency synthesizing subunit which is set to be the last adjustment when the judgment result is The first branch of the second clock of the current adjustment period when the branch of the second clock of the period selection is the last one Performing frequency synthesis; when the result of the determination is that the branch of the second clock selected in the last adjustment period is not the last one, the frequency is synthesized by the next branch of the second clock of the current adjustment period;
  • the module is set to enter the next adjustment period after the duration of the adjustment period.
  • the frequency synthesis subunit is also arranged to output a square wave. Specifically, when the determining result is that the branch of the second clock selected in the last adjustment period is the last one, when the rising edge of the first branch of the second clock of the current adjustment period occurs, the number of occurrences reaches a high level of the square wave when the reciprocal of the frequency combining coefficient is reached; when the number of falling edges of the first branch of the second clock of the current adjustment period reaches a reciprocal of the combining frequency coefficient, Triggering a low level of the square wave; when the determining result is that the branch of the second clock selected in the last adjustment period is not the last one, when the next branch of the second clock of the current adjustment period When the number of rising edges of the rising edge reaches the reciprocal of the combining frequency coefficient, the high level of the square wave is triggered; when the falling edge of the next branch of the second clock of the current adjustment period occurs, the number reaches When the reciprocal of the combining coefficient is used, the low level of the square wave is triggered; the
  • the duration T of the adjustment period is l/(
  • R is the frequency of the reference clock of the last adjustment period
  • D is the first period of the previous adjustment period
  • M is the frequency of the second clock
  • N is the total number of branches of the second clock.
  • the phase difference between the n-1th branch and the nth branch of the second clock is ⁇ / ⁇ , where ⁇ is the branch number of the second clock, 0 ⁇ n ⁇ N, and ⁇ is the second clock The total number of branches.
  • phase detecting sub-module 41 is configured to perform phase-collection statistics on the synthesized frequency and the reference clock.
  • the adjustment sub-module 42 initializes the phase-locked loop module, sends configuration information (such as a multiplication factor, etc.) to the phase-locked loop, and dynamically adjusts the adjustment information of the frequency synthesis module according to the phase-detection result (for example, a frequency-combination coefficient, etc.);
  • the ring module 43 is for multiplying the source clock of the clock source to a higher frequency;
  • the frequency synthesis module 44 is configured to generate the second clock of the high frequency to generate the first clock of the low frequency.
  • FIG. 5 is a schematic flow chart of an application scenario of the device for adjusting frequency according to FIG. The following description describes the application scenario of the frequency synthesizing apparatus according to the present invention with reference to Figs. 4 and 5.
  • Step 51 Configure the second clock outputted by the phase-locked loop module 43 to be 200 MHz according to the reference clock 5.0000001 MHz, so that the second clock is a common multiple of the reference clock and the source clock. (In this application scenario, the integer bit of the reference clock frequency is selected. ), configuring the input and output points of the frequency synthesis module 44 Don't be 200MHz and 5MHz, 5 ⁇ is first generated by the first branch count of the second clock. There are 4 second clocks for adjustment; that is, the multiplication factor is 20 and the combining frequency is 1/40.
  • Step 52 the phase detector sub-module 41 performs phase-collecting statistics on the 5 MHz first clock and the reference clock 5.0000001 MHz output by the frequency synthesizing module 44;
  • Step 53 The adjustment sub-module 42 processes the phase-detection value, and calculates the compensation times per second and the compensated frequency difference of the frequency synthesis module 44 according to the above, which are 16 times and 0.00625 Hz respectively; Step 54 The sub-module 42 sends the adjustment information to the frequency synthesis module 44, and updates in real time according to the latest preset reference clock;
  • Step 55 the frequency synthesis module 44 according to the adjustment information to obtain an adjustment interval of 0.0625 seconds;
  • Step 56 determine whether the current 5MHz is the fourth clock count, if yes, proceed to step 57, otherwise proceed to step 58;
  • Step 57 the 5MHz clock is switched from the second clock count to the first split clock count, and step 59 is performed;
  • Step 58 the 5MHz clock is switched from the second clock count to the next split clock count, and step 59 is performed;
  • Step 59 After adjusting the period of time, proceed to step 55.
  • the present invention provides a method and apparatus for adjusting a frequency that dynamically adjusts the clock source frequency.
  • H has no clock source of 10 MHz, and the clock source has an adjustment range of 10 MHz ⁇ 50 Hz, and when 10 MHz + 60 Hz is desired. Due to the limited adjustment range of the clock source itself, this frequency is not achieved, and the common phase-locked loop corresponds to an input frequency of 10 MHz ⁇ 50 Hz. In the above way, it is easy to implement.
  • the frequency multiplication coefficient of the phase locked loop is a ratio between the frequency of the output clock of the phase locked loop and the frequency of the input clock, and may be a positive integer; the frequency combining coefficient of the frequency synthesizing module is the output clock of the frequency synthesizing module.
  • the ratio between the frequency and the frequency of the input clock can be the reciprocal of a positive integer.
  • the steps of the foregoing embodiments may be implemented by a program to instruct related hardware, and the program may be stored in a computer readable storage medium.
  • the method includes the steps of the foregoing method embodiment, such as: a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (No. RAM) and so on.
  • sequence numbers of the steps are not used to limit the sequence of the steps.
  • the steps of the steps are changed without any creative work. It is also within the scope of the invention.
  • the method and apparatus for adjusting a frequency provided by the present invention can dynamically adjust a clock source frequency.
  • ⁇ Combining a plurality of high-frequency clocks of different phases to synthesize a low-frequency clock can realize not only high-precision frequency synthesis but also low frequency.
  • the fine adjustment can effectively improve the performance and performance indexes of the output clock, reduce the overall cost of the clock system, and can be used in various clock frequency recovery applications, and has strong versatility.

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Abstract

La présente invention se rapporte à un procédé et à un appareil pour le réglage de fréquences. L'invention appartient au domaine des produits numériques et a pour objectif de résoudre le problème technique lié, dans l'art antérieur, à l'impossibilité de régler les fréquences d'horloge source de façon dynamique. Le procédé selon l'invention comprend les étapes suivantes : un module de synthèse de fréquences délivre en sortie un premier signal d'horloge du dernier cycle d'échantillonnage ; un module de commande reçoit un signal d'horloge de référence du dernier cycle d'échantillonnage ainsi que le premier signal d'horloge du dernier cycle d'échantillonnage et il délivre en sortie la durée d'un cycle de réglage générée sur la base du signal d'horloge de référence et du premier signal d'horloge ; un module à boucle à verrouillage de phase reçoit un signal d'horloge source du cycle d'échantillonnage en cours et délivre en sortie un second signal d'horloge du cycle d'échantillonnage en cours sur la base d'un coefficient de doublage de fréquence prédéterminé, le second signal d'horloge contenant un nombre total prédéterminé de shunts et les shunts présentant des différences de phase prédéterminées entre eux ; le module de synthèse de fréquences reçoit le second signal horloge et sélectionne les shunts du second signal horloge les uns après les autres ; il exécute une synthèse de fréquences sur la base de la durée du cycle de réglage et d'un coefficient de synthèse de fréquences prédéterminé ; et il délivre en sortie le premier signal d'horloge du cycle de réglage en cours. Le procédé et le dispositif selon l'invention permettent de régler de façon dynamique les fréquences de l'horloge source.
PCT/CN2010/074667 2010-06-10 2010-06-29 Procédé et appareil pour le réglage de fréquences WO2011153721A1 (fr)

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